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Texas Instruments Generation of a VCOM buffer input using PWM signal Application notes
Application Report
SLVA763 – February 2016
How to Generate a VCOM Voltage Using a PWM Signal
Sokhna Diaara Diop and Nigel Smith
ABSTRACT
In an LCD, the backlight shines through the liquid crystal material and the voltage across the liquid crystal
controls how much light shines through it. An active matrix LCD (AMLCD) contains many pixels arranged
in a grid pattern. The voltage across each pixel is controlled individually so that high resolution images can
be created. One terminal of every pixel is connected to a common plane. The voltage on this plane is
called the VCOM voltage and it is the reference voltage for each pixel. The VCOM voltage is typically
adjusted for best image quality during production and is often generated by a digital-to-analog converter
(DAC), such as the LM8342 device, buffered by an amplifier.
A typical VCOM voltage generator has two functions:
• It provides a way to adjust the VCOM voltage
• It buffers the adjusted VCOM voltage
This application note describes how to use a PWM signal to generate the input for a VCOM buffer. Many
timing controllers can generate PWM signals which are capable of good performance at low cost.
1
2
3
4
5
6
Contents
Basic PWM Circuit to Generate the VCOM Voltage .................................................................... 2
Modified Circuit With Reduced Adjustment Range ...................................................................... 4
Using an Operational Amplifier to Generate the VCOM Voltage From a PWM Signal ............................. 8
VCOM Adjustment Circuit for Bipolar Displays .......................................................................... 9
A Note About Component Selection ..................................................................................... 10
Conclusion .................................................................................................................. 11
List of Figures
1
Basic PWM Circuit to Generate the VCOM Voltage .................................................................... 2
2
VCOM Voltage Characteristic of the Circuit Shown in Figure 1 ....................................................... 3
3
Modified Circuit With Reduced Adjustment Range ...................................................................... 4
4
VCOM Voltage Characteristic of the Circuit Shown in
5
Propagation Delay (50 kHz) ................................................................................................ 6
6
Propagation Delay (10 kHz)
7
8
9
10
11
12
13
14
15
.................................................................
5
............................................................................................... 6
Application Example ......................................................................................................... 7
Fall Time of VCOM Voltage ................................................................................................ 7
VCOM Switching Waveforms and Voltage Ripple ....................................................................... 7
VCOM Voltage Variation over Temperature ............................................................................. 8
Using an Op-Amp to Generate V(VCOM) Directly ........................................................................... 8
High-Speed Level Shifter Devices ......................................................................................... 9
VCOM Adjustment Circuit for Bipolar Displays .......................................................................... 9
VCOM Voltage Characteristic of Circuit Shown in .................................................................... 10
Using an Op-Amp to Generate V(VCOM) Directly ......................................................................... 10
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Basic PWM Circuit to Generate the VCOM Voltage
1
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Basic PWM Circuit to Generate the VCOM Voltage
V(AVDD)
R3
R4
V(VCOM)
R1
10 k
C1
Q1
R2
10 k
Figure 1. Basic PWM Circuit to Generate the VCOM Voltage
Figure 1 shows a simple circuit that converts the logic-level PWM signal from a microcontroller to an
analog VCOM voltage. This circuit is composed essentially of two stages: an amplification stage followed
by a low pass filter.
Transistor Q1 amplifies and inverts the input signal. Thus, the output at the collector of Q1 has a duty
cycle of 1 – D (where D is the duty cycle of the logic-level input signal) and an amplitude of V(AVDD) volts.
The low-pass filter of resistor R4 and capacitor C1 converts the PWM signal at the collector of Q1 to a dc
output. If R4 >> R3, high and low signals have an almost equal and opposite effect on the low-pass filter
and the output voltage changes almost linearly with duty cycle and is given by Equation 1:
WHITESPACE
V(VCOM) 1 D V(AVDD)
(1)
WHITESPACE
The collector-emitter saturation voltage (VCE(sat)) of transistor Q1 is approximately 100 mV at these current
levels, which is small compared with V(AVDD). Because the VCOM voltage of every display is set individually
during production, a nonzero collector-emitter saturation voltage does not have an important effect on the
circuit performance. During production of the display, if the VCE(sat) of a transistor is different from the
nominal value, the operator adjusts the duty cycle of the PWM signal to correct the difference. It is
important that VCE(sat) does not change a lot with temperature, because this has an effect on the VCOM
voltage. In typical applications, with the components shown, the change of VCE(sat) with temperature is too
small to have an important effect.
If the values of R3 and R4 have the same order of magnitude (for example, if the value of R4 is less than
ten times the value of R3), then the output voltage changes nonlinearly with duty cycle. For instance if R3
= R4 = 100 kΩ in the circuit of Figure 1, C1 will charge up through 200 kΩ (R3 + R4) when Q1 is off and it
will discharge through 100 kΩ (R4) when Q1 is on. This difference in charge and discharge resistance
makes the output voltage change nonlinearly with duty cycle:
WHITESPACE
§ 1 D R4 ·
V(VCOM) ¨
¸V
¨ D R3 R4 ¸ (AVDD)
©
¹
(2)
WHITESPACE
Inserting R3 = 100 kΩ and R4 = 100 kΩ in Equation 2 gives,
WHITESPACE
V(VCOM)
§1 D·
¨ 1 D ¸ V(AVDD)
©
¹
(3)
WHITESPACE
Figure 2 shows the nonlinear response of the circuit shown in Figure 1.
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Basic PWM Circuit to Generate the VCOM Voltage
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1
0.9
Multiplication Factor k
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4 0.5 0.6
Duty Cycle (%)
0.7
0.8
0.9
1
D001
Figure 2. VCOM Voltage Characteristic of the Circuit Shown in Figure 1
The VCOM voltage is typically adjusted during the manufacture of the display to get the highest image
quality. In most practical applications, a linear relationship between the duty cycle and the VCOM voltage
is not necessary.
1.1
Filter Selection
The low-pass filter formed by resistor R4 and capacitor C1 converts the PWM signal at the collector of Q1
to a dc voltage. The cutoff frequency of the low-pass filter sets the output voltage ripple. For example, if a
ripple of less than 1 LSB for a resolution of N bits is required, the value of C1 is determined as follows:
• First determine the attenuation needed:
WHITESPACE
§ 1 ·
a
20log ¨ N ¸
©2 ¹
(4)
or a = 20log(VLSB/VPWM)
WHITESPACE
where
•
•
•
VLSB is the minimum step size of the PWM signal
VPWM is the adjustment range of the circuit
(5)
The cutoff frequency of the low-pass filter is given by Equation 6
WHITESPACE
f
fco
2
§ 20a ·
¨ 10 ¸ 1
©
¹
WHITESPACE
where
•
•
•
fco is the cutoff frequency of a first-order low-pass filter necessary to attenuate sufficiently.
f is the frequency of the PWM signal
Finally, the value of C1 is given by Equation 7
WHITESPACE
1
fCO
2S(R4)(C1)
(6)
(7)
WHITESPACE
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Modified Circuit With Reduced Adjustment Range
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The cutoff frequency of the low-pass filter also sets the rise time of the VCOM voltage during start-up as
follows:
WHITESPACE
tr (4.6)(R4)(C1)
where
•
•
•
tr is the VCOM voltage rise time from 0% to 99% of its final value
R4 is the low-pass filter resistance
C1 is the low-pass filter capacitance
(8)
WHITESPACE
Equation 7 and Equation 8 show that a reduction of the rise time of the VCOM voltage will lead to an
increase of the voltage ripple amplitude. For this reason, depending on the application, you have to make
a tradeoff between the required rise time and the maximum allowed ripple.
2
Modified Circuit With Reduced Adjustment Range
The circuit shown in Figure 1 is sufficient for many applications, but it has the disadvantage that the
adjustment range of the VCOM voltage is from 0 V to V(AVDD). In typical display applications, a much
smaller adjustment range is used.
Figure 3 shows a circuit that uses an additional resistor to set the adjustment range.
V(AVDD)
R3
100 k
R1
200 k
V(VCOM)
10 k
Q1
R2
200 k
C1
10 k
Figure 3. Modified Circuit With Reduced Adjustment Range
The operation of this circuit is best understood with Thévenin equivalent circuits:
• When transistor Q1 is off, capacitor C1 is supplied from an equivalent voltage source of V(AVDD)/2
through a resistance of 100 kΩ.
• When transistor Q1 is on, capacitor C1 is supplied from an equivalent voltage source of V(AVDD)/4
through an equivalent resistance of 50 kΩ.
• The adjustment range of the VCOM voltage is thus from V(AVDD)/4 to V(AVDD)/2.
Capacitor C1 makes a low-pass filter with the output resistance of the level shifter. The minimum output
resistance of the level shifter is 50 kΩ, and this value must be used to calculate the filter cutoff frequency.
Because the output resistance of the level shifter is different when the output is high than when it is low,
the VCOM voltage varies nonlinearly, as follows:
4
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WHITESPACE
V(VCOM)
§
¨
¨1
¨
¨¨
©
1 D
·
¸
1 D
¸ V(AVDD)
4
§ R1|| R2 · ¸
D¨
¸ ¸¸
© R1|| R2 || R3 ¹ ¹
(9)
WHITESPACE
Inserting R1//R2//R3 = 50 kΩ and R1//R2 = 100 kΩ in Equation 9 gives,
WHITESPACE
1
V(VCOM)
V(AVDD)
2 1 D
(10)
WHITESPACE
Figure 4 shows the nonlinear relationship between the VCOM voltage and the PWM duty cycle of the
circuit shown in Figure 3.
0.5
Multiplication Factor k
0.45
0.4
0.35
0.3
0.25
0
0.1
0.2
0.3
0.4 0.5 0.6
Duty Cycle (%)
0.7
0.8
0.9
1
D001
Figure 4. VCOM Voltage Characteristic of the Circuit Shown in Figure 3
The value of capacitor C1 is selected as described in Section 1.1. Because this circuit has an adjustment
range of V(AVDD)/4 (four times smaller than in the circuit of Figure 1), the output voltage ripple is four times
smaller.
2.1
Improvement of Transistor Switching Time
Because of the propagation delay, which occurs during normal switching operation of the transistor, the
duty cycle of the input signal differs a little from the duty cycle of the PWM at the collector of Q1. This is
observed in Figure 5 where an 100-kHz PWM signal with a duty cycle of 0.35 gives an output with a duty
cycle of approximately 0.5.
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Modified Circuit With Reduced Adjustment Range
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PWM
V(collector)
Figure 5. Propagation Delay (50 kHz)
If you use a lower PWM frequency, the delay becomes negligible compared to the period of the PWM
signal and the resulting error is very small. For example in Figure 5, the delay is approximately 1.5 µs,
which represents an increase of the duty cycle of 15% when the frequency of the PWM is 100 kHz and
only 1.5% when it is lowered to 10 kHz (see Figure 6). This solution is simple and does not require
additional components. Because of the reduction of the frequency, a bigger filter is necessary to meet the
same output voltage ripple requirement.
Figure 6. Propagation Delay (10 kHz)
If it is not possible to change the frequency of the PWM signal, another solution is to add a capacitor
across the base resistor and a Schottky diode between the base and collector of transistor Q1 (see
Figure 7). The capacitor speeds up the removal of charge stored on the base of the transistor and the
diode prevents the transistor saturating, thus reducing the overall delay (see Figure 9).
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2.2
Application Example
V(AVDD)
R3
10 k
35 pF
R1
20 k
V(VCOM)
10 k
Q1
R2
20 k
C1
75 nF
10 k
Figure 7. Application Example
In this section the performance of the circuit in Figure 7 is evaluated. The PWM signal frequency is set to
100 kHz and this gives a resolution of approximately 8 bits, that is a minimum step size of 12.5 mV. To
achieve a ripple of less than 1 LSB (47-dB attenuation), a 75-nF capacitor is necessary with the minimum
output resistance of 5 kΩ. Thus the VCOM voltage takes 1.7 ms to reach 99% of its final value with 0.4%
accuracy. This is observed in Figure 8 and Figure 9, which show the fall time and the ripple of the VCOM
voltage.
Figure 8. Fall Time of VCOM Voltage
Figure 9. VCOM Switching Waveforms and Voltage Ripple
Figure 10 shows that a temperature variation lead to a variation of ±0.15% of the VCOM voltage. The
considered temperature range is larger than what we would expect on an actual application, which means
that the actual variation of the VCOM voltage would be lower than what is shown in Figure 10.
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Using an Operational Amplifier to Generate the VCOM Voltage From a PWM Signal
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4.100
4.075
VCOM Voltage (V)
4.050
4.025
4.000
3.975
3.950
3.925
3.900
-10
0
10
20
30
40
50
Temperature (°C)
60
70
80
90
Figure 10. VCOM Voltage Variation over Temperature
3
Using an Operational Amplifier to Generate the VCOM Voltage From a PWM Signal
If your application uses an operational amplifier (that is, not a unity-gain buffer) to generate V(VCOM), you
can use the operational amplifier to scale and filter the input PWM signal. The circuit shown in Figure 11
converts a 50-kHz, 3.3-V PWM signal to a dc level in the range 2.5 V to 5 V. Compared to the previous
examples, this circuit is more linear, changes less over temperature, and can be used at higher
frequencies.
C2
10n
3.3-V PWM
50 kHz
R1
33k
V(AVDD)
R2
33k
R4
49k9
±
C1
10n
3.3 V
R3
39k2
+
R5
10k
R6
10k
V(VCOM)
2.5 V to 5 V
LMH6642 or
LM8261
Figure 11. Using an Op-Amp to Generate V(VCOM) Directly
The output voltage of the circuit in Figure 11 is given by Equation 11
WHITESPACE
R6
R4
R4
V(VCOM) = 3.3 ml
p l1 +
+
p
R5 + R6
R3 R1+R2
R4
Dl
pq
R1 + R2
(11)
WHITESPACE
If the tolerance of the 3.3-V supply is too high, use one of the level shifter solutions shown in Figure 12 to
convert the 3.3-V PWM signal to a more steady supply voltage (typically V(AVDD) or V(AVDD+)).
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VCOM Adjustment Circuit for Bipolar Displays
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3.3 V
10 V
1
2
7
9
15
16
CD40109B
3
4
6
5
5V
5
3.3-V
PWM
11
10
10-V
PWM
3.3-V
PWM
2
4
3
5-V
PWM
SN74LV1T34
14
13
8
Figure 12. High-Speed Level Shifter Devices
4
VCOM Adjustment Circuit for Bipolar Displays
Figure 13 shows how to generate the VCOM voltage in displays that use ±V(AVDD) supplies. Unlike the
circuits in Figure 1 and Figure 3, where the VCOM voltage decreases as the duty cycle of the PWM signal
increases, the VCOM voltage increases as the duty cycle increases with this circuit. The accuracy of this
solution also depends on the tolerance of the VCC supply, which must not be too high. With the values
shown in Figure 13, the VCOM voltage adjustment range is –V(AVDD)/2 to 0 V.
VCC
3.3 V
10 k
+V(AVDD)
Q1
R3
93 k
R1
340 k
V(VCOM)
R2
113 k
C1
±V(AVDD)
Figure 13. VCOM Adjustment Circuit for Bipolar Displays
The VCOM voltage changes with PWM duty cycle as follows:
WHITESPACE
V(VCOM)
§ VCC
(R2 R1)(R3) (1 D)(R1)(R2) ¨
¨ V(AVDD)
©
(1 D)(R1)(R2) (R1 R2)(R3)
·
¸
¸
¹V
(AVDD)
(12)
WHITESPACE
Figure 14 shows how the VCOM voltage changes with the PWM duty cycle.
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A Note About Component Selection
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-0.5
-0.45
Multiplication Factor k
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0
0.1
0.2
0.3
0.4 0.5 0.6
Duty Cycle (%)
0.7
0.8
0.9
1
D001
Figure 14. VCOM Voltage Characteristic of Circuit Shown in Figure 13
The cutoff frequency of the low-pass filter is calculated as described in Section 1.1
The circuit in Figure 15 shows how to drive an operational amplifier directly from the PWM signal. As in
Figure 11, the accuracy of the V(VCOM) voltage depends on the tolerance of the 3.3-V supply. In most
cases, the variation of this supply will be too small to have an effect on image quality, but if the tolerance
is too high, you can use one of the level shifter solutions shown in Figure 12 to convert the 3.3-V PWM
signal to a more regulated voltage (typically V(AVDD) or +V(AVDD)).
C2
10n
3.3-V PWM
50 kHz
R1
33k
R2
33k
V(AVDD+)
R4
49k9
±
C1
10n
+
LMH6642 or
LM8261
V(VCOM)
±2.5 V to 0 V
V(AVDD±)
Figure 15. Using an Op-Amp to Generate V(VCOM) Directly
The output voltage of the circuit in Figure 15 is given by Equation 13:
WHITESPACE
V(VCOM) = 3.3 lD
R4
p
R1 + R2
(13)
WHITESPACE
5
A Note About Component Selection
The capacitance of a ceramic capacitor changes not only with tolerance and temperature, but also with dc
voltage. The change in capacitance with voltage is called the dc bias effect, and you must think about it
when selecting a capacitor for the low-pass filter.
The circuits described in this application note use 2N3904 and 2N3906 transistors because they are
commonly available. The same circuit performance is expected with equivalent transistors. Note that
devices are available that include a transistor and two resistors in one package. These devices reduce the
component count and minimize the PCB area of the circuit. The FJV4102R and FJV3102R devices from
Fairchild Semiconductor are examples of such devices but equivalent devices from other manufacturers
are also available.
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Conclusion
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6
Conclusion
In this application note, different circuits to generate the input of a VCOM buffer with a PWM signal are
presented. These circuits are composed of an amplification stage followed by a low-pass filter. The
switching delays during the normal operation of the transistor cause a difference between the duty cycle of
the PWM signal and the input signal of the filter. To minimize these delays:
• Reduce the PWM frequency such that the delay is negligible compared to the period of the PWM
signal
• Add a capacitor across the base resistor and a Schottky diode between the base and collector of the
transistor
When you choose the low-pass filter components you must decide on the right balance between rise time
and output voltage ripple. A lower rise time means higher ripple and vice versa.
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