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Texas Instruments 1Q 2012 Issue Analog Applications Journal Application notes
Texas Instruments Incorporated
High-Performance Analog Products
Analog Applications
Journal
First Quarter, 2012
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power Management
Turbo-boost charger supports CPU turbo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
High-performance mobile computers with turbo-mode CPUs have peak power demands that could
require an AC adapter with a significantly higher power rating than standard CPUs. Instead of a highercost adapter, a high-efficiency, turbo-boost charger can be used to manage the power from the battery
and adapter to meet the excessive power demands when the CPU operates in turbo mode. This article
discusses the operation of a typical turbo-boost charger and presents efficiency analysis of its two
modes of operation.
Benefits of a multiphase buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Single-phase, low-voltage buck converters work well at up to about 25 A; but at higher currents, multi­
phase buck converters offer several performance advantages. These include higher efficiency due to lower
transitional losses; lower output ripple; better transient performance; and lower ripple-current-power
dissipation in the input capacitor, FETs, and inductors. This article discusses these advantages, shows
waveforms from a typical application, and provides a performance analysis and tips for board layout.
Downslope compensation for buck converters when the duty cycle
exceeds 50%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current-mode control in a PWM forward converter with a duty cycle greater than 50% has the potential
of going into subharmonic oscillations. This article presents as an example a three-switch forward
converter that provides improved stability with downslope compensation and extends the maximum
duty cycle to 67%. Included are typical waveforms and calculations to determine the value of the
current-sensing resistor.
High-efficiency AC adapters for USB charging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Battery chargers with USB outlets are becoming a universal standard for 10- to 25-W chargers. This
article explores the advantages of using a synchronous rectifier to increase efficiency and satisfy the
push towards high-density, small-form-factor adapters. Included are typical waveforms and efficiency
plots comparing the performance of a Schottky diode to that of a synchronous rectifier.
Amplifiers: Op Amps
Measuring op amp settling time by using sample-and-hold technique . . . . . . . . . . . . 21
This article describes a new methodology that has proven to be effective in making settling-time
measurements for modern op amps. Detailed is a relatively inexpensive and simple way to measure
settling time that bases accuracy and precision on the relative speed of the waveform generator and the
sample-and-hold circuit. Included with a description of the test setup are typical waveforms and
settling-time plots.
Index of Articles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
To view past issues of the
Analog Applications Journal, visit the Web site
www.ti.com/aaj
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Introduction
Analog Applications Journal is a collection of analog application articles
designed to give readers a basic understanding of TI products and to provide
simple but practical examples for typical applications. Written not only for
design engineers but also for engineering managers, technicians, system
designers and marketing and sales personnel, the book emphasizes general
application concepts over lengthy mathematical analyses.
These applications are not intended as “how-to” instructions for specific
circuits but as examples of how devices could be used to solve specific design
requirements. Readers will find tutorial information as well as practical
engineering solutions on components from the following categories:
• Data Acquisition
• Power Management
• Interface (Data Transmission)
• Amplifiers: Audio
• Amplifiers: Op Amps
• Low-Power RF
• General Interest
Where applicable, readers will also find software routines and program
structures. Finally, Analog Applications Journal includes helpful hints and
rules of thumb to guide readers in preparing for their design.
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Turbo-boost charger supports
CPU turbo mode
By Jinrong Qian, Product Line Manager,
and Suheng Chen, Design Engineer
Introduction
Figure 1. Adapter and battery-charger system
To continuously improve a CPU’s dynamic
performance for fast processing of multiple
complicated tasks in mobile computers, it is
Adapter
essential to increase the CPU frequency with
full utilization of the CPU’s thermal capability
in a short time period. This could cause the
total power required by the system to exceed
the power delivered from a power source like
an AC adapter, which may result in crashing
the adapter. One possible solution is to
increase the adapter’s power rating, but at a
higher cost. This article discusses the turboboost ­charger, which allows the adapter and
battery to power the system simultaneously to
meet instantaneous and excessive power
demands from a notebook computer system
operating in CPU turbo mode.
In traditional mobile computer systems, an AC adapter
provides the power, and any power not needed by the system is used to charge the battery. When an AC adapter is
not available, the battery provides power to the system by
turning on switch S1 (see Figure 1). The adapter can be
used to power the system and charge the battery simultaneously, which may require it to have a high power rating,
increasing both its size and its cost without active control.
Dynamic power management (DPM) typically is used to
accurately monitor the total power drawn from the adapter,
which gives high priority to powering the system.
Once the adapter’s power limit is reached, the DPM
control system regulates the input current (power) by
reducing the charge current, providing power directly
from the adapter to the system without power conversion
for optimum efficiency. With the heaviest system load, all
the adapter power is used to power the system without
charging the battery at all. Therefore, the main design
criterion is to make sure that the adapter’s power rating
is high enough to support peak CPU power and other
system power.
To meet the increasing demand for improved system
performance in processing complicated tasks fast with
multiple CPU cores and enhanced graphics processor
units (GPUs), Intel developed its turbo-boost technology
in the Sandy Bridge processors. This technology allows
processors to burst their power above the thermal design
System
Load
RAC
S1
Synchronous Buck
Charge Mode:
Buck
Battery
Pack
power (TDP) for a short time period in the range from a
few tens of milliseconds to tens of seconds. However, an
AC adapter is designed to provide the power just above
the demand from the processors and platform at a TDP
level considering the design tolerance. When a charger
system detects that the adapter has reached its input
power rating after its charge current has been reduced to
zero through DPM, the simplest way to avoid crashing the
AC adapter is to achieve CPU throttling by reducing the
CPU frequency, which compromises system performance.
How can the CPU be operated faster at above the TDP
level for a short time period without crashing the adapter
or increasing its power rating?
Turbo-boost battery charger
When the total power required by the system load and
battery charger reaches the adapter’s power limit, DPM
starts to reduce the battery’s charge current. The battery
charger stops charging, and its charge current is reduced
to zero when the system load alone reaches the AC adapter’s power limit. As the system continues to increase its
load during the CPU turbo mode, the battery charger,
which is usually a synchronous buck converter, is idle, as
no remaining power is available to charge the battery. The
synchronous buck converter is actually a bidirectional
DC/DC converter that can operate in either buck or boost
mode, depending on the operating conditions. If the battery has enough capacity, the battery charger can operate
in boost mode to provide power to the system in addition
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to the power from the AC adapter. Figure 2
Figure 2. Turbo-boost battery charger in CPU turbo mode
shows a block diagram of a turbo-boost battery
charger.
When and how does the battery charger
System
Adapter
start to transition from buck charge mode to
Load
RAC
boost discharge mode? The system can enter
S1
CPU turbo mode at any time, and it is usually
too late to inform the charger to initiate this
Synchronous Buck
Discharge Mode:
transition through an SMBus. The charger
Boost
should automatically detect which operating
mode is needed. It is also critical that the sysBattery
Pack
tem be designed to achieve a fast transition
from buck to boost mode and vice versa. A DC/
DC converter needs a soft-start time of a few
hundred microseconds to a few milli­seconds to
minimize the inrush current. The adapter
should have a strong overloading capability to
to sense the battery charge current programmed from the
support the whole system’s peak power before the charger
host through the SMBus based on the battery conditions.
transitions into boost discharge mode. Most of the AC
The total power drawn by both the charger and the sysadapters currently available can hold their output voltage
tem can be monitored through the IOUT output, which is
over a few milliseconds.
20 times the voltage drop across sense resistor RAC for
Figure 3 shows an application circuit for a turbo-boost
achiev­ing CPU throttling, if needed. Through SMBus conbattery charger supporting CPU turbo mode. The RAC
trol registers, the battery’s boost discharge mode can be
current-sense resistor is used to detect the AC adapter
enabled or disabled based on the battery’s state of charge
current for the DPM function and to determine whether
and temperature conditions. In boost discharge mode, the
the battery charger is operating in buck charge mode or
circuit provides additional cycle-by-cycle current-limit
boost discharge mode. Current-sense resistor R7 is used
protection by monitoring the voltage drop across the
Figure 3. Application circuit for turbo-boost battery charger
Adapter
Q2
Q1
RAC
10 mΩ
System Load
10 Ω
R6
4.02 kΩ
R5
4.02 kΩ
1 µF
ACN
bq24735
0.1 µF
VCC
Q5
BATDRV
ACP
1 µF
CMSRC
REGN
R2
66.5 kΩ
C2
10 µF
ACDRV
R1
430 kΩ
BTST
ACDET
R3
100 kΩ
+3.3 V
Q3
HIDRV
R4
316 kΩ
ILIM
47 nF
L
4.7 µH
PHASE
Q4
R7
10 mΩ
Battery
Pack
C1
10 µF (x2)
LODRV
SDA
GND
SMBus
SCL
ACOK
Host
IOUT
SRP
SRN
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Efficiency (%)
low-side MOSFET, Q4. To achieve a small
Figure 4. Waveforms between buck charge mode and boost
form factor for a notebook computer like
discharge mode
Intel’s Ultrabook™, the switching frequency
can be programmed at 615, 750, or 885 kHz.
This minimizes the inductor size and the
number of output capacitors. To further
reduce the number of external components,
the charger’s controller chip fully integrates
the loop compensators for the charge current,
Adapter Current (2 A/div)
the charge voltage, and the input-current regulation loops. The power-source selector
MOSFET controller is also integrated in the
0A
charger. Furthermore, the charger system
uses all n-channel MOSFETs for cost
Battery Current (2 A/div)
reduction instead of the p-channel power
Charging
MOSFETs used in traditional charge solu0A
tions. Another benefit of this turbo-boost
charger system is that it can be used for
either function without changing the bill of
Boost: Discharging
materials. System designers can do a quick
system-performance evaluation without additional hardware-design effort.
Time (10 ms/div)
Figure 4 shows the switching waveforms
that occur during the transition from buck
charge mode to boost discharge mode. When
the input current reaches the adapter’s maximum power limit due to a system-load
Figure 5. Efficiency of turbo-boost charger
increase, the battery charger stops charging
and the battery transitions into boost mode
98
to provide additional power to the system.
97
Figure 5 shows the efficiency of the turbo96
boost charger. It can be seen that over 94%
95
efficiency is achieved for charging and discharging a 3-cell or 4-cell battery pack. If the
94
battery is removed or the battery’s remaining
93
capacity is not high enough, it is necessary to
92
throttle the CPU to avoid the adapter crash.
91
4-Cell, 14.4-V Boost Mode
Now the battery can be discharged even
90
3-Cell, 11.1-V Boost Mode
when the adapter is connected. However, one
2-Cell, 7.2-V Boost Mode
89
possible concern is the battery cycle life.
4-Cell, 16.8-V Boost Mode
VIN = 20 V
88
3-Cell, 12.6-V Boost Mode
f = 750 kHz
Since the boost discharge mode lasts from
87
2-Cell, 8.4-V Boost Mode
L = 4.7 µH
only tens of milliseconds to tens of seconds,
86
the impact on battery cycle life will be mini85
mal. Battery degradation is proportional to
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
the battery-cell voltage; so the higher this
Battery Charge and Discharge Current (A)
voltage is, the faster the battery will degrade
and the shorter its cycle life will be. Dis­
charging the battery in the boost discharge
mode results in a lower battery-cell voltage, reducing the
for upgrading to an AC adapter rated for peak system
degradation of the battery and lengthening its cycle life.
power. The test results show that the turbo-boost charger
Conclusion
is a practical solution in real mobile-computer designs.
A turbo-boost charger is a simple and cost-effective way
Related Web sites
for a battery to supplement AC adapter power for short
power.ti.com
periods when an AC adapter and battery simultaneously
www.ti.com/product/bq24735
power the system. This topology supports CPU turbo mode
while ensuring the lowest system cost without the need
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Benefits of a multiphase buck converter
By David Baba
Applications Engineering Manager
Introduction
Single-phase buck controllers work well for
low-voltage converter applications with currents of up to approximately 25 A, but power
dissipation and efficiency start to become an
issue at higher currents. One suitable approach
is to use a multiphase buck controller. This
article briefly dis­cusses the benefits of using a
multiphase buck converter versus a singlephase converter and the value a multiphase
buck converter can provide when implemented.
Figure 1 shows a two-phase circuit. From
this circuit’s waveforms, shown in Figure 2, it is
clear that the phases are interleaved. Inter­leav­
ing reduces ripple currents at the input and
output. It also reduces hot spots on a printed
circuit board or a particular component. In
effect, a two-phase buck con­verter reduces the
RMS-current power dissipation in the FETs and
inductors by half. Interleaving also reduces
transitional losses.
Figure 1. Two-phase buck converter
VIN
Q1
Q1 Gate
Phase 1
Node
L1
Q2
Q2 Gate
VOUT
Multiphase
Controller
VIN
Q3
Q3 Gate
Phase 2
Node
L2
Q4
Q4 Gate
Output-filter consideration
Output ripple voltage
Ripple-current cancellation in the output-filter
stage results in a reduced ripple voltage across
the output capacitor compared to a single-phase
converter. This is another reason why a multiphase converter is preferred. Equations 1 and 2
calculate the percentage of ripple current canceled in each inductor.
m = D × Phases
(1)
and
I Rip _ norm ( D) =
Figure 2. Node waveforms of phases 1 and 2
Phase 1
Phase 2
6
5
Switch-Node Voltage (V)
The output-filter requirements decrease in a
multiphase implementation due to the reduced
current in the power stage for each phase. For
a 40-A, two-phase solution, an average current
of only 20 A is delivered to each inductor.
Compared to a 40-A single-phase approach,
the inductance and inductor size are drastically
reduced because of lower average current and
lower saturation current.
4
3
2
1
0
1.628
1.629
1.630
1.631
1.632
1.633
1.634
Time (ms)
mp( D)   1 + mp( D)


 D − Phases  ×  Phases − D 
Phases ×
, (2)
(1 − D) × D
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Figure 3. Normalized capacitor ripple current as a function
of duty cycle
1
0.9
0.8
Normalized Ripple Current
where D is the duty cycle, IRip_norm is the normalized ripple current as a function of D, and
mp is the integer of m. Figure 3 plots these
equations. For example, using two phases at
a 20% duty cycle (D) yields a 25% reduction
in ripple current. The amount of ripple voltage the capacitor must tolerate is calculated
by multiplying the ripple current by the capacitor’s equivalent series resistance. Clearly, both
maximum current and voltage requirements
are reduced.
Figure 4 shows the simulation results for a
two-phase buck converter at a duty cycle of
25%. The inductor ripple current is 2.2 A, but
the output capacitor sees only 1.5 A due to
ripple-current cancellation. With a duty cycle
of 50% and two phases, the capacitor sees no
ripple current at all.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Load-transient performance
0
Load-transient performance is improved due
to the reduction of energy stored in each output inductor. The reduction in ripple voltage
as a result of current cancellation contributes
to minimal output-voltage overshoot and under­shoot
because many cycles will pass before the loop responds.
The lower the ripple current is, the less the perturbation
will be.
10
20
30
40
50
60
70
80
90
100
Duty Cycle, D (%)
Cancellation of input RMS ripple current
The input capacitors supply all the input current to the
buck converter if the input wire to the converter is inductive. These capacitors should be carefully selected to satisfy
the RMS-ripple-current requirements to ensure that they
Figure 4. Cancellation of inductor ripple current with D = 25%
Inductor Current (A)
6
4
Phase 1 Phase 2
2
0
–2
Output Capacitor Current (A)
–4
24
22
20
18
16
14
12
10
8
6
4
2
4.463
4.464
4.465
4.466
4.467
4.468
4.469
Time (ms)
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Figure 5. Normalized input RMS ripple current as a function
of duty cycle
Normalized Input RMS Ripple Current
0.250
0.225
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle, D (%)
Table 1. Operating conditions of LM3754
evaluation board
do not overheat. It is well understood that, for a singlephase converter with a duty cycle of 50%, the worst-case
input RMS ripple current is typically rated at 50% of the
output current. Figure 5 and Equation 3 indicate that, for
a two-phase solution, the worst-case RMS ripple current
occurs at duty cycles of 25 and 75% and is only 25% of the
output current.
I Input _ norm (D) =
mp(D)   mp(D) + 1


 D − Phases  ×  Phases − D 
(3)
The value of a multiphase solution as compared to a
single-phase solution is clear. Less input capacitance can
be used to satisfy the RMS-ripple-current demands of the
buck stage.
Application example
The LM3754 high-power-density evaluation board delivers
1.2 V at 40 A from a 12-V input supply. The board is 2 × 2
inches, and the area covered by the components is 1.4 × 1.3
inches. The switching frequency of each phase is set to
300 kHz. Table 1 provides a summary of these and other
operating conditions. The components are placed on a
4-layer board, with 1 oz. of copper on all layers. Additional
pins are included on this board for remote sensing, and a
pin is used for margining the output voltage.
Because the LM3754 evaluation board is designed to
operate in high-power-density configurations, it utilizes the
optimized input capacitors to provide the reduced RMS
ripple current that is required. The evaluation board also
has a low ripple voltage and good transient perform­ance.
The board layout shown in the LM3754 application note1
should be followed as closely as possible. However, if this
Input voltage
10.8 to 13.2 V
Output voltage
1.2 V ± 1%
Output current
40 A (max)
Switching frequency
300 kHz
Module size
2 × 2 inches
Circuit area
1.4 × 1.3 inches
Module height
0.5 inches
Air flow
200 LFM
Number of phases
2
is not possible, close attention should be paid to these
considerations. Several more layout considerations will
now be described, followed by the test results from a test
board using the LM3754. These results are presented in
Figures 6–11 on pages 12–13. They are typical of what one
can expect to achieve or even improve upon in making the
necessary modifications.
Layout considerations
High-current traces require enough copper to minimize
voltage drops and temperature rises. The general rule of
using a minimum of 7 mils per ampere was applied for the
2 oz. of copper used, and 14 mils per ampere for the inner
layers for the 1 oz. of copper used. The input capacitors of
each phase were placed as close as possible to the top
MOSFET drain and the bottom MOSFET source to ensure
minimal ground “bounce.”
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Signal components connected to the IC
Minimizing the switch node
All small-signal components that connected to the IC were
placed as close to it as possible. Decoupling capacitors for
VREF and VCC were also placed as close as possible to the
IC. The signal ground (SGND) was configured to ensure a
low-impedance path from the ground of the signal components to the ground of the IC.
To follow the common rules of keeping the switch-node
area as small as possible but large enough to carry high
currents, the switch node was built on multiple layers.
Because the small evaluation board essentially folds back
on itself from input to output, the switch node naturally sits
on the outer layer, and the IC sits directly underneath the
switch node. Therefore, it is essential to keep the switch
node well away from the sense lines and also from the IC.
Hence, the switch node was strategically placed facing
outwards toward the edge of the board.
SGND and PGND connections
Good layout techniques include a dedicated ground plane;
this board dedicated as much of inner-layer 2 as possible
for the ground plane. Vias and signal lines were strategically placed to avoid high-impedance points that could
pinch off wide copper areas. The power ground (PGND)
and SGND were kept separate, only connected to each
other at the ground plane (inner layer 2).
Gate drive
The designer should ensure that a differential pair of
traces is connected from the high-gate output to the top
MOSFET gate and the return, which is the switch node.
The distance between the controller and the MOSFET
should be as short as possible. The same procedure should
be followed for the LG and GND pins when the traces for
the low-side MOSFET are routed.
A differential pair of traces must also be routed from the
CSM and CS2 pins to the RC network located across the
output inductor. Notice in the layout in Reference 1 that,
in order to provide additional noise suppression, the filter
capacitor is split into two capacitors—one positioned by
the inductor and the other close to the IC. These sense
lines should not be run for long lengths in close proximity
to the switch node. If possible, they should be shielded by
using a ground plane.
Conclusion
There are a number of benefits to using multiphase buck
converters, such as higher efficiency from lower transitional losses; lower output ripple voltage; better transient
performance; and lower ripple-current-rating requirements
for the input capacitor. Some examples of multiphase buck
converters that can deliver the full benefits described
herein are the LM3754, LM5119, and LM25119 families.
Reference
1. Robert Sheehan and Michael Null, “LM3753/54 evaluation board,” National Semiconductor Corp., Application
Note 2021, Dec. 15, 2009 [Online]. Available: http://
www.national.com/an/AN/AN-2021.pdf
Related Web sites
power.ti.com
www.ti.com/product/partnumber
Replace partnumber with LM3754, LM5119, or LM25119
11
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Test results
Texas Instruments Incorporated
Figure 6. Efficiency plot with 12-V input
90
VOUT = 1.2 V
Efficiency (%)
85
VOUT = 0.9 V
80
75
70
65
4
8
12
16
20
24
28
32
36
40
I OUT (A)
Figure 7. Power loss with 12-V input
9.65
8.65
Power Loss (W)
7.65
6.65
VOUT = 0.9 V
5.65
VOUT = 1.2 V
4.65
3.65
2.65
1.65
0.65
4
8
12
16
20
24
28
32
36
40
I OUT (A)
Figure 8. Switch-node voltages
VIN = 12 V, VOUT = 1.2 V at 40 A
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Figure 9. Output voltage ripple
VIN = 12 V, VOUT = 1.2 V at 40 A
Figure 10. Transient response: 20 µs with 10-A load
step (undershoot/overshoot ~ 27 mV)
Figure 11. VOUT start-up for 1.2-V output with 40-A load
13
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Downslope compensation for buck
converters when the duty cycle exceeds 50%
By John Bottrill
Senior Applications Engineer
Current-mode control (CMC) in a pulse-widthFigure 1. Three-switch forward topology
modulated (PWM) buck converter with a duty cycle
greater than 50% has the potential of going into sub­
VIN
harmonic oscillations. Lloyd H Dixon, Jr., discusses this
D1
Q1
in detail in Reference 1. According to Dixon, the solution is to add to the current-sensing signal a ramp that
is equal to the downslope of the output inductor current.
This additional voltage needs to be added into the
D4
required calculation in order to select the currentL1
sensing resistor.
D8
VOUT
D2
D5
A push-pull converter, a phase-shifted full-bridge
Q3
Controller
converter, or any forward converter with duty cycles
D9
C1
greater than 50% at the output inductor are topologies
RTN
that require this compensation. However, for demonstration purposes, the topology selected for this discusD6
sion is one that is relatively unknown: a three-switch
forward converter. See a basic schematic of the power
D3
Q2
D7
section in Figure 1. This topology, though patented by
Texas Instruments (TI), is licensed to the public when a
RTN
TI control IC is used in the circuit.
This topology has several advantages, particularly
when the input-voltage range is that which is normally
considered the telephone-battery range of 36 to 72 V.
The topology limits the maximum duty cycle to 67%,
used for the output. The first step is to determine the
which limits the design to a maximum duty cycle at a minturns ratio of the transformer. At the minimum input voltimum input voltage of 67%. At the same time, the voltage
age, the duty cycle will be at the maximum limit (67%).
on the main switches when they turn off is limited to the
The voltage needed at the output of the transformer can
input voltage of the power rail. This means that low-voltage
be determined by the equation
FETs can be used with their corresponding lower RDS(on)
VOUT + Vfd 3.3 V + 0.5 V
(1)
=
= 5.672 V.
resistance. This topology also provides a means of recoverDmax
0.67
ing the magnet­izing energy in the power transformer and
If 36 V across the transformer primary windings is
in the primary-side leakage inductance, thereby removing
assumed, the turns ratio (Np) will be 6.147, so a primary
the need for wasteful snubbers.
with six turns will be used. The primary is divided into two
The converter design, in most other respects, is typical
sections of three turns each (see Figure 1). As is standard
of any buck topology, with the exception that the duty
practice, the secondary is sandwiched between the primary
cycle must be limited to 67% to avoid transformer saturasections, and Q3 is placed between the two primary section. This limit can be accomplished by selecting a control
tions. With the input at 78 V, the transformer output voltIC where the maximum duty cycle can be programmed,
age is 12.3 V, which will yield a minimum duty cycle, Dmin,
such as the UCC2807-1 (see Reference 2). Because this
of about 31%. Therefore, the maximum OFF time equals
controller has the required duty-cycle-limiting feature, it is
perfect for this application. Therefore, it was used in this
1 − Dmin
,
study along with its characteristics for the analysis.
fsw
The following analysis assumes a theoretical switching
where fsw is the planned switching frequency of 200 kHz.
supply with a 3.3-V output at 100 W. The supply has a
The minimum output inductance (L1 in Figure 1) to
maximum peak-to-peak ripple current through the output
achieve the desired peak-to-peak ripple current of 10% is
inductor equal to 10% of the maximum output DC load
thus defined as
current of 30 A, and the input voltage is expected to be
(V
+ Vfd ) × (1 − Dmin ) / fsw
between 36 and 78 V. It is also assumed that synchronous
(2)
LOUT = OUT
.
rectifiers with a forward voltage drop, Vfd, of 0.5 V will be
IOUT × 0.1
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The output inductor in Equation 2 was determined to be
4.33 µH. For design purposes, 4.5 µH will be used. From
this value, the current downslope, Ids, of the output inductor can be calculated:
Ids =
VOUT + Vfd
LOUT
to be 0.489 A/µs. Knowing the duty cycle and frequency
permits calculation of the time that the current is increasing in the output inductor, making it possible to determine
the ripple current under these conditions. Finally, the peak
current under the minimum input voltage is found to be
31.122 A. The waveforms are shown in Figure 2. These
values are almost equal, but if the downslope is added,
they change—and in a surprising way. The downslope
current that must be added to the peak current for the
maximum input voltage is
(3)
The inductor’s downslope current (Ids) is determined to
be 0.844 A/µs.
It can also be determined that the peak current through
the output inductor at maximum input voltage is
I ds × Dmin
= 1.306 A,
fsw
IOUT + 0.5 × (IOUT × 0.1),
and the downslope current that needs to be added to the
peak current for the minimum input voltage is
because the maximum peak-to-peak ripple current was
defined as being 10% of the output current, and that current is balanced about the nominal DC output. The peak
current that results is 31.884 A.
For the minimum input voltage, it is possible to determine the differential voltage across LOUT. From that, the
rate of change in the output inductor can be determined
I ds × Dmax
= 2.829 A.
fsw
See Figure 3, where the effective downslope current is
added to the currents shown in Figure 2. The result is that
Figure 2. Output inductor ripple at maximum load for VIN(min) and VIN(max)
33
Output Current, IOUT (A)
Peak IOUT at VIN(max)
32
Peak IOUT at VIN(min)
31
30
Minimum IOUT at VIN(min)
29
Minimum IOUT at VIN(max)
28
0
1
2
3
4
5
Time (µs)
6
7
8
9
10
Figure 3. Secondary currents plus effective downslope current
Output Current, IOUT (A)
34
Effective peak IOUT with downslope
current added at VIN(min)
33
Effective peak IOUT
with downslope current
added at VIN(max)
32
Peak IOUT at VIN(max)
Peak IOUT at VIN(min)
31
30
Minimum IOUT at VIN(max)
Minimum IOUT at VIN(min)
29
0
1
2
3
4
5
Time (µs)
6
7
8
9
10
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Figure 4. Circuit used to generate the desired current
through Rdspri
VDD
Q5
To Trig
Pin
Q7
Q6
Q4
R3
Q2
Rdspri
R2
CT
Three-Switch
Converter
(See Figure 1)
R6
R1
R5
R4 To CS
Pin
the effective peak current for the minimum input voltage
is higher than the effective peak current for the maximum
input voltage, even though the real peaks were the reverse.
The effective maximum current, including downslope at
the minimum input voltage, has a peak of 33.9 A, which is
the value that must be used to set the current-sensing
resistor, Rs. This current, including the downslope current
translated to the primary, is 5.658 A.
The IC chosen as the controller has a typical current-trip
level of 1.0 V, but the tolerance is between 0.9 and 1.1 V.
To make certain that all units can provide the required
power, the lower limit is used, and the value of Rs is set so
that the voltage across it at 5.658 A will be 95% of the 0.9-V
minimum. This gives a 5% safety margin for transients and
sets Rs at 0.15 W. Of course, there will be about 5 W of
power loss, which most likely would be replaced by a
current transformer. With a 100:1 transformer, Rs would
increase to 15 W. The remaining discussion assumes that
such a transformer is used.
In reality, the downslope current (Ids) does not go
through either the current transformer or the power
transformer, but the effect needs to be accounted for and
added to the voltage on resistor Rs. To do this, a resistor
Rdspri is added between resistor Rs and the IC’s currentsensing pin. At the IC’s current-sensing pin, a current ramp
is injected into the circuit. This current ramp is such that
the ramp voltage developed across resistor Rdspri between
the IC’s current-sensing pin and resistor Rs is equivalent to
the voltage that would be developed across resistor Rs by
the Ids translated to the primary. It is assumed that an
equivalent downslope current is flowing through resistor
Rs, taking into account both the power-transformer and
the current-transformer winding ratios. For this case,
Rs
Current
Transformer
resistor Rdspri is set at 1 kW for ease of calculation and
because it is much larger than resistor Rs.
The next step is to determine the dv/dt required across
Rdspri:
Vdspri =
I ds × Rs
= 21 V/ms
Np × 100
(4)
From this result, the current ramp needed through the
1-kW resistor can be determined:
I dspri =
Vdspri
Rdspri
= 21.1 µA/µs
(5)
This current times the maximum ON time gives a peak
current of 70.7 µA.
With a programmable, maximum-duty-cycle PWM controller like the UCC2807, it is relatively simple to set the
maximum duty cycle to 67% by setting the two timing
resistors to the same value, as shown in the datasheet.
Also, the specification for the part states that the valley
and peak voltages on the timing capacitor equal ¹⁄³ VCC and
²⁄³ VCC, respectively. This gives a voltage-ramp amplitude
of ¹⁄³ VCC . With this information, a circuit can now be
designed to generate a ramp current that can be injected
into the current-sensing circuit to provide the current
downslope to the current signal.
A circuit to generate the desired current is shown in
Figure 4. This circuit is based on the UCC2807-1 control
IC, with VDD set at 11 V. The valley and peak voltages of
the Trig ramp are 3.667 V minimum and 7.33 V maximum,
and the time from minimum to maximum is equal to the
maximum ON time. In this circuit, R3 is equal to twice R4.
This sets the voltage at the base of Q6 equal to ¹⁄³ VCC ,
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which is the valley of the Trig voltage. As the voltage on
the Trig pin swings from the valley to the peak (²⁄³ VCC ),
the voltage across R2 goes from 0 to ¹⁄³ VCC in a linear
manner. By choosing a value for R2 that gives a current of
70.7 µA with 3.667 V (51.8 kW) across it and then having
the unity current mirror formed by Q5/R1 and Q7/R6, the
designer can develop and add to the current-sensing signal the needed current with the correct shape and timing
for the 1-kW resistor.
Conclusion
The three-switch forward converter offers unique advantages in energy recovery by returning the magnetizing
energy and primary-side leakage energy to the source,
preventing the need for snubbers and reducing the electro­
magnetic interference common with normal forward converters. It also offers the advantage over a two-switch
forward topology of a duty cycle greater than 50%. This
article has shown an example of the calculations necessary
to determine the value of the current-sensing resistor and
the impact of the downslope necessary for stability in a
buck converter operating at a duty cycle greater than 50%.
It has also shown a method of adding in the downslope in
a converter.
References
For more information related to this article, you can down­
load an Acrobat® Reader® file at www.ti.com/lit/litnumber
and replace “litnumber” with the TI Lit. # for the
materials listed below.
Document Title
TI Lit. #
1. Lloyd H. Dixon, Jr., “Current-mode control
of switching power supplies,” 1985 Texas
Instruments Power Supply Design Seminar
(SEM400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLUP075
2. “Programmable maximum duty cycle PWM
controller,” UCC1807-x/2807-x/3807-x
Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLUS163
Related Web sites
power.ti.com
www.ti.com/product/UCC2807-1
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High-efficiency AC adapters for
USB charging
By Adnaan Lokhandwala
Product Manager
USB charging for electronic gadgets
Universal serial bus (USB) charging has become a common
means for powering electronic gadgets. The AC power
adapter/battery charger for many new consumer devices
like smartphones, tablets, and e-readers is in the 5- to 25-W
power range and presents a USB Standard-A receptacle.
The adapter output voltage of 5 V has become the preferred
choice for compatibility with PC/desktop-port charging
and communication. The current dominant interface is via
a standard (mini or Micro-B) USB cable or, in some cases,
a nonstandard connector. With battery charging gaining
consumer attention, the odd “wall wart” is transforming
into a “cool,” light, sleek, green charger. Beyond meeting
standard regulatory requirements, original equipment
manufacturers are pushing the performance envelope on
adapter efficiency and no-load power, which is also known
as vampire power. For example, leading manufacturers of
mobile-phone chargers have agreed to a five-star (<30 mW
of no-load power) charger-rating system. This makes it easy
for consumers to compare and choose the most energyefficient chargers.
Recently, there has been much talk about standardizing
the input to mobile phones and creating a universal charger
to charge any cell phone. In 2006, China issued a new regulation aimed at standardizing the wall charger and its
connecting cable. Similarly, the GSM Association (GSMA)
is now leading the Universal Charging Solution adapter
initiative for powering mobile phones with a micro USB
connector. The common charger is required to provide 5 V
± 5%, a minimum of 850 mA, and <150 mW of no-load
power. It must also comply with the USB Implementers
Forum (USB-IF) Battery Charging Specification 1.1
(BC1.1).* Besides providing ease of use for consumers, the
standard­ized charger could potentially eliminate a multi­
tude of duplicate chargers. Additionally, AC adapters with
multiple USB outlets offer consumers the convenience of
charging multiple devices without the need for a dedicated
charger for each gadget. Chargers with higher output current also allow the possibility of fast battery charging, a key
advantage over standard USB 2.0 ports that are limited to
500 mA. The increasing demand for these improvements,
along with the continued push towards adapter designs with
a smaller form factor, makes thermal management in this
“black box” a huge challenge for power-supply designers.
Power-supply architecture
For the power levels under consideration here, the flyback
topology shown in Figure 1 is the preferred choice today
due to its simplicity and low cost. The conduction loss on
the secondary-side Schottky-diode rectifier (Figure 1a)
becomes a limiting factor in achieving high-efficiency,
compact adapter designs. For instance, in a typical 5-V/3-A
adapter, the power loss in the diode rectifier alone at full
load can be 30 to 40% of the total system losses (neglecting
the compounding effect of secondary losses on increased
primary-side losses). Implementing a synchronous rectifier
(SR) for the output (Figure 1b) can increase the overall
efficiency of the converter and, because much less heat is
generated (fundamentally important in adapter designs),
ease system thermal management.
*USB-IF BC1.2 extends the charging-current range from 1.5 A to 5 A.
Figure 1. Simplified flyback topology
VIN
+
+
Primary
Controller
VOUT
VIN
+
+
SR
Controller
IC
Primary
Controller
(a) With Schottky-diode rectification
VOUT
(b) With SR-MOSFET rectification
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The conceptually simple change of adding an
SR to the classic flyback topology can significantly reduce overall system power losses. The
power level at which such a modi­fi­ca­tion is
practical has been decreasing with the rapid
advancement in power MOSFET technology.
Hence, synchronous rectification is now applicable to an ever-growing range of products. The
lower power dissipation of an SR allows designers to take advantage of smaller components
that have less heat sinking, thus increasing
power density while lowering assembly costs,
product size, and shipping weight.
Note that if the SR MOSFET is allowed to
switch during no-load/standby conditions, the
system power perform­ance could be compromised. The SR-MOSFET switching losses, in
addi­tion to the quiescent power required by the
SR controller IC, can be limiting factors in achiev­
ing the best possible system no-load performance.
Figure 2. Simplified flyback waveforms with Schottkydiode and SR-MOSFET output rectification
ISEC
VTHOFF
VTHON
MOSFET Switch, VDS
Schottky Diode, VF
VGATE
Time
Green output rectification: Full load
to no load
This article will now discuss how an IC such as
the Texas Instruments (TI) UCC24610 Green
Figure 3. Typical CCM flyback waveforms with primaryRectifier™ controller can simplify USB charger
side synchronization
designs and enable high system efficiency across
the full load range. Simpli­fied system waveforms
for a flyback converter with and without syn­chro­
Primary-Side
nous rectification are shown in Figure 2. The
MOSFET Gate
waveforms are the results of a control scheme
(10 V/div )
that directly senses the MOSFET drain-to-source
1
voltage (VDS). This control method is widely
adopted today instead of other implementation
Synchronizing Signal
choices such as primary-side synchronization or
(5 V/div)
4
synchronous control from a secondary-side current transformer. Having the SR controller’s
SR Gate
(5 V/div )
turn-off threshold (VTHOFF) as close as possible
3
to zero in this control scheme allows maxi­mum
conduction time in the MOSFET channel.
Flyback converters can be designed to operate
SR Current
(10 A/div )
in different modes depending on the end2
application requirements. For designs operating
in continuous-conduction mode (CCM), the current in the transformer sec­ond­ary does not fall to
Time (2 µs/div)
zero before the primary-side MOSFET is turned
on, which results in a period of cross-conduction.
When synchronous rectification is implemented
As described earlier, implementing synchronous rectifi­ca­
in such converters, it is imperative that the SR MOSFET be
tion could possibly compromise light-load efficiency and
turned off as soon as the primary-side switch turns on. This
no-load power consumption. The major contributors to
prevents reverse conduction and limits additional power
loss at light or no load are SR-MOSFET switching and SR
losses and device stresses. Instead of waiting for the VTHOFF
controller-IC bias. The Green Rectifier overcomes these
threshold detection, the synchronizing function in the
issues with (1) an automatic light-load-detection circuit
Green Rectifier detects the primary-side turn-on transition
that disables gate switching of the SR MOSFET when its
and turns off the SR MOSFET. Figure 3 illustrates how the
conduction time falls below a certain threshold, and (2) an
SR-gate turn-off transition is now controlled by a synchroEN function to put the IC in sleep mode and disable
nizing signal from the primary side and not by VDS sensing.
19
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Figure 4. Full-load waveforms from PMP4305
Primary-Side
MOSFET, VDS
(200 V/div)
1
3
SR, VDS
(500 mV/div )
SR Current
(10 A/div )
4
Time (2 µs/div)
Figure 5. Comparison of system efficiency with Schottky
diode versus synchronous rectifier (SR)
85
115-V SR
84
83
230-V SR
82
Efficiency (%)
quiescent power loss. The light-load-detection
circuit compares the SR conduction time and the
programmed minimum ON time (MOT) for every
switching cycle. When the load decreases, the secondary conduction time becomes shorter than the
MOT, and the next SR gate pulse is disabled.
Further reduction in no-load power can be achieved
by using the EN function of the controller IC. A
simple averaging circuit on the MOSFET drain voltage can be used to put the IC in sleep mode at a
no-load condition that limits the IC’s bias-current
consumption to 100 µA. An additional 10 mW of
no-load power consumption can be saved with this
approach. The last gasp in improving no-load performance is to add a low-current Schottky diode in
parallel with the SR MOSFET.
As an example, a USB charger with a 3-A current
rating was designed using two controller chipsets,
TI’s UCC28610 and UCC24610, for a tablet-PC end
application. The reference design for this charger,
the PMP4305, can be seen at the Web site listed at
the end of this article. The UCC24610 is good for
applications with a 5-V flyback switch-mode power
supply and can operate within the specified USB
voltage range of 4.75 to 5.25 V. Hence, this SR
controller was biased directly from the converter
output, eliminating the need for an auxiliary winding on the main power transformer. The controller
also allowed external programming of two blanking
timers to prevent SR false triggering from VDS
ringing sensed during the turn-on and turn-off
transitions. Figure 4 shows typical power-stage
waveforms of the PMP4305 at full load. The IC control scheme was not affected by the severe ringing
on the VDS signal at turn-on because the programmable MOT timer disabled the VTHOFF comparator
during this period.
A comparison of the efficiency of SR-MOSFET
versus Schottky-diode output rectification at 115and 230-V AC line conditions is shown in Figure 5.
Implementing synchronous rectification enables
over 80% efficiency from full load down to about
25% of full load. Additionally, for this load range,
an SR configuration can achieve a three- to fivepoint improvement in efficiency over Schottkydiode rectification.
Texas Instruments Incorporated
81
115-V Schottky Diode
80
79
230-V Schottky Diode
78
77
76
75
0.5
1
1.5
2
2.5
3
3.5
Load Current (A)
Conclusion
Related Web sites
USB power charging for consumer devices is gaining traction. A universal standard for 10- to 25-W chargers with
USB outlets that power multiple devices eliminates the
need for a new wall charger with every new gadget purchase. High-efficiency AC/DC converters are needed to
satisfy the push towards high-density, small-form-factor
adapters. Devices like the UCC24610 Green Rectifier can
help improve AC/DC converter efficiency and enable the
high-density USB-charger designs.
power.ti.com
www.ti.com/product/UCC24610
www.ti.com/product/UCC28610
Reference design for tablet-PC charger:
www.ti.com/tool/PMP4305
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Amplifiers: Op Amps
Texas Instruments Incorporated
Measuring op amp settling time by using
sample-and-hold technique
By Roger Liang, Systems Engineer,
and Xavier Ramus, System Engineer, High-Speed Amplifiers
Introduction
Figure 1. Flat-bottom pulse generator (FBPG)
Modern high-speed operational amplifiers
(op amps) are designed with settling time in the
range of nanoseconds. This time is so brief that
+
5V
measuring it within a reasonable error band
– Vsupply
Pulse Generator
Output
R supply
pre­sents a challenging task not only on autoR generator
matic test equipment (ATE) but also on the
VOUT
bench. In today’s op amp datasheets, settling
50 Ω
D1
D2
time is usually given as a simulated value due to
50 Ω
R3
Vgenerator
the cost and challenges associated with implementing addi­tional hardware to test it on the
bench. Traditional high-speed oscilloscopes have
only a 10-bit analog-to-digital converter, which
limits any measurement resolution to a maximum of 0.1%.
This article describes a new methodology that
can be used to clean up the low-voltage level of the generhas proven to be effective in making these measurements.
ated signal. The FBPG clamps the falling voltage to ground
Detailed is a relatively inexpen­sive and simple way to meaat the cost of a bigger overshoot. This gives test engineers
sure settling time that bases accuracy and precision on the
some control over trade-offs in the test setup. Similarly, a
relative speed of the waveform generator and the sampleflat-top pulse generator can be used to clean up the highand-hold circuit.
voltage level.
Figure 1 illustrates two back-to-back high-speed Zener
Step input for the device under test
diodes, each with a separate, adjustable power supply. As
In this article, settling time refers to the time that elapses
a rule of thumb, the setup should be started as follows:
from the application of an ideal step input to the time at
The Rsupply should be adjusted to obtain 5 V at the D1/D2
which the device under test (DUT) enters and remains
connection, and the Vgenerator output voltage should be
within a specified error band that is symmetrical about
adjusted to swing between a 2-V high and a –5-V low. This
the final value. An ideal step input is easily generated in
should bias the output at 2 VPP and the low-voltage level
simulation, but there are no instruments that can produce
at 0 V. When Vgenerator is high, D2 is turned off and D1 is
an ideal step waveform in any lab setting. Even under
turned on. During this time, the output voltage becomes a
ideal conditions, the output of overdamped and critically
function of D1’s forward voltage (Vsupply) and of the amount
damped instruments would take a few RC time constants
of current that flows through Rsupply and D1. When the
to monotonically settle to within tenths of a percent of the
input is low, D1 is turned off and D2 is turned on. During
final value.
this time, the output voltage swings to ground, and its slew
For underdamped systems, a step waveform can overrate is proportional to the amount of current that flows into
shoot the final value, and ringing may occur. In practice,
the matching resistor, R3. The transient response is a func­
even critically damped systems have underdamped
tion of the diode’s capacitance, reverse recovery time, and
behaviors. Generally, the faster the fall time of the step
forward recovery voltage.
waveform, the more overshoot and ringing one observes.
Because of the diodes’ nonlinearity, it does not make
This non-ideality is then propagated into the measured
sense to derive rigorous equations to determine the DC
output wave­form of the DUT. Fortunately, with the aid of
levels and transient response of the FBPG. Instead, the
computer-logged records of input and output data, the
equations can be simulated in software such as TINA-TI™
output can be normalized by lining up the two and subfrom Texas Instruments. Assuming that the pulse generatracting the input from the output (with the DUT in a
tor is very fast, the fall time and overshoot of the output
non-inverting unity-gain configuration).
waveform become functions of the diodes’ speed and
recovery time, as well as of the parasitic capacitance and
Flat-bottom pulse generator
inductance of the printed circuit board (PCB) on which
When the falling edge of a waveform generator is used as
the FBPG is built. In other words, the designer should pick
the input to the DUT, a flat-bottom pulse generator (FBPG)
the fastest, most robust diode and follow guidelines for
21
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1Q 2012
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Amplifiers: Op Amps
Texas Instruments Incorporated
good PCB layout when using FBPG for generating high-speed waveforms.
Figure 2. Sample-and-hold (S/H) circuit
Sample-and-hold methodology for
measuring settling time
Hold Control
For the example presented here, the TI
100 Ω
OPA615 (see Figure 2) was chosen to imple­
ment the sample-and-hold (S/H) functions of
OPA615
7
settling-time measurement because of its wide­
12
150 Ω 10
VIN
band operational transconductance ampli­fier
+
100
Ω
4
(OTA), which is optimized for low input-bias
OTA
SOTA
11
3
50
Ω
–
current, and its fast and precise sampling OTA
CHOLD
22 pF
(SOTA), which also serves as a comparator
2
VOUT
and buffer. The analog input (VIN) is sampled
50 Ω
by the SOTA onto the capac­itor (CHOLD) when
the Hold-Control pin is high. The voltage on
300 Ω
CHOLD is held and reflected at the output
300 Ω
(VOUT) when the Hold-Control pin swings
low. During sampling, the voltage on CHOLD is
adjusted to the real-time voltage level on the
input. If there is a large voltage difference
between the input and CHOLD and there are
arbitrary waveform generator should work if it has a marker
only a few nanoseconds of sampling time, then fast slewoutput that synchronizes with the output, thus creating a
ing is required. During holding, the voltage on CHOLD
very convenient Hold-Control signal. The example test
invariably charges/discharges due to its leakage current
used a Tektronix AWG610, which has a sampling time of
and any biasing current needed for the OTA. The current2.6 Gbps and a minimum marker step of 100 ps, making it
feedback loop ensures that the SOTA slews fast enough to
fast enough for most measurements of high-speed op amp
capture the correct voltage level at VIN.
settling time.
Figure 3 shows an example of a S/H output of a 100-kHz
Figure 4 shows how to capture points on a curve by
sine-wave input. A waveform generator can be used to pro­
using a S/H circuit with the marker as the Hold-Control
duce the input step function for the DUT and to synchrosig­nal. The designer can capture sequential points on the
nize a S/H signal to that step function. A S/H circuit can be
curve by moving the marker position. After all the points
used to capture points on the DUT’s output waveform. Any
Figure 4. Example of AWG610 output
and marker synchronization
5
4
3
2
Output Voltage, VOUT ( V )
1
+2.5
0
Hold-Control Signal ( V)
Figure 3. Example 1-MHz S/H output of a 100-kHz sine wave
2.0 V
Sampled Waveform
( VIN )
1.0 V
0.2 V
0V
2.5 V
Hold Control
Marker
Position 1
+1.5
+0.5
0V
–0.5
Hold Control
Marker
Position 2
–1.5
2.5 V
–2.5
Time (1 µs/div)
0V
Time
22
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Limitations and challenges
Figure 5. Test setup for measuring settling time
Waveform
Generator
(AWG610)
DUT
(OPA656)
Signal
Output
DMM 2
DUT
Output
Value
S/H Circuit 2
(OPA615)
IN
OUT
Hold Control
Marker
Output
DMM 1
DUT
Input
Value
S/H Circuit 1
(OPA615)
IN
OUT
Hold Control
Figure 6. Step waveforms of op amp’s input
and output
120
Normalized DUT Step Response (%)
have been recorded, the S/H curve can be plotted and
analyzed. Programming the waveform generator with
software like MATLAB® or LabVIEW™ makes changing
the marker and recording the results very simple. With
the marker set in position 1, the S/H circuit tracks the
VIN voltage level when the marker is high and holds that
value when the marker is low. At position 1, the output is
held at 1 V. At position 2, the output is held at 0.2 V.
Figure 5 shows the test setup for measuring settling
time where the AWG610 and OPA615 were used for the
S/H functions. All signal lines were matched at 50 W. The
output of the waveform generator was used as the test
signal with two S/H circuits: One measured the input of
the DUT (OPA656), and the other measured the DUT
output. Digital multimeters (DMMs) were used to record
the held values.
As an example of this method, take measuring a
settling time of up to 100 ns. Assume that the waveform
generator is programmed to continually output a square
wave with a duty cycle of 50% and a period of 200 ns.
The marker is initially set at the beginning of the falling
edge of the waveform generator’s output. The generator
runs continually (executes many cycles of sampling and
holding), and the S/H circuit integrates its output voltage
to a steady DC value. This value is then recorded by the
DMM, and the test engineer moves the marker to the
next position, repeating this cycle until data for 100 ns
has been recorded.
Figure 6 shows the plotted waveforms that resulted
when the test setup in Figure 5 was used. To obtain a
settling-time error waveform, the DC error was offset,
and the output was normalized to the input. The result
is shown in Figure 7.
OPA656 DUT
Input
Output
100
RLoad = 100 Ω
80
CLoad = 1.2 pF
60
40
20
0
There are some limitations to the setup described here
that should be kept in mind. When in doubt, the designer
should always use the following equation:
0
20
40
60
80
100
Time (ns)
120
140
160
I = CHOLD × dv/dt
For example, CHOLD should be no less than 50 pF under
the following conditions: The biasing current of the OTA
is 0.5 µA; an error of less than 0.1% of a 1-VPP signal is to
be achieved; and the duration to be measured is 100 ns.
Figure 7. Op amp’s normalized settling error
Normalized Settling-Time Error (%)
For this equation, the size of the initial CHOLD should be
chosen based on three factors:
1. During the holding time, the OTA biasing current will
flow in or out of the capacitor, thus affecting the accuracy of the voltage held.
2. Since a voltage droop will occur on the capacitor due
to the biasing current, a delta voltage should be chosen
based on the percentage of error within which the
measurement should stay.
3. Delta time is the duration for which the sampled voltage is held and should be no longer than the planned
settling time to be measured.
0.2
0
–0.2
–0.4
–0.6
–0.8
RLoad = 100 Ω
CLoad = 1.2 pF
Output Step = 2 V
–1.0
–1.2
–1.4
0
20
40
60
Time (ns)
80
100
23
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Figure 8. Charge leakage on sampling capacitor
VIN
2.5 V
Hold
Control
VOUT
VError
2.5 V
Hold
Sample
Conclusion
Other considerations
DUT Sampled Output (mV)
Numerous techniques exist for measuring settling time.
The duration of the sampling time could greatly affect the
This article has introduced a simple yet accurate techresult of the measurement. During holding, the voltage on
nique that uses a relatively fast waveform generator and a
the sampling capacitor invariably strays from the supposed
S/H circuit. Knowing the limitations of this method, the
DC value because the OTA demands a biasing current. This
user should be able to adjust any measurement parameters
voltage is then readjusted back to the expected DC value
necessary to obtain the best results for a given settlingduring sampling. The DMM that is reading the output of
time range and expected accuracy.
the S/H circuit is thus essentially taking an average value
of this triangle waveform. This phenomenon is shown in
Related Web sites
Figure 8. To reduce this error, the holding time should be
amplifier.ti.com
minimized and the capacitor size maximized. It should be
www.ti.com/product/OPA615
kept in mind that the bigger the sampling capacitor is, the
www.ti.com/product/OPA656
more S/H cycles (integration time) will be needed for the
www.ti.com/tinati-ca
charges to integrate to a steady DC value.
Of course, increasing the sampling time
does not mitigate the leakage problem. A
Figure 9. Settling time measured with different
minimum sampling time should be used that
sampling times
still guarantees the SOTA’s holding-time delay
and ensures enough time for the sampling
60
capacitor’s charge/discharge while it is trackSampling Times
ing the S/H circuit’s input. Figure 9 shows the
40
12 ns
6 ns
recorded values of the op amp’s settling time
20 ns
10 ns
20
when different sampling times were used with
the same holding and integration times. The
0
results were measured against the same wave–20
form taken from a 6-GHz, 10-bit oscilloscope,
which showed a maximum overshoot of
–40
–60 mV. The measurement using a 20-ns sam–60
pling time matched that from the oscilloscope,
but at the cost of applying a significant filter
–80
over the result. Conversely, the measurement
–100
using 6 ns applied a smaller filter but produced
a bigger overshoot, which is an artifact of the
–120
measurement.
0
1
2
3
4
5
6
7
8
9
10
Settling Time (ns)
24
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Analog Applications Journal
Index of Articles
Texas Instruments Incorporated
Index of Articles
Title
Issue
Data Acquisition
Page
Aspects of data acquisition system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 1999 . . . . . . . 1
Low-power data acquisition sub-system using the TI TLV1572 . . . . . . . . . . . . . . . . . . . . . . . . . . . August 1999 . . . . . . . 4
Evaluating operational amplifiers as input amplifiers for A-to-D converters . . . . . . . . . . . . . . . . . August 1999 . . . . . . . 7
Precision voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 1999 . . . . 1
Techniques for sampling high-speed graphics with lower-speed A/D converters . . . . . . . . . . . . . November 1999 . . . . 5
A methodology of interfacing serial A-to-D converters to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2000 . . . . . 1
The operation of the SAR-ADC based on charge redistribution . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2000 . . . . 10
The design and performance of a precision voltage reference circuit for 14-bit and
16-bit A-to-D and D-to-A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . May 2000 . . . . . . . . . 1
Introduction to phase-locked loop system modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . May 2000 . . . . . . . . . 5
New DSP development environment includes data converter plug-ins . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . . 1
Higher data throughput for DSP analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . . 5
Efficiently interfacing serial data converters to high-speed DSPs . . . . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . 10
Smallest DSP-compatible ADC provides simplest DSP interface . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . . 1
Hardware auto-identification and software auto-configuration for the
TLV320AIC10 DSP Codec — a “plug-and-play” algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . . 8
Using quad and octal ADCs in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . 15
Building a simple data acquisition system using the TMS320C31 DSP . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . . 1
Using SPI synchronous communication with data converters — interfacing the
MSP430F149 and TLV5616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . . 7
A/D and D/A conversion of PC graphics and component video signals, Part 1: Hardware . . . . . February 2001 . . . . 11
A/D and D/A conversion of PC graphics and component video signals, Part 2: Software
and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . . . 5
Intelligent sensor system maximizes battery life: Interfacing the MSP430F123
Flash MCU, ADS7822, and TPS60311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . . . 5
SHDSL AFE1230 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . . 5
Synchronizing non-FIFO variations of the THS1206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 12
Adjusting the A/D voltage reference to provide gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2002 . . . . . . . . . . 5
MSC1210 debugging strategies for high-precision smart sensors . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2002 . . . . . . . . . . 7
Using direct data transfer to maximize data acquisition throughput . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2002 . . . . . . . . . 14
Interfacing op amps and analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2002 . . . . . . . . . . 5
ADS82x ADC with non-uniform sampling clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2003 . . . . . . . . . . 5
Calculating noise figure and third-order intercept in ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2003 . . . . . . . . . 11
Evaluation criteria for ADSL analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2003 . . . . . . . . . 16
Two-channel, 500-kSPS operation of the ADS8361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . . . 5
ADS809 analog-to-digital converter with large input pulse signal . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . . . 8
Streamlining the mixed-signal path with the signal-chain-on-chip MSP430F169 . . . . . . . . . . . . . 3Q, 2004 . . . . . . . . . . 5
Supply voltage measurement and ADC PSRR improvement in MSC12xx devices . . . . . . . . . . . . 1Q, 2005 . . . . . . . . . . 5
14-bit, 125-MSPS ADS5500 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2005 . . . . . . . . . 13
Clocking high-speed data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2005 . . . . . . . . . 20
Implementation of 12-bit delta-sigma DAC with MSC12xx controller . . . . . . . . . . . . . . . . . . . . . . 1Q, 2005 . . . . . . . . . 27
Using resistive touch screens for human/machine interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2005 . . . . . . . . . . 5
Simple DSP interface for ADS784x/834x ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2005 . . . . . . . . . 10
Operating multiple oversampling data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2005 . . . . . . . . . . 5
Low-power, high-intercept interface to the ADS5424 14-bit, 105-MSPS converter for
undersampling applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2005 . . . . . . . . . 10
Understanding and comparing datasheets for high-speed ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2006 . . . . . . . . . . 5
Matching the noise performance of the operational amplifier to the ADC . . . . . . . . . . . . . . . . . . . 2Q, 2006 . . . . . . . . . . 5
Using the ADS8361 with the MSP430™ USI port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2006 . . . . . . . . . . 5
Clamp function of high-speed ADC THS1041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2006 . . . . . . . . . . 5
Conversion latency in delta-sigma converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2007 . . . . . . . . . . 5
Calibration in touch-screen systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2007 . . . . . . . . . . 5
Using a touch-screen controller’s auxiliary inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2007 . . . . . . . . . . 5
Lit. No.
SLYT191
SLYT192
SLYT193
SLYT183
SLYT184
SLYT175
SLYT176
SLYT168
SLYT169
SLYT158
SLYT159
SLYT160
SLYT148
SLYT149
SLYT150
SLYT136
SLYT137
SLYT138
SLYT129
SLYT123
SLYT114
SLYT115
SLYT109
SLYT110
SLYT111
SLYT104
SLYT089
SLYT090
SLYT091
SLYT082
SLYT083
SLYT078
SLYT073
SLYT074
SLYT075
SLYT076
SLYT209A
SLYT210
SLYT222
SLYT223
SLYT231
SLYT237
SLYT244
SLYT253
SLYT264
SLYT277
SLYT283
25
Analog Applications Journal
1Q 2012
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High-Performance Analog Products
Index of Articles
Texas Instruments Incorporated
Title
Issue
Page
Data Acquisition (Continued)
Understanding the pen-interrupt (PENIRQ) operation of touch-screen controllers . . . . . . . . . . . 2Q, 2008 . . . . . . . . . . 5
A DAC for all precision occasions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2008 . . . . . . . . . . 5
Stop-band limitations of the Sallen-Key low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2008 . . . . . . . . . . 5
How the voltage reference affects ADC performance, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2009 . . . . . . . . . . 5
Impact of sampling-clock spurs on ADC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2009 . . . . . . . . . . 5
How the voltage reference affects ADC performance, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2009 . . . . . . . . . 13
How the voltage reference affects ADC performance, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2009 . . . . . . . . . . 5
How digital filters affect analog audio-signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2010 . . . . . . . . . . 5
Clock jitter analyzed in the time domain, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2010 . . . . . . . . . . 5
Clock jitter analyzed in the time domain, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2010 . . . . . . . . . . 5
The IBIS model: A conduit into signal-integrity analysis, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2010 . . . . . . . . . 11
The IBIS model, Part 2: Determining the total quality of an IBIS model . . . . . . . . . . . . . . . . . . . . 1Q, 2011 . . . . . . . . . . 5
The IBIS model, Part 3: Using IBIS models to investigate signal-integrity issues . . . . . . . . . . . . . 2Q, 2011 . . . . . . . . . . 5
Clock jitter analyzed in the time domain, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2011 . . . . . . . . . . 5
How delta-sigma ADCs work, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2011 . . . . . . . . . 13
How delta-sigma ADCs work, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2011 . . . . . . . . . . 5
Power Management
Stability analysis of low-dropout linear regulators with a PMOS pass element . . . . . . . . . . . . . . . August 1999 . . . . . . 10
Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . . August 1999 . . . . . . 13
Migrating from the TI TL770x to the TI TLC770x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 1999 . . . . . . 14
TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 1999 . . . . 8
Synchronous buck regulator design using the TI TPS5211 high-frequency
hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 1999 . . . 10
Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . . November 1999 . . . 14
Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . . February 2000 . . . . 12
Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . . February 2000 . . . . 20
Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump . . . . May 2000 . . . . . . . . 11
Low-cost, minimum-size solution for powering future-generation Celeron™-type
processors with peak currents up to 26 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . May 2000 . . . . . . . . 14
Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . . August 2000 . . . . . . 16
Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . 22
Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . 19
Comparison of different power supplies for portable DSP solutions
working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . 24
Optimal design for an interleaved synchronous buck converter under high-slew-rate,
load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . 15
–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . 20
Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . . . 9
Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . . 15
Power control design key to realizing InfiniBandSM benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2002 . . . . . . . . . 10
Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . . 1Q, 2002 . . . . . . . . . 12
Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2002 . . . . . . . . . 18
SWIFT™ Designer power supply design program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 15
Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 23
Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 28
Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . . 4Q, 2002 . . . . . . . . . . 8
Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . . 4Q, 2002 . . . . . . . . . 12
Understanding piezoelectric transformers in CCFL backlight applications . . . . . . . . . . . . . . . . . . 4Q, 2002 . . . . . . . . . 18
Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . 1Q, 2003 . . . . . . . . . . 5
Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2003 . . . . . . . . . . 7
Auto-Track™ voltage sequencing simplifies simultaneous power-up and power-down . . . . . . . . 3Q, 2003 . . . . . . . . . . 5
Soft-start circuits for LDO linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2003 . . . . . . . . . 10
UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1 . . . . . . . . . . . . . . . . . 3Q, 2003 . . . . . . . . . 13
UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2 . . . . . . . . . . . . . . . . . 4Q, 2003 . . . . . . . . . 21
LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . . 14
Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2004 . . . . . . . . . 11
Lit. No.
SLYT292
SLYT300
SLYT306
SLYT331
SLYT338
SLYT339
SLYT355
SLYT375
SLYT379
SLYT389
SLYT390
SLYT400
SLYT413
SLYT422
SLYT423
SLYT438
SLYT194
SLYT195
SLYT196
SLYT185
SLYT186
SLYT187
SLYT177
SLYT178
SLYT170
SLYT171
SLYT161
SLYT162
SLYT151
SLYT152
SLYT139
SLYT140
SLYT130
SLYT131
SLYT124
SLYT125
SLYT126
SLYT116
SLYT117
SLYT118
SLYT105
SLYT106
SLYT107
SLYT100
SLYT101
SLYT095
SLYT096
SLYT097
SLYT092
SLYT084
SLYT079
26
High-Performance Analog Products
www.ti.com/aaj
1Q 2012
Analog Applications Journal
Index of Articles
Texas Instruments Incorporated
Title
Issue
Power Management (Continued)
Page
A better bootstrap/bias supply circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2005 . . . . . . . . . 33
Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2005 . . . . . . . . . . 5
Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2005 . . . . . . . . . . 8
Miniature solutions for voltage isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2005 . . . . . . . . . 13
New power modules improve surface-mount manufacturability . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2005 . . . . . . . . . 18
Li-ion switching charger integrates power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2005 . . . . . . . . . 19
TLC5940 dot correction compensates for variations in LED brightness . . . . . . . . . . . . . . . . . . . . 4Q, 2005 . . . . . . . . . 21
Powering today’s multi-rail FPGAs and DSPs, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2006 . . . . . . . . . . 9
TPS79918 RF LDO supports migration to StrataFlash® Embedded Memory (P30) . . . . . . . . . . . 1Q, 2006 . . . . . . . . . 14
Practical considerations when designing a power supply with the TPS6211x . . . . . . . . . . . . . . . . 1Q, 2006 . . . . . . . . . 17
TLC5940 PWM dimming provides superior color quality in LED video displays . . . . . . . . . . . . . . 2Q, 2006 . . . . . . . . . 10
Wide-input dc/dc modules offer maximum design flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2006 . . . . . . . . . 13
Powering today’s multi-rail FPGAs and DSPs, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2006 . . . . . . . . . 18
TPS61059 powers white-light LED as photoflash or movie light . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . . 8
TPS65552A powers portable photoflash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2006 . . . . . . . . . 10
Single-chip bq2403x power-path manager charges battery while powering system . . . . . . . . . . . . 3Q, 2006 . . . . . . . . . 12
Complete battery-pack design for one- or two-cell portable applications . . . . . . . . . . . . . . . . . . . 3Q, 2006 . . . . . . . . . 14
A 3-A, 1.2-VOUT linear regulator with 80% efficiency and PLOST < 1 W . . . . . . . . . . . . . . . . . . . . . 4Q, 2006 . . . . . . . . . 10
bq25012 single-chip, Li-ion charger and dc/dc converter for Bluetooth® headsets . . . . . . . . . . . 4Q, 2006 . . . . . . . . . 13
Fully integrated TPS6300x buck-boost converter extends Li-ion battery life . . . . . . . . . . . . . . . . 4Q, 2006 . . . . . . . . . 15
Selecting the correct IC for power-supply applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2007 . . . . . . . . . . 5
LDO white-LED driver TPS7510x provides incredibly small solution size . . . . . . . . . . . . . . . . . . . 1Q, 2007 . . . . . . . . . . 9
Power management for processor core voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . 11
Enhanced-safety, linear Li-ion battery charger with thermal regulation and
input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2007 . . . . . . . . . . 8
Current balancing in four-pair, high-power PoE applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2007 . . . . . . . . . 11
Power-management solutions for telecom systems improve performance, cost, and size . . . . . . 3Q, 2007 . . . . . . . . . 10
TPS6108x: A boost converter with extreme versatility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2007 . . . . . . . . . 14
Get low-noise, low-ripple, high-PSRR power with the TPS717xx . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2007 . . . . . . . . . 17
Simultaneous power-down sequencing with the TPS74x01 family of linear regulators . . . . . . . . 3Q, 2007 . . . . . . . . . 20
Driving a WLED does not always require 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2007 . . . . . . . . . . 9
Host-side gas-gauge-system design considerations for single-cell handheld applications . . . . . . 4Q, 2007 . . . . . . . . . 12
Using a buck converter in an inverting buck-boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2007 . . . . . . . . . 16
Understanding output voltage limitations of DC/DC buck converters . . . . . . . . . . . . . . . . . . . . . . 2Q, 2008 . . . . . . . . . 11
Battery-charger front-end IC improves charging-system safety . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2008 . . . . . . . . . 14
New current-mode PWM controllers support boost, flyback, SEPIC, and
LED-driver applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2008 . . . . . . . . . . 9
Getting the most battery life from portable systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2008 . . . . . . . . . . 8
Compensating and measuring the control loop of a high-power LED driver . . . . . . . . . . . . . . . . . 4Q, 2008 . . . . . . . . . 14
Designing DC/DC converters based on SEPIC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2008 . . . . . . . . . 18
Paralleling power modules for high-current applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2009 . . . . . . . . . . 5
Improving battery safety, charging, and fuel gauging in portable media applications . . . . . . . . . . 1Q, 2009 . . . . . . . . . . 9
Cell balancing buys extra run time and battery life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2009 . . . . . . . . . 14
Using a portable-power boost converter in an isolated flyback application . . . . . . . . . . . . . . . . . . 1Q, 2009 . . . . . . . . . 19
Taming linear-regulator inrush currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2009 . . . . . . . . . . 9
Designing a linear Li-Ion battery charger with power-path control . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2009 . . . . . . . . . 12
Selecting the right charge-management solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2009 . . . . . . . . . 18
Reducing radiated EMI in WLED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . . 17
Using power solutions to extend battery life in MSP430™ applications . . . . . . . . . . . . . . . . . . . . 4Q, 2009 . . . . . . . . . 10
Designing a multichemistry battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2009 . . . . . . . . . 13
Efficiency of synchronous versus nonsynchronous buck converters . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2009 . . . . . . . . . 15
Fuel-gauging considerations in battery backup storage systems . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2010 . . . . . . . . . . 5
Li-ion battery-charger solutions for JEITA compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2010 . . . . . . . . . . 8
Power-supply design for high-speed ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2010 . . . . . . . . . 12
Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2010 . . . . . . . . . 12
Designing DC/DC converters based on ZETA topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2010 . . . . . . . . . 16
Coupled inductors broaden DC/DC converter usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2010 . . . . . . . . . 10
Lit. No.
SLYT077
SLYT201
SLYT202
SLYT211
SLYT212
SLYT224
SLYT225
SLYT232
SLYT233
SLYT234
SLYT238
SLYT239
SLYT240
SLYT245
SLYT246
SLYT247
SLYT248
SLYT254
SLYT255
SLYT256
SLYT259
SLYT260
SLYT261
SLYT269
SLYT270
SLYT278
SLYT279
SLYT280
SLYT281
SLYT284
SLYT285
SLYT286
SLYT293
SLYT294
SLYT302
SLYT307
SLYT308
SLYT309
SLYT320
SLYT321
SLYT322
SLYT323
SLYT332
SLYT333
SLYT334
SLYT340
SLYT356
SLYT357
SLYT358
SLYT364
SLYT365
SLYT366
SLYT371
SLYT372
SLYT380
27
Analog Applications Journal
1Q 2012
www.ti.com/aaj
High-Performance Analog Products
Index of Articles
Texas Instruments Incorporated
Title
Issue
Page
Power Management (Continued)
Computing power going “Platinum” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2010 . . . . . . . . . 13
A low-cost, non-isolated AC/DC buck converter with no transformer . . . . . . . . . . . . . . . . . . . . . . 4Q, 2010 . . . . . . . . . 16
Save power with a soft Zener clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2010 . . . . . . . . . 19
An introduction to the Wireless Power Consortium standard and TI’s compliant solutions . . . . . 1Q, 2011 . . . . . . . . . 10
Fine-tuning TI’s Impedance Track™ battery fuel gauge with LiFePO4 cells in
shallow-discharge applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2011 . . . . . . . . . 13
Implementation of microprocessor-controlled, wide-input-voltage, SMBus smart
battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2011 . . . . . . . . . 11
Benefits of a coupled-inductor SEPIC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2011 . . . . . . . . . 14
IQ: What it is, what it isn’t, and how to use it . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2011 . . . . . . . . . 18
Backlighting the tablet PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2011 . . . . . . . . . 23
Challenges of designing high-frequency, high-input-voltage DC/DC converters . . . . . . . . . . . . . . 2Q, 2011 . . . . . . . . . 28
A boost-topology battery charger powered from a solar panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2011 . . . . . . . . . 17
Solar charging solution provides narrow-voltage DC/DC system bus for
multicell-battery applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2011 . . . . . . . . . . 8
Solar lantern with dimming achieves 92% efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2011 . . . . . . . . . 12
Turbo-boost charger supports CPU turbo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2012 . . . . . . . . . . 5
Benefits of a multiphase buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2012 . . . . . . . . . . 8
Downslope compensation for buck converters when the duty cycle exceeds 50% . . . . . . . . . . . . 1Q, 2012 . . . . . . . . . 14
High-efficiency AC adapters for USB charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2012 . . . . . . . . . 18
Interface (Data Transmission)
TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS) . . . . . . . . . . . . . . . August 1999 . . . . . .
Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 1999 . . .
Skew definition and jitter analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2000 . . . .
LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2000 . . . .
LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . May 2000 . . . . . . . .
Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . .
A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . .
The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . .
The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . .
Power consumption of LVPECL and LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2002 . . . . . . . . .
Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . .
The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . .
Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2004 . . . . . . . . .
Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2005 . . . . . . . . .
Device spacing on RS-485 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2006 . . . . . . . . .
Improved CAN network security with TI’s SN65HVD1050 transceiver . . . . . . . . . . . . . . . . . . . . . 3Q, 2006 . . . . . . . . .
Detection of RS-485 signal loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2006 . . . . . . . . .
Enabling high-speed USB OTG functionality on TI DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2007 . . . . . . . . .
When good grounds turn bad—isolate! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2008 . . . . . . . . .
Cascading of input serializers boosts channel density for digital inputs . . . . . . . . . . . . . . . . . . . . . 3Q, 2008 . . . . . . . . .
RS-485: Passive failsafe for an idle bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2009 . . . . . . . . .
Message priority inversion on a CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2009 . . . . . . . . .
Designing with digital isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2009 . . . . . . . . .
Magnetic-field immunity of digital capacitive isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . .
Interfacing high-voltage applications to low-power controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2010 . . . . . . . . .
Designing an isolated I2C Bus® interface by using digital isolators . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2011 . . . . . . . . .
Isolated RS-485 transceivers support DMX512 stage lighting and special-effects applications . . 3Q, 2011 . . . . . . . . .
Industrial data-acquisition interfaces with digital isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2011 . . . . . . . . .
Extending the SPI bus for long-distance communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2011 . . . . . . . . .
16
17
29
33
19
30
30
35
19
23
18
21
16
11
25
17
18
18
11
16
22
25
21
19
20
17
21
24
16
Lit. No.
SLYT382
SLYT391
SLYT392
SLYT401
SLYT402
SLYT410
SLYT411
SLYT412
SLYT414
SLYT415
SLYT424
SLYT439
SLYT440
SLYT448
SLYT449
SLYT450
SLYT451
SLYT197
SLYT188
SLYT179
SLYT180
SLYT172
SLYT163
SLYT153
SLYT154
SLYT132
SLYT127
SLYT085
SLYT086
SLYT080
SLYT203
SLYT241
SLYT249
SLYT257
SLYT271
SLYT298
SLYT301
SLYT324
SLYT325
SLYT335
SLYT381
SLYT393
SLYT403
SLYT425
SLYT426
SLYT441
28
High-Performance Analog Products
www.ti.com/aaj
1Q 2012
Analog Applications Journal
Index of Articles
Texas Instruments Incorporated
Title
Issue
Amplifiers: Audio
Page
Reducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 1999 . . . . . .
Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . . August 1999 . . . . . .
PCB layout for the TPA005D1x and TPA032D0x Class-D APAs . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2000 . . . .
An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . .
1.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . .
Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . .
An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . .
An audio circuit collection, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . .
Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . .
Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2002 . . . . . . . . .
Precautions for connecting APA outputs to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2010 . . . . . . . . .
Lit. No.
19
24
39
39
23
27
41
34
40
26
22
SLYT198
SLYT199
SLYT182
SLYT155
SLYT141
SLYT142
SLYT145
SLYT134
SLYT135
SLYT128
SLYT373
Single-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 1999 . . . 20
Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 1999 . . . 23
Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2000 . . . . 36
Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . May 2000 . . . . . . . . 22
Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . May 2000 . . . . . . . . 26
Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . 33
Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . 38
The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . 42
Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . . August 2000 . . . . . . 48
Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . 44
Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . November 2000 . . . 48
Fully differential amplifiers applications: Line termination, driving high-speed ADCs,
and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . 32
Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . 38
Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . . 48
Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . July 2001 . . . . . . . . 25
Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 35
Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 42
Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . . 46
Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2002 . . . . . . . . . 21
FilterPro™ low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2002 . . . . . . . . . 24
Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2002 . . . . . . . . . 24
RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2003 . . . . . . . . . . 9
Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2003 . . . . . . . . . 14
Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2003 . . . . . . . . . 20
Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2003 . . . . . . . . . 23
Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2003 . . . . . . . . . 31
Op amp stability and input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . . 24
Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2004 . . . . . . . . . 28
Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2004 . . . . . . . . . 21
Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2005 . . . . . . . . . 19
So many amplifiers to choose from: Matching amplifiers to applications . . . . . . . . . . . . . . . . . . . . 3Q, 2005 . . . . . . . . . 24
Getting the most out of your instrumentation amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2005 . . . . . . . . . 25
High-speed notch filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2006 . . . . . . . . . 19
Low-cost current-shunt monitor IC revives moving-coil meter design . . . . . . . . . . . . . . . . . . . . . . 2Q, 2006 . . . . . . . . . 27
Accurately measuring ADC driving-circuit settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2007 . . . . . . . . . 14
New zero-drift amplifier has an IQ of 17 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2007 . . . . . . . . . 22
A new filter topology for analog high-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2008 . . . . . . . . . 18
Input impedance matching with fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2008 . . . . . . . . . 24
A dual-polarity, bidirectional current-shunt monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2008 . . . . . . . . . 29
Output impedance matching with fully differential operational amplifiers . . . . . . . . . . . . . . . . . . 1Q, 2009 . . . . . . . . . 29
Using fully differential op amps as attenuators, Part 1: Differential bipolar input signals . . . . . . 2Q, 2009 . . . . . . . . . 33
Using fully differential op amps as attenuators, Part 2: Single-ended bipolar input signals . . . . . 3Q, 2009 . . . . . . . . . 21
Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs . . . . . . . . . . . . . . . . . . . . 3Q, 2009 . . . . . . . . . 24
SLYT189
SLYT190
SLYT181
SLYT173
SLYT174
SLYT164
SLYT165
SLYT166
SLYT167
SLYT156
SLYT157
Amplifiers: Op Amps
SLYT143
SLYT144
SLYT146
SLYT133
SLYT119
SLYT120
SLYT121
SLYT112
SLYT113
SLYT108
SLYT102
SLYT103
SLYT098
SLYT099
SLYT094
SLYT087
SLYT088
SLYT081
SLYT204
SLYT213
SLYT226
SLYT235
SLYT242
SLYT262
SLYT272
SLYT299
SLYT310
SLYT311
SLYT326
SLYT336
SLYT341
SLYT342
29
Analog Applications Journal
1Q 2012
www.ti.com/aaj
High-Performance Analog Products
Index of Articles
Texas Instruments Incorporated
Title
Issue
Page
Amplifiers: Op Amps (Continued)
Using the infinite-gain, MFB filter topology in fully differential active filters . . . . . . . . . . . . . . . . 3Q, 2009 . . . . . . . . .
Using fully differential op amps as attenuators, Part 3: Single-ended unipolar input signals . . . . 4Q, 2009 . . . . . . . . .
Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs . . . . . . . . . . . . . . . . . . 4Q, 2009 . . . . . . . . .
Operational amplifier gain stability, Part 1: General system analysis . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2010 . . . . . . . . .
Signal conditioning for piezoelectric sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Q, 2010 . . . . . . . . .
Interfacing op amps to high-speed DACs, Part 3: Current-sourcing DACs simplified . . . . . . . . . . 1Q, 2010 . . . . . . . . .
Operational amplifier gain stability, Part 2: DC gain-error analysis . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2010 . . . . . . . . .
Operational amplifier gain stability, Part 3: AC gain-error analysis . . . . . . . . . . . . . . . . . . . . . . . . . 3Q, 2010 . . . . . . . . .
Using single-supply fully differential amplifiers with negative input voltages to drive ADCs . . . . 4Q, 2010 . . . . . . . . .
Converting single-ended video to differential video in single-supply systems . . . . . . . . . . . . . . . . 3Q, 2011 . . . . . . . . .
Measuring op amp settling time by using sample-and-hold technique . . . . . . . . . . . . . . . . . . . . . . 1Q, 2012 . . . . . . . . .
Lit. No.
33
19
23
20
24
32
24
23
26
29
21
SLYT343
SLYT359
SLYT360
SLYT367
SLYT369
SLYT368
SLYT374
SLYT383
SLYT394
SLYT427
SLYT452
Using the CC2430 and TIMAC for low-power wireless sensor applications: A powerconsumption study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2008 . . . . . . . . . 17
Selecting antennas for low-power wireless applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2008 . . . . . . . . . 20
SLYT295
SLYT296
Low-Power RF
General Interest
Synthesis and characterization of nickel manganite from different carboxylate
precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . February 2001 . . . .
Analog design tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2002 . . . . . . . . .
Spreadsheet modeling tool helps analyze power- and ground-plane voltage drops
to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Q, 2007 . . . . . . . . .
Analog linearization of resistance temperature detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Q, 2011 . . . . . . . . .
52
50
SLYT147
SLYT122
29
21
SLYT273
SLYT442
30
High-Performance Analog Products
www.ti.com/aaj
1Q 2012
Analog Applications Journal
Texas Instruments Incorporated
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SLYT447
© 2012 Texas Instruments Incorporated
31
Analog Applications Journal
1Q 2012
www.ti.com/aaj
High-Performance Analog Products
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