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Texas Instruments Measuring op-amp settling time by using sample-and-hold technique Application notes
Amplifiers: Op Amps
Texas Instruments Incorporated
Measuring op amp settling time by using
sample-and-hold technique
By Roger Liang, Systems Engineer,
and Xavier Ramus, System Engineer, High-Speed Amplifiers
Introduction
Figure 1. Flat-bottom pulse generator (FBPG)
Modern high-speed operational amplifiers
(op amps) are designed with settling time in the
range of nanoseconds. This time is so brief that
+
5V
measuring it within a reasonable error band
– Vsupply
Pulse Generator
Output
R supply
pre­sents a challenging task not only on autoR generator
matic test equipment (ATE) but also on the
VOUT
bench. In today’s op amp datasheets, settling
50 Ω
D1
D2
time is usually given as a simulated value due to
50 Ω
R3
Vgenerator
the cost and challenges associated with implementing addi­tional hardware to test it on the
bench. Traditional high-speed oscilloscopes have
only a 10-bit analog-to-digital converter, which
limits any measurement resolution to a maximum of 0.1%.
This article describes a new methodology that
can be used to clean up the low-voltage level of the generhas proven to be effective in making these measurements.
ated signal. The FBPG clamps the falling voltage to ground
Detailed is a relatively inexpen­sive and simple way to meaat the cost of a bigger overshoot. This gives test engineers
sure settling time that bases accuracy and precision on the
some control over trade-offs in the test setup. Similarly, a
relative speed of the waveform generator and the sampleflat-top pulse generator can be used to clean up the highand-hold circuit.
voltage level.
Figure 1 illustrates two back-to-back high-speed Zener
Step input for the device under test
diodes, each with a separate, adjustable power supply. As
In this article, settling time refers to the time that elapses
a rule of thumb, the setup should be started as follows:
from the application of an ideal step input to the time at
The Rsupply should be adjusted to obtain 5 V at the D1/D2
which the device under test (DUT) enters and remains
connection, and the Vgenerator output voltage should be
within a specified error band that is symmetrical about
adjusted to swing between a 2-V high and a –5-V low. This
the final value. An ideal step input is easily generated in
should bias the output at 2 VPP and the low-voltage level
simulation, but there are no instruments that can produce
at 0 V. When Vgenerator is high, D2 is turned off and D1 is
an ideal step waveform in any lab setting. Even under
turned on. During this time, the output voltage becomes a
ideal conditions, the output of overdamped and critically
function of D1’s forward voltage (Vsupply) and of the amount
damped instruments would take a few RC time constants
of current that flows through Rsupply and D1. When the
to monotonically settle to within tenths of a percent of the
input is low, D1 is turned off and D2 is turned on. During
final value.
this time, the output voltage swings to ground, and its slew
For underdamped systems, a step waveform can overrate is proportional to the amount of current that flows into
shoot the final value, and ringing may occur. In practice,
the matching resistor, R3. The transient response is a func­
even critically damped systems have underdamped
tion of the diode’s capacitance, reverse recovery time, and
behaviors. Generally, the faster the fall time of the step
forward recovery voltage.
waveform, the more overshoot and ringing one observes.
Because of the diodes’ nonlinearity, it does not make
This non-ideality is then propagated into the measured
sense to derive rigorous equations to determine the DC
output wave­form of the DUT. Fortunately, with the aid of
levels and transient response of the FBPG. Instead, the
computer-logged records of input and output data, the
equations can be simulated in software such as TINA-TI™
output can be normalized by lining up the two and subfrom Texas Instruments. Assuming that the pulse generatracting the input from the output (with the DUT in a
tor is very fast, the fall time and overshoot of the output
non-inverting unity-gain configuration).
waveform become functions of the diodes’ speed and
recovery time, as well as of the parasitic capacitance and
Flat-bottom pulse generator
inductance of the printed circuit board (PCB) on which
When the falling edge of a waveform generator is used as
the FBPG is built. In other words, the designer should pick
the input to the DUT, a flat-bottom pulse generator (FBPG)
the fastest, most robust diode and follow guidelines for
21
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good PCB layout when using FBPG for generating high-speed waveforms.
Figure 2. Sample-and-hold (S/H) circuit
Sample-and-hold methodology for
measuring settling time
Hold Control
For the example presented here, the TI
100 Ω
OPA615 (see Figure 2) was chosen to imple­
ment the sample-and-hold (S/H) functions of
OPA615
7
settling-time measurement because of its wide­
12
150 Ω 10
VIN
band operational transconductance ampli­fier
+
100
Ω
4
(OTA), which is optimized for low input-bias
OTA
SOTA
11
3
50
Ω
–
current, and its fast and precise sampling OTA
CHOLD
22 pF
(SOTA), which also serves as a comparator
2
VOUT
and buffer. The analog input (VIN) is sampled
50 Ω
by the SOTA onto the capac­itor (CHOLD) when
the Hold-Control pin is high. The voltage on
300 Ω
CHOLD is held and reflected at the output
300 Ω
(VOUT) when the Hold-Control pin swings
low. During sampling, the voltage on CHOLD is
adjusted to the real-time voltage level on the
input. If there is a large voltage difference
between the input and CHOLD and there are
arbitrary waveform generator should work if it has a marker
only a few nanoseconds of sampling time, then fast slewoutput that synchronizes with the output, thus creating a
ing is required. During holding, the voltage on CHOLD
very convenient Hold-Control signal. The example test
invariably charges/discharges due to its leakage current
used a Tektronix AWG610, which has a sampling time of
and any biasing current needed for the OTA. The current2.6 Gbps and a minimum marker step of 100 ps, making it
feedback loop ensures that the SOTA slews fast enough to
fast enough for most measurements of high-speed op amp
capture the correct voltage level at VIN.
settling time.
Figure 3 shows an example of a S/H output of a 100-kHz
Figure 4 shows how to capture points on a curve by
sine-wave input. A waveform generator can be used to pro­
using a S/H circuit with the marker as the Hold-Control
duce the input step function for the DUT and to synchrosig­nal. The designer can capture sequential points on the
nize a S/H signal to that step function. A S/H circuit can be
curve by moving the marker position. After all the points
used to capture points on the DUT’s output waveform. Any
Figure 4. Example of AWG610 output
and marker synchronization
5
4
3
2
Output Voltage, VOUT ( V )
1
+2.5
0
Hold-Control Signal ( V)
Figure 3. Example 1-MHz S/H output of a 100-kHz sine wave
2.0 V
Sampled Waveform
( VIN )
1.0 V
0.2 V
0V
2.5 V
Hold Control
Marker
Position 1
+1.5
+0.5
0V
–0.5
Hold Control
Marker
Position 2
–1.5
2.5 V
–2.5
Time (1 µs/div)
0V
Time
22
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Limitations and challenges
Figure 5. Test setup for measuring settling time
Waveform
Generator
(AWG610)
DUT
(OPA656)
Signal
Output
DMM 2
DUT
Output
Value
S/H Circuit 2
(OPA615)
IN
OUT
Hold Control
Marker
Output
DMM 1
DUT
Input
Value
S/H Circuit 1
(OPA615)
IN
OUT
Hold Control
Figure 6. Step waveforms of op amp’s input
and output
120
Normalized DUT Step Response (%)
have been recorded, the S/H curve can be plotted and
analyzed. Programming the waveform generator with
software like MATLAB® or LabVIEW™ makes changing
the marker and recording the results very simple. With
the marker set in position 1, the S/H circuit tracks the
VIN voltage level when the marker is high and holds that
value when the marker is low. At position 1, the output is
held at 1 V. At position 2, the output is held at 0.2 V.
Figure 5 shows the test setup for measuring settling
time where the AWG610 and OPA615 were used for the
S/H functions. All signal lines were matched at 50 W. The
output of the waveform generator was used as the test
signal with two S/H circuits: One measured the input of
the DUT (OPA656), and the other measured the DUT
output. Digital multimeters (DMMs) were used to record
the held values.
As an example of this method, take measuring a
settling time of up to 100 ns. Assume that the waveform
generator is programmed to continually output a square
wave with a duty cycle of 50% and a period of 200 ns.
The marker is initially set at the beginning of the falling
edge of the waveform generator’s output. The generator
runs continually (executes many cycles of sampling and
holding), and the S/H circuit integrates its output voltage
to a steady DC value. This value is then recorded by the
DMM, and the test engineer moves the marker to the
next position, repeating this cycle until data for 100 ns
has been recorded.
Figure 6 shows the plotted waveforms that resulted
when the test setup in Figure 5 was used. To obtain a
settling-time error waveform, the DC error was offset,
and the output was normalized to the input. The result
is shown in Figure 7.
OPA656 DUT
Input
Output
100
RLoad = 100 Ω
80
CLoad = 1.2 pF
60
40
20
0
There are some limitations to the setup described here
that should be kept in mind. When in doubt, the designer
should always use the following equation:
0
20
40
60
80
100
Time (ns)
120
140
160
I = CHOLD × dv/dt
For example, CHOLD should be no less than 50 pF under
the following conditions: The biasing current of the OTA
is 0.5 µA; an error of less than 0.1% of a 1-VPP signal is to
be achieved; and the duration to be measured is 100 ns.
Figure 7. Op amp’s normalized settling error
Normalized Settling-Time Error (%)
For this equation, the size of the initial CHOLD should be
chosen based on three factors:
1. During the holding time, the OTA biasing current will
flow in or out of the capacitor, thus affecting the accuracy of the voltage held.
2. Since a voltage droop will occur on the capacitor due
to the biasing current, a delta voltage should be chosen
based on the percentage of error within which the
measurement should stay.
3. Delta time is the duration for which the sampled voltage is held and should be no longer than the planned
settling time to be measured.
0.2
0
–0.2
–0.4
–0.6
–0.8
RLoad = 100 Ω
CLoad = 1.2 pF
Output Step = 2 V
–1.0
–1.2
–1.4
0
20
40
60
Time (ns)
80
100
23
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Figure 8. Charge leakage on sampling capacitor
VIN
2.5 V
Hold
Control
VOUT
VError
2.5 V
Hold
Sample
Conclusion
Other considerations
DUT Sampled Output (mV)
Numerous techniques exist for measuring settling time.
The duration of the sampling time could greatly affect the
This article has introduced a simple yet accurate techresult of the measurement. During holding, the voltage on
nique that uses a relatively fast waveform generator and a
the sampling capacitor invariably strays from the supposed
S/H circuit. Knowing the limitations of this method, the
DC value because the OTA demands a biasing current. This
user should be able to adjust any measurement parameters
voltage is then readjusted back to the expected DC value
necessary to obtain the best results for a given settlingduring sampling. The DMM that is reading the output of
time range and expected accuracy.
the S/H circuit is thus essentially taking an average value
of this triangle waveform. This phenomenon is shown in
Related Web sites
Figure 8. To reduce this error, the holding time should be
amplifier.ti.com
minimized and the capacitor size maximized. It should be
www.ti.com/product/OPA615
kept in mind that the bigger the sampling capacitor is, the
www.ti.com/product/OPA656
more S/H cycles (integration time) will be needed for the
www.ti.com/tinati-ca
charges to integrate to a steady DC value.
Of course, increasing the sampling time
does not mitigate the leakage problem. A
Figure 9. Settling time measured with different
minimum sampling time should be used that
sampling times
still guarantees the SOTA’s holding-time delay
and ensures enough time for the sampling
60
capacitor’s charge/discharge while it is trackSampling Times
ing the S/H circuit’s input. Figure 9 shows the
40
12 ns
6 ns
recorded values of the op amp’s settling time
20 ns
10 ns
20
when different sampling times were used with
the same holding and integration times. The
0
results were measured against the same wave–20
form taken from a 6-GHz, 10-bit oscilloscope,
which showed a maximum overshoot of
–40
–60 mV. The measurement using a 20-ns sam–60
pling time matched that from the oscilloscope,
but at the cost of applying a significant filter
–80
over the result. Conversely, the measurement
–100
using 6 ns applied a smaller filter but produced
a bigger overshoot, which is an artifact of the
–120
measurement.
0
1
2
3
4
5
6
7
8
9
10
Settling Time (ns)
24
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