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Texas Instruments AN-1662 LMV551 Evaluation Board (Rev. A) User guides
User's Guide
SNOA492A – July 2007 – Revised April 2013
AN-1662 LMV551 Evaluation Board
1
Introduction
The 551013116-001 evaluation board, is designed to aid in the characterization of Texas Instruments
LMV551 3 MHz, low voltage, low power, RR output op amp, that is available in the 5-Pin SC70 package.
The board layout allows for either inverting gain or non-inverting gain configurations. Use the evaluation
board as a:
• Guide to high frequency layout
• Tool to aid in device testing and characterization
2
Basic Operation
Figure 1 shows the basic configuration that allows either inverting gain or non-inverting gain operation.
The input signal is brought into the board through SMA connectors for either the inverting or non-inverting
input of the amplifier.
For non-inverting operation, the closed-loop gain is:
RF
Non-Inverting gain: 1+
RG + R T
(1)
The value of the feedback resistor, RF, has a strong influence on AC performance.
+VCC
1
+VCC
C2
C6
C5
-IN
1
RIN
+IN
5
+
4
U1
3
OUT
ROUT
CL
-
2
RF
RG
C4
RT
C3
C1
-VCC
1
-VCC
Figure 1. Evaluation Board Schematic
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SNOA492A – July 2007 – Revised April 2013
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AN-1662 LMV551 Evaluation Board
Copyright © 2007–2013, Texas Instruments Incorporated
1
Layout Considerations
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For inverting gain operation, the gain is set by Equation 2:
Inverting gain:
RF
RG
Select RT to yield the desired input impedance (input impedance = RG||RT).
(2)
To minimize offset voltages, RIN should equal the parallel combination of RG and RT with RF as shown in
Equation 3:
RIN = (RG + RT)||RF
(3)
The output of the op amp travels through a series resistance, Rout, and then leaves the board through an
SMA connector. The series resistance, ROUT, matches transmission lines and isolates the output from
capacitive loads.
3
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance. When designing
your own board, use the evaluation board as a guide and follow these steps as a basis for high frequency
layout:
1. Use a ground plane.
2. Include 6.8 μF tantalum (C1, C2), and 0.1 μF ceramic (C3, C6) capacitors, on both supplies.
3. Place the 6.8 μF capacitors within 0.75 inches of the power pins.
4. Place the 0.1 μF capacitors less than 0.1 inches from the power pins.
5. Place 0.01 μF ceramic capacitors (C4, C5) as optional decoupling.
6. Remove the ground plane under and around the part, especially near the input and output pins to
reduce parasitic capacitance.
7. Minimize all trace lengths to reduce series inductances.
4
Evaluation Board
Figure 2. Layer 1
2
AN-1662 LMV551 Evaluation Board
SNOA492A – July 2007 – Revised April 2013
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Evaluation Board
www.ti.com
Figure 3. Layer 2
SNOA492A – July 2007 – Revised April 2013
Submit Documentation Feedback
AN-1662 LMV551 Evaluation Board
Copyright © 2007–2013, Texas Instruments Incorporated
3
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