Texas Instruments | TLV320AIC3204 Ultra Low Power Stereo Audio Codec (Rev. E) | Datasheet | Texas Instruments TLV320AIC3204 Ultra Low Power Stereo Audio Codec (Rev. E) Datasheet

Texas Instruments TLV320AIC3204 Ultra Low Power Stereo Audio Codec (Rev. E) Datasheet
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TLV320AIC3204
SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
TLV320AIC3204 Ultra Low Power Stereo Audio Codec
1 Features
2 Applications
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Stereo Audio DAC with 100dB SNR
4.1mW Stereo 48ksps DAC Playback
Stereo Audio ADC with 93dB SNR
6.1mW Stereo 48ksps ADC Record
PowerTune™
Extensive Signal Processing Options
Six Single-Ended or 3 Fully-Differential Analog
Inputs
Stereo Analog and Digital Microphone Inputs
Stereo Headphone Outputs
Stereo Line Outputs
Very Low-Noise PGA
Low Power Analog Bypass Mode
Programmable Microphone Bias
Programmable PLL
Integrated LDO
5-mm × 5-mm, 32-Pin VQFN Package
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing
3 Description
The TLV320AIC3204 (also called the AIC3204) is a
flexible, low-power, low-voltage stereo audio codec
with programmable inputs and outputs, PowerTune
capabilities, fixed predefined and parameterizable
signal-processing blocks, integrated PLL, integrated
LDOs and flexible digital interfaces.
Device Information(1)
PART NUMBER
PACKAGE
TLV320AIC3204
BODY SIZE (NOM)
VQFN (32)
5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Block Diagram
IN1_L
IN2_L
IN3_L
0…+47.5 dB
+
Left
ADC
tpl
+
DRC
ADC
Signal
Proc.
DAC
Signal
Proc.
Vol. Ctrl
-72...0dB
Left
DAC
´
-6...+29dB
HPL
+
1dB steps
Gain Adj.
0.5 dB
steps
CM
´
AGC
-6...+29dB
-30...0 dB
LOL
+
1dB steps
Data Interface
-6...+29dB
-30...0 dB
LOR
+
CM
1dB steps
0…
+47.5 dB
+
Gain Adj.
Right
ADC
IN3_R
+
tpr
´
0.5 dB steps
IN2_R
ADC
Signal
Proc.
DAC
Signal
Proc.
AGC
DRC
-6...+29dB
Right
DAC
´
Vol. Ctrl
HPR
+
1dB steps
-72...0dB
IN1_R
SPI_Select
SPI / I2C
Control Block
Reset
Digital Interrupt Secondary
Mic.
Ctrl
I2S IF
PLL
Primary
I2S Interface
HPVdd
MicBias
Mic
Bias
ALDO
Ref
Ref
DLDO
Supplies
Pin Muxing / Clock Routing
BCLK
WCLK
DIN
DOUT
GPIO
MCLK
SCLK
MISO
SDA/MOSI
SCL/SSZ
IOVss
DVss
AVss
IOVdd
DVdd
AVdd
LDO Select
LDO in
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320AIC3204
SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 9
Electrical Characteristics, ADC ................................. 9
Electrical Characteristics, Bypass Outputs ............. 11
Electrical Characteristics, Microphone Interface..... 12
Electrical Characteristics, Audio DAC Outputs ....... 13
Electrical Characteristics, LDO ............................... 15
Electrical Characteristics, Misc. ............................ 16
Electrical Characteristics, Logic Levels................. 17
I2S LJF and RJF Timing in Master Mode (see
Figure 1)................................................................... 17
7.13 I2S LJF and RJF Timing in Slave Mode (see
Figure 2)................................................................... 18
7.14 DSP Timing in Master Mode (see Figure 3) ......... 19
7.15 DSP Timing in Slave Mode (see Figure 4) ........... 20
7.16 Digital Microphone PDM Timing (see Figure 5).... 20
7.17 I2C Interface Timing .............................................. 21
7.18 SPI Interface Timing (See Figure 7) ..................... 22
7.19 Typical Characteristics .......................................... 23
7.20 Typical Characteristics, FFT ................................. 25
8
9
Parameter Measurement Information ................ 25
Detailed Description ............................................ 26
9.1
9.2
9.3
9.4
9.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Map...........................................................
26
27
27
35
35
10 Application and Implementation........................ 40
10.1 Application Information.......................................... 40
10.2 Typical Application ................................................ 40
11 Power Supply Recommendations ..................... 44
12 Layout................................................................... 44
12.1 Layout Guidelines ................................................. 44
12.2 Layout Example .................................................... 45
13 Device and Documentation Support ................. 46
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
46
14 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2019) to Revision E
Page
•
Added BCLK to rise and fall time parameter names in I2S LJF and RJF Timing in Master Mode table.............................. 17
•
Added BCLK to rise and fall time parameter names in I2S LJF and RJF Timing in Slave Mode table................................ 18
•
Added BCLK to rise and fall time parameter names in DSP Timing in Master Mode table................................................. 19
•
Added BCLK to rise and fall time parameter names in DSP Timing in Slave Mode table................................................... 20
•
Added CLK to rise and fall time parameter names in Digital Microphone PDM Timing table.............................................. 20
Changes from Revision C (November 2014) to Revision D
Page
•
Changed ESD Ratings title and format to current standards ................................................................................................ 8
•
Added footnote to I2S LJF and RJF Timing in Slave Mode table......................................................................................... 18
•
Added footnote to DSP Timing in Slave Mode table ............................................................................................................ 20
Changes from Revision B (October 2012) to Revision C
Page
•
Added the Device information table, Handling Ratings table, Applications and Implementation section, Layout
section, and the Device and Documentation Support section................................................................................................ 1
•
Changed the pin description From: connect to DVss. To: D-LDO enable signal ................................................................... 7
•
Added "DVDD" to LDOs disabled in operating conditions statement..................................................................................... 8
•
Added "Audio input max ac signal swing" to the Recommended Operating Conditions table............................................... 8
2
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•
Added the Digital Microphone PDM Timing (see Figure 5) section ..................................................................................... 20
•
Corrected thi to th(DIN) ............................................................................................................................................................. 22
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5 Device Comparison Table
4
ORDER NUMBER
DESCRIPTION
TLV320AIC3254
Low power stereo audio codec with miniDSP.
TLV320AIC3204
Same as TLV320AIC3204 but without miniDSP.
TLV320AIC3256
Similar to TLV320AIC3254 but with ground centered headphone output.
TLV320AIC3206
Same as TLV320AIC3256 but without miniDSP.
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6 Pin Configuration and Functions
This document describes signals that take on different names depending on how they are configured. In such
cases, the different names are placed together and separated by slash (/) characters. For example, "SCL/SS".
Active low signals are represented by overbars.
IOVSS
8
1
GPIO/MFP5
SCLK/MFP3
IOVDD
DOUT/MFP2
DIN/MFP1
BCLK
WCLK
MCLK
RHB Package
(Bottom View)
32
9
RESET
SCL/SS
SDA/MOSI
LDO_SELECT
MISO/MFP4
DVDD
SPI_SELECT
DVSS
IN1_L
HPR
IN1_R
LDOIN
HPL
IN2_L
25
16
REF
AVSS
MICBIAS
IN3_L
LOL
IN3_R
17
LOR
AVDD
24
IN2_R
Pin Functions
(1)
PIN
NAME
TYPE
1
MCLK
DI
DESCRIPTION
2
BCLK
DIO
Audio serial data bus (primary) bit clock
3
WCLK
DIO
Audio serial data bus (primary) word clock
Master Clock Input
Primary function:
Audio serial data bus data input
4
DIN / MFP1
DI
Secondary function:
Digital Microphone Input
General Purpose Clock Input
General Purpose Input
Primary function:
Audio serial data bus data output
Secondary function:
(1)
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
5
DOUT / MFP2
DO
6
IOVDD
Power
IO voltage supply 1.1V – 3.6V
7
IOVSS
Ground
IO ground supply
DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)
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Pin Functions (continued)
PIN
NAME
TYPE
(1)
DESCRIPTION
Primary function: (SPI_Select = 1)
SPI serial clock
Secondary function: (SPI_Select = 0)
Headphone-detect input
Digital microphone input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC or common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
8
SCLK / MFP3
DI
9
SCL/SS
DI
I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
10
SDA/MOSI
DI
I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
Primary function: (SPI_Select = 1)
Serial data output
Secondary function: (SPI_Select = 0)
11
MISO / MFP4
DO
12
SPI_ SELECT
DI
Control mode select pin ( 1 = SPI, 0 = I2C )
13
IN1_L
AI
Multifunction Analog Input,
or Single-ended configuration: MIC 1 or Line 1 left
or Differential configuration: MIC or Line right, negative
14
IN1_R
AI
Multifunction Analog Input,
or Single-ended configuration: MIC 1 or Line 1 right
or Differential configuration: MIC or Line right, positive
15
IN2_L
AI
Multifunction Analog Input,
or Single-ended configuration: MIC 2 or Line 2 left
or Differential configuration: MIC or Line left, positive
16
IN2_R
AI
Multifunction Analog Input,
or Single-ended configuration: MIC 2 or Line 2 right
or Differential configuration: MIC or Line left, negative
17
AVSS
Ground
18
REF
AO
Reference voltage output for filtering
19
MICBIAS
AO
Microphone bias voltage output
AI
Multifunction Analog Input,
or Single-ended configuration: MIC3 or Line 3 left,
or Differential configuration: MIC or Line left, positive,
or Differential configuration: MIC or Line right, negative
20
IN3_L
Analog ground supply
21
IN3_R
AI
Multifunction Analog Input,
or Single-ended configuration: MIC3 or Line 3 right,
or Differential configuration: MIC or Line left, negative,
or Differential configuration: MIC or Line right, positive
22
LOL
AO
Left line output
23
LOR
AO
Right line output
24
AVDD
Power
6
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Digital microphone clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
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Pin Functions (continued)
TYPE
(1)
PIN
NAME
25
HPL
AO
26
LDOIN /
HPVDD
Power
27
HPR
AO
28
DVSS
Ground
DESCRIPTION
Left high power output driver
LDO Input supply and Headphone Power supply 1.9V– 3.6V
Right high power output driver
Digital Ground and Chip-substrate
If LDO_SELECT Pin = 0 (D-LDO disabled)
Digital voltage supply 1.26V – 1.95V
29
DVDD
Power
30
LDO_ SELECT
DI
D-LDO enable signal (1 = D-LDO enable, 0 = D-LDO disabled)
31
RESET
DI
Reset (active low)
If LDO_SELECT Pin = 1 (D-LDO enabled)
Digital voltage supply filtering output
Primary function:
General Purpose digital IO
Secondary function:
32
GPIO / MFP5
DI
Thermal Pad
Thermal Pad
N/A
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
Connect to PCB ground plane. Not internally connected.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
AVDD to AVSS
–0.3
2.2
V
DVDD to DVSS
–0.3
2.2
V
IOVDD to IOVSS
–0.3
3.9
V
LDOIN to AVSS
–0.3
3.9
V
Digital Input voltage to ground
–0.3
IOVDD + 0.3
V
Analog input voltage to ground
–0.3
AVDD + 0.3
V
Operating temperature range
–40
85
°C
105
°C
125
°C
Input voltage
Junction temperature (TJ Max)
Storage temperature, Tstg
(1)
–55
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
LDOIN
Referenced to AVSS (1)
AVDD
Power Supply Voltage Range
IOVDD
DVDD (2)
PLL Input Frequency
MCLK
Master Clock Frequency
SCL
SCL Clock Frequency
HPL, HPR
1.26
1.95
3.6
1.8
V
1.95
Clock divider uses fractional divide
(D > 0), P = 1, DVDD ≥ 1.65V (Refer to the table in
SLAA557, Maximum TLV320AIC3204 Clock Frequencies)
10
20
MHz
Clock divider uses integer divide
(D = 0), P = 1, DVDD ≥ 1.65V (Refer to the table in
SLAA557, Maximum TLV320AIC3204 Clock Frequencies)
0.512
20
MHz
MCLK; Master Clock Frequency; DVDD ≥ 1.65V
50
MCLK; Master Clock Frequency; DVDD ≥ 1.26V
25
400
MHz
kHz
0.530
CM = 0.9 V
0
0.707
0.9 or
AVDD-0.9 (3)
0.6
10
kΩ
Stereo headphone output load resistance Single-ended configuration
14.4
16
Ω
Headphone output load resistance
24.4
32
Ω
10
pF
Stereo line output load resistance
TOPR
Operating Temperature Range
8
Referenced to DVSS (1)
1.8
0
Digital output load capacitance
(3)
1.1
UNIT
3.6
CM = 0.75 V
CLout
(1)
(2)
1.5
Referenced to IOVSS (1)
MAX
0.75 or
AVDD-0.75 (3)
Audio input max ac signal swing
(IN1_L, IN1_R, IN2_L, IN2_R, IN3_L,
IN3_R)
LOL, LOR
NOM
1.9
Differential configuration
–40
85
Vpeak
Vpeak
°C
All grounds on board are tied together to prevent voltage differences of more than 0.2V maximum for any combination of ground signals.
At DVDD values lower than 1.65V, the PLL does not function. Refer to the Maximum TLV320AIC3204 Clock Frequencies table in the
TLV320AIC3204 Application Reference Guide (SLAA557) for details on maximum clock frequencies.
Whichever is smaller.
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7.4 Thermal Information
TLV320AIC3204
THERMAL METRIC (1)
UNIT
RHB (32 PINS)
RθJA
Junction-to-ambient thermal resistance
31.4
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
21.4
°C/W
RθJB
Junction-to-board thermal resistance
5.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
5.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics, ADC
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
AUDIO ADC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1) (2)
Input signal level (0dB)
Single-ended, CM = 0.9V
Device Setup
1kHz sine wave input , Single-ended Configuration
IN1_R to Right ADC and IN1_L to Left ADC,
Rin = 20K, fs = 48kHz,
AOSR = 128, MCLK = 256 x fs,
PLL Disabled; AGC = OFF, Channel Gain = 0dB,
Processing Block = PRB_R1,
Power Tune = PTM_R4
Inputs ac-shorted to ground
0.5
80
VRMS
93
SNR
Signal-to-noise ratio, A-weighted (1) (2)
IN2_R, IN3_R routed to Right ADC and ac-shorted to ground
IN2_L, IN3_L routed to Left ADC and ac-shorted to ground
93
DR
Dynamic range A-weighted (1) (2)
–60dB full-scale, 1-kHz input signal
92
–3 dB full-scale, 1-kHz input signal
–85
THD+N
Total Harmonic Distortion plus Noise
IN2_R, IN3_R routed to Right ADC
IN2_L, IN3_L routed to Left ADC
–3dB full-scale, 1-kHz input signal
–85
dB
dB
–70
dB
AUDIO ADC
Input signal level (0dB)
Single-ended, CM = 0.75V, AVDD = 1.5V
Device Setup
1kHz sine wave input, Single-ended Configuration
IN1_R, IN2_R, IN3_R routed to Right ADC
IN1_L, IN2_L, IN3_L routed to Left ADC
Rin = 20kΩ, fs = 48kHz,
AOSR = 128, MCLK = 256 x fs,
PLL Disabled, AGC = OFF, Channel Gain = 0dB,
Processing Block = PRB_R1
Power Tune = PTM_R4
(1) (2)
0.375
VRMS
SNR
Signal-to-noise ratio, A-weighted
Inputs ac-shorted to ground
91
dB
DR
Dynamic range A-weighted (1) (2)
–60dB full-scale, 1-kHz input signal
90
dB
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1-kHz input signal
–80
dB
(1)
(2)
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher
THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-ofband noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, ADC (continued)
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC
ICN
Input signal level (0dB)
Differential Input, CM = 0.9V
Device Setup
1kHz sine wave input, Differential configuration
IN1_L and IN1_R routed to Right ADC
IN2_L and IN2_R routed to Left ADC
Rin = 10K, fs = 48kHz, AOSR = 128
MCLK = 256* fs PLL Disabled
AGC = OFF, Channel Gain = 40dB Processing Block = PRB_R1,
Power Tune = PTM_R4
Idle-Channel Noise, A-weighted (1) (2)
Inputs ac-shorted to ground, input referred noise
10
mV
2
μVRMS
AUDIO ADC
Gain Error
1kHz sine wave input , Single-ended configuration
Rin = 20kΩ fs = 48kHz, AOSR = 128,
MCLK = 256 x fs, PLL Disabled
AGC = OFF, Channel Gain = 0dB
Processing Block = PRB_R1,
Power Tune = PTM_R4, CM = 0.9V
Input Channel Separation
1kHz sine wave input at -3dBFS
Single-ended configuration
IN1_L routed to Left ADC
IN1_R routed to Right ADC, Rin = 20kΩ
AGC = OFF, AOSR = 128,
Channel Gain = 0dB, CM = 0.9V
–0.05
dB
108
dB
115
dB
55
dB
1kHz sine wave input at –3dBFS on IN2_L, IN2_L internally not
routed.
IN1_L routed to Left ADC
ac-coupled to ground
Input Pin Crosstalk
1kHz sine wave input at –3dBFS on IN2_R,
IN2_R internally not routed.
IN1_R routed to Right ADC
ac-coupled to ground
Single-ended configuration Rin = 20kΩ,
AOSR = 128 Channel, Gain = 0dB, CM = 0.9V
PSRR
217Hz, 100mVpp signal on AVDD,
Single-ended configuration, Rin = 20kΩ,
Channel Gain = 0dB; CM = 0.9V
Single-Ended, Rin = 10kΩ, PGA gain set to 0dB
0
dB
47.5
dB
–6
dB
Single-Ended, Rin = 20kΩ, PGA gain set to 47.5dB
41.5
dB
Single-Ended, Rin = 40kΩ, PGA gain set to 0dB
–12
dB
Single-Ended, Rin = 40kΩ, PGA gain set to 47.5dB
35.5
dB
0.5
dB
Single-Ended, Rin = 10kΩ, PGA gain set to 47.5dB
ADC programmable gain amplifier
gain
ADC programmable gain amplifier
step size
10
Single-Ended, Rin = 20kΩ, PGA gain set to 0dB
1-kHz tone
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7.6 Electrical Characteristics, Bypass Outputs
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Load = 16Ω (single-ended), 50pF;
Input and Output CM = 0.9V;
Headphone Output on LDOIN Supply;
IN1_L routed to HPL and IN1_R routed to
HPR;
Channel Gain = 0dB
Device Setup
Gain Error
THD
–0.8
Noise, A-weighted (1)
Idle Channel, IN1_L and IN1_R ac-shorted to
ground
Total Harmonic Distortion
446mVrms, 1kHz input signal
3
dB
μVRMS
–89
dB
0.6
dB
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Load = 10kΩ (single-ended), 56pF;
Input and Output CM = 0.9V;
LINE Output on LDOIN Supply;
IN1_L routed to ADCPGA_L and IN1_R
routed to ADCPGA_R; Rin = 20kΩ
ADCPGA_L routed to LOL and ADCPGA_R
routed to LOR; Channel Gain = 0dB
Device Setup
Gain Error
Idle Channel,
IN1_L and IN1_R ac-shorted to ground
Noise, A-weighted
(1)
(1)
Channel Gain = 40dB,
Input Signal (0dB) = 5mVrms
Inputs ac-shorted to ground, Input Referred
7
μVRMS
3.4
μVRMS
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in
higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
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7.7 Electrical Characteristics, Microphone Interface
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
Bias voltage CM = 0.9V, LDOIN = 3.3V
Micbias Mode 0, Connect to AVDD or LDOIN
1.25
V
Micbias Mode 1, Connect to LDOIN
1.7
V
Micbias Mode 2, Connect to LDOIN
2.5
V
Micbias Mode 3, Connect to AVDD
Bias voltage
AVDD
V
LDOIN
V
Micbias Mode 0, Connect to AVDD or LDOIN
1.04
V
Micbias Mode 1, Connect to AVDD or LDOIN
1.425
V
Micbias Mode 2, Connect to LDOIN
2.075
V
AVDD
V
LDOIN
V
Micbias Mode 3, Connect to LDOIN
CM = 0.75V, LDOIN = 3.3V
Micbias Mode 3, Connect to AVDD
Micbias Mode 3, Connect to LDOIN
Output Noise
CM = 0.9V, Micbias Mode 2, A-weighted,
20Hz to 20kHz bandwidth,
Current load = 0mA.
Current Sourcing
Micbias Mode 2, Connect to LDOIN
Inline Resistance
12
Micbias Mode 3, Connect to AVDD
Micbias Mode 3, Connect to LDOIN
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10
μVRMS
3
mA
140
87
Ω
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SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
7.8 Electrical Characteristics, Audio DAC Outputs
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
VRMS
87
100
dB
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Device Setup
Load = 10kΩ (single-ended), 56pF
Line Output on AVDD Supply
Input and Output CM = 0.9V
DOSR = 128, MCLK = 256 x fs,
Channel Gain = 0dB, word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio A-weighted (1) (2)
All zeros fed to DAC input
DR
Dynamic range, A-weighted (1) (2)
–60dB 1kHz input full-scale signal, Word
length = 20 bits
100
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1kHz input signal
–83
DAC Gain Error
0 dB, 1kHz input full scale signal
0.3
dB
DAC Mute Attenuation
Mute
119
dB
DAC channel separation
–1 dB, 1kHz signal, between left and right HP
out
113
dB
100mVpp, 1kHz signal applied to AVDD
73
dB
100mVpp, 217Hz signal applied to AVDD
77
dB
DAC PSRR
–70
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Device Setup
Load = 10kΩ (single-ended), 56pF
Line Output on AVDD Supply
Input and Output CM = 0.75V; AVDD = 1.5V
DOSR = 128
MCLK = 256 * fs
Channel Gain = –2dB
word length = 20 bits
Processing Block = PRB_P1
Power Tune = PTM_P4
Full scale output voltage (0dB)
0.375
VRMS
SNR
Signal-to-noise ratio, A-weighted (1) (2)
All zeros fed to DAC input
99
dB
DR
Dynamic range, A-weighted (1) (2)
–60dB 1 kHz input full-scale signal
97
dB
THD+N
Total Harmonic Distortion plus Noise
–1 dB full-scale, 1-kHz input signal
–85
dB
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT
Device Setup
Load = 16Ω (single-ended), 50pF
Headphone Output on AVDD Supply,
Input and Output CM = 0.9V, DOSR = 128,
MCLK = 256 * fs, Channel Gain = 0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Full scale output voltage (0dB)
0.5
VRMS
100
dB
99
dB
Signal-to-noise ratio, A-weighted (1) (2)
All zeros fed to DAC input
DR
Dynamic range, A-weighted (1) (2)
–60dB 1kHz input full-scale signal, Word
Length = 20 bits, Power Tune = PTM_P4
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1kHz input signal
–83
DAC Gain Error
0dB, 1kHz input full scale signal
–0.3
dB
DAC Mute Attenuation
Mute
122
dB
SNR
(1)
(2)
87
–70
dB
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in
higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Audio DAC Outputs (continued)
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
DAC channel separation
MIN
–1dB, 1kHz signal, between left and right HP
out
DAC PSRR
Power Delivered
TYP
MAX
UNIT
110
dB
100mVpp, 1kHz signal applied to AVDD
73
dB
100mVpp, 217Hz signal applied to AVDD
78
dB
RL = 16Ω, Output Stage on AVDD = 1.8V
THDN < 1%, Input CM = 0.9V,
Output CM = 0.9V
15
RL = 16Ω Output Stage on LDOIN = 3.3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.65V
64
mW
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT
Load = 16Ω (single-ended), 50pF,
Headphone Output on AVDD Supply,
Input and Output CM = 0.75V; AVDD = 1.5V,
DOSR = 128, MCLK = 256 * fs,
Channel Gain = –2dB, word length = 20-bits;
Processing Block = PRB_P1,
Power Tune = PTM_P4
Device Setup
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio, A-weighted (1) (2)
(1) (2)
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
0.375
All zeros fed to DAC input
VRMS
99
dB
-60dB 1kHz input full-scale signal
98
dB
–1dB full-scale, 1kHz input signal
–83
dB
1778
mVRMS
AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT
Device Setup
Load = 32Ω (differential), 50pF,
Headphone Output on LDOIN Supply
Input CM = 0.75V, Output CM = 1.5V,
AVDD = 1.8V, LDOIN = 3.0V, DOSR = 128
MCLK = 256 * fs, Channel (headphone driver)
Gain = 5dB for full scale output signal,
word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio, A-weighted (1) (2)
All zeros fed to DAC input
98
dB
DR
Dynamic range, A-weighted (1) (2)
–60dB 1kHz input full-scale signal
96
dB
THD
Total Harmonic Distortion
–3dB full-scale, 1kHz input signal
–82
dB
RL = 32Ω, Output Stage on LDOIN = 3.3V,
THDN < 1%, Input CM = 0.9V,
Output CM = 1.65V
136
mW
RL = 32Ω Output Stage on LDOIN = 3.0V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.5V
114
mW
Power Delivered
14
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SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
7.9 Electrical Characteristics, LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW DROPOUT REGULATOR (AVdd)
Output Voltage
LDOMode = 1, LDOIN > 1.95V
1.67
LDOMode = 0, LDOIN > 2.0V
1.72
LDOMode = 2, LDOIN > 2.05V
1.77
Output Voltage Accuracy
V
±2%
Load Regulation
Load current range 0 to 50mA
Line Regulation
Input Supply Range 1.9V to 3.6V
Decoupling Capacitor
15
mV
5
mV
60
μA
1
Bias Current
μF
LOW DROPOUT REGULATOR (DVdd)
Output Voltage
LDOMode = 1, LDOIN > 1.95V
1.67
LDOMode = 0, LDOIN > 2.0V
1.72
LDOMode = 2, LDOIN > 2.05V
1.77
Output Voltage Accuracy
V
±%2
Load Regulation
Load current range 0 to 50mA
Line Regulation
Input Supply Range 1.9V to 3.6V
Decoupling Capacitor
15
mV
5
mV
1
Bias Current
μF
60
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7.10 Electrical Characteristics, Misc.
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF
pin, PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Reference Voltage Settings
Reference Noise
CMMode = 0 (0.9V)
0.9
CMMode = 1 (0.75V)
0.75
CM = 0.9V, A-weighted, 20Hz to 20kHz bandwidth,
Cref = 10μF
Decoupling Capacitor
1
1
V
μVRfcMS
10
μF
120
μA
I(DVDD)
0.9
μA
I(AVDD)
<0.9
μA
I(LDOIN)
<0.9
μA
I(IOVDD)
13
nA
Bias Current
Shutdown Current
Device Setup
16
Coarse AVDD supply turned off, LDO_select held at
ground, No external digital input is toggled
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SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
7.11 Electrical Characteristics, Logic Levels (1)
At 25°C, AVDD, DVDD, IOVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC FAMILY (CMOS)
VIH
Logic Level
VIL
IIH = 5 μA, IOVDD > 1.6V
0.7 × IOVDD
V
IIH = 5μA, 1.2V ≤ IOVDD < 1.6V
0.9 × IOVDD
V
IIH = 5μA, IOVDD < 1.2V
IOVDD
V
IIL = 5 μA, IOVDD > 1.6V
–0.3
IIL = 5μA, 1.2V ≤ IOVDD < 1.6V
0.3 × IOVDD
V
0.1 × IOVDD
V
0
V
IIL = 5μA, IOVDD < 1.2V
VOH
IOH = 2 TTL loads
VOL
IOL = 2 TTL loads
0.8 × IOVDD
V
0.1 × IOVDD
Capacitive Load
(1)
V
10
pF
Applies to all DI, DO, and DIO pins shown in Pin Configuration and Functions.
7.12 I2S LJF and RJF Timing in Master Mode (see Figure 1)
IOVDD = 1.8 V
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
td(WS)
WCLK delay
30
20
ns
td(DO-WS)
WCLK to DOUT delay (For LJF Mode only)
20
20
ns
td(DO-BCLK)
BCLK to DOUT delay
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
BCLK rise time
24
12
ns
tf
BCLK fall time
24
12
ns
22
ns
ns
WCLK
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
DOUT
th(DI)
tS(DI)
DIN
All specifications at 25°C, DVdd = 1.8V
Figure 1. I2S LJF and RJF Timing in Master Mode
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7.13 I2S LJF and RJF Timing in Slave Mode (see Figure 2)
IOVDD = 1.8V
MIN
IOVDD = 3.3V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
td(DO-WS)
WCLK to DOUT delay (For LJF mode only)
td(DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
20
22
(1)
tr
BCLK rise time
4
tf
BCLK fall time
4 (1)
(1)
ns
20
ns
22
ns
ns
ns
(1)
ns
4 (1)
ns
4
The BCLK maximum rise and fall time can be as high as 10 ns, if the BCLK high and low period are greater than 50 ns.
WCLK
th(WS)
BCLK
tL(BCLK)
tH(BCLK)
ts(WS)
td(DO-WS)
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 2. I2S LJF and RJF Timing in Slave Mode
18
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SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
7.14 DSP Timing in Master Mode (see Figure 3)
IOVDD = 1.8V
MIN
MAX
IOVDD = 3.3V
MIN
UNIT
MAX
td(WS)
WCLK delay
30
20
ns
td(DO-BCLK)
BCLK to DOUT delay
22
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
BCLK rise time
24
12
ns
tf
BCLK fall time
24
12
ns
ns
ns
WCLK
td(WS)
td(WS)
BCLK
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
All specifications at 25°C, DVdd = 1.8V
Figure 3. DSP Timing in Master Mode
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7.15 DSP Timing in Slave Mode (see Figure 4)
IOVDD = 1.8V
MIN
IOVDD = 3.3V
MAX
MIN
UNIT
MAX
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
td(DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
BCLK rise time
tf
(1)
22
BCLK fall time
ns
22
ns
ns
ns
4 (1)
4 (1)
ns
(1)
(1)
ns
4
4
The BCLK maximum rise and fall time can be as high as 10 ns, if the BCLK high and low period are greater than 50 ns.
WCLK
th(ws)
BCLK
tH(BCLK)
ts(ws)
th(ws)
th(ws)
tL(BCLK)
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 4. DSP Timing in Slave Mode
7.16 Digital Microphone PDM Timing (see Figure 5)
Based on design simulation. Not tested in actual silicon.
IOVDD = 1.8V
MIN
IOVDD = 3.3V
MAX
MIN
UNIT
MAX
ts
DIN setup
20
20
ns
th
DIN hold
5
5
ns
tr
CLK rise time
4
4
ns
tf
CLK fall time
4
4
ns
th
tr
tf
ts
ADC_MOD_CLK
DIG_MIC_IN
DATA-LEFT
DATA-RIGHT
DATA-LEFT
DATA-RIGHT
Figure 5. PDM Input Timing
20
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7.17 I2C Interface Timing
Standard-Mode
MIN
TYP
Fast-Mode
MAX
MIN
100
0
0
TYP
UNIT
MAX
fSCL
SCL clock frequency
tHD;STA
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
4.0
0.8
μs
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4.0
0.6
μs
tSU;STA
Setup time for a repeated START condition
4.7
tHD;DAT
Data hold time: For I2C bus devices
tSU;DAT
Data set-up time
tr
SDA and SCL Rise Time
1000
20+0.1Cb
300
ns
tf
SDA and SCL Fall Time
300
20+0.1Cb
300
ns
tSU;STO
Set-up time for STOP condition
4.0
0.8
μs
tBUF
Bus free time between a STOP and START condition
4.7
1.3
μs
Cb
Capacitive load for each bus line
0
400
kHz
0.8
3.45
250
0
μs
0.9
100
400
μs
ns
400
pF
Figure 6. I2C Interface Timing
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7.18 SPI Interface Timing (See Figure 7)
IOVDD = 1.8V
MIN
IOVDD = 3.3V
TYP MAX
MIN
TYP
UNIT
MAX
tsck
SCLK Period (1)
100
50
ns
tsckh
SCLK Pulse width High
50
25
ns
tsckl
SCLK Pulse width Low
50
25
ns
tlead
Enable Lead Time
30
20
ns
ttrail
Enable Trail Time
30
20
ns
td;seqxfr
Sequential Transfer Delay
40
ta
Slave DOUT access time
40
20
ns
tdis
Slave DOUT disable time
40
20
ns
tsu
DIN data setup time
15
10
th(DIN)
DIN data hold time
15
10
tv(DOUT)
DOUT data valid time
tr
tf
(1)
20
ns
ns
ns
25
18
ns
SCLK Rise Time
4
4
ns
SCLK Fall Time
4
4
ns
These parameters are based on characterization and are not tested in production.
SS
S
t
t Lead
t Lag
t
td
sck
SCLK
t sckl
tf
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
ta
MOSI
t su
BIT 6 . . . 1
LSB OUT
t h(DIN)
MSB IN
BIT 6 . . . 1
LSB IN
At 25°C, DVdd = 1.8V
Figure 7. SPI Interface Timing Diagram
22
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7.19 Typical Characteristics
100
0
THD - Total Harmonic Distortion - dB
SNR - Signal-to-Noise Ratio - dB
CM=0.9 V,
-10 RL = 32 W
RIN = 10 kW, Differential
95
90
RIN = 20 kW, Differential
85
80
75
RIN = 10 kW, Single Ended
70
65
RIN = 20 kW, Single Ended
60
-40
-50
-60
-70
-80
-90
-100
20
60
40
CM=1.65 V,
RL = 16 W
-30
50
0
0
20
Channel Gain - dB
Figure 8. ADC SNR vs Channel Gain
40
60
80
Headphone Output Power - mW
100
Figure 9. Total Harmonic Distortion vs Headphone Output
Power
0
70
105
Load = 32 W BTL
-10
100
-20
SNR - Signal-to-Noise Ratio - dB
THD - Total Harmonic Distortion - dB
CM=1.65 V,
RL = 32 W
-20
55
-20
CM=0.9 V,
RL = 16 W
-30
CM=1.5 V
-40
CM=1.65 V
-50
-60
-70
-80
60
SNR
95
50
90
40
85
80
30
OUTPUT POWER
75
20
70
10
65
-90
-100
60
0
50
100
150
Headphone output Power - mW
0
200
0.75
Figure 10. Total Harmonic Distortion vs Headphone Output
Power
1.65
0.9
1.5
1.25
Output Common Mode Setting - V
Figure 11. Headphone SNR and Output Power vs Output
Common Mode Setting
350
20
DVDD LDO
15
Change In Output Voltage - mV
300
Dropout Voltage - mV
250
200
AVDD LDO
150
100
50
10
AVDD LDO
5
0
DVDD LDO
-5
-10
-15
0
-20
0
10
20
30
Load - mA
40
50
0
Figure 12. LDO Dropout Voltage vs Load Current
10
20
Load - mA
30
40
Figure 13. LDO Load Response
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Typical Characteristics (continued)
2.6
MicBIAS Voltage - mV
2.55
2.5
2.45
2.4
0
0.5
1
1.5
2
MicBIAS Load - mA
2.5
3
CM = 0.9 V
Figure 14. MICBIAS Mode 2, LDOIN OP Stage vs MICBIAS Load Current
24
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7.20 Typical Characteristics, FFT
0
0
DAC
ADC
-20
-20
-40
Power - dBr
Power - dBFs
-40
-60
-80
-60
-80
-100
-100
-120
-120
-140
0
5000
20000
15000
10000
f - Frequency - Hz
0
5000
10000
f - Frequency - Hz
15000
20000
Figure 16. DAC Playback to Headphone FFT at -1dBFS vs
Frequency
Figure 15. Single Ended Line Input to ADC FFT at -1dBr vs
Frequency
0
0
DAC
-20
-20
-40
Power - dBr
Power - dBr
-40
-60
-60
-80
-80
-100
-100
-120
-140
-120
0
5000
10000
f - Frequency - Hz
15000
0
20000
5000
10000
f - Frequency - Hz
15000
20000
Figure 18. Line Input to Headphone FFT at 446mVrms vs
Frequency
Figure 17. DAC Playback to Line-out FFT at -1dBFS vs
Frequency
0
-20
Power - dBr
-40
-60
-80
-100
-120
-140
0
5000
10000
15000
20000
f - Frequency - Hz
Figure 19. Line Input to Line-out FFT at 446mVrms vs Frequency
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
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9 Detailed Description
9.1 Overview
The TLV320AIC3204 includes extensive register-based control of power, input/output channel configuration,
gains, effects, pin-multiplexing and clocks, allowing precise targeting of the device to its application. Combined
with the advanced PowerTune technology, the device covers operations from 8 kHz mono voice playback to
audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3204 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations covering single-ended and differential setups, as well as
floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by
mechanical coupling, e.g. optical zooming in a digital camera.
The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC
and analog input signals as well as programmable volume controls. The playback path contains two high-power
output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways,
including stereo and mono BTL.
The integrated PowerTune technology allows the device to be tuned to an optimum power-performance trade-off.
Mobile applications frequently have multiple use cases requiring very low power operation while being used in a
mobile environment. When used in a docked environment power consumption typically is less of a concern, while
minimizing noise is important. With PowerTune, the TLV320AIC3204 addresses both cases.
The voltage supply range for the TLV320AIC3204 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To
ease system-level design, integrated LDOs generate the appropriate analog or digital supply from input voltages
ranging from 1.8V to 3.6V. The device supports digital I/O voltages in the range of 1.1V–3.6V.
The required internal clock of the TLV320AIC3204 can be derived from multiple sources, including the MCLK pin,
the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived
from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable clock
signal, PLL use is not recommended for the lowest power settings. The PLL is highly programmable and can
accept available input clocks in the range of 512 kHz to 50 MHz.
26
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9.2 Functional Block Diagram
Figure 20 shows the basic functional blocks of the device.
IN1_L
IN2_L
IN3_L
0…+47.5 dB
+
Left
ADC
tpl
+
DRC
ADC
Signal
Proc.
DAC
Signal
Proc.
Vol. Ctrl
-72...0dB
HPL
+
Left
DAC
´
-6...+29dB
1dB steps
Gain Adj.
0.5 dB
steps
CM
´
AGC
-6...+29dB
-30...0 dB
LOL
+
1dB steps
Data Interface
-6...+29dB
-30...0 dB
LOR
+
CM
1dB steps
0…
+47.5 dB
+
Gain Adj.
Right
ADC
IN3_R
+
tpr
´
0.5 dB steps
IN2_R
ADC
Signal
Proc.
DAC
Signal
Proc.
AGC
DRC
-6...+29dB
Right
DAC
´
Vol. Ctrl
HPR
+
1dB steps
-72...0dB
IN1_R
SPI_Select
SPI / I2C
Control Block
Reset
Digital Interrupt Secondary
Mic.
Ctrl
I2S IF
PLL
Primary
I2S Interface
HPVdd
MicBias
Mic
Bias
ALDO
Ref
Ref
DLDO
Supplies
Pin Muxing / Clock Routing
BCLK
WCLK
DIN
DOUT
GPIO
MCLK
SCLK
MISO
SDA/MOSI
SCL/SSZ
IOVss
DVss
AVss
IOVdd
DVdd
AVdd
LDO Select
LDO in
Figure 20. Block Diagram
9.3 Feature Description
9.3.1 Device Connections
9.3.1.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are Reset, LDO_Select and the SPI_Select pin, which are HW control pins. Depending on
the state of SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI
protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Multifunction Pins.
9.3.1.1.1 Multifunction Pins
Table 1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
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Feature Description (continued)
Table 1. Multifunction Pin Assignments
Pin Function
A
B
1
2
3
4
5
6
7
8
MCLK
BCLK
WCLK
DIN
MFP1
DOUT
MFP2
DMDIN/
MFP3/
SCLK
DMCLK/
MFP4/
MISO
GPIO
MFP5
S (1)
S (2)
PLL Input
Codec Clock Input
2
S
(1)
,D
(4)
S
C
I S BCLK input
S,D
D
I2S BCLK output
E (5)
E
I2S WCLK input
F
I2S WCLK output
G
I2S ADC word clock input
H
I2S ADC WCLK out
2
S (3)
E
(2)
S (3)
E, D
E
E
E
E
E
I
I S DIN
J
I2S DOUT
E, D
K
General Purpose Output I
K
General Purpose Output II
K
General Purpose Output III
L
General Purpose Input I
L
General Purpose Input II
L
General Purpose Input III
M
INT1 output
E
E
E
N
INT2 output
E
E
E
O
Digital Microphone Data Input
P
Digital Microphone Clock Output
Q
Secondary I2S BCLK input
E, D
E
E
E
E
E
E
E
E
E
E
2
E
E
E
E
R
Secondary I S WCLK in
E
S
Secondary I2S DIN
E
T
Secondary I2S DOUT
U
Secondary I2S BCLK OUT
E
E
E
V
Secondary I2S WCLK OUT
E
E
E
W
Headphone Detect Input
X
Aux Clock Output
E
E
(1)
(2)
(3)
(4)
(5)
E
E
E
E
S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S(3): The GPIO/MFP5 pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/MFP5 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
9.3.1.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
28
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9.3.2 Analog Audio IO
The analog IO path of the TLV320AIC3204 features a large set of options for signal conditioning as well as signal
routing:
• 6 analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• 2 mixer amplifiers for analog bypass
• 2 low power analog bypass channels
• Mute function
• Automatic gain control (AGC)
• Built in microphone bias
• Stereo digital microphone interface
• Channel-to-channel phase adjustment
• Fast charge of ac-coupling capacitors
• Anti thump
9.3.2.1 Analog Low Power Bypass
The TLV320AIC3204 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation; this configuration supports low-power operation during analog-bypass
mode.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1_L to the
left headphone amplifier (HPL) and IN1_R to HPR.
9.3.2.2 ADC Bypass Using Mixer Amplifiers
In addition to the analog low-power bypass mode, another bypass mode uses the programmable gain amplifiers
of the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line or headphone outputs, fully bypassing the ADC and DAC.
To enable this mode, the mixer amplifiers are powered on via software command.
9.3.2.3 Headphone Outputs
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in singleended AC-coupled headphone configurations, or loads down to 32Ω in differential mode, where a speaker is
connected between HPL and HPR. In single-ended drive configuration these drivers can drive up to 15mW
power into each headphone channel while operating from 1.8V analog supplies. While running from the AVDD
supply, the output common-mode of the headphone driver is set by the common-mode setting of analog inputs in
Page 1, Register 10, Bit D6, to allow maximum utilization of the analog supply range while simultaneously
providing a higher output-voltage swing. In cases when higher output-voltage swing is required, the headphone
amplifiers can run directly from the higher supply voltage on LDOIN input (up to 3.6V). To use the higher supply
voltage for higher output signal swing, the output common-mode can be adjusted to either 1.25V, 1.5V or 1.65V
by configuring Page 1, Register 10, Bits D5-D4. When the common-mode voltage is configured at 1.65V and
LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power into a 16Ω load.
The headphone drivers are capable of driving a mixed combination of DAC signal, left and right ADC PGA signal
and line-bypass from analog input IN1_L and IN1_R by configuring Page 1, Register 12 and Page 1, Register 13
respectively. The ADC PGA signals can be attenuated up to 30dB before routing to headphone drivers by
configuring Page 1, Register 24 and Page 1, Register 25. The analog line-input signals can be attenuated up to
72dB before routing by configuring Page 1, Register 22 and 23. The level of the DAC signal can be controlled
using the digital volume control of the DAC in Page 0, Reg 65 and 66. To control the output-voltage swing of
headphone drivers, the digital volume control provides a range of –6.0dB to +29.0dB (1) in steps of 1dB. These
can be configured by programming Page 1, Register 16 and 17. These level controls are not meant to be used
as dynamic volume control, but to set output levels during initial device configuration. Refer to for
recommendations for using headphone volume control for achieving 0dB gain through the DAC channel with
various configurations.
(1)
If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute.
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9.3.2.4 Line Outputs
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in
the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the
analog input common-mode setting or to 1.65V. With output common-mode setting of 1.65V and DRVdd_HP
supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a
mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable.
9.3.3 ADC
The TLV320AIC3204 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable
oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates from 8kHz to
192kHz. In order to provide optimal system power management, the stereo recording path can be powered up
one channel at a time, to support the case where only mono record capability is required.
The ADC path of the TLV320AIC3204 features a large set of options for signal conditioning as well as signal
routing:
• Two ADCs
• Six analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• Two programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• Two mixer amplifiers for analog bypass
• Two low power analog bypass channels
• Fine gain adjustment of digital channels with 0.1dB step size
• Digital volume control with a range of -12 to +20dB
• Mute function
• Automatic gain control (AGC)
In addition to the standard set of ADC features the TLV320AIC3204 also offers the following special functions:
• Built in microphone bias
• Stereo digital microphone interface
• Channel-to-channel phase adjustment
• Fast charge of ac-coupling capacitors
• Anti thump
• Adaptive filter mode
9.3.3.1 ADC Processing
The TLV320AIC3204 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range. The
decimation filter can be chosen from three different types, depending on the required frequency response, group
delay and sampling rate.
9.3.3.1.1 ADC Processing Blocks
The TLV320AIC3204 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the device.
Table 2 gives an overview of the available processing blocks and their properties. The Resource Class Column
(RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
• AGC
30
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The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column
(RC) gives an approximate indication of power consumption.
Table 2. ADC Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required
AOSR Value
Resource
Class
PRB_R1 (1)
Stereo
A
Yes
0
No
128,64
6
PRB_R2
Stereo
A
Yes
5
No
128,64
8
PRB_R3
Stereo
A
Yes
0
25-Tap
128,64
8
PRB_R4
Right
A
Yes
0
No
128,64
3
PRB_R5
Right
A
Yes
5
No
128,64
4
PRB_R6
Right
A
Yes
0
25-Tap
128,64
4
PRB_R7
Stereo
B
Yes
0
No
64
3
PRB_R8
Stereo
B
Yes
3
No
64
4
(1)
PRB_R9
Stereo
B
Yes
0
20-Tap
64
4
PRB_R10
Right
B
Yes
0
No
64
2
PRB_R11
Right
B
Yes
3
No
64
2
PRB_R12
Right
B
Yes
0
20-Tap
64
2
PRB_R13
Stereo
C
Yes
0
No
32
3
PRB_R14
Stereo
C
Yes
5
No
32
4
PRB_R15
Stereo
C
Yes
0
25-Tap
32
4
PRB_R16
Right
C
Yes
0
No
32
2
PRB_R17
Right
C
Yes
5
No
32
2
PRB_R18
Right
C
Yes
0
25-Tap
32
2
Default
For more detailed information see the TLV320AIC3204 Application Reference Guide, SLAA557.
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9.3.4 DAC
The TLV320AIC3204 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation
filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed
within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and
performance, the TLV320AIC3204 allows the system designer to program the oversampling rates over a wide
range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and
lower oversampling ratios for higher input data rates.
The TLV320AIC3204 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3204 features many options for signal conditioning and signal routing:
• 2 headphone amplifiers
– Usable in single-ended or differential mode
– Analog volume setting with a range of -6 to +29dB
– Class-D mode
• 2 line-out amplifiers
– Usable in single-ended or differential mode
– Analog volume setting with a range of -6 to +29dB
• Digital volume control with a range of -63.5 to +24dB
• Mute function
• Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320AIC3204 also offers the following special features:
• Built in sine wave generation (beep generator)
• Digital auto mute
• Adaptive filter mode
9.3.4.1 DAC Processing Blocks
The TLV320AIC3204 implements signal processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy balancing power conservation
and signal processing flexibility. Less signal processing capability will result in less power consumed by the
device. Table 3 gives an overview over all available processing blocks of the DAC channel and their properties.
The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• 3D – Effect
• Beep Generator
The processing blocks are tuned for typical cases and can achieve high image rejection or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients. The Resource Class Column (RC)
gives an approximate indication of power consumption.
32
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Table 3. Overview – DAC Predefined Processing Blocks
(1)
Processing
Block No.
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
Resource
Class
PRB_P1 (1)
A
Stereo
No
3
No
No
No
8
PRB_P2
A
Stereo
Yes
6
Yes
No
No
12
PRB_P3
A
Stereo
Yes
6
No
No
No
10
PRB_P4
A
Left
No
3
No
No
No
4
PRB_P5
A
Left
Yes
6
Yes
No
No
6
PRB_P6
A
Left
Yes
6
No
No
No
6
PRB_P7
B
Stereo
Yes
0
No
No
No
6
PRB_P8
B
Stereo
No
4
Yes
No
No
8
PRB_P9
B
Stereo
No
4
No
No
No
8
PRB_P10
B
Stereo
Yes
6
Yes
No
No
10
PRB_P11
B
Stereo
Yes
6
No
No
No
8
PRB_P12
B
Left
Yes
0
No
No
No
3
PRB_P13
B
Left
No
4
Yes
No
No
4
PRB_P14
B
Left
No
4
No
No
No
4
PRB_P15
B
Left
Yes
6
Yes
No
No
6
PRB_P16
B
Left
Yes
6
No
No
No
4
PRB_P17
C
Stereo
Yes
0
No
No
No
3
PRB_P18
C
Stereo
Yes
4
Yes
No
No
6
PRB_P19
C
Stereo
Yes
4
No
No
No
4
PRB_P20
C
Left
Yes
0
No
No
No
2
PRB_P21
C
Left
Yes
4
Yes
No
No
3
PRB_P22
C
Left
Yes
4
No
No
No
2
PRB_P23
A
Stereo
No
2
No
Yes
No
8
PRB_P24
A
Stereo
Yes
5
Yes
Yes
No
12
PRB_P25
A
Stereo
Yes
5
Yes
Yes
Yes
12
Default
For more detailed information see the TLV320AIC3204 Application Reference Guide, SLAA557.
9.3.5 PowerTune
The TLV320AIC3204 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application. The TLV320AIC3204 PowerTune
modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback
(DAC) path.
For more detailed information see the TLV320AIC3204 Application Reference Guide, SLAA557.
9.3.6 Digital Audio IO Interface
Audio data flows between the host processor and the TLV320AIC3204 on the digital audio data serial interface,
or audio bus. This very flexible bus includes left or right-justified data options, support for I2S or PCM protocols,
programmable data length options, a TDM mode for multichannel operation, very flexible master-slave
configurability for each bus clock line, and the ability to communicate with multiple devices within a system
directly.
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The audio bus of the TLV320AIC3204 can be configured for left or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0,
Register 27, D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or
Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the
beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this
clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word
lengths, and to support the case when multiple TLV320AIC3204s may share the same audio bus.
The TLV320AIC3204 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.
The TLV320AIC3204 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as
compared to the default clock polarity used. This feature can be used independently of the mode of audio
interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.
The TLV320AIC3204 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3204, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock operation
reduces power consumption. However, it also supports a feature when both the word clocks and bit-clocks can
be active even when the codec in the device is powered down. This continuous clock feature is useful when
using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the
system as general-purpose clocks.
9.3.7 Clock Generation and PLL
The TLV320AIC3204 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for the ADC and DAC
sections. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK,
BCLK or GPIO, the TLV320AIC3204 also provides the option of using the on-chip PLL which supports a wide
range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the
TLV320AIC3204 provides several programmable clock dividers to help achieve a variety of sampling rates for
ADC, DAC and clocks for the processing block.
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3204.
For more detailed information see the TLV320AIC3204 Application Reference Guide, SLAA557.
9.3.8 Control Interfaces
The TLV320AIC3204 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
Changing the state of SPI_SELECT during device operation is not recommended.
34
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9.3.8.1 I2C Control
The TLV320AIC3204 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver
contention.
9.3.8.2 SPI Control
In the SPI control mode, the TLV320AIC3204 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3204) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the TLV320AIC3204 Application Reference Guide, SLAA557.
9.4 Device Functional Modes
The following special functions are available to support advanced system requirements:
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TLV320AIC3204 Application Reference Guide, SLAA557.
9.5 Register Map
Table 4. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2
0x00
0x02
Reserved Register
0
3
0x00
0x03
Reserved Register
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P&R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9-10
0x00
0x09-0x0A
Reserved Register
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15
0x00
0x0F
Reserved Register
0
16
0x00
0x10
Reserved Register
0
17
0x00
0x11
Reserved Register
0
18
0x00
0x12
Clock Setting Register 8, NADC Values
0
19
0x00
0x13
Clock Setting Register 9, MADC Values
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
20
0x00
0x14
ADC Oversampling (AOSR) Register
0
21
0x00
0x15
Reserved Register
0
22
0x00
0x16
Reserved Register
0
23
0x00
0x17
Reserved Register
0
24
0x00
0x18
Reserved Register
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Digital Interface Misc. Setting Register
0
35
0x00
0x23
Reserved Register
0
36
0x00
0x24
ADC Flag Register
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Register
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Sticky Flag Register 3
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Interrupt Flag Register 3
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Register
0
52
0x00
0x34
GPIO/MFP5 Control Register
0
53
0x00
0x35
DOUT/MFP2 Function Control Register
0
54
0x00
0x36
DIN/MFP1 Function Control Register
0
55
0x00
0x37
MISO/MFP4 Function Control Register
0
56
0x00
0x38
SCLK/MFP3 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
0
60
0x00
0x3C
DAC Signal Processing Block Control Register
0
61
0x00
0x3D
ADC Signal Processing Block Control Register
0
62
0x00
0x3E
Reserved Register
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
Left DAC Channel Digital Volume Control Register
0
66
0x00
0x42
Right DAC Channel Digital Volume Control Register
0
67
0x00
0x43
Headset Detection Configuration Register
0
68
0x00
0x44
DRC Control Register 1
0
69
0x00
0x45
DRC Control Register 2
36
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
70
0x00
0x46
DRC Control Register 3
0
71
0x00
0x47
Beep Generator Register 1
0
72
0x00
0x48
Beep Generator Register 2
0
73
0x00
0x49
Beep Generator Register 3
0
74
0x00
0x4A
Beep Generator Register 4
0
75
0x00
0x4B
Beep Generator Register 5
0
76
0x00
0x4C
Beep Generator Register 6
0
77
0x00
0x4D
Beep Generator Register 7
0
78
0x00
0x4E
Beep Generator Register 8
0
79
0x00
0x4F
Beep Generator Register 9
0
80
0x00
0x50
Reserved Register
0
81
0x00
0x51
ADC Channel Setup Register
0
82
0x00
0x52
ADC Fine Gain Adjust Register
0
83
0x00
0x53
Left ADC Channel Volume Control Register
0
84
0x00
0x54
Right ADC Channel Volume Control Register
0
85
0x00
0x55
ADC Phase Adjust Register
0
86
0x00
0x56
Left Channel AGC Control Register 1
0
87
0x00
0x57
Left Channel AGC Control Register 2
0
88
0x00
0x58
Left Channel AGC Control Register 3
0
89
0x00
0x59
Left Channel AGC Control Register 4
0
90
0x00
0x5A
Left Channel AGC Control Register 5
0
91
0x00
0x5B
Left Channel AGC Control Register 6
0
92
0x00
0x5C
Left Channel AGC Control Register 7
0
93
0x00
0x5D
Left Channel AGC Control Register 8
0
94
0x00
0x5E
Right Channel AGC Control Register 1
0
95
0x00
0x5F
Right Channel AGC Control Register 2
0
96
0x00
0x60
Right Channel AGC Control Register 3
0
97
0x00
0x61
Right Channel AGC Control Register 4
0
98
0x00
0x62
Right Channel AGC Control Register 5
0
99
0x00
0x63
Right Channel AGC Control Register 6
0
100
0x00
0x64
Right Channel AGC Control Register 7
0
101
0x00
0x65
Right Channel AGC Control Register 8
0
102
0x00
0x66
DC Measurement Register 1
0
103
0x00
0x67
DC Measurement Register 2
0
104
0x00
0x68
Left Channel DC Measurement Output Register 1
0
105
0x00
0x69
Left Channel DC Measurement Output Register 2
0
106
0x00
0x6A
Left Channel DC Measurement Output Register 3
0
107
0x00
0x6B
Right Channel DC Measurement Output Register 1
0
108
0x00
0x6C
Right Channel DC Measurement Output Register 2
0
109
0x00
0x6D
Right Channel DC Measurement Output Register 3
0
110-127
0x00
0x6E-0x7F
Reserved Register
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
Power Configuration Register
1
2
0x01
0x02
LDO Control Register
1
3
0x01
0x03
Playback Configuration Register 1
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
1
4
0x01
0x04
Playback Configuration Register 2
1
5-8
0x01
0x05-0x08
Reserved Register
1
9
0x01
0x09
Output Driver Power Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
Over Current Protection Configuration Register
1
12
0x01
0x0C
HPL Routing Selection Register
1
13
0x01
0x0D
HPR Routing Selection Register
1
14
0x01
0x0E
LOL Routing Selection Register
1
15
0x01
0x0F
LOR Routing Selection Register
1
16
0x01
0x10
HPL Driver Gain Setting Register
1
17
0x01
0x11
HPR Driver Gain Setting Register
1
18
0x01
0x12
LOL Driver Gain Setting Register
1
19
0x01
0x13
LOR Driver Gain Setting Register
1
20
0x01
0x14
Headphone Driver Startup Control Register
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
IN1_L to HPL Volume Control Register
1
23
0x01
0x17
IN1_R to HPR Volume Control Register
1
24
0x01
0x18
Mixer Amplifier Left Volume Control Register
1
25
0x01
0x19
Mixer Amplifier Right Volume Control Register
1
26-50
0x01
0x1A-0x32
Reserved Register
1
51
0x01
0x33
MICBIAS Configuration Register
1
52
0x01
0x34
Left MICPGA Positive Terminal Input Routing Configuration Register
1
53
0x01
0x35
Reserved Register
1
54
0x01
0x36
Left MICPGA Negative Terminal Input Routing Configuration Register
1
55
0x01
0x37
Right MICPGA Positive Terminal Input Routing Configuration Register
1
56
0x01
0x38
Reserved Register
1
57
0x01
0x39
Right MICPGA Negative Terminal Input Routing Configuration Register
1
58
0x01
0x3A
Floating Input Configuration Register
1
59
0x01
0x3B
Left MICPGA Volume Control Register
1
60
0x01
0x3C
Right MICPGA Volume Control Register
1
61
0x01
0x3D
ADC Power Tune Configuration Register
1
62
0x01
0x3E
ADC Analog Volume Control Flag Register
1
63
0x01
0x3F
DAC Analog Gain Control Flag Register
1
64-70
0x01
0x40-0x46
Reserved Register
1
71
0x01
0x47
Analog Input Quick Charging Configuration Register
1
72-122
0x01
0x48-0x7A
Reserved Register
1
123
0x01
0x7B
Reference Power-up Configuration Register
1
124-127
0x01
0x7C-0x7F
Reserved Register
8
0
0x08
0x00
Page Select Register
8
1
0x08
0x01
ADC Adaptive Filter Configuration Register
8
2-7
0x08
0x02-0x07
Reserved
8
8-127
0x08
0x08-0x7F
ADC Coefficients Buffer-A C(0:29)
9-16
0
0x09-0x10
0x00
Page Select Register
9-16
1-7
0x09-0x10
0x01-0x07
Reserved
9-16
8-127
0x09-0x10
0x08-0x7F
ADC Coefficients Buffer-A C(30:255)
38
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
26-34
0
0x1A-0x22
0x00
Page Select Register
26-34
1-7
0x1A-0x22
0x01-0x07
Reserved.
26-34
8-127
0x1A-0x22
0x08-0x7F
ADC Coefficients Buffer-B C(0:255)
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02-0x07
Reserved
44
8-127
0x2C
0x08-0x7F
DAC Coefficients Buffer-A C(0:29)
45-52
0
0x2D-0x34
0x00
Page Select Register
45-52
1-7
0x2D-0x34
0x01-0x07
Reserved.
45-52
8-127
0x2D-0x34
0x08-0x7F
DAC Coefficients Buffer-A C(30:255)
62-70
0
0x3E-0x46
0x00
Page Select Register
62-70
1-7
0x3E-0x46
0x01-0x07
Reserved.
62-70
8-127
0x3E-0x46
0x08-0x7F
DAC Coefficients Buffer-B C(0:255)
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLV320AIC3204 is a highly integrated stereo audio codec with integrated processing blocks and flexible
digital audio interface options. It enables many different types of audio platforms having a need for stereo audio
record and playback and needing to interface with other devices in the system over a digital audio interface.
10.2 Typical Application
Figure 21 shows a typical circuit configuration for a system using theTLV320AIC3204.
Host Processor
Reset MCLK
SCL
SDA
BCLK
WCLK
DIN
DOUT
SPI_Select
1k
1k
2.7k
MICBIAS
1k
0.1uF
4700pF
0.1uF
LOL
0.1uF
1k
IN1_R
TPA2012
0.1uF Class D Amp
LOR
4700pF
0.1uF
0.1uF
IN1_L
0.1uF
1.9...3.6V
IN2_L
LDOIN
0.1uF 1.0uF 10uF
0.1uF
IN2_R
1.1...3.6V
1k
1k
IOVDD
MFP3/SCLK
0.1uF
IN3_R
HPR
Headset_Mic
Earjack
microphone
and headset
speakers
LDO_SELECT
HPL
AVSS
DVSS
IOVSS
AVDD
DVDD
REF
Headset_Spkr_R 47uF
10 uF
Headset_Spkr_L
Headset_Gnd
10 uF
10 uF
47uF
Figure 21. Typical Circuit Configuration
40
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Typical Application (continued)
10.2.1 Design Requirements
10.2.1.1 Reference Filtering Capacitor
The TLV320AIC3204 has a built-in bandgap used to generate reference voltages and currents for the device. To
achieve high SNR, the reference voltage on REF should be filtered using a 10-μF capacitor from REF terminal to
ground.
10.2.1.2
MICBIAS
The TLV320AIC3204 has a built-in bias voltage output for biasing of microphones. No intentional capacitors
should be connected directly to the MICBIAS output for filtering.
10.2.2 Detailed Design Procedures
10.2.2.1 Analog Input Connection
The analog inputs to TLV320AIC3204 should be ac-coupled to the device terminals to allow decoupling of signal
source's common mode voltage with that of TLV320AIC3204's common mode voltage. The input coupling
capacitor in combination with the selected input impedance of TLV320AIC3204 forms a high-pass filter.
Fc = 1/(2 x π x ReqCc)
Cc = 1/(2 x π x ReqFc)
(1)
(2)
For high fidelity audio recording application it is desirable to keep the cutoff frequency of the high pass filter as
low as possible. For single-ended input mode, the equivalent input resistance Req can be calculated as
Req = Rin x (1 + 2g)/(1+g)
(3)
where g is the analog PGA gain calculated in linear terms.
g = 10000 x 2floor(G/6)/Rin
(4)
where G is the analog PGA gain programmed in P1_R59-R60 (in dB) and Rin is the value of the resistor
programmed in P1_R52-R57 and assumes Rin = Rcm (as defined in P1_R52-R57).
For differential input mode, Req of the half circuit can be calculated as:
Req = Rin
(5)
where Rin is the value of the resistor programmed in P1_R52-R57, assuming symmetrical inputs.
Signal Connector
Device Analog Input
Cc
Req
Rpd
Figure 22. Analog Input Connection With Pull-down Resistor
When the analog signal is connected to the system through a connector such as audio jack, it is recommended
to put a pull-down resistor on the signal as shown in Figure 22. The pulldown resistor helps keep the signal
grounded and helps improve noise immunity when no source is connected to the connector. The pulldown
resistor value should be chosen large enough to avoid loading of signal source.
Each analog input of the TLV320AIC3204 is capable of handling signal amplitude of 0.5 Vrms. If the input signal
source can drive signals higher than the maximum value, an external resistor divider network as shown in
Figure 23 should be used to attenuate the signal to less than 0.5Vrms before connecting the signal to the device.
The resistor values of the network should be chosen to provide desired attenuation as well as Equation 6.
R1|| R2<< Req
(6)
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Typical Application (continued)
Device Analog Input
Signal Connector
Cc
R1
Req
R2
Figure 23. Analog Input Connection With Resistor Divider Network
Whenever any of the analog input terminals IN1_L, IN2_L, IN3_L, IN1_R, IN2_R or IN3_R are not used in an
application, it is recommended to short the unused input terminals together (if convenient) and connect them to
ground using a small capacitor (example 0.1 µF).
10.2.2.2 Analog Output Connection
The line outputs of the TLV320AIC3204 drive a signal biased around the device common mode voltage. To avoid
loading the common mode with the load, it is recommended to connect the single-ended load through an accoupling capacitor. The ac-coupling capacitor in combination with the load impedance forms a high pass filter.
Fc = 1/(2 x π x RLCc)
Cc = 1/(2 x π x RLFc)
(7)
(8)
For high fidelity playback, the cutoff frequency of the resultant high-pass filter should be kept low. For example
with RL of 10 kΩ, using 1-µF coupling capacitor results in a cut-off frequency of 8 Hz.
For differential lineout configurations, the load should be directly connected between the differential outputs, with
no coupling capacitor.
Whenever any of the analog output terminals LOL, LOR, HPL or HPR are not used in an application, they should
be left open or not connected.
42
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Typical Application (continued)
10.2.3 Application Curves
Figure 24 shows the excellent low-distortion performance of the TLV320AIC3204 in a system over the 20-Hz to
20-kHz audio spectrum.
Figure 25 shows the distortion performance of the TLV320AIC3204 in a system over the input amplitude range.
-30
-50
-40
-60
-50
THDN (dB)
THDN (dB)
-70
-80
-90
-60
-70
-80
-100
-90
-110
20
200
2000
20000
-100
-70
-60
Frequency (Hz)
Differential Lineout
Input Amplitude = -3 dBFS
Rload = 10 kΩ
CM = 0.9 V
Figure 24. Total Harmonic Distortion + Noise vs
Input Frequency
-50
-40
-30
-20
Input Amplitude (dBFS)
Differential Lineout
Frequency = 997 Hz
Rload = 10 kΩ
-10
0
D001
CM = 0.9 V
Figure 25. Total Harmonic Distortion + Noise vs
Input Amplitude
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www.ti.com
11 Power Supply Recommendations
Device power consumption largely depends on PowerTune configuration.
The TLV320AIC3204 needs several power supplies for its operation.
The AVDD and LDOIN power inputs are used to power the analog circuits including analog to digital converters,
digital to analog converters, programmable gain amplifiers, headphone amplifiers etc. The analog blocks in
TLV320AIC3204 have high power supply rejection ratio, however it is recommended that these supplies be
powered by well regulated power supplies like low dropout regulators (LDO) for optimal performance. When
these power terminals are driven from a common power source, the current drawn from the source will depend
upon blocks enabled inside the device. However as an example when all the internal blocks powered are
enabled the source should be able to deliver 150mA of current.
The DVDD powers the digital core of TLV320AIC3204, including the audio serial interface, control interfaces (SPI
or I2C), clock generation and PLL. The DVDD power can be driven by high efficiency switching regulators or low
drop out regulators. When the PRB modes are used then the peak current load on DVDD supply source could be
approximately 20 mA.
The IOVDD powers the digital input and digital output buffers of TLV320AIC3204. The current consumption of
this power depends on configuration of digital terminals as inputs or outputs. When the digital terminals are
configured as outputs, the current consumption would depend on switching frequency of the signal and the load
on the output terminal, which depends on board design and input capacitance of other devices connected to the
signal.
Refer to Figure 21 for recommendations on decoupling capacitors.
Refer to the application note SLAA492 for power supply sequencing information.
For more detailed information, see the TLV320AIC3204 Application Reference Guide, SLAA557.
12 Layout
12.1 Layout Guidelines
Each system design and PCB layout is unique. The layout should be carefully reviewed in the context of a
specific PCB design. However, the following guidelines can optimize TLV320AIC3204 performance:
• Connect the thermal pad to ground.
• The decoupling capacitors for the power supplies should be placed close to the device terminals. Figure 21
shows the recommended decoupling capacitors for the TLV320AIC3204.
• The TLV320AIC3204 internal voltage references must be filtered using external capacitors. Place the filter
capacitors on REF near the device terminals for optimal performance.
• For analog differential audio signals, the signals should be routed differentially on the PCB for better noise
immunity. Avoid crossing of digital and analog signals to avoid undesirable crosstalk.
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TLV320AIC3204
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SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
12.2 Layout Example
To Audio
Interface Host
MCLK
BCLK
WCLK
Helps prevent
overshoot and reduce
coupling.
Place near the source.
Starting point: 10 for
MCLK, 27 for others.
DIN
IOVSS
Limit current and voltage for
any audio input exposed to
the outside world (optional)
IOVDD
0.1 F
Trace
Via to ground planes
Via to inner bottom layer plane/trace
SYS I/O Voltage
Inner/bottom layer plane/trace
Keep decoupling
capacitors as close
as possible to
supply pins
DOUT
Top layer ground pour
+1.8V
8
To
Audio
Jack
Rlimit
Add multiple vias to
connect ground planes
throughout the board.
1
9
+1.8V connection only if
LDO_SELECT is low.
32
DVDD
Cin
IN1_L
DVSS
LDOin
16
HPL
25
17
AVDD
IN3_R
IN3_L
+3.3V
To Audio
Jack / Low
Pass Filter
DC Blocking cap
does not need to be
close to the chip.
+1.8V
0.1 F
0.1 F
GND
Mic-
Mic+
GND
- Use differential signaling.
- Keep traces in parallel and close for best
common mode rejection of external noise.
- Place 33pF caps from each input to
ground.
- Route the signal between ground planes
and shield with GND to the sides if routing
through noisy areas such as high speed
clocks and high current traces.
MICBIAS
REF
AVSS
For sensitive signals, if possible:
+3.3V LDOin allows
higher output swing,
more MICBIAS options
and +1.8V generation.
0.1 F
24
17
33pF capacitor close to the
input pin to reduce RF
interference (optional)
+1.8V
0.1 F
Pull down resistor for
de-pop circuit.
+1.8V connection
only if not using
internal analog LDO.
Use a
dedicated
ground
plane from
audio jack to
AVSS.
To Mic Circuit
Figure 26. TLV320AIC3204 Layout
Example layout views can be found in the EVM User Guide:
• http://www.ti.com/tool/TLV320AIC3204EVM-K
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SLOS602E – SEPTEMBER 2008 – REVISED SEPTEMBER 2019
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Texas Instruments, TLV320AIC32x4 Power Supply Sequencing application report
Texas Instruments, Core Voltage Accumulation application report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
PowerTune, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA02197IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AIC
3204
TLV320A3204IRHBRG4
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AIC
3204
TLV320AIC3204IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AIC
3204
TLV320AIC3204IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AIC
3204
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV320AIC3204IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
TLV320AIC3204IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV320AIC3204IRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
TLV320AIC3204IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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