Texas Instruments | TAS5825P 4.5 V to 26.4 V, 38 W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Audio Amplifier with Hybrid-Pro Algorithm | Datasheet | Texas Instruments TAS5825P 4.5 V to 26.4 V, 38 W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Audio Amplifier with Hybrid-Pro Algorithm Datasheet

Texas Instruments TAS5825P 4.5 V to 26.4 V, 38 W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Audio Amplifier with Hybrid-Pro Algorithm Datasheet
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TAS5825P
SLASET9 – OCTOBER 2019
TAS5825P 4.5 V to 26.4 V, 38 W Stereo, Digital Input, High Efficiency Closed-Loop Class-D
Audio Amplifier with Hybrid-Pro Algorithm
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
High-efficiency Class-D operation with Hybrid-Pro:
– Approximately 50% longer battery life
compared to fixed supply voltage solutions
– > 90% Power efficiency, 90 mΩ RDSon
– Low quiescent current, < 20 mA at 12 V PVDD
Supports multiple output configurations:
– 1 × 53 W, 1.0 Mode (4-Ω, 22 V, THD+N=1%)
– 1 × 65 W, 1.0 Mode (4-Ω, 22 V, THD+N=10%)
– 2 × 30 W, 2.0 Mode (8-Ω, 24 V, THD+N=1%)
– 2 × 38 W, 2.0 Mode (8-Ω, 24 V, THD+N=10%)
Excellent audio performance:
– THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V
– SNR ≥ 110 dB (A-weighted), ICN ≤ 35 µVRMS
Flexible audio I/O:
– Supports 32, 44.1, 48, 88.2, 96 kHz SR
– Supports I2S, LJ, RJ, TDM format
– Supports 3-wire digital audio interface
Flexible processing features:
– 3-Band advanced DRC + AGL, 2 × 15 BQs
– PVDD sensing to avoid clipping distortion while
voltage rail drops
– Up to 4 ms lookahead delay buffer for HybridPro algorithm audio signal tracking
– Optional 8 or 16 Hybrid-Pro DC-DC control
steps with max 10 ms peak sample hold
Flexible power supply configurations:
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
Excellent integrated self-protection:
– Over-current error (OCE)
– Cycle-by-cycle current limit
– Over-temperature warning (OTW)
– Over-temperature error (OTE)
– Under, over-voltage lock-out (UVLO, OVLO)
Easy System Integration:
– I2C Software Control
– Reduced solution size:
– Small 5 × 5 mm package
– Fewer passives required compared to
open-loop Class-D devices
– No bulky electrolytic capacitors or large
inductors required for most applications
Battery-powered speaker
Set-top box (STB)
Soundbar or Subwoofer
Wireless or Bluetooth speaker
Heat or efficiency sensitive audio system
3 Description
TAS5825P is a stereo high-efficiency Closed-Loop
audio Class-D audio amplifier with an advanced
Hybrid-Pro algorithm to improve system efficiency
and reduce heat without clipping distortion.
The supply voltage (PVDD) of an audio amplifier is
normally provided by a DC-DC converter. Compared
with a fixed PVDD, a variable PVDD that fluctuates
based on the audio signal significantly improves
efficiency, lowers idle current, and reduces heat.
The powerful audio DSP core of TAS5825P
implements a proprietary algorithm called Hybrid-Pro.
The Hybrid-Pro algorithm detects the upcoming audio
power demand and provides a PWM control signal for
the former DC-DC converter via the Hybrid-Pro
feedback pin (HPFB). The TAS5825P supports up to
4 ms of delay buffer to look ahead at the audio signal
and prevent audio clipping distortion. In various
experiments, the TAS5825P increased the runtime of
1S and 2S batteries by greater than 50% while
continuously playing music.
Device Information(1)
PART NUMBER
PACKAGE
TAS5825P
BODY SIZE (NOM)
VQFN (32) RHB
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TAS5825P
Hybrid-Pro
Hybrid-Pro Control Algorithm
Audio Signal
AMP Left
Delay Buffer
Digital to PWM
AMP Right
Hybrid PWM
Modulation
8-bit ADC
PVDD Sensing
PVDD Feedback Loop Control
Battery
V_battery
DC-DC Converter
FB
LPF &
Matching Resistor
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5825P
SLASET9 – OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
9.5 Programming and Control ....................................... 40
9.6 Register Maps ......................................................... 46
1
1
1
2
3
3
5
10 Application and Implementation........................ 80
10.1 Application Information.......................................... 80
10.2 Typical Applications ............................................. 82
11 Power Supply Recommendations ..................... 87
11.1 DVDD Supply ........................................................ 87
11.2 PVDD Supply ........................................................ 88
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Typical Characteristics ............................................ 10
12 Layout................................................................... 89
12.1 Layout Guidelines ................................................. 89
12.2 Layout Example .................................................... 91
13 Device and Documentation Support ................. 93
13.1
13.2
13.3
13.4
13.5
13.6
Parameter Measurement Information ................ 27
Detailed Description ............................................ 28
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
28
28
29
35
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
93
93
94
94
94
94
14 Mechanical, Packaging, and Orderable
Information ........................................................... 94
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Device Comparison Table
DEVICE NAME
RDS(on)
DSP Audio Process Flows
TAS5825P
90 mΩ
Hybrid-Pro Algorithm for Audio Class-H Envelope Tracking
TAS5825M
90 mΩ
Flexible DSP Process Flows: Smart Amp, Sound Field Spatializer,
192 kHz Processing
TAS5805M
180 mΩ
ROM Fixed Process Flows
6 Pin Configuration and Functions
PGND
PGND
OUT_A-
BST_A-
BST_B-
OUT_B-
PGND
PGND
32
31
30
29
28
27
26
25
RHB Package
32-Pin VQFN
BST_A+
1
24
BST_B+
OUT_A+
2
23
OUT_B+
PVDD
3
22
PVDD
PVDD
4
21
PVDD
DGND
5
20
AGND
DVDD
6
19
AVDD
VR_DIG
7
18
GVDD
ADR
8
17
PDN
Thermal
9
10
11
12
13
14
15
16
GPIO0
GPIO1
GPIO2
LRCLK
SCLK
SDIN
SDA
SCL
Pad
Not to scale
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
DGND
5
P
Digital ground
DVDD
6
P
3.3-V or 1.8-V digital power supply
VR_DIG
7
P
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
ADR
8
AI
A table of resistor value (Pull down to GND) will decide device I2C address. See Table 5.
GPIO0
9
DI/O
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x61h). Can be configured to be CMOS output or Open drain output (HPFB: Hybrid-Pro Feedback, WARNZ or
FAULTZ)
GPIO1
10
DI/O
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x62h). Can be configured to be CMOS output or Open drain output (HPFB: Hybrid-Pro Feedback, WARNZ or
FAULTZ)
GPIO2
11
DI/O
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x63h). Can be configured to be CMOS output or Open drain output (HPFB: Hybrid-Pro Feedback, WARNZ or
FAULTZ)
(1)
AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
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Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
LRCLK
12
DI
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
SCLK (2)
13
DI
Bit clock for the digital signal that is active on the input data line of the serial data port. Sometimes, this pin also be
written as "bit clock (BCLK)"
SDIN
14
DI
Data line to the serial data port
SDA
15
DI/O
SCL
16
DI
I2C serial control clock input
PDN
17
DI
Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
GVDD
18
P
Gate drive internal regulator output. This pin must not be used to drive external devices
AVDD
19
P
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
AGND
20
P
Analog ground
3
P
PVDD
PGND
4
P
21
P
22
P
25
P
26
P
31
P
I2C serial control data interface input/output
PVDD voltage input
Ground reference for power device circuitry. Connect this pin to system ground.
32
P
OUT_B+
23
O
Positive pin for differential speaker amplifier output B
BST_B+
24
P
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+
OUT_B-
27
O
Negative pin for differential speaker amplifier output B
BST_B-
28
P
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-
BST_A-
29
P
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-
OUT_A-
30
O
Negative pin for differential speaker amplifier output A
BST_A+
1
P
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+
OUT_A+
2
O
Positive pin for differential speaker amplifier output A
P
Connect to the system Ground
PowerPAD™
(2)
4
Typically written "bit clock (BCLK)" in some audio codecs.
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7 Specifications
7.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted)
(1)
MIN
MAX
DVDD
Low-voltage digital supply
–0.3
3.9
V
PVDD
PVDD supply
–0.3
30
V
VI(DigIn)
DVDD referenced digital inputs (2)
–0.5 VDVDD + 0.5
V
VI(SPK_OUTxx)
Voltage at speaker output pins
–0.3
32
V
TA
Ambient operating temperature,
–25
85
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
DVDD referenced digital pins include: ADR, GPIO0, GPIO1,GPIO2, LRCLK, SCLK, SDIN,,SCL, SDA, PDN
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DVDD
1.62
3.63
PVDD
4.5
26.4
BTL Mode
3.2
4
PBTL Mode
1.6
2
Ω
1
4.7
µH
V(POWER)
Power supply inputs
RSPK
Minimum speaker load
LOUT
Minimum inductor value in LC filter under short-circuit condition
V
Ω
7.4 Thermal Information
TAS5825P
VQFN (RHB)
32 PINS
THERMAL METRIC (1)
UNIT
JEDEC
STANDARD
2-LAYER PCB
JEDEC
STANDARD
4-LAYER PCB
TAS5825PEVM-4
4-LAYER PCB
RθJA
Junction-to-ambient thermal resistance
N/A
30.0
24.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
N/A
19.1
19.1
°C/W
RθJB
Junction-to-board thermal resistance
N/A
9.9
9.9
°C/W
ψJT
Junction-to-top characterization parameter
N/A
0.2
0.9
°C/W
ψJB
Junction-to-board characterization parameter
N/A
10.5
8.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
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7.5 Electrical Characteristics
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital I/O
|IIH|
Input logic high current level
for DVDD referenced digital
input pins
VIN(DigIn) = VDVDD
|IIL|
Input logic low current level
for DVDD referenced digital
input pins
VIN(DigIn) = 0 V
VIH(Digin)
Input logic high threshold for
DVDD referenced digital
inputs
VIL(Digin)
Input logic low threshold for
DVDD referenced digital
inputs
VOH(Digin)
Output logic high voltage
level
IOH = 4 mA
VOL(Digin)
Output logic low voltage level
IOH = –4 mA
10
µA
–10
µA
70%
VDVDD
30%
80%
VDVDD
VDVDD
20%
VDVDD
400
pF
2
I C Control Port
CL(I2C)
Allowable load capacitance
for each I2C Line
fSCL(fast)
Support SCL frequency
No wait states, fast mode
400
kHz
fSCL(slow)
Support SCL frequency
No wait states, slow mode
100
kHz
Serial Audio Port
tDLY
Required LRCK/FS to SCLK
rising edge delay
DSCLK
Allowable SCLK duty cycle
40%
60%
fS
Supported input sample rates
32
192
fSCLK
Supported SCLK frequencies
32
64
fSCLK
SCLK frequency
5
ns
24.576
kHz
fS
MHz
Speaker Amplifier (All Output Configurations)
toff
Turn-off Time
Excluding volume ramp
ICC
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V, Play mode,
General Audio Process flow with full DSP running
25.5
mA
ICC
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V,Sleep mode
0.87
mA
ICC
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V,Deep Sleep mode
0.82
mA
ICC
Quiescent supply current of
DVDD
PDN = 0.8 V, DVDD = 3.3 V,Shutdown mode
7.4
uA
ICC
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter =
10 µH + 0.68 µF, FSW = 384 kHz, Hybrid
Modulation, Play Mode
29.5
mA
ICC
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter =
22 µH + 0.68 µF, FSW = 384 kHz, Hybrid
Modulation, Play Mode
20.5
mA
ICC
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter =
10 µH + 0.68 µF, FSW = 384 kHz, Output Hiz
Mode
10.7
mA
ICC
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter =
10 µH + 0.68 µF, Fsw = 384 kHz, Sleep Mode
7.26
mA
ICC
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter =
10 µH + 0.68 µF,FSW = 384 khz, Deep Sleep
Mode
12.01
uA
ICC
Quiescent supply current of
PVDD
PDN = 0.8 V, PVDD = 13.5 V, No Load, LC filter =
10 µH + 0.68 µF, FSW = 384 khz, Shutdown Mode
7.8
uA
AV(SPK_AMP)
Programmable Gain
Value represents the "peak voltage" disregarding
clipping due to lower PVDD).
Measured at 0 dB input (1FS)
ΔAV(SPK_AMP)
Amplifier gain error
Gain = 29.5 VP
6
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10
4.87
29.5
0.5
ms
V
dB
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Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
384
kHz
768
kHz
fSPK_AMP
Switching frequency of the
speaker amplifier
RDS(on)
Drain-to-source on resistance
of the individual output
FET + Metallization.
MOSFETs
90
mΩ
Over-Current Error Threshold
7.5
A
Over-Current cycle-by-cycle
limit
6.5
A
OVETHRES(PVDD
PVDD over voltage error
threshold
28
V
UVETHRES(PVDD
PVDD under voltage error
threshold
4.2
V
OTETHRES
Over temperature error
threshold
160
°C
OTEHystersis
Over temperature error
hysteresis
10
°C
OTWTHRES
Over temperature warning
level 1
Read by register 0x73 bit0
112
°C
OTWTHRES
Over temperature warning
level 2
Read by register 0x73 bit1
122
°C
OTWTHRES
Over temperature warning
level 3
Read by register 0x73 bit2
134
°C
OTWTHRES
Over temperature warning
level 4
Read by register 0x73 bit3
146
°C
OCETHRES
Any short to supply, ground, or other channels
Speaker Amplifier (Stereo BTL)
|VOS|
PO(SPK)
THD+NSPK
Amplifier offset voltage
Output Power (Per Channel)
Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz, RSPK =
6 Ω)
ICN(SPK)
ICN(SPK)
ICN(SPK)
Idle channel noise(Aweighted, AES17)
ICN(SPK)
DR
Dynamic range
SNR
Signal-to-noise ratio
Measured differentially with zero input data,
programmable gain configured with 29.5 VP gain,
VPVDD = 16 V
–7.5
7.5
mV
VPVDD = 14.4 V, SPK_GAIN = 29.5 VP, RSPK = 6
Ω, f = 1 KHz THD+N = 10%
17.8
W
VPVDD = 14.4 V, SPK_GAIN = 29.5 VP, RSPK = 6
Ω, f = 1 KHz THD+N = 1%
14.5
W
VPVDD = 24 V, SPK_GAIN = 29.5 VP, RSPK = 8 Ω, f
= 1 KHz THD+N = 10% (Instantaneous Output
Power)
38
W
VPVDD = 24 V, SPK_GAIN = 29.5 VP, RSPK = 8 Ω, f
= 1 KHz THD+N = 1% (Continuous Output Power)
30
W
VPVDD = 12 V, SPK_GAIN = 20.9 VP LC-filter
0.03%
VPVDD = 24 V, SPK_GAIN = 29.5 VP, LC-filter
0.03%
VPVDD = 12 V, LC-filter, Load = 6 Ω, Hybrid
Modulation
32
VPVDD = 12 V, LC-filter, Load = 6 Ω, BD
Modulation
40
VPVDD = 24 V, LC-filter ,Load = 6 Ω, Hybrid
Modualtion
35
VPVDD = 24 V, LC-filter ,Load = 6 Ω, BD
Modualtion
45
µVrms
A-Weighted, -60 dBFS method. PVDD = 24 V,
SPK_GAIN = 29.5 Vp
111
dB
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 24 V
111
dB
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 14.4 V
108
dB
72
dB
100
dB
KSVR
Power supply rejection ratio
Injected Noise = 1 KHz, 1 Vrms, PVDD = 14.4 V,
input audio signal = digital zero
X-talkSPK
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
f = 1 KHz
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Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Speaker Amplifier (Mono PBTL)
PO(SPK)
Output Power
THD+NSPK
Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz
DR
Dynamic range
SNR
Signal-to-noise ratio
8
VPVDD = 19 V, SPK_GAIN = 29.5 VP, RSPK = 3 Ω, f
= 1KHz, THD+N = 1%
50
W
VPVDD = 19 V, SPK_GAIN = 29.5 VP, RSPK = 3 Ω, f
= 1KHz, THD+N = 10%
60
W
VPVDD = 22 V, SPK_GAIN = 29.5 VP, RSPK = 4 Ω, f
= 1KHz, THD+N = 1%
53
W
VPVDD = 22 V, SPK_GAIN = 29.5 VP, RSPK = 4 Ω, f
= 1KHz, THD+N = 10%
65
W
VPVDD = 19 V, SPK_GAIN = 20.9 Vp, LC-filter
RSPK = 3 Ω)
0.03%
VPVDD = 24 V, SPK_GAIN = 29.5 VP, LC-filter
RSPK = 4 Ω)
0.03%
A-Weighted, -60 dBFS method, PVDD=19V
109
dB
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 19 V
109
dB
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 24 V
111
dB
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7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Serial Audio Port Timing – Slave Mode
fSCLK
SCLK frequency
tSCLK
SCLK period
1.024
40
MHz
ns
tSCLKL
SCLK pulse width, low
16
ns
tSCLKH
SCLK pulse width, high
16
ns
tSL
SCLK rising to LRCK/FS edge
8
ns
tLS
LRCK/FS Edge to SCLK rising edge
8
ns
tSU
Data setup time, before SCLK rising edge
8
ns
tDH
Data hold time, after SCLK rising edge
8
ns
tDFS
Data delay time from SCLK falling edge
15
ns
100
kHz
I2C Bus Timing – Standard
ns
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
4.7
µs
tLOW
Low period of the SCL clock
4.7
µs
tHI
High period of the SCL clock
4
µs
tRS-SU
Setup time for (repeated) START condition
4.7
µs
tS-HD
Hold time for (repeated) START condition
4
µs
tD-SU
Data setup time
tD-HD
Data hold time
tSCL-R
250
ns
0
900
ns
Rise time of SCL signal
20 + 0.1CB
1000
ns
tSCL-R1
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
20 + 0.1CB
1000
ns
tSCL-F
Fall time of SCL signal
20 + 0.1CB
1000
ns
tSDA-R
Rise time of SDA signal
20 + 0.1CB
1000
ns
tSDA-F
Fall time of SDA signal
20 + 0.1CB
1000
tP-SU
Setup time for STOP condition
4
ns
µs
I2C Bus Timing – Fast
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
400
tLOW
tHI
kHz
1.3
µs
Low period of the SCL clock
1.3
µs
High period of the SCL clock
600
ns
tRS-SU
Setup time for (repeated)START condition
600
ns
tRS-HD
Hold time for (repeated)START condition
600
ns
tD-SU
Data setup time
100
tD-HD
Data hold time
tSCL-R
ns
0
900
ns
Rise time of SCL signal
20 + 0.1CB
300
ns
tSCL-R1
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
20 + 0.1CB
300
ns
tSCL-F
Fall time of SCL signal
20 + 0.1CB
300
ns
tSDA-R
Rise time of SDA signal
20 + 0.1CB
300
ns
tSDA-F
Fall time of SDA signal
20 + 0.1CB
300
ns
tP-SU
Setup time for STOP condition
tSP
Pulse width of spike suppressed
600
ns
50
ns
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7.7 Typical Characteristics
7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter
used was 10μH / 0.68 μF, unless otherwise noted.
10
10
5 PVcc=7.4V
TA=25qC
2 R L=8:
1
5 PVcc=7.4V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 8Ω
10k
0.001
20
20k
PO = 1W, 2.5W
BTL Mode
1k
Frequency (Hz)
Hybrid Modulation
Load = Ω
FSW = 384 kHz
10k
20k
D002
D301
PO = 1W, 2.5W
BTL Mode
Figure 2. THD+N vs Frequency-BTL
10
10
5 PVcc=7.4V
TA=25qC
2 R L=4:
1
5 PVcc=12V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D300
Figure 1. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
0.001
20
20k
100
D002
D302
PO = 1W, 2.5W
BTL Mode
FSW = 384 kHz
Figure 3. THD+N vs Frequency-BTL
1k
Frequency (Hz)
Hybrid Modulation
Load = 8Ω
10k
20k
D002
D303
PO = 1W,2.5W,5W
BTL Mode
Figure 4. THD+N vs Frequency-BTL
10
10
5 PVcc=12V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
P O=5W
5 PVcc=12V
TA=25qC
2 R L=4:
1
0.5
P O=1W
P O =2.5W
P O=5W
0.5
0.2
THD+N(%)
THD+N(%)
P O=1W
P O =2.5W
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.005
0.01
0.002
0.005
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 6Ω
10k
20k
D002
D304
PO = 1 W,2.5W,5W
BTL Mode
Figure 5. THD+N vs Frequency-BTL
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
20k
D002
D305
PO = 1W
BTL Mode
Figure 6. THD+N vs Frequency-BTL
10
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Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
10
10
5 PVcc=18V
TA=25qC
2 R L=8:
1
5 PVcc=18V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 8Ω
10k
0.001
20
20k
PO = 1W,2.5W,5W
BTL Mode
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 6Ω
10k
20k
D002
D307
PO = 1W,2.5W,5W
BTL Mode
Figure 8. THD+N vs Frequency-BTL
10
10
5 PVcc=18V
TA=25qC
2 R L=4:
1
5 PVcc=24V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D306
Figure 7. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
0.001
20
20k
100
1k
Frequency (Hz)
10k
20k
D002
D309
D002
D308
PO = 1W,2.5W,5W
BTL Mode
FSW = 384 kHz
Hybrid Modulation
Load = 8Ω
PO = 1W,2.5W,5W
BTL Mode
Figure 10. THD+N vs Frequency-BTL
Figure 9. THD+N vs Frequency-BTL
10
10
5 PVcc=24V
TA=25qC
2 R L=6:
1
5 PVcc=24V
TA=25qC
2 R L=4:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
P O=1W
P O =2.5W
P O=5W
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 6Ω
10k
20k
0.001
20
100
D002
D310
PO = 1W,2.5W,5W
BTL Mode
FSW = 384 kHz
Figure 11. THD+N vs Frequency-BTL
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
20k
D002
D311
PO = 1W,2.5W,5W
BTL Mode
Figure 12. THD+N vs Frequency-BTL
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Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
10
10
5 PV CC =7.4V
TA=25qC
2 Fin=1kHz
1
5 PV CC =12V
TA=25qC
2 Fin=1kHz
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
Load= 4:
Load= 6:
Load= 8:
0.005
0.002
0.001
0.01
0.002
0.1
1
0.001
0.01
10
Output Power (W)
FSW = 384 kHz
Hybrid Modulation
Load = 4Ω /6Ω /8Ω
Fin = 1 kHz
BTL Mode
FSW = 384 kHz
10
D007
D112
Hybrid Modulation
Load = 4Ω /6Ω /8Ω
Fin = 1 kHz
BTL Mode
10
5 PV CC =18V
TA=25qC
2 Fin=1kHz
5 PV CC =24V
TA=25qC
2 Fin=1kHz
1
1
0.5
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
Load=4:
Load=6:
Load=8:
0.005
0.002
0.001
0.01
0.1
One channel run
FSW = 384 kHz
Load=4:
Load=6:
Load=8:
0.005
0.002
1
Output Power (W)
10
0.001
0.01
20
0.1
D007
D113
Hybrid Modulation
Load = 4Ω /6Ω /8Ω
Fin = 1 kHz
BTL Mode
One Channel run
FSW = 384 kHz
Figure 15. THD+N vs Output Power-BTL
1
Output Power (W)
10
Hybrid Modulation
Load = 4Ω /6Ω /8Ω
20
D007
D114
Fin = 1 kHz
BTL Mode
Figure 16. THD+N vs Output Power-BTL
60
0
Fsw=384kHz, Hybrid Modulation
-20
40
Crosstalk (dB)
Idle Channel Noise (PVrms)
1
Output Power (W)
Figure 14. THD+N vs Output Power-BTL
10
20
PVDD=12V, Fsw=384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-40
-60
-80
-100
0
5
FSW = 384 kHz
10
15
18
Supply Voltage (V)
20
Hybrid Modulation
Load = 6Ω
-120
20
25
D115
D030
D007
BTL Mode
PVDD=12V
FSW = 384 kHz
Figure 17. Idle Channel Noise vs Supply Voltage
12
0.1
D007
D111
Figure 13. THD+N vs Output Power-BTL
THD+N (%)
Load=4:
Load=6:
Load=8:
0.005
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100
1k
Frequency (Hz)
Hybrid Modulation
Load = 6Ω
10k
20k
D900
D001
D003
BTL Mode
Figure 18. Crosstalk
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SLASET9 – OCTOBER 2019
Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
100
0
90
80
70
-40
Efficiency (%)
Crosstalk (dB)
-20
PVDD=24V, Fsw=384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-60
-80
60
50
40
30
20 TA=25qC
10 R L=4:
BTL Mode
0
0
10
-100
-120
20
100
PVDD=24V
FSW = 384 kHz
1k
Frequency (Hz)
10k
20k
Hybrid Modulation
Load = 6Ω
BTL Mode
30
40
50
Output Power (W)
60
70
D024
D116
Hybrid Modulation
Load = 4Ω
FSW = 384 kHz
BTL Mode
Figure 20. Efficiency vs Output Power
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
20
D901
D001
D003
Figure 19. Crosstalk
60
50
40
30
60
50
40
30
20 TA=25qC
10 R L=6:
BTL Mode
0
0
10
20
PVDD = 7.4V
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
30
40
50
60
Output Power (W)
70
80
90
20 TA=25qC
10 R L=8:
BTL Mode
0
0
10
20
100
TAS5
D024
D117
Hybrid Modulation
Load = 6Ω
FSW = 384 kHz
BTL Mode
90
TAS5825P EVM Efficiency (%)
100
90
70
60
50
40
30
20
RL=4:,BTL
Hybrid Mode
EVM 5V Battery Input
10
Hybrid Pro = Enable
Hybrid Pro = Disable
40
50
60
Output Power (W)
70
80
90
100
D024
D118
BTL Mode
80
70
60
50
40
30
20
RL=6:,BTL
Hybrid Mode
EVM 5V Battery Input
10
0
30
Figure 22. Efficiency vs Output Power
100
80
PVDD = 7.4V
PVDD = 12 V
PVDD = 18 V
PVDD = 24V
Hybrid Modulation
Load = 8Ω
FSW = 384 kHz
Figure 21. Efficiency vs Output Power
TAS5825P EVM Efficiency (%)
PVDD = 7.4V
PVDD = 12 V
PVDD = 18 V
Hybrid Pro = Enable
Hybrid Pro = Disable
0
0
FSW = 384 kHz
Load=4Ω, BTL
5
10
15
20
25
30
Output Power (W)
Hybrid Modulation
5V Battery Input
5V~16V Boost
35
40
45
0
D002
Default PPC3 Setting
(-5.5dB AGAIN)
Figure 23. EVM Efficiency Comparison ON/OFF Hybrid-Pro
FSW = 384 kHz
Load=6Ω, BTL
5
10
15
20
25
30
Output Power (W)
Hybrid Modulation
5V Battery Input
5V~16V Boost
35
40
45
D003
Default PPC3 Setting
(-5.5dB AGAIN)
Figure 24. EVM Efficiency Comparison ON/OFF Hybrid-Pro
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Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
100
TAS5825P EVM Efficiency (%)
90
80
70
60
50
40
30
20
RL=8:,BTL
Hybrid Mode
EVM 5V Battery Input
10
Hybrid Pro = Enable
Hybrid Pro = Disable
0
0
FSW = 384 kHz Load=8Ω, BTL
5
10
15
20
Ourput Power (W)
25
30
Hybrid Modulation
5V Battery Input 5V~16V Boost
35
D004
Default PPC3 Setting (-5.5dB AGAIN)
Figure 25. EVM Efficiency Comparison ON/OFF Hybrid-Pro
14
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7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter
used was 10 μH / 0.68 μF (Pre-Filter PBTL, the merging of the two output channels in this device can be done
before the inductor portion of the output filter, see connect method in MONO (PBTL) Systems), unless
otherwise noted.
10
10
5 PVcc=12V
TA=25qC
2 R L=4:
1
5 PVcc=12V
TA=25qC
2 R L=3:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
0.001
20
20k
PO = 1W,2.5W,5W
PBTL Mode
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 3Ω
10k
20k
D002
D401
PO = 1W,2.5W,5W
PBTL Mode
Figure 27. THD+N vs Frequency-PBTL
10
10
5 PVcc=18V
TA=25qC
2 R L=4:
1
5 PVcc=18V
TA=25qC
2 R L=3:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D400
Figure 26. THD+N vs Frequency-PBTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
0.001
20
20k
100
D002
D402
PO = 1W,2.5W,5W
PBTL Mode
FSW = 384 kHz
Figure 28. THD+N vs Frequency-PBTL
1k
Frequency (Hz)
Hybrid Modulation
Load = 3Ω
10k
20k
D002
D403
PO = 1W,2.5W,5W
PBTL Mode
Figure 29. THD+N vs Frequency-PBTL
10
10
5 PVcc=24V
TA=25qC
2 R L=4:
1
5 PVcc=24V
TA=25qC
2 R L=3:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
P O=1W
P O =2.5W
P O=5W
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 384 kHz
1k
Frequency (Hz)
Hybrid Modulation
Load = 4Ω
10k
20k
0.001
20
100
D002
D404
PO = 1W,2.5W,5W
PBTL Mode
FSW = 384 kHz
Figure 30. THD+N vs Frequency-PBTL
1k
Frequency (Hz)
Hybrid Modulation
Load = 3Ω
10k
20k
D002
D405
PO = 1W,2.5W,5W
PBTL Mode
Figure 31. THD+N vs Frequency-PBTL
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Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation (continued)
10
10
5 PV CC =12V
TA=25qC
2 PBTL Mode
1
5 PV CC =18V
TA=25qC
2 PBTL Mode
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
Load=4:
Load=3:
0.002
0.001
0.01
0.1
FSW = 384 kHz
1
Output Power (W)
10
0.001
0.01
20
0.1
D007
D406
Hybrid Modulation
Load = 4Ω, 3Ω
PBTL Mode
1
Output Power (W)
10
20
D007
D407
Hybrid Modulation
Load = 4Ω, 3Ω
FSW = 384 kHz
Figure 32. THD+N vs Output Power-PBTL
PBTL Mode
Figure 33. THD+N vs Output Power-PBTL
10
100
5 PV CC =24V
TA=25qC
2 PBTL Mode
1
90
80
70
Efficiency (%)
0.5
THD+N (%)
Load=4:
Load=3:
0.002
0.2
0.1
0.05
0.02
60
50
40
30
0.01
20
0.005
Load=4:
Load=3:
0.002
0.001
0.1
0
1
10
20
100
Output Power (W)
FSW = 384 kHz
0
Hybrid Modulation
Load = 4Ω, 3Ω
PBTL Mode
90
TAS5825P EVM Efficiency (%)
100
80
70
60
50
40
30
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
30
40
50
Output Power (W)
60
70
80
D024
D120
Hybrid Modulation
Load = 4Ω
PBTL Mode
Figure 35. Efficiency vs Output Power
90
FSW = 384 kHz
20
FSW = 384 kHz
100
20 TA=25qC
10 R L=3:
PBTL Mode
0
0
10
20
10
D007
D408
Figure 34. THD+N vs Output Power-PBTL
Efficiency (%)
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
TA=25qC
R L=4:
10
80
70
60
50
40
30
20
RL=3:,PBTL
Hybrid Mode
EVM 5V Battery Input
10
Hybrid Pro = Enable
Hybrid Pro = Disable
0
30
40
50
60
Output Power (W)
Hybrid Modulation
Load = 3Ω
70
80
90
100
0
D024
D119
PBTL Mode
FSW = 384 kHz
Load=3Ω, PBTL
5
10
15
20
25
30
Output Power (W)
Hybrid Modulation
5V Battery Input
5V~16V Boost
35
40
45
D005
Default PPC3 Setting
(-5.5dB AGAIN)
Figure 36. Efficiency vs Output Power
Figure 37. EVM Efficiency Comparison ON/OFF Hybrid-Pro
16
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Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation (continued)
100
60
Fsw=384kHz, Hybrid Modulation, PBTL Mode
80
Idle Channel Noise (PVrms)
TAS5825P EVM Efficiency (%)
90
70
60
50
40
30
20
RL=4:,PBTL
Hybrid Mode
EVM 5V Battery Input
10
40
20
Hybrid Pro = Enable
Hybrid Pro = Disable
0
0
0
FSW = 384 kHz
Load=4Ω, PBTL
5
10
15
20
Output Power (W)
Hybrid Modulation
5V Battery Input
5V~16V Boost
25
30
35
5
10
D006
Default PPC3 Setting
(-5.5dB AGAIN)
FSW = 384 kHz
15
18
Supply Voltage (V)
Hybrid Modulation
Load = 6Ω
20
D121
D030
D007
PBTL Mode
Figure 39. Idle Channel Noise vs Supply Voltage
Figure 38. EVM Efficiency Comparison ON/OFF Hybrid-Pro
100
THD+N=1%, R L=4:
THD+N=10%, R L=4:
THD+N=1%, R L=3:
THD+N=10%, R L=3:
90
Output Power (W)
80
70
60
50
40
30
20
10
0
4
6
FSW = 384 kHz
8
10
12
14
16
18
Supply Voltage (V)
20
Hybrid Modulation
Load = 3Ω, 4Ω
22
24
D122
PBTL Mode
Figure 40. Output Power vs Supply Voltage
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7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter
used was 4.7μH / 0.68 μF, unless otherwise noted.
10
10
5 PVcc=5V
TA=25qC
2 BTL Mode
1 Pout=1W
5 PVcc=7.4V
TA=25qC
2 R L=4:
1
Load=2:
Load=4:
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 2Ω, 4Ω
FSW = 768 kHz
10k
0.001
20
20k
PO = 1W
BTL Mode
10k
20k
D002
D201
PO = 1W, 2.5W
BTL Mode
Figure 42. THD+N vs Frequency-BTL
10
5 PVcc=7.4V
TA=25qC
2 R L=6:
1
5 PVcc=7.4V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
0.5
P O=1W
P O =2.5W
0.5
THD+N(%)
THD+N(%)
1k
Frequency (Hz)
BD Modulation
Load = 4Ω
FSW = 768 kHz
10
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 6Ω
FSW = 768 kHz
10k
0.001
20
20k
100
D002
D202
PO = 1W, 2.5W
BTL Mode
1k
Frequency (Hz)
BD Modulation
Load = 8Ω
FSW = 768 kHz
Figure 43. THD+N vs Frequency-BTL
10k
20k
D003
D203
D004
D002
PO = 1W, 2.5W
BTL Mode
Figure 44. THD+N vs Frequency-BTL
10
10
5 PVcc=12V
TA=25qC
2 R L=4:
1
5 PVcc=12V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D200
Figure 41. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 768 kHz
1k
Frequency (Hz)
BD Modulation
Load = 4Ω
10k
20k
0.001
20
100
D002
D204
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
Figure 45. THD+N vs Frequency-BTL
18
P O=1W
P O =2.5W
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1k
Frequency (Hz)
BD Modulation
Load = 6Ω
10k
20k
D002
D205
PO = 1W,2.5W,5W
BTL Mode
Figure 46. THD+N vs Frequency-BTL
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SLASET9 – OCTOBER 2019
Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
10
10
5 PVcc=12V
TA=25qC
2 R L=8:
1
5 PVcc=18V
TA=25qC
2 R L=4:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 8Ω
FSW = 768 kHz
10k
0.001
20
20k
PO = 1W,2.5W,5W
BTL Mode
1k
Frequency (Hz)
BD Modulation
Load = 4Ω
FSW = 768 kHz
10k
20k
D002
D207
PO = 1W,2.5W,5W
BTL Mode
Figure 48. THD+N vs Frequency-BTL
10
10
5 PVcc=18V
TA=25qC
2 R L=6:
1
5 PVcc=18V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D206
Figure 47. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 6Ω
FSW = 768 kHz
10k
0.001
20
20k
100
D002
D208
PO = 1W,2.5W 5W
BTL Mode
1k
Frequency (Hz)
BD Modulation
Load = 8Ω
FSW = 768 kHz
Figure 49. THD+N vs Frequency-BTL
10k
20k
D002
D209
PO = 1W,2.5W,5W
BTL Mode
Figure 50. THD+N vs Frequency-BTL
10
10
5 PVcc=24V
TA=25qC
2 R L=4:
1
5 PVcc=24V
TA=25qC
2 R L=6:
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
1
0.5
THD+N(%)
0.5
THD+N(%)
P O=1W
P O =2.5W
P O=5W
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 768 kHz
1k
Frequency (Hz)
BD Modulation
Load = 4Ω
10k
20k
0.001
20
100
D002
D210
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
Figure 51. THD+N vs Frequency-BTL
1k
Frequency (Hz)
BD Modulation
Load = 6Ω
10k
20k
D002
D211
PO = 1W,2.5W,5W
BTL Mode
Figure 52. THD+N vs Frequency-BTL
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Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
10
10
5 PVcc=24V
TA=25qC
2 R L=8:
1
5 PV CC =7.4V
TA=25qC
2 BTL Mode
1
P O=1W
PO=2.5W
PO=5W
0.5
THD+N (%)
THD+N(%)
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 8Ω
FSW = 768 kHz
10k
0.001
0.01
20k
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
10
D007
D223
BD Modulation
Load = 4Ω, 6Ω, 8Ω
BTL Mode
Figure 54. THD+N vs Output Power-BTL
10
5 PV CC =12V
TA=25qC
2 BTL Mode
1
5 PV CC =18V
TA=25qC
2 BTL Mode
1
0.5
THD+N (%)
0.5
THD+N (%)
1
Output Power (W)
10
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
Load=4:
Load=6:
Load=8:
0.005
0.002
0.001
0.01
Load=4:
Load=6:
Load=8:
0.005
0.002
0.1
FSW = 768 kHz
1
Output Power (W)
0.001
0.01
10
0.1
D007
D222
BD Modulation
Load = 4Ω, 6Ω, 8Ω
BTL Mode
FSW = 768 kHz
Figure 55. THD+N vs Output Power-BTL
1
Output Power (W)
BD Modulation
Load = 4Ω, 6Ω, 8Ω
10
20
D007
D221
Two Channel Run
BTL Mode
Figure 56. THD+N vs Output Power-BTL
10
10
5 PV CC =18V
TA=25qC
2 BTL Mode, 1CH Run
1
5 PV CC =24V
TA=25qC
2 BTL Mode
1
0.5
THD+N (%)
0.5
THD+N (%)
0.1
D002
D212
Figure 53. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
Load=6:
Load=4:
0.002
0.001
0.01
FSW = 768 kHz
Load=4:
Load=6:
Load=8:
0.002
0.1
1
Output Power (W)
BD Modulation
Load =4Ω, 6Ω
10
0.001
0.01
20
D004
D231
D010
D007
1 Channel Run
BTL Mode
FSW = 768 kHz
Figure 57. THD+N vs Output Power-BTL
20
Load=4:
Load=6:
Load=8:
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0.1
1
Output Power (W)
BD Modulation
Load = 4Ω, 6Ω, 8Ω
10
20
D007
D233
2 Channel Run
BTL Mode
Figure 58. THD+N vs Output Power-BTL
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SLASET9 – OCTOBER 2019
Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
10
45
5 PV CC =24V
TA=25qC
2 BTL Mode
1
Output Power (W)
35
0.5
THD+N (%)
THD+N=1%, R L=4:
THD+N=10%, R L=4:
40
0.2
0.1
0.05
0.02
0.01
30
25
20
15
10
0.005
Load=6:
Load=4:
0.002
0.001
0.01
BTL Mode
TA=25qC
5
0
0.1
1
Output Power (W)
10
4
6
8
10
12
14
Supply Voltage (V)
D007
D232
BD Modulation
Load = 4Ω, 6Ω
FSW = 768 kHz
20
1 Channel Run
BTL Mode
16
18 19
D014
D224
D037
Dashed lines represent thermally limited region.
BD Modulation
FSW = 768 kHz
Load = 4Ω
BTL Mode
Figure 59. THD+N vs Output Power-BTL
Figure 60. Output Power vs Supply Voltage
50
45
THD+N=1%, R L=6:
THD+N=10%, R L=6:
45
35
35
Output Power (W)
Output Power (W)
40
30
25
20
15
30
25
20
15
10
10
BTL Mode
TA=25qC
5
BTL Mode
TA=25qC
5
0
0
4
6
8
10
12
14
16
18
Supply Voltage (V)
20
Dashed lines represent thermally limited region.
BD Modulation
FSW = 768 kHz
Load = 6Ω
22
24
4
6
8
10
D014
D007
D037
D225
BTL Mode
12 14 16 18
Supply Voltage (V)
20
22
Dashed lines represent thermally limited region.
BD Modulation
FSW = 768 kHz
Load = 8Ω
Figure 61. Output Power vs Supply Voltage
24
26
D014
D226
D037
BTL Mode
Figure 62. Output Power vs Supply Voltage
72
0
-20
48
Crosstalk (dB)
Idle Channel Noise (PVrms)
THD+N=1%, R L=8:
THD+N=10%, R L=8:
40
24
PVDD=12V, Fsw=768kHz, LC filter=4.7uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-40
-60
-80
-100
A Channel
B Channel
0
5
FSW = 768 kHz
10
15
18
Supply Voltage (V)
BD Modulation
Load = 6Ω
20
-120
20
25
D227
D030
D007
BTL Mode
PVDD=12V
FSW = 768 kHz
Figure 63. Idle Channel Noise vs Supply Voltage
100
1k
Frequency (Hz)
BD Modulation
Load = 6Ω
10k
20k
D902
D001
D003
BTL Mode
Figure 64. Crosstalk
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Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
100
0
90
80
70
-40
Efficiency (%)
Crosstalk (dB)
-20
PVDD=24V, Fsw=768kHz, LC filter=4.7uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-60
-80
60
50
40
30
20 TA=25qC
R L=4:
10
BTL Mode
0
0
-100
-120
20
100
PVDD=12V
FSW = 768 kHz
1k
Frequency (Hz)
10k
20k
BD Modulation
Load = 6Ω
BTL Mode
30
40
D024
D228
BTL Mode
Figure 66. Efficiency vs Output Power
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
20
Output Power (W)
BD Modulation
Load = 4Ω
FSW = 768 kHz
60
50
40
30
60
50
40
30
PVDD = 7.4V
PVDD = 12V
PVDD = 18V
PVDD = 24V
20 TA=25qC
10 R L=6:
BTL Mode
0
0
10
20
30
40
Output Power (W)
50
60
70
BTL Mode
90
TAS5825P EVM Efficiency (%)
100
90
80
70
60
50
40
30
10
Hybrid Pro = Enable
Hybrid Pro = Disable
50
60
D024
D230
BD Modulation
Load = 8Ω
BTL Mode
80
70
60
50
40
30
20
RL=6:,BTL
BD Mode
EVM 5V Battery Input
10
0
30
40
Output Power (W)
Figure 68. Efficiency vs Output Power
100
RL=4:,BTL
BD Mode
EVM 5V Battery Input
20
FSW = 768 kHz
Figure 67. Efficiency vs Output Power
20
PVDD = 7.4V
PVDD = 12V
PVDD = 18V
PVDD = 24V
20 TA=25qC
10 R L=8:
BTL Mode
0
0
10
D024
D229
BD Modulation
Load = 6Ω
FSW = 768 kHz
TAS5825P EVM Efficiency (%)
10
D903
D001
D003
Figure 65. Crosstalk
Hybrid Pro = Enable
Hybrid Pro = Disable
0
0
FSW = 384 kHz
Load=4Ω, BTL
5
10
15
20
25
30
Output Power (W)
BD Modulation
5V Battery Input
5V~16V Boost
35
40
45
0
D007
Default PPC3 Setting
(-5.5dB AGAIN)
Figure 69. EVM Efficiency Comparison ON/OFF Hybrid-Pro
22
PVDD = 4.5V
PVDD = 7.4 V
PVDD = 12 V
PVDD = 18V
FSW = 384 kHz
Load=6Ω, BTL
5
10
15
20
25
30
Output Power (W)
BD Modulation
5V Battery Input
5V~16V Boost
35
40
45
D008
Default PPC3 Setting
(-5.5dB AGAIN)
Figure 70. EVM Efficiency Comparison ON/OFF Hybrid-Pro
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Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
100
TAS5825P EVM Efficiency (%)
90
80
70
60
50
40
30
20
RL=8:,BTL
BD Mode
EVM 5V Battery Input
10
Hybrid Pro = Enable
Hybrid Pro = Disable
0
0
5
10
15
20
Output Power (W)
25
30
BD Modulation
5V Battery Input 5V~16V Boost
FSW = 384 kHz Load=8Ω, BTL
35
D009
Default PPC3 Setting (-5.5dB AGAIN)
Figure 71. EVM Efficiency Comparison ON/OFF Hybrid-Pro
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7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter
used was 4.7 μH / 0.68 μF (Pre-Filter PBTL, the merging of the two output channels in this device can be done
before the inductor portion of the output filter, see details in MONO (PBTL) Systems), unless otherwise noted.
10
10
5 PVcc=12V
TA=25qC
2 R L=3:
1
5 PVcc=12V
TA=25qC
2 R L=4:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 3Ω
FSW = 768 kHz
10k
0.001
20
20k
PO = 1W,2.5W,5W
PBTL Mode
10k
20k
D002
D236
PO = 1W,2.5W,5W
PBTL Mode
Figure 73. THD+N vs Frequency-PBTL
10
5 PVcc=18V
TA=25qC
2 Load=3:
1 PBTL Mode
5 PVcc=18V
TA=25qC
2 R L=4:
1 PBTL Mode
P O=1W
PO=2.5W
PO=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
1k
Frequency (Hz)
BD Modulation
Load = 4Ω
FSW = 768 kHz
10
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
1k
Frequency (Hz)
BD Modulation
Load = 3Ω
FSW = 768 kHz
10k
0.001
20
20k
100
D002
D237
PO = 1W,2.5W,5W
PBTL Mode
1k
Frequency (Hz)
BD Modulation
Load = 4Ω
FSW = 768 kHz
Figure 74. THD+N vs Frequency-PBTL
10k
20k
D002
D238
PO = 1W,2.5W,5W
PBTL Mode
Figure 75. THD+N vs Frequency-PBTL
10
10
P O=1W
P O =2.5W
P O=5W
5 PVcc=24V
TA=25qC
2 R L=3:
1 PBTL Mode
5 PVcc=24V
TA=25qC
2 R L=4:
1 PBTL Mode
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D235
Figure 72. THD+N vs Frequency-PBTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
FSW = 768 kHz
1k
Frequency (Hz)
BD Modulation
Load = 3Ω
10k
20k
0.001
20
100
D002
D239
PO = 1W,2.5W,5W
PBTL Mode
FSW = 768 kHz
Figure 76. THD+N vs Frequency-PBTL
24
P O=1W
PO=2.5W
PO=5W
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1k
Frequency (Hz)
BD Modulation
Load = 4Ω
10k
20k
D002
D240
PO = 1W,2.5W,5W
PBTL Mode
Figure 77. THD+N vs Frequency-PBTL
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SLASET9 – OCTOBER 2019
Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation (continued)
10
10
5 PV CC =12V
TA=25qC
2 PBTL Mode
1
5 PV CC =18V
TA=25qC
2 PBTL Mode
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
Load=3:
Load=4:
0.002
0.001
0.01
0.1
1
Output Power (W)
10
0.001
0.01
20
PBTL Mode
Output Power (W)
5 PV CC =24V
TA=25qC
2 PBTL Mode
1
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.01
0.005
Load=4:
Load=3:
0.1
1
Output Power (W)
10
100
PBTL Mode
20
D007
D242
PBTL Mode
THD+N=1%, R L=3:
THD+N=10%, R L=3:
PBTL Mode
TA=25qC
4
6
FSW = 768 kHz
Figure 80. THD+N vs Output Power-PBTL
8
10
12
14
Supply Voltage (V)
16
18
20
D014
D244
D037
BD Modulation
Load = 3Ω
PBTL Mode
Figure 81. Output Power vs Supply Voltage
100
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
THD+N=1%, R L=4:
THD+N=10%, R L=4:
90
80
70
Efficiency (%)
Output Power (W)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
D007
D243
BD Modulation
Load = 3Ω, 4Ω
FSW = 768 kHz
20
10
Figure 79. THD+N vs Output Power-PBTL
10
0.001
0.01
1
Output Power (W)
BD Modulation
Load = 3Ω, 4Ω
FSW = 768 kHz
Figure 78. THD+N vs Output Power-PBTL
0.002
0.1
D007
D241
BD Modulation
Load = 3Ω, 4Ω
FSW = 768 kHz
Load=3:
Load=4:
0.002
60
50
40
30
PBTL Mode
TA=25qC
4
6
FSW = 768 kHz
8
10
12
14
16
18
Supply Voltage (V)
BD Modulation
Load = 4Ω
20
22
24
20 TA=25qC
10 R L=3:
PBTL Mode
0
0
10
D014
D245
D037
PBTL Mode
FSW = 768 kHz
Figure 82. Output Power vs Supply Voltage
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
20
30
40
Output Power (W)
BD Modulation
Load = 3Ω
50
60
D024
D246
PBTL Mode
Figure 83. Efficiency vs Output Power
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Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation (continued)
100
90
90
TAS5825P EVM Efficiency (%)
100
80
Efficiency (%)
70
60
50
40
30
20 TA=25qC
10 R L=4:
PBTL Mode
0
0
10
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
80
70
60
50
40
30
20
RL=3:,PBTL
BD Mode
EVM 5V Battery Input
10
Hybrid Pro = Enable
Hybrid Pro = Disable
0
20
30
Output Power (W)
40
0
50
5
10
D024
D247
BD Modulation
FSW = 768 kHz
Load = 3Ω, PBTL
5V EVM Battery with default PPC3 setting (-5.5dB AGAIN)
Figure 84. Efficiency vs Output Power
FSW = 384 kHz
Load=3Ω, PBTL
15
20
25
30
Output Power (W)
BD Modulation
5V Battery Input
5V~16V Boost
35
40
45
D010
Default PPC3 Setting
(-5.5dB AGAIN)
Figure 85. EVM Efficiency Comparison ON/OFF Hybrid-Pro
80
100
80
Idle Channel Noise (PVrms)
TAS5825P EVM Efficiency (%)
90
70
60
50
40
30
20
RL=4:,PBTL
BD Mode
EVM 5V Battery Input
10
60
40
20
Hybrid Pro = Enable
Hybrid Pro = Disable
Fsw=768kHz, PBTL Mode
0
0
0
FSW = 384 kHz
Load=4Ω, PBTL
5
10
15
20
Output Power (W)
BD Modulation
5V Battery Input
5V~16V Boost
25
30
35
5
D011
Default PPC3 Setting
(-5.5dB AGAIN)
FSW = 768 kHz
10
15
18
Supply Voltage (V)
BD Modulation
Load =4Ω
20
25
D248
D030
D007
PBTL Mode
Figure 87. Idle Channel Noise vs Supply Voltage
Figure 86. EVM Efficiency Comparison ON/OFF Hybrid-Pro
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8 Parameter Measurement Information
LRCK/FS
(Input)
0.5 × DVDD
tSCLKH
tSCLKL
tLS
SCLK
(Input)
0.5 × DVDD
tSCLK
tSL
DATA
(Input)
0.5 × DVDD
tSU
tDH
tDFS
DATA
(Output)
0.5 × DVDD
Figure 88. Serial Audio Port Timing in Slave Mode
Repeated
START
START
tD-SU
SDA
STOP
tD-HD
tSDA-F
tSDA-R
tP-SU
tBUF.
tSCL-R.
tRS-HD
tSP
tLOW.
SCL
tHI.
tRS-SU
tS-HD.
tSCL-F.
Figure 89. I2C Communication Port Timing Diagram
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9 Detailed Description
9.1 Overview
TAS5825P is a proprietary and comprehensive device to provide excellent audio performance and high system
efficiency when paired with an external DC-DC converter. Audio performance is specified by the coherent whole
signal path: digital I/O and processor, stereo digital to PWM modulator and Closed-Loop Class-D amplifier.
Hybrid-Pro algorithm improves audio system efficiency by controlling the external supply voltage and maintaining
just enough margin to provide high dynamic range without clipping distortion to save as much power as possible.
More details can be found: Digital Audio Processing.
•
•
•
Digital I/O and processor: I2C control, serial audio port, three digital GPIO pins, audio DSP subsystem with
Hybrid-Pro algorithm and rich audio processing blocks.
A stereo digital to PWM modulator.
A flexible Closed-Loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the
audio amplifier. Two internal LDOs generate 5 V / 1.5 V for analog / digital supply voltage respectively.
9.2 Functional Block Diagram
4.5-24V
3.3/1.8V
DVDD
VR_DIG
AVDD
LDO 1.5V
PVDD1/2/3/4
LDO 5V
BST_A+
Close Loop Feedback
ADR
IO
OUT_A+
PDN
GPIO0
GPIO1
GPIO2
I2S/TDM
OUT_A-
Audio DSP
Subsystem
Digital to PWM
Conversion
SDA
SCL
SDIN
Digital
Modulator
H Bridge
&
Gate Driver
&
OC/DC Protect
BST_A-
BST_BOUT_BBST_B+
LRCLK
SCLK
PLL & OSC
LDO 5V
Close Loop Feedback
DGND
AGND
OUT_B+
(PVDD to GVDD)
GVDD
PGND 1/2/3/4
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9.3 Feature Description
9.3.1 Power Supplies
For system design, TAS5825P needs one 3.3-V or 1.8-V digital supply and another power-stage supply. Two
internal voltage regulators provide suitable voltage levels for the gate drive circuitry and internal circuitry. The
external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply.
Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the
device. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only a few external capacitors. To provide good electrical
and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent
half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive voltages
(GVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors
as close to their associated pins as possible. In general, inductance between the power-supply pins and
decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic capacitor
must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the powerstage output is low, the bootstrap capacitor is charged through an internal diode connected between the gatedrive regulator output pin (GVDD) and the bootstrap pin. When the power-stage output is high, the bootstrap
capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the highside gate driver.
9.3.2 Device Clocking
The TAS5825P devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
Audio In
LRCLK/FS
DSPCLK
Serial Audio
Interface (Input)
DSP
(Including
interpolator)
DACCLK
OSRCLK
Delta Sigma
Modulator
DAC
Figure 90. Audio Flow with Respective Clocks
Figure 90 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
• SCLK (Bit Clock)
• LRCLK/FS (Left/Right Word Clock or Frame Sync)
• SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP
and the DAC clock.
The TAS5825P device has an audio sampling rate detection circuit that automatically senses which frequency
the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96
kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
If the input LRCLK/SCLK stopped during music playing, the TAS5825P DSP switches to sleep state and waiting
for the clock recovery (Class D output switches to Hiz automatically), once LRCLK/SCLK recovered, TAS5825P
auto recovers to the play mode. There is no need to reload the DSP code.
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Feature Description (continued)
9.3.3 Serial Audio Port – Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the TAS5825P device with SCLK. The LRCLK/FS pin is the serial audio
left/right word clock or frame sync when the device is operated in TDM Mode.
Table 1. Audio Data Formats, Bit Depths and Clock Rates
FORMAT
2
I S/LJ/RJ
TDM
DATA BITS
MAXIMUM LRCLK/FS FREQUENCY
(kHz)
SCLK RATE (fS)
32, 24, 20, 16
32 to 92
64, 32
32
128
44.1,48
128,256,512
96
128,256
32, 24, 20, 16
When Clock halt, non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register
113 (Register Address 0x71).
9.3.4 Clock Halt Auto-recovery
As some of host processor halts the I2S clock when there is no audio playing. When Clock halt, the device puts
all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio
clocks recovery, the device automatically returns to the previous state.
9.3.5
Sample Rate on the Fly Change
TAS5825P supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32 kHz to 48 kHz or
96 kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 10ms before changing to the
new sample rate.
9.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (Register Address 0x33h -D[5:4]). If the high width of
LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (Register Address 0x33h -D[3:2]) should
set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted.
All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats
are detailed in Figure 91 through Figure 95. The word length are selected via Register (Register Address 0x33h D[1:0]). The offsets of data are selected via Register (Register Address 0x33h -D[7]) and Register (Register
Address 0x34h -D[7:0]). Default setting is I2S and 24 bit word length.
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1 tS
LRCLK/FS
Right-channel
Left-channel
SCLK
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1 2
15 16
MSB
1 2
LSB
15 16
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1 2
1 2
23 24
MSB
LSB
23 24
MSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1 2
31 32 1 2
MSB
31 32
MSB
LSB
LSB
Figure 91. Left Justified Audio Data Format
1 tS
LRCLK/FS
Right-channel
Left-channel
SCLK
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1 2
15 16
MSB
1 2
LSB
15 16
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1 2
1 2
23 24
MSB
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1 2
31 32 1 2
MSB
LSB
31 32
MSB
LSB
2
I S Data Format; L-channel = LOW, R-channel = HIGH
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 92. I2S Audio Data Format
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1 tS
LRCLK/FS
Right-channel
Left-channel
SCLK
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1 2
15 16
MSB
1 2
LSB
15 16
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1 2
1 2
23 24
MSB
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1 2
31 32 1 2
MSB
31 32
MSB
LSB
LSB
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 93. Right Justified Audio Data Format
1 /fS .
LRCK/FS
«
SCLK
«
«
«
«
Audio data word = 16-bit, Offset = 0
DATA
1
2
«
15 16 1
Data Slot 1
LSB
MSB
Audio data word = 24-bit, Offset = 0
- ,
«
1 2
DATA
«
2
15 16
1
Data Slot 2
LSB
MSB
23 24 1
2
«
23 24
1
Data Slot 1
LSB
MSB
LSB
MSB
Audio data word = 32-bit, Offset = 0
DATA
1
2
«
31 32 1
2
«
LSB
MSB
31 32
1
LSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 94. TDM 1 Audio Data Format
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1 /fS .
LRCK/FS
OFFSET = 1
«
SCLK
«
«
«
«
Audio data word = 16-bit, Offset = 1
DATA
1
«
2
MSB
15 16 1
Data Slot 1
LSB
MSB
«
2
15 16
1
Data Slot 2
LSB
Audio data word = 24-bit, Offset = 1
DATA
1
2
23 24 1
«
2
Data Slot 1
23 24
1
Data Slot 2
LSB
MSB
«
LSB
MSB
Audio data word = 32-bit, Offset = 1
DATA
1
«
2
31 32 1
Data Slot 1
2
«
1
Data Slot 2
LSB
MSB
31 32
LSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 95. TDM 2 Audio Data Format
9.3.7 Digital Audio Processing
TAS5825P digital audio processing includes three main functions: basic audio tuning blocks, Hybrid-Pro
algorithm and advanced features.
Basic audio tuning blocks are SRC (sample rate converter), stereo channel Input Mixer, 15 BQs for each
channel, pop click free Volume, multi-bands DRC, and AGL. Detailed introduction of each block can be found
with TAS5825M Process Flows.
Hybrid-Pro can be used in conjunction with Hybrid Modulation, which is an innovative Class-D internal PWM
modulation scheme to improve efficiency even more without compromising THD+N performance. Hybrid-Pro
goes beyond Hybrid PWM modulation from system efficiency perspective, by tracking audio signal envelope with
advanced look-ahead DSP structure, controlling the external PVDD supply voltage rail, and maintaining just
enough margin to provide high dynamic range without clipping distortion to save as much power as possible.
Refer TAS5825P User Guide for more configurable options:
•
•
•
•
Optional 8 steps 384 kHz PWM format or 16 steps 192kHz PWM format Hybrid-Pro control waveform for
external DC-DC converter.
Configurable max 4ms look-ahead audio signal delay buffer, which provides capability to fit various
applications systems' DC-DC bandwidth and power supply coupling capacitance.
Max 512 samples audio signal peak hold to optimize power supply voltage rail transition from large audio
input to small level, which is useful to avoid clipping distortion.
Hybrid-Pro Margin automatically adjusts audio signal trigger level and each step level. Fine tune it to achieve
the balance between efficiency and envelope tracking speed.
Advanced features include PVDD Sensing (Dynamic Headroom Tracking), Thermal Foldback and Hybrid PWM
modulation. They are implemented based on integrated 8-bit PVDD sense ADC and 4 level temperature sensor.
Refer to application note:TAS5825M Advanced Features.
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9.3.8 Class-D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker
amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and
increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D
amplifier section of the device. The gain structures are discussed in detail below for both Figure 96 and Table 2.
The switching rate of the amplifier is configurable by register (Register Address 0x02h -D[6:4])
9.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As seen
in Figure 96, the audio path of the TAS5825P consists of a digital audio input port, a digital audio path, a digital
to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds the
output information back into the DPC block to correct for distortion sensed on the output pins. The total amplifier
gain is comprised of digital gain, shown in the digital audio path and the analog gain from the input of the analog
modulator to the output of the speaker amplifier power stage.
Analog
Analog Gain
Gain
Digital
Digital Gain
Gain
Closed
Closed Loop
Loop Class
Class DD Amplifier
Amplifier
Gate
Gate
Drivers
Drivers
Serial
Serial
Audio
Audio In
In
Serial
Serial
Audio
Audio
Port
Port
Audio
Audio Processing
Processing
(Flexible
(FlexibleAudio
AudioProcess
ProcessFlows)
Flows)
SCL
SDA
SPK_OUTASPK_OUTA-
Digital
Digital to
to PWM
PWM
Conversion
Conversion
Gate
Gate
Drivers
Drivers
I2C
I2C Interface
Interface
SPK_OUTA+
SPK_OUTA+
Full
Full Bridge
Bridge Power
Power
Stage
Stage
AA
Control
Control Register
Register
SPK_OUTB+
SPK_OUTB+
Full
Full Bridge
Bridge Power
Power
Stage
Stage
BB
SPK_OUTBSPK_OUTB-
Closed
Closed Loop
Loop Class
Class DD Amplifier
Amplifier
Copyright
Copyright©
©2017,
2017,Texas
TexasInstruments
InstrumentsIncorporated
Incorporated
Figure 96. Speaker Amplifier Gain
As shown in Figure 96, the first gain stage for the speaker amplifier is present in the digital audio path. It consists
of the volume control and the digital boost block. The volume control is set to 0 dB by default, it does not change.
For all settings of the register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These gain settings
ensure that the output signal is not clipping at different PVDD levels. 0dBFS output is 29.5-V peak output voltage
Table 2. Analog Gain Setting
AGAIN <4:0>
GAIN (dBFS)
00000
0
AMPLIFIER OUTPUT PEAK VOLTAGE (V)
29.5
00001
-0.5
27.85
…….
……..
…….
11111
-15.5
4.95
9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
closed loop structure provides Loop bandwidth setting option (Setting by register 83 -Register address 0x53hD[6-5]) to co-work with different switching frequency (Setting by register 2 -Register address 0x02h-D[6-4] ).
Table 3 shows recommended settings for the Loop Bandwidth and Switching Frequency selection. Same Fsw,
Better THD+N performance with higher BW.
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Table 3. Loop Bandwidth and Switching Frequency Setting
Modulation
Scheme
Hybrid, 1SPW
BD
Fsw
BW (Loop Band Width)
384kHz
80kHz
480kHz
80kHz, 100kHz
576kHz
80kHz, 100kHz, 120kHz
768kHz
80kHz, 100kHz, 120kHz, 175kHz
384kHz
80kHz, 100kHz, 120kHz
480kHz
80kHz, 100kHz, 120kHz
576kHz
80kHz, 100kHz, 120kHz, 175kHz
768kHz
80kHz, 100kHz, 120kHz, 175kHz
Notes
Principle: Fsw (Switching Frequency) ≥ 4.2 × Loop
Bandwidth
Principle: Fsw (Switching Frequency) ≥ 3 × Loop
Bandwidth
9.4 Device Functional Modes
9.4.1 Software Control
The TAS5825P device is configured via an I2 C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections.
There are two methods to program TAS5825P DSP memory.
• Loading with I2C Communication Port by host processor. This method is recommend for most of applications.
• Fast loading from external EEPROM with SPI communication Port. This method can be used in some
applications which need fast loading to save initialization time or release the Host Controller's loading.
TAS5825P supports to load the DSP memory data from external EEPROM via SPI. The GPIOs can be
configured as SI,SO and SCK for EEPROM via Register (0x60,0x61,0x62,0x63,0x64). The chip selection CS
of EEPROM is controlled by the Host Processor. See application note: Load TAS5825M Configurations from
EEPROM via SPI.
9.4.2 Speaker Amplifier Operating Modes
The TAS5825P device can be used with two different amplifier configurations, can be configured by Register
0x02h -D[2]:
• BTL Mode
• PBTL Mode
9.4.2.1 BTL Mode
In BTL mode, the TAS5825P amplifies two independent signals, which represent the left and right portions of a
stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+ and OUT_A-,
the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.
9.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
TAS5825P device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive
inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the TAS5825P device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
9.4.3 Low EMI Modes
TAS5825P employs several modes to minimize EMI during playing audio, and they can be used based on
different applications.
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Device Functional Modes (continued)
9.4.3.1 Spread Spectrum
Spread spectrum is used in some inductor free case to minimize EMI noise. The TAS5825P supports Spread
Spectrum with triangle mode.
User need configure register SS_CTRL0 (0x6B) to Enable triangle mode and enable spread spectrum, select
spread spectrum frequency and range with SS_CTRL1 (0x6C). For 384kHz FSW which configured by
DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in Table 4.
Table 4. Triangle Mode Spread Spectrum Frequency and Range Selection
SS_TRI_CTRL[3:0]
0
1
Triangle Freq
Spread Spectrum
Range
2
3
4
5
24k
5%
10%
6
7
20%
25%
48k
20%
25%
5%
10%
User Application example: Central Switching Frequency is 384kHz, Triangle Frequency is 24kHz.
Register 0x6b = 0x03 // Enable Spread Spectrum
Register 0x6c = 0x03 // SS_CTRL[3:0]=0011, Triangle Frequency = 24kHz, Spread Spectrum Range should be
25% (336kHz~432kHz)
9.4.3.2 Channel to Channel Phase Shift
This device supports channel to channel 180-degree PWM phase shift to minimize the EMI. Bit 0 of Register
0x53 can be used to disable or enable the phase shift. If better pop/click performance is needed, then it is
suggested to disable this function with BD mode.
NOTE
Channel to Channel Phase Shift and Multi-Devices PWM Phase Synchronization only
works in BD Modulation, but inoperative in 1SPW Modulation and Hybrid Modulation.
9.4.3.3 Multi-Devices PWM Phase Synchronization
TAS5825P support up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 TAS5825P devices, user can select phase0/1/2/3 for each device by register
PHASE_CTRL(0x6A), which means there is a 45 degree phase shift between each device to minimize the EMI.
There are two methods for Multi-Device PWM phase synchronization. Phase Synchronization With I2S Clock In
Startup Phase or Phase Synchronization With GPIO.
9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
1. Step 1, Halt I2S clock.
2. Step 2, Configure each device phase selection and enable the phase synchronization. For example: Register
0x6A=0x03 for device 0; Register 0x6A=0x07 for device 1; Register 0x6A=0x0B for device 2; Register
0x6A=0x0F for device 3.
3. Step 3, Configure each device into HIZ mode.
4. Step 4, Provide I2S to each device. Phase synchronization for all 4 devices is automatically done by internal
sequence.
5. Step 5, Initialize the DSP code (This step can be skipped if only need to do the Phase Synchronization).
6. Step 6, Device to Device PWM phase shift should be fixed with 45 degree.
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9.4.3.3.2 Phase Synchronization With GPIO
1. Step 1, Connect GPIOx pin of each device to SOC's GPIO pin on PCB.
2. Step 2, Configure each device GPIOx as phase sync input usage by registers GPIO_CTRL (0X60) and
GPIO_INPUT_SEL (0x64).
3. Step 3, Select different phase for each device and enable phase synchronization by register PHASE_CTRL
(0x6A).
4. Step 4, Configure each device into PLAY mode by register DEVICE_CTRL2 (0x03) and monitor the
POWER_STATE register (0x68) until device changed to HIZ state.
5. Step 5, Give a 0 to 1 toggle on SOC GPIO. Then all 4 devices enters into PLAY mode and device to Device
PWM phase shift should be fixed with 45 degree.
6. Step 6, Phase Synchronization has been finished. Configure the GPIOx pin to other function based on the
application.
9.4.4 Thermal Foldback
The Thermal Foldback (TFB), is designed to protect TAS5825P from excessive die temperature increases, in
case the device operates beyond the recommended temperature/power limit, or with a weaker thermal system
design than recommended. It allows the TAS5825P to play as loud as possible without triggering unexpected
thermal shutdown. When the die temperature triggers the over-temperature warning (OTW) level (TAS5825P has
four different temperature threshold, each threshold is indicated in I2C register 0x73 bits 0,1,2 and 3 ), an internal
AGL (Automatic Gain Limiter) reduces the digital gain gradually, lower value of OTW, smaller attenuation added,
with the OTW waring goes higher, more attenuation added. Once the die temperature drops below the OTW, the
device’s digital gain gradually returns to the former setting. Both the attenuation gain and adjustable rate are
programmable. The TFB gain regulation speed (attack rate and release rate) settings are the same as a regular
AGL, which is also configurable with TAS5825P App in PurePathTM Console3.
9.4.5 Device State Control
Except Shutdown Mode, TAS5825P has other 4 states for different power dissipation which listed in the Electrical
Characteristics Table.
• Deep Sleep Mode. Register 0x03h -D[1:0]=00, Device stays in Deep Sleep Mode. In this mode, I2 C block
keep works. This mode can be used to extend the battery life time in some portable speaker application case,
once the host processor stopped playing audio for a long time, TAS5825P can be set to Deep Sleep Mode to
minimize power dissipation until host processor start playing audio again. Device returns back to Play Mode
by setting Register 0x03h -D[1:0] to 11. Compare with Shutdown Mode (Pull PDN Low), enter or exit Deep
Sleep Mode, DSP keeps active.
• Sleep Mode. Register 0x03h -D[1:0]=01, Device stays in Sleep Mode. In this mode, I2 C block, Digital core,
DSP Memory , 5V Analog LDO keep works. Compare with Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP keeps active.
• Output Hiz Mode. Register 0x03h -D[1:0]=10, Device stays in Hiz Mode. In this mode, Only output driver set
to be Hiz state, all other block work normally.
• Play Mode. Register 0x03h -D[1:0]=11, Device stays in Play Mode.
9.4.6 Device Modulation
TAS5825P has 3 modulation schemes: BD modulation, 1SPW modulation and Hybrid modulation. Select
modulation schemes for TAS5825P with Register 0x02 [1:0]-DAMP_MOD.
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9.4.6.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
OUTP- OUTN
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP - OUTN
0V
- PVCC
Speaker
Current
0A
Figure 97. BD Mode Modulation
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9.4.6.2 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In Low Idle Current mode the
outputs operate at ~17% modulation during idle conditions. When an audio signal is applied, one output
decreases and one increases. The decreasing output signal rails to GND. At this point all the audio modulation
takes place through the rising output. The result is that only one output is switching during a majority of the audio
cycle. Efficiency is improved in this mode due to the reduction of switching losses.
OUTP
OUTN
OUTP -OUTN
No Output
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP -OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP -OUTN
0V
- PVCC
Speaker
Current
0A
Figure 98. 1SPW Mode Modulation
9.4.6.3 Hybrid Modulation
Hybrid Modulation is designed for minimized power loss without compromising the THD+N performance, and is
optimized for battery-powered applications. With Hybrid modulation, TAS5825P detects the input signal level and
adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and
maintains the same audio performance level as the BD Modulation.
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NOTE
As Hybrid Modulation need the internal DSP to detect the input signal level and adjust
PWM duty cycle dynamically. To use the Hybrid Modulation, users need to select the
corresponding process flows which support Hybrid Modulation in TAS5825P PPC3 App.
Look into TAS5825P PPC3 App for more information about TAS5825P flexible audio
process flows.
9.5 Programming and Control
I2 C Serial Communication Bus
9.5.1
The device has a bidirectional serial control interface that is compatible with I2C bus protocol and supports 100
and 400-kHz data transfer rates for random and sequential write and read operations as a slave device. Because
the TAS5825P register map and DSP memory spans multi pages, the user should change from page to page
before writing individual register or DSP memory. Changing from page to page is accomplished via register 0 on
each page. This register value selects the page address, from 0 to 255. All registers listed in TAS5825P
Datasheet belongs to Page 0
9.5.2 I2 C Slave Address
The TAS5825P device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are factory
preset to 10011(0x9x). The next two bits of address byte are the device select bits which can be user-defined by
ADR pin in Table 5.
Table 5. I2 C Slave Address Configuration
ADR PIN Configuration
MSBs
User Define
LSB
0 Ω to GND
1
0
0
1
1
0
0
R/W
1kΩ to GND
1
0
0
1
1
0
1
R/W
4.7kΩ to GND
1
0
0
1
1
1
0
R/W
15kΩ to GND
1
0
0
1
1
1
1
R/W
9.5.2.1 Random Write
As shown in Figure 99, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4 A3
A2
A1
A0 R/W ACK A7
I2C Device Address
and R/W Bit
Acknowledge
A6
A5
A4
A3
A2
A1
A0 ACK D7
Subaddress
Acknowledge
D6
D5 D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
Figure 99. Random Write Transfer
9.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in Figure 100. After receiving each data byte, the device
responds with an acknowledge bit and the I2 subaddress is automatically incremented by one.
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Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
I2C Device Address
and R/W Bit
A5
A4
A3
A1
Subaddress
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Byte
Last Data Byte
Stop
Condition
Figure 100. Sequential Write Transfer
9.5.2.3 Random Read
As shown in Figure 101, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the
device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the
master device transmits another start condition followed by the address and the read/write bit again. This time
the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device
again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop
condition to complete the single-byte data-read transfer.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address
and R/W Bit
A6
A5
A4
A0 ACK
A6
A5
A1 A0 R/W ACK D7 D6
I2C Device Address
and R/W Bit
Subaddress
Not
Acknowledge
Acknowledge
D0 D6 ACK
Stop
Condition
Data Byte
Figure 101. Random Read Transfer
9.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in Figure 102. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C sub
address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed by a
stop condition to complete the transfer.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address
and R/W Bit
A6
A5
A0 ACK
Subaddress
A6
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I2C Device Address
and R/W Bit
First Data Byte
Other Data Byte
Last Data Byte
Stop
Condition
Figure 102. Sequential Read Transfer
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9.5.2.5 DSP Memory Book, Page and BQ update
On Page 0x00 of each book, Register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a Page first write 0x00 to Register 0x00 to switch to Page 0 then write the book
number to Register 0x7f on Page 0. To switch between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in book 0xAA. The five coefficients of every Biquad Filter should
be written entirely and sequentially from the lowest address to the highest address. The address of all Biquad
Filters can be found in Register Maps
All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5825P Process Flows
9.5.2.6 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers
changes the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.
The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register
locations.
9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the
same register locations where the CRC checksum is valid.
9.5.2.6.2 Exclusive or (XOR) Checksum
The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with
the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all
registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book
0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register
location where it is read.
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9.5.3 Control via Software
• Startup Procedures
• Shutdown Procedures
9.5.3.1 Startup Procedures
1. Configure ADR pin with proper setting for I2C device address.
2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).
3. Once power supplies are stable, bring up PDN to High, then start SCLK, LRCLK.
4. Once I2S clock are stable, set the device into HiZ state and enable DSP via the I2C control port.
5. Wait 5 ms at least. Then initialize the DSP Coefficient, and set the device to Play state
6. The device is now in normal operation.
Initialization
DVDD
0 ns
PVDD
0 ns
PDN
I2S
I2S
I2 S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2C
Deep sleep
HiZ - DSP enable
(Book0/Page-0 Register) (Book0/Page-0 Register)
DSP ready to configure
Play
5 ms for device settle down
(1)
I2S only permits to start after DVDD fully powered up. But No sequence requirement with PDN.
A.
I2C only response with PDN brought up to HIGH.
B.
If I2C register is general register in Book 0, no sequence requirement, write/read BEFORE or AFTER I2S clock ready.
But if I2C register is DSP register (Other BOOK/PAGE), suggest to follow the 5ms requirements and make sure I2S
clock is ready (Especially for the first time initialization after power up).
C.
No sequence requirement for PVDD and DVDD.
Figure 103. Start-up Sequence
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9.5.3.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]=10 (Hiz) via the I2C control port or Pull PDN low.
3. Wait at least 6ms (this time depends on the LRCLK rate ,digital volume and digital volume ramp down rate).
4. Bring down power supplies.
5. The device is now fully shutdown and powered off.
PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
A.
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C
B.
At least 6 ms delay needed based on LRCLK (Fs) = 48 kHz, Digital volume ramp down update every sample period,
decreased by 0.5 dB for each update, digital volume = 24 dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
Figure 104. Power-Down Sequence
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9.5.3.3 Protection and Monitoring
9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
The CBC current-limiting circuit terminates each PWM pulse limit the output current flow to the average current
limit (ILIM) threshold. The overall effect on the audio in the case of a current overload is quite similar a voltageclipping event, temporarily limiting power at the peaks of the music signal and normal operation continues without
disruption on removal of the overload.
NOTE
CBC (Cycle-By-Cycle) current-limiting only allows in BTL mode, not allowed under PBTL.
9.5.3.3.2 Overcurrent Shutdown (OCSD)
Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,
and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends
on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The
user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2 fault register
saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not
severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the output
FETs, and operation returns to normal after the short is removed.
9.5.3.3.3 DC Detect
If the TAS5825P device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the
OUTxx outputs transition to high impedance, signifying a fault.
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9.6 Register Maps
9.6.1 CONTROL PORT Registers
Table 6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in
Table 6 should be considered as reserved locations and the register contents should not be modified.
Table 6. CONTROL PORT Registers
Offset
46
Acronym
Register Name
1h
RESET_CTRL
Register 1
Section
Go
2h
DEVICE_CTRL_1
Register 2
Go
3h
DEVICE_CTRL2
Register 3
Go
Fh
I2C_PAGE_AUTO_INC
Register 15
Go
28h
SIG_CH_CTRL
Register 40
Go
29h
CLOCK_DET_CTRL
Register 41
Go
30h
SDOUT_SEL
Register 48
Go
31h
I2S_CTRL
Register 49
Go
33h
SAP_CTRL1
Register 51
Go
34h
SAP_CTRL2
Register 52
Go
37h
FS_MON
Register 55
Go
38h
BCK (SCLK)_MON
Register 56
Go
39h
CLKDET_STATUS
Register 57
Go
40h
DSP_PGM_MODE
Register 64
Go
46h
DSP_CTRL
Register 70
Go
4Ch
DIG_VOL
Register 76
Go
4Eh
DIG_VOL_CTRL1
Register 78
Go
4Fh
DIG_VOL_CTRL2
Register 79
Go
50h
AUTO_MUTE_CTRL
Register 80
Go
51h
AUTO_MUTE_TIME
Register 81
Go
53h
ANA_CTRL
Register 83
Go
54h
AGAIN
Register 84
Go
55h
SPI_CLK
Register 85
Go
56h
EEPROM_CTRL0
Register 86
Go
57h
EEPROM_RD_CMD
Register 87
Go
58h
EEPROM_ADDR_START0
Register 88
Go
59h
EEPROM_ADDR_START1
Register 89
Go
5Ah
EEPROM_ADDR_START2
Register 90
Go
5Bh
EEPROM_BOOT_STATUS
Register 91
Go
5Ch
BQ_WR_CTRL1
Register 92
Go
5Eh
PVDD_ADC
Register 94
Go
60h
GPIO_CTRL
Register 96
Go
61h
GPIO0_SEL
Register 97
Go
62h
GPIO1_SEL
Register 98
Go
63h
GPIO2_SEL
Register 99
Go
64h
GPIO_INPUT_SEL
Register 100
Go
65h
GPIO_OUT
Register 101
Go
66h
GPIO_OUT_INV
Register 102
Go
67h
DIE_ID
Register 103
Go
68h
POWER_STATE
Register 104
Go
69h
AUTOMUTE_STATE
Register 105
Go
6Ah
PHASE_CTRL
Register 106
Go
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Table 6. CONTROL PORT Registers (continued)
Offset
Acronym
Register Name
6Bh
SS_CTRL0
Register 107
Section
Go
6Ch
SS_CTRL1
Register 108
Go
6Dh
SS_CTRL2
Register 109
Go
6Eh
SS_CTRL3
Register 110
Go
6Fh
SS_CTRL4
Register 111
Go
70h
CHAN_FAULT
Register 112
Go
71h
GLOBAL_FAULT1
Register 113
Go
72h
GLOBAL_FAULT2
Register 114
Go
73h
WARNING
Register 115
Go
74h
PIN_CONTROL1
Register 116
Go
75h
PIN_CONTROL2
Register 117
Go
76h
MISC_CONTROL
Register 118
Go
77h
CBC_CONTROL
Register 119
Go
78h
FAULT_CLEAR
Register 120
Go
Complex bit access types are encoded to fit into small table cells. Table 7 shows the codes that are used for
access types in this section.
Table 7. CONTROL PORT Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
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9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in Figure 105 and described in Table 8.
Return to Summary Table.
Figure 105. RESET_CTRL Register
7
6
RESERVED
R/W
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
Table 8. RESET_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
RST_DIG_CORE
W
0
WRITE CLEAR BIT
4
Reset DIG_CORE
WRITE CLEAR BIT Reset Full Digital Core. This bit resets the Full
Digital Signal Path (Include DSP coefficient RAM and I2C Control
Port Registers), Since the DSP is also reset, the coeffient RAM
content will also be cleared by the DSP.
0: Normal
1: Reset Full Digital Signal Path
3-1
0
RESERVED
R
000
This bit is reserved
RST_REG
W
0
WRITE CLEAR BIT
Reset Registers
This bit resets the mode registers back to their initial values. Only
reset Control Port Registers, The RAM content is not cleared.
0: Normal
1: Reset I2C Control Port Registers
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9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in Figure 106 and described in Table 9.
Return to Summary Table.
Figure 106. DEVICE_CTRL_1 Register
7
RESERVED
R/W
6
5
FSW_SEL
R/W
4
3
RESERVED
R/W
2
DAMP_PBTL
R/W
1
0
DAMP_MOD
R/W
Table 9. DEVICE_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
FSW_SEL
R/W
000
SELECT FSW
000: 384K
010: 480K
011: 576K
100: 768K
001: Reserved
101: Reserved
110: Reserved
111: Reserved
3
RESERVED
R/W
0
This bit is reserved
2
DAMP_PBTL
R/W
0
0: SET DAMP TO BTL MODE
1: SET DAMP TO PBTL MODE
1-0
DAMP_MOD
R/W
00
00: BD MODE
01: 1SPW MODE
10: HYBRID MODE (Need to select supporting process flows in
PPC3)
7
6-4
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9.6.1.3 DEVICE_CTRL2 Register (Offset = 3h) [reset = 00x10]
DEVICE_CTRL2 is shown in Figure 107 and described in Table 10.
Return to Summary Table.
Figure 107. DEVICE_CTRL2 Register
7
6
RESERVED
R/W
5
4
DIS_DSP
R/W
3
MUTE_LEFT
R/W
2
RESERVED
R/W
1
0
CTRL_STATE
R/W
Table 10. DEVICE_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
4
DIS_DSP
R/W
1
DSP reset
When the bit is made 0, DSP will start powering up and send out
data. This needs to be made 0 only after all the input clocks are
settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute both Left and Right Channel
This bit issues soft mute request for both left and right channel. The
volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2
RESERVED
R/W
0
This bit is reserved
CTRL_STATE
R/W
00
device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY
1-0
50
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9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in Figure 108 and described in Table 11.
Return to Summary Table.
Figure 108. I2C_PAGE_AUTO_INC Register
7
6
5
4
RESERVED
R/W
3
PAGE_AUTOIN
C_REG
R/W
2
1
RESERVED
0
R/W
Table 11. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
PAGE_AUTOINC_REG
R/W
0
Page auto increment disable
Disable page auto increment mode. for non -zero books. When end
of page is reached it goes back to 8th address location of next page
when this bit is 0. When this bit is 1 it goes to 0 th location of current
page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
RESERVED
R/W
000
This bit is reserved
3
2-0
9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in Figure 109 and described in Table 12.
Return to Summary Table.
Figure 109. SIG_CH_CTRL Register
7
6
5
SCLK_RATIO_CONFIGURE
R/W
4
3
FSMODE
R/W
2
1
RESERVED
R/W
0
Table 12. SIG_CH_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SCLK_RATIO_CONFIGU
RE
R/W
0000
These bits indicate the configured SCLK ratio, the number of SCLK
clocks in one audio frame. Device will set this ratio automatically.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
FSMODE
R/W
0
FS Speed Mode These bits select the FS operation mode, which
must be set according to the current audio sampling rate. Need set it
manually If the input Fs is 44.1kHz/88.2kHz/176.4kHz.
4 'b0000 Auto detection
4 'b0100 Reserved
4 'b0110 32KHz
4 'b1000 44.1KHz
4 'b1001 48KHz
4'b1010 88.2KHz
4 'b1011 96KHz
4 'b1100 176.4KHz
4 'b1101 192KHz
Others Reserved
RESERVED
R/W
000
This bit is reserved
3
2-0
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9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in Figure 110 and described in Table 13.
Return to Summary Table.
Figure 110. CLOCK_DET_CTRL Register
7
RESERVED
6
DIS_DET_PLL
R/W
R/W
5
DIS_DET_SCL
K_RANGE
R/W
4
DIS_DET_FS
R/W
3
DIS_DET_SCL
K
R/W
2
DIS_DET_MIS
S
R/W
1
RESERVED
R/W
0
DIS_DET_LOC
K
R/W
Table 13. CLOCK_DET_CTRL Register Field Descriptions
Bit
52
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6
DIS_DET_PLL
R/W
0
Ignore PLL overate Detection
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150MHz or an error will be reported. When
ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_SCLK_RANGE
R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the SCLK range detection. The
SCLK must be stable between 256KHz and 50MHz or an error will
be reported. When ignored, a SCLK range error will not cause a
clock error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
DIS_DET_FS
R/W
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error will not cause a clock error.But CLKDET_STATUS
will report fs error.
0: Regard FS detection
1: Ignore FS detection
3
DIS_DET_SCLK
R/W
0
Ignore SCLK Detection
This bit controls whether to ignore the SCLK detection against
LRCK. The SCLK must be stable between 32FS and 512FS
inclusive or an error will be reported. When ignored, a SCLK error
will not cause a clock error.
0: Regard SCLK detection
1: Ignore SCLK detection
2
DIS_DET_MISS
R/W
0
Ignore SCLK Missing Detection
This bit controls whether to ignore the SCLK missing detection.
When ignored an SCLK missing will not cause a clock error.
0: Regard SCLK missing detection
1: Ignore SCLKmissing detection
1
RESERVED
R/W
0
This bit is reserved
0
DIS_DET_LOCK
R/W
0
This bit is reserved
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9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0x00]
SDOUT_SEL is shown in Figure 112 and described in Table 14.
Return to Summary Table.
Figure 111. SDOUT_SEL Register
7
6
5
RESERVED
R/W
4
3
2
1
RESERVED
R/W
0
SDOUT_SEL
R/W
Table 14. SDOUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000000
These bits are reserved
0
SDOUT_SEL
R/W
0
SDOUT Select. This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in Figure 112 and described in Table 15.
Return to Summary Table.
Figure 112. I2S_CTRL Register
7
6
RESERVED
R/W
5
SCLK_INV
R/W
4
RESERVED
R/W
3
RESERVED
R
2
1
RESERVED
R
0
RESERVED
R/W
Table 15. I2S_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5
SCLK_INV
R/W
0
SCLK Polarity
This bit sets the inverted SCLK mode. In inverted SCLK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the
rising edge of the SCLK. Normally they are assumed to be aligned to
the falling edge of theSCLK
0: Normal SCLKmode
1: Inverted SCLK mode
4
RESERVED
R/W
0
This bit is reserved
3
RESERVED
R
0
This bit is reserved
2-1
RESERVED
R/W
00
This bit is reserved
0
RESERVED
R/W
0
This bit is reserved
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9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in Figure 113 and described in Table 16.
Return to Summary Table.
Figure 113. SAP_CTRL1 Register
7
I2S_SHIFT_MS
B
R/W
6
RESERVED
5
4
DATA_FORMAT
3
2
I2S_LRCLK_PULSE
1
0
WORD_LENGTH
R/W
R/W
R/W
R/W
Table 16. SAP_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2S_SHIFT_MSB
R/W
0
I2S Shift MSB
6
RESERVED
R/W
0
This bit is reserved
5-4
DATA_FORMAT
R/W
00
I2S Data Format
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
I2S_LRCLK_PULSE
R/W
00
01: lrclk pulse < 8 SCLK
1-0
WORD_LENGTH
R/W
10
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in Figure 114 and described in Table 17.
Return to Summary Table.
Figure 114. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
Table 17. SAP_CTRL2 Register Field Descriptions
54
Bit
Field
Type
Reset
Description
7-0
I2S_SHIFT
R/W
00000000
I2S Shift LSB
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of SCLK from
the starting (MSB) of audio frame to the starting of the desired audio
sample.
000000000: offset = 0 SCLK (no offset)
000000001: ofsset = 1 SCLK
000000010: offset = 2 SCLKs
and
111111111: offset = 512 SCLKs
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9.6.1.11 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in Figure 115 and described in Table 18.
Return to Summary Table.
Figure 115. FS_MON Register
7
6
RESERVED
R/W
5
4
SCLK_RATIO_HIGH
R
3
2
1
0
FS
R
Table 18. FS_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5-4
SCLK_RATIO_HIGH
R
00
2 msbs of detected SCLK ratio
3-0
FS
R
0000
These bits indicate the currently detected audio sampling rate.
4 'b0000 FS Error
4 'b0100 16KHz
4 'b0110 32KHz
4 'b1000 Reserved
4 'b1001 48KHz
4 'b1011 96KHz
4 'b1101 192KHz
Others Reserved
9.6.1.12 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in Figure 116 and described in Table 19.
Return to Summary Table.
Figure 116. BCK (SCLK)_MON Register
7
6
5
4
3
BCLK (SCLK)_RATIO_LOW
R
2
1
0
Table 19. BCK_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BCLK
(SCLK)_RATIO_LOW
R
00000000
These bits indicate the currently detected BCK (SCLK) ratio, the
number of BCK (SCLK) clocks in one audio frame.
BCK (SCLK) = 32 FS~512 FS
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9.6.1.13 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in Figure 117 and described in Table 20.
Return to Summary Table.
Figure 117. CLKDET_STATUS Register
7
6
5
4
RESERVED
R/W
3
2
1
0
DET_STATUS
R
Table 20. CLKDET_STATUS Register Field Descriptions
56
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5-0
DET_STATUS
R
000000
bit0: In auto detection mode(reg_fsmode=0),this bit indicated
whether the audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag will be also asserted.
bit1: This bit indicates whether the SCLK is valid or not. The SCLK
ratio must be stable and in the range of 32-512FS to be valid.
bit2: This bit indicates whether the SCLK is missing or not.
bit3:This bit indicates whether the PLL is locked or not. The PLL will
be reported as unlocked when it is disabled.
bits4:This bit indicates whether the PLL is overrate
bits5:This bit indicates whether the SCLK is overrate or underrate
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9.6.1.14 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]
DSP_PGM_MODE is shown in Figure 118 and described in Table 21.
Return to Summary Table.
Figure 118. DSP_PGM_MODE Register
7
6
5
4
RESERVED
R/W
3
CH_A_HIZ
R/W
2
CH_B_HIZ
R/W
1
0
MODE_SEL
R/W
Table 21. DSP_PGM_MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
These bits are reserved
CH_A_HIZ
R/W
0
1: Force Channel A (L channel) to Hiz mode.
3
0: Exit Force Hi-Z mode, Channel A is now controlled by Register
0x03, see Table 10.
Notes: If channel has been forced to Hiz, only method to exit Force
Hi-Z mode is set this bit to 0. This function is disabled in PBTL
mode.
2
CH_B_HIZ
R/W
0
1: Force Channel B (R channel) to Hiz mode.
0: Exit Force Hi-Z mode, Channel B is now controlled by Register
0x03, see Table 10.
Notes: If channel has been forced to Hiz, only method to exit Force
Hi-Z mode is set this bit to 0. This function is disabled in PBTL
mode.
1-0
MODE_SEL
R/W
01
DSP Program Selection
These bits select the DSP program to use for audio processing.
00 => ram mode
01 => rom mode 1
10 => rom mode 2
11 => rom mode 3
9.6.1.15 DSP_CTRL Register (Offset = 46h) [reset = 0x01]
DSP_CTRL is shown in Figure 119 and described in Table 22.
Return to Summary Table.
Figure 119. DSP_CTRL Register
7
6
RESERVED
5
R/W
4
3
USER_DEFINED_PROCESSING
_RATE
R/W
2
RESERVED
R
1
BOOT_FROM_
IRAM
R/W
0
USE_DEFAUL
T_COEFFS
R/W
Table 22. DSP_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
4-3
USER_DEFINED_PROCE R/W
SSING_RATE
00
00:input
01:48k
10:96k
11:192k
2
RESERVED
R
0
This bit is reserved
1
RESERVED
R
0
This bit is reserved
0
USE_DEFAULT_COEFFS R/W
1
Use default coefficients from ZROM this bit controls whether to use
default coefficients from ZROM or use the non-default coefficients
downloaded to device by the Host
0 : don't use default coefficients from ZROM
1 : use default coefficents from ZROM
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9.6.1.16 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL is shown in Figure 120 and described in Table 23.
Return to Summary Table.
Figure 120. DIG_VOL Register
7
6
5
4
3
2
1
0
PGA_LEFT
R/W
Table 23. DIG_VOL Register Field Descriptions
58
Bit
Field
Type
Reset
Description
7-0
PGA
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
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9.6.1.17 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL1 is shown in Figure 121 and described in Table 24.
Return to Summary Table.
Figure 121. DIG_VOL_CTRL1 Register
7
6
PGA_RAMP_DOWN_SPEED
R/W
5
4
PGA_RAMP_DOWN_STEP
R/W
3
2
PGA_RAMP_UP_SPEED
R/W
1
0
PGA_RAMP_UP_STEP
R/W
Table 24. DIG_VOL_CTRL1 Register Field Descriptions
Bit
Field
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
Type
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
PGA_RAMP_DOWN_STE R/W
P
11
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-2
PGA_RAMP_UP_SPEED
R/W
00
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
1-0
PGA_RAMP_UP_STEP
R/W
11
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each updat
e 01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
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9.6.1.18 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL2 is shown in Figure 122 and described in Table 25.
Return to Summary Table.
Figure 122. DIG_VOL_CTRL2 Register
7
6
FAST_RAMP_DOWN_SPEED
R/W
5
4
FAST_RAMP_DOWN_STEP
R/W
3
2
1
0
RESERVED
R/W
Table 25. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
Type
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST
EP
R/W
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
9.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in Figure 123 and described in Table 26.
Return to Summary Table.
Figure 123. AUTO_MUTE_CTRL Register
7
6
5
RESERVED
R/W
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
Table 26. AUTO_MUTE_CTRL Register Field Descriptions
60
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000
This bit is reserved
2-0
REG_AUTO_MUTE_CTR
L
R/W
111
bit0:
0: Disable left channel auto mute
1: Enable left channel auto mute
bit1:
0: Disable right channel auto mute
1: Enable right channel auto mute
bit2:
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted.
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9.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in Figure 124 and described in Table 27.
Return to Summary Table.
Figure 124. AUTO_MUTE_TIME Register
7
RESERVED
R/W
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
RESERVED
R/W
2
1
AUTOMUTE_TIME_RIGHT
R/W
0
Table 27. AUTO_MUTE_TIME Register Field Descriptions
Bit
7
6-4
3
2-0
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
AUTOMUTE_TIME_LEFT
R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
RESERVED
R/W
0
This bit is reserved
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
AUTOMUTE_TIME_RIGH R/W
T
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9.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0h]
ANA_CTRL is shown inFigure 125 and described in Table 28
Return to Summary Table
Figure 125. ANA_CTRL Register
7
6
5
4
3
2
1
0
AMUTE_DLY
R/W
Table 28. ANA_CTRL Register Field Descriptions
Bit
7
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-5
Class D bandwidth control R/W
00
00: 100kHz
01: 80kHz
10: 120kHz
11:175kHz
With Fsw=384kHz, 100kHz bandwidth is selected for high audio
performance. With Fsw=768kHz, 175kHz bandwidth should be
selected for high audio performance.
4-1
RESERVED
R/W
0000
These bits are reserved
L and R PWM output
phase control
R/W
0
0: out of phase
1: in phase
0
62
Field
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9.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in Figure 126 and described in Table 29.
Return to Summary Table.
Figure 126. AGAIN Register
7
6
RESERVED
R/W
5
4
3
2
ANA_GAIN
R/W
1
0
1
0
Table 29. AGAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
4-0
ANA_GAIN
R/W
00000
Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001: -0.5db
...
11111: -15.5 dB
9.6.1.23 SPI_CLK Register (Offset = 55h) [reset = 0x00]
SPI_CLK is shown in Figure 127 and described in Table 30.
Return to Summary Table.
Figure 127. SPI_CLK Register
7
6
5
4
3
RESERVED
R/W
2
SPI_CLK_SEL
R/W
Table 30. SPI_CLK Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
3-0
SPI_CLK_SEL
R/W
0000
00: 1.25M
01: 2.5M
10: 5M
11: 10M
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9.6.1.24 EEPROM_CTRL0 Register (Offset = 56h) [reset = 0x00]
EEPROM_CTRL0 is shown in Figure 128 and described in Table 31.
Return to Summary Table.
Figure 128. EEPROM_CTRL0 Register
7
6
5
EEPROM_ADD
R_24BITS_EN
ABLE
R/W
RESERVED
R/W
4
3
SPI_CLK_RATE
2
1
SPI_INV_POLA SPI_MST_LSB
R
R/W
R/W
R/W
0
LOAD_EEPRO
M_START
R/W
Table 31. EEPROM_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
EEPROM_ADDR_24BITS R/W
_ENABLE
0
enable 24 bits mode for EEPROM address
4-3
SPI_CLK_RATE
R/W
00
0: spi clock rate
1: spi clock rate
2: spi clock rate
3: spi clock rate
2
SPI_INV_POLAR
R/W
0
0: spi serial data change at post edge SCK
1: spi serial data change at neg edge SCK
1
SPI_MST_LSB
R/W
0
0: msb first 1: lsb first
0
LOAD_EEPROM_START
R/W
0
0: dsp coefficients read from host
1: dsp coefficients read from EEPROM
5
= 1.25MHz
= 2.5MHz
= 5MHz
= 10MHz
9.6.1.25 EEPROM_RD_CMD Register (Offset = 57h) [reset = 0x03]
EEPROM_RD_CMD is shown in Figure 129 and described in Table 32.
Return to Summary Table.
Figure 129. EEPROM_RD_CMD Register
7
6
5
4
3
EEPROM_RD_CMD
R/W-00000011
2
1
0
Table 32. EEPROM_RD_CMD Register Field Descriptions
64
Bit
Field
Type
Reset
Description
7-0
EEPROM_RD_CMD
R/W
00000011
EEPROM read command
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9.6.1.26 EEPROM_ADDR_START0 Register (Offset = 58h) [reset = 0x00]
EEPROM_ADDR_START0 is shown in Figure 130 and described in Table 33.
Return to Summary Table.
Figure 130. EEPROM_ADDR_START0 Register
7
6
5
4
3
EEPROM_ADDR_START_HIGH
R/W
2
1
0
Table 33. EEPROM_ADDR_START0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EEPROM_ADDR_START
_HIGH
R/W
00000000
8 msb of EEPROM read starting address for coefficient
9.6.1.27 EEPROM_ADDR_START1 Register (Offset = 59h) [reset = 0x00]
EEPROM_ADDR_START1 is shown in Figure 131 and described in Table 34.
Return to Summary Table.
Figure 131. EEPROM_ADDR_START1 Register
7
6
5
4
3
EEPROM_ADDR_START_MIDDLE
R/W
2
1
0
Table 34. EEPROM_ADDR_START1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EEPROM_ADDR_START
_MIDDLE
R/W
00000000
8 middle of EEPROM read starting address for coefficients
9.6.1.28 EEPROM_ADDR_START2 Register (Offset = 5Ah) [reset = 0h]
EEPROM_ADDR_START2 is shown in Figure 132 and described in Table 35.
Return to Summary Table.
Figure 132. EEPROM_ADDR_START2 Register
7
6
5
4
3
EEPROM_ADDR_START_LOW
R/W
2
1
0
Table 35. EEPROM_ADDR_START2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EEPROM_ADDR_START
_LOW
R/W
00000000
8 lsb of EEPROM read starting address for coefficients
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9.6.1.29 EEPROM_BOOT_STATUS Register (Offset = 5Bh) [reset = 0x00]
EEPROM_BOOT_STATUS is shown in Figure 133 and described in Table 36.
Return to Summary Table.
Figure 133. EEPROM_BOOT_STATUS Register
7
6
5
4
3
2
RESERVED
R
1
0
LOAD_EEPRO LOAD_EEPRO
M_CRC_ERRO
M_DONE
R
R
R
Table 36. EEPROM_BOOT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000
This bit is reserved
1
LOAD_EEPROM_CRC_E
RROR
R
0
0: CRC pass for EEPROM boot load
1: CRC don't passs for EEPROM boot load.
0
LOAD_EEPROM_DONE
R
0
Indicate that the EEPROM boot load has been finished.
9.6.1.30 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x000]
BQ_WR_CTRL1 is shown in Figure 134 and described in Table 37.
Return to Summary Table.
Figure 134. BQ_WR_CTRL1 Register
7
6
5
4
RESERVED
3
2
1
R/W
0
BQ_WR_FIRST
_COEF
R/W
Table 37. BQ_WR_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000000
This bit is reserved
BQ_WR_FIRST_COEF
R/W
0
Indicate the first coefficient of a BQ is starting to write.
0
9.6.1.31 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
PVDD_ADC is shown in Figure 135 and described in Table 38.
Return to Summary Table.
Figure 135. PVDD_ADC Register
7
66
6
5
4
3
ADC_DATA_OUT
R
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Table 38. PVDD_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PVDD_ADC[7:0]
R
00000000
PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V)
223: 26.45V
222: 26.34V
221:26.22V
...
39: 4.63V
38: 4.51V
37: 4.39V
9.6.1.32 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]
GPIO_CTRL is shown in Figure 136 and described in Table 39.
Return to Summary Table.
Figure 136. GPIO_CTRL Register
7
6
5
RESERVED
R/W
4
3
2
GPIO2_OE
R/W
1
GPIO1_OE
R/W
0
GPIO0_OE
R/W
Table 39. GPIO_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
0000
This bit is reserved
2
GPIO2_OE
R/W
0
GPIO2 Output Enable This bit sets the direction of the GPIO2 pin
0: GPIO2 is input
1: GPIO2 is output
1
GPIO1_OE
R/W
0
GPIO1 Output Enable This bit sets the direction of the GPIO1 pin
0: GPIO1 is input
1: GPIO1 is output
0
GPIO0_OE
R/W
0
GPIO0 Output Enable This bit sets the direction of the GPIO0 pin
0: GPIO0 is input
1: GPIO0 is output
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9.6.1.33 GPIO0_SEL Register (Offset = 61h) [reset = 0x00]
GPIO0_SEL is shown in Figure 137 and described in Table 40.
Return to Summary Table.
Figure 137. GPIO0_SEL Register
7
6
5
4
3
2
RESERVED
R/W
1
0
GPIO0_SEL
R/W
Table 40. GPIO0_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
3-0
GPIO0_SEL
R/W
0000
0000: off (low)
0001: Hybrid-Pro two level classG waveform control output
0010: Register GPIO0 output
0011: Auto mute flag (asserted when both L and R channels are
auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO0 as WARNZ output
1001: Hybrid-Pro multi-level classH control waveform output
1011: GPIO0 as FAULTZ output
1100: GPIO0 as SPI CLK
1101: GPIO0 as SPI_MOSI
1110: Reserved
1111: Reserved
9.6.1.34 GPIO1_SEL Register (Offset = 62h) [reset = 0x00]
GPIO1_SEL is shown in Figure 138 and described in Table 41.
Return to Summary Table.
Figure 138. GPIO1_SEL Register
7
6
5
4
3
RESERVED
R/W
2
1
0
GPIO1_SEL
R/W
Table 41. GPIO1_SEL Register Field Descriptions
68
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
3-0
GPIO1_SEL
R/W
0000
0000: off (low)
0001: Hybrid-Pro two level classG waveform control output
0010: Register GPIO1 output
0011: Auto mute flag (asserted when both L and R channels are
auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO1 as WARNZ output
1001: Hybrid-Pro multi-level classH control waveform output
1011: GPIO1 as FAULTZ output
1100: GPIO1 as SPI CLK
1101: GPIO1 as SPI_MOSI
1110: Reserved
1111: Reserved
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9.6.1.35 GPIO2_SEL Register (Offset = 63h) [reset = 0x00]
GPIO2_SEL is shown in Figure 139 and described in Table 42.
Return to Summary Table.
Figure 139. GPIO2_SEL Register
7
6
5
4
3
2
RESERVED
R/W
1
0
GPIO2_SEL
R/W
Table 42. GPIO2_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
3-0
GPIO2_SEL
R/W
0000
0000: off (low)
0001: Hybrid-Pro two level classG waveform control output
0010: Register GPIO2 output
0011: Auto mute flag (asserted when both L and R channels are
auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO2 as WARNZ output
1001: Hybrid-Pro multi-level classH control waveform output
1011: GPIO2 as FAULTZ output
1100: GPIO2 as SPI CLK
1101: GPIO2 as SPI_MOSI
1110: Reserved
1111: Reserved
9.6.1.36 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]
GPIO_INPUT_SEL is shown in Figure 140 and described in Table 43.
Return to Summary Table.
Figure 140. GPIO_INPUT_SEL Register
7
6
GPIO_SPI_MISO_SEL
R/W
5
4
GPIO_PHASE_SYNC_SEL
R/W
3
2
GPIO_RESETZ_SEL
R/W
1
0
GPIO_MUTEZ_SEL
R/W
Table 43. GPIO_INPUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GPIO_SPI_MISO_SEL
R/W
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
5-4
GPIO_PHASE_SYNC_SE R/W
L
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
3-2
GPIO_RESETZ_SEL
R/W
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2 can not be reset by GPIO reset
1-0
GPIO_MUTEZ_SEL
(Enable device into Hiz
mode)
R/W
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
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9.6.1.37 GPIO_OUT Register (Offset = 65h) [reset = 0x00]
GPIO_OUT is shown in Figure 141 and described in Table 44.
Return to Summary Table.
Figure 141. GPIO_OUT Register
7
6
5
RESERVED
R/W
4
3
2
1
GPIO_OUT
R/W
0
1
GPIO_OUT
R/W
0
1
0
Table 44. GPIO_OUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000
This bit is reserved
2-0
GPIO_OUT
R/W
000
bit0: GPIO0 output
bit1: GPIO1 output
bit2: GPIO2 output
9.6.1.38 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]
GPIO_OUT_INV is shown in Figure 142 and described in Table 45.
Return to Summary Table.
Figure 142. GPIO_OUT_INV Register
7
6
5
RESERVED
R/W
4
3
2
Table 45. GPIO_OUT_INV Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000
This bit is reserved
2-0
GPIO_OUT
R/W
000
bit0: GPIO0 output invert
bit1: GPIO1 output invert
bit2: GPIO2 output invert
9.6.1.39 DIE_ID Register (Offset = 67h) [reset = 97h]
DIE_ID is shown in Figure 143 and described in Table 46.
Return to Summary Table.
Figure 143. DIE_ID Register
7
6
5
4
3
2
DIE_ID
R
Table 46. DIE_ID Register Field Descriptions
70
Bit
Field
Type
Reset
Description
7-0
DIE_ID
R
10010111
DIE ID
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9.6.1.40 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in Figure 144 and described in Table 47.
Return to Summary Table.
Figure 144. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
Table 47. POWER_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
STATE_RPT
R
00000000
00: Deep sleep
01: Seep
10: HIZ
11: Play
others: reserved
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9.6.1.41 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in Figure 145 and described in Table 48.
Return to Summary Table.
Figure 145. AUTOMUTE_STATE Register
7
6
5
4
3
2
RESERVED
R
1
ZERO_RIGHT_
MON
R
0
ZERO_LEFT_
MON
R
Table 48. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000
This bit is reserved
ZERO_RIGHT_MON
R
0
This bit indicates the auto mute status for right channel.
1
0: Not auto muted
1: Auto muted
0
ZERO_LEFT_MON
R
0
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
9.6.1.42 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]
PHASE_CTRL is shown in Figure 146 and described in Table 49.
Return to Summary Table.
Figure 146. PHASE_CTRL Register
7
6
RESERVED
5
4
3
2
RAMP_PHASE_SEL
R/W
R/W
1
PHASE_SYNC
_SEL
R/W
0
PHASE_SYNC
_EN
R/W
Table 49. PHASE_CTRL Register Field Descriptions
72
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
3-2
RAMP_PHASE_SEL
R/WTAS
00
select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current, it is
recomended set all devices the same RAMP frequency and same
spread spectrum. it must be set before driving device into PLAY
mode if this feature is needed.
2'b00: phase 0
2'b01: phase 1
2'b10: phase 2
2'b11: phase 3 all of above have a 45 degree of phase shift
1
PHASE_SYNC_SEL
R/W
0
ramp phase sync sel,
0: is gpio sync;
1: intenal sync
0
PHASE_SYNC_EN
R/W
0
ramp phase sync enable
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9.6.1.43 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
RAMP_SS_CTRL0 is shown in Figure 147 and described in Table 50.
Return to Summary Table.
Figure 147. SS_CTRL0 Register
7
RESERVED
6
RESERVED
R/W
R/W
5
SS_PRE_DIV_
SEL
R/W
4
SS_MANUAL_
MODE
R/W
3
RESERVED
2
1
SS_RDM_EN
0
SS_TRI_EN
R/W
R/W
R/W
Table 50. RAMP_SS_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6
RESERVED
R/W
0
This bit is reserved
5
SS_PRE_DIV_SEL
R/W
0
select pll clock divide 2 as source clock in manual mode
4
SS_MANUAL_MODE
R/W
0
set ramp ss controller to manual mode
RESERVED
R/W
00
This bit is reserved
1
SS_RDM_EN
R/W
0
random SS enable
0
SS_TRI_EN
R/W
0
triangle SS enable
3-2
9.6.1.44 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in Figure 148 and described in Table 51.
Return to Summary Table.
Figure 148. SS_CTRL1 Register
7
RESERVED
R/W
6
5
SS_RDM_CTRL
R/W
4
3
2
1
0
SS_TRI_CTRL
R/W
Table 51. SS_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-4
SS_RDM_CTRL
R/W
000
Add Dither
3-0
SS_TRI_CTRL
R/W
0000
triangle SS frequency and range control
7
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9.6.1.45 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]
SS_CTRL2 is shown in Figure 149 and described in Table 52.
Return to Summary Table.
Figure 149. SS_CTRL2 Register
7
6
5
4
3
TM_FREQ_CTRL
R/W
2
1
0
Table 52. SS_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TM_FREQ_CTRL
R/W
10100000
control ramp frequency in manual mode, F=61440000/N
9.6.1.46 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in Figure 150 and described in Table 53.
Return to Summary Table.
Figure 150. SS_CTRL3 Register
7
6
5
TM_DSTEP_CTRL
R/W
4
3
2
1
TM_USTEP_CTRL
R/W
0
Table 53. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
control triangel mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
control triangle mode spread spectrum rise step in ramp ss manual
mode
9.6.1.47 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in Figure 151 and described in Table 54.
Return to Summary Table.
Figure 151. SS_CTRL4 Register
7
RESERVED
R/W
6
5
TM_AMP_CTRL
R/W
4
3
2
1
SS_TM_PERIOD_BOUNDRY
R/W
0
Table 54. SS_CTRL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-5
TM_AMP_CTRL
R/W
01
control ramp amp ctrl in ramp ss manual model
4-0
SS_TM_PERIOD_BOUN
DRY
R/W
00100
control triangle mode spread spectrum boundary in ramp ss manual
mode
7
74
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9.6.1.48 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in Figure 152 and described in Table 55.
Return to Summary Table.
Figure 152. CHAN_FAULT Register
7
6
5
4
RESERVED
R
3
CH1_DC_1
R
2
CH2_DC_1
R
1
CH1_OC_I
R
0
CH2_OC_I
R
Table 55. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000
This bit is reserved
3
CH1_DC_1
R
0
left channel DC fault
2
CH2_DC_1
R
0
right channel DC fault
1
CH1_OC_I
R
0
left channel over current fault
0
CH2_OC_I
R
0
right channel over current fault
9.6.1.49 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in Figure 153 and described in Table 56.
Return to Summary Table.
Figure 153. GLOBAL_FAULT1 Register
7
6
5
OTP_CRC_ER BQ_WR_ERRO LOAD_EEPRO
ROR
R
M_ERROR
R
R
R
4
DVDD_UV_I
3
DVDD_OV_I
2
CLK_FAULT_I
1
PVDD_OV_I
0
PVDD_UV_I
R
R
R
R
R
Table 56. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OTP_CRC_ERROR
R
0
Indicate OTP CRC check error.
6
BQ_WR_ERROR
R
0
the recent BQ is written failed
5
LOAD_EEPROM_ERROR R
0
0:
EEPROM
boot
load
was
done
1: EEPROM boot load was done unsuccessfully
RESERVED
R
00
This bit is reserved
2
CLK_FAULT_I
R
0
clock fault
1
PVDD_OV_I
R
0
PVDD OV fault
0
PVDD_UV_I
R
0
PVDD UV fault
4-3
successfully
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9.6.1.50 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in Figure 154 and described in Table 57.
Return to Summary Table.
Figure 154. GLOBAL_FAULT2 Register
7
6
5
RESERVED
4
3
R
2
1
CBC_FAULT_C CBC_FAULT_C
H2_I
H1_I
R
R
0
OTSD_I
R
Table 57. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0000
This bit is reserved
2
CBC_FAULT_CH2_I
R
0
right channel cycle by cycle over current fault
1
CBC_FAULT_CH1_I
R
0
left channel cycle by cycle over current fault
0
OTSD_I
R
0
over temperature shut down fault
9.6.1.51 WARNING Register (Offset = 73h) [reset = 0x00]
WARNING is shown in Figure 155 and described in Table 58.
Return to Summary Table.
Figure 155. WARNING Register
7
RESERVED
6
5
CBCW_CH1_I
4
CBCW_CH2_I
R
R
R
3
2
1
0
OTW_LEVEL4_ OTW_LEVEL3_ OTW_LEVEL2_ OTW_LEVEL1_
I
I
I
I
R
R
R
R
Table 58. WARNING Register Field Descriptions
76
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0
This bit is reserved
5
CBCW_CH1_I
R
0
left channel cycle by cycle over current warning
4
CBCW_CH2_I
R
0
right channel cycle by cycle over current warning
3
OTW_LEVEL4_I
R
0
over temperature warning leve4, 146C
2
OTW_LEVEL3_I
R
0
over temperature warning leve3, 134C
1
OTW_LEVEL2_I
R
0
over temperature warning leve2, 122C
0
OTW_LEVEL1_I
R
0
over temperature warning leve1, 112C
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9.6.1.52 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in Figure 156 and described in Table 59.
Return to Summary Table.
Figure 156. PIN_CONTROL1 Register
7
MASK_OTSD
R/W
6
MASK_DVDD_
UV
R/W
5
MASK_DVDD_
OV
R/W
4
MASK_CLK_F
AULT
R/W
3
RESERVED
R
2
MASK_PVDD_
UV
R/W
1
MASK_DC
0
MASK_OC
R/W
R/W
Table 59. PIN_CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MASK_OTSD
R/W
0
mask OTSD fault report
6
MASK_DVDD_UV
R/W
0
mask DVDD UV fault report
5
MASK_DVDD_OV
R/W
0
mask DVDD OV fault report
4
MASK_CLK_FAULT
R/W
0
mask clock fault report
3
RESERVED
R
0
2
MASK_PVDD_UV
R/W
0
mask PVDD UV fault report mask PVDD OV fault report
1
MASK_DC
R/W
0
mask DC fault report
0
MASK_OC
R/W
0
mask OC fault report
9.6.1.53 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in Figure 157 and described in Table 60.
Return to Summary Table.
Figure 157. PIN_CONTROL2 Register
7
6
CBC_FAULT_L CBC_WARN_L
ATCH_EN
ATCH_EN
R/W
R/W
5
CLKFLT_LATC
H_EN
R/W
4
OTSD_LATCH
_EN
R/W
3
OTW_LATCH_
EN
R/W
2
MASK_OTW
1
MASK_CBCW
R/W
R/W
0
MASK_CBC_F
AULT
R/W
Table 60. PIN_CONTROL2 Register Field Descriptions
Bit
Reset
Description
7
Field
CBC_FAULT_LATCH_EN R/W
Type
1
enable CBC fault latch
6
CBC_WARN_LATCH_EN
R/W
1
enable CBC warning latch
5
CLKFLT_LATCH_EN
R/W
1
enable clock fault latch
4
OTSD_LATCH_EN
R/W
1
enable OTSD fault latch
3
OTW_LATCH_EN
R/W
1
enable OT warning latch
2
MASK_OTW
R/W
0
mask OT warning report
1
MASK_CBCW
R/W
0
mask CBC warning report
0
MASK_CBC_FAULT
R/W
0
mask CBC fault report
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9.6.1.54 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in Figure 158 and described in Table 61.
Return to Summary Table.
Figure 158. MISC_CONTROL Register
7
DET_STATUS_
LATCH
R/W
6
5
4
OTSD_AUTO_
REC_EN
R/W
RESERVED
R/W
3
2
1
0
RESERVED
R/W
Table 61. MISC_CONTROL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
DET_STATUS_LATCH
R/W
0
1:latch clock detection status
RESERVED
R/W
00
This bit is reserved
OTSD_AUTO_REC_EN
R/W
0
OTSD auto recovery enable
RESERVED
R/W
0000
This bit is reserved
0:don't latch clock detection status
6-5
4
3-0
9.6.1.55 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]
CBC_CONTROL is shown in Figure 159 and described in Table 62.
Return to Summary Table.
Figure 159. CBC_CONTROL Register
7
6
5
RESERVED
4
3
R/W
2
CBC_EN
R/W
1
0
CBC_WARN_E CBC_FAULT_E
N
N
R/W
R/W
Table 62. CBC_CONTROL Register Field Descriptions
78
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000
This bit is reserved
2
CBC_EN
R/W
0
enable CBC function
1
CBC_WARN_EN
R/W
0
enable CBC warning
0
CBC_FAULT_EN
R/W
0
enable CBC fault
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9.6.1.56 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in Figure 160 and described in Table 63.
Return to Summary Table.
Figure 160. FAULT_CLEAR Register
7
ANALOG_FAU
LT_CLEAR
W
6
5
4
3
RESERVED
2
1
0
R/W
Table 63. FAULT_CLEAR Register Field Descriptions
Bit
7
6-0
Field
Reset
Description
ANALOG_FAULT_CLEAR W
Type
0
WRITE CLEAR BIT once write this bit to 1, device will clear analog
fault
RESERVED
0000000
This bit is reserved
R/W
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the TAS5825P device into the larger system.
10.1.1 Bootstrap Capacitors
The output stage of the TAS5825P uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.22-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.22-µF capacitor between OUT_A and BST_A for
bootstrapping the A channel. Similarly, connect another 0.22-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
10.1.2 Inductor Selections
It is required that the peak current is smaller than the OCP (Over current protection) value which is 7.5 A, there
are 3 cases which cause high peak current flow through inductor.
1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ.
I peak _ power _ up | PVDD u C / L u sin(1 / L u C u T / Fsw )
(1)
NOTE
θ=0.5 (BD Modulation), 0.14 (1SPW Modulation), 0.14 (Hybrid Modulation)
Table 64. Peak Current During Power Up
PVDD
L (µH)
C (µF)
Fsw (kHz)
Ipeak_power_up
24
4.7
0.68
384
6.07A
24
4.7
0.68
768
3.25A
24
10
0.68
384
3A
24
10
0.68
768
1.55A
12
4.7
0.68
384
3.32A
12
10
0.68
384
1.55A
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping causes PWM
duty cycle increase dramatically. This is the worst case and it rarely happens.
I peak _ clipping | PVDD u (1 T ) /( Fsw u L)
(2)
3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.
I peak _ output _ power | 2 u Max _ Output _ Power / Rspea ker_ Load
(3)
Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
It's suggested that inductor saturation current ISAT, is larger than the amplifier peak current during power-up and
play audio.
80
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I SAT t max(I peak _ power _ up , I peak _ clipping, I peak _ output_ power )
(4)
In addition, the effective inductance at the peak current is required to be at least 80% of the inductance value in
Table 65 to meet datasheet specifications.
Table 65. Inductor Requirements
PVDD (V)
Switching Frequency (kHz)
Minimum Inductance (L) (µH)
≤ 12
384
4.7
> 12
384
10
For higher switching frequencies (Fsw), select the inductors with minimum inductance to be 384kHz / Fsw × L.
10.1.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
10.1.4 Output EMI Filtering
The TAS5825P device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power and
film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design
(SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon
the desired load and response.
For EMI performance and EMI Design consideration, reference to application report: TAS5825M Design
Considerations for EMC.
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10.2 Typical Applications
10.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels are
amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based
upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
Figure 161 shows the 2.0 (Stereo BTL) system application.
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Figure 161. 2.0 (Stereo BTL) System Application Schematic
82
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Typical Applications (continued)
10.2.2 Design Requirements
• Power supplies:
– 3.3-V supply
– 5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (such as EEPROM and FLASH) used for coefficients.
The requirements for the supporting components for the TAS5825P device in a Stereo 2.0 (BTL) system is
provide in Table 66.
Table 66. Supporting Component Requirements for Stereo 2.0 (BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1, C16
0.1 µF
0402
CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
C2, C17, C37, C38
22 µF
0805
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
C3
4.7 µF
0603
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
C4
0.1 µF
0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
1 µF
0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
C6, C9, C10, C13
0.47 µF
0603
CAP, CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
C41, C42, C43, C44
0.68 µF
0805
CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
C5, C14, C15
L1, L2, L3, L4
R1
Inductor, Shielded, Ferrite, 10 µH, 4.4 A, 0.0304 Ω,
SMD 1274AS-H-100M=P3
10 µH
0Ω
0402
RES, 0, 5%, 0.063 W, 0402
R20, R21, R23
10 kΩ
0402
RES, 10.0 k, 1%, 0.063 W, 0402
R22
1 kΩ
0402
RES, 1.0 k, 1%, 0.063 W, 0402
10.2.3 Detailed Design procedures
This Design procedures can be used for both Stereo 2.0 and Mono Mode.
10.2.3.1 Step One: Hardware Integration
• Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Following the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they
are given precedent as design trade-offs are made is recommended.
– For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
10.2.3.2 Step Two: Hardware Integration
Using the TAS5825PEVM evaluation module and the PPC3 app to configure the desired device settings.
10.2.3.3 Step Three: Software Integration
• Using the End System Integration feature of the PPC3 app to generate a baseline configuration file.
• Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
• Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
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10.2.4 Application Curves
45
10
THD+N=1%, R L=8:
THD+N=10%, R L=8:
40
5 PVcc=12V
TA=25qC
2 R L=8:
1
0.5
30
THD+N(%)
Output Power (W)
35
25
20
15
0.2
0.1
0.05
0.02
0.01
10
0.005
BTL Mode
TA=25qC
5
0.002
0
4
6
8
Load=8Ω
10
12 14 16 18
Supply Voltage (V)
Hybrid Modulation
20
22
24
0.001
20
26
Fsw=384kHz
PVDD=12V
5 PVcc=24V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=5W
20k
D002
D303
Fsw=384kHz
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD=18V
1k
Frequency (Hz)
Hybrid Modulation
10k
0.001
20
20k
100
D002
D306
Fsw=384kHz
PVDD=24V
Figure 164. THD+N vs Frequency
1k
Frequency (Hz)
Hybrid Modulation
10k
20k
D002
D309
Fsw=384kHz
Figure 165. THD+N vs Frequency
10
10
5 PV CC =18V
TA=25qC
2 Fin=1kHz
5 PV CC =12V
TA=25qC
2 Fin=1kHz
1
1
0.5
THD+N (%)
0.5
THD+N (%)
Hybrid Modulation
10k
10
5 PVcc=18V
TA=25qC
2 R L=8:
1
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.002
1k
Frequency (Hz)
Figure 163. THD+N vs Frequency
10
0.005
100
D014
D226
D037
Figure 162. Output Power vs PVDD
0.01
Load=4:
Load=6:
Load=8:
0.001
0.01
PVDD=12V
0.005
0.002
0.1
1
Output Power (W)
Hybrid Modulation
Load=4:
Load=6:
Load=8:
0.001
0.01
10
D007
D112
Fsw=384kHz
PVDD=18V
Figure 166. THD+N vs Power
84
P O=1W
P O =2.5W
P O=5W
0.1
1
Output Power (W)
Hybrid Modulation
10
20
D007
D113
Fsw=384kHz
Figure 167. THD+N vs Power
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10.2.5 MONO (PBTL) Systems
In MONO mode, TAS5805M can be used as PBTL mode to drive sub-woofer with more output power.
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Figure 168. Sub-woofer (PBTL) Application Schematic
Table 67. Supporting Component Requirements for Sub-woofer (PBTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1, C2
390uF
10mmx10mm
CAP, AL, 390 μF, 35 V, +/- 20%, 0.08 ohm, SMD
C4, C5
0.1 µF
0402
CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
C3, C6
22 µF
0805
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
C7
4.7 µF
0603
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
C8
0.1 µF
0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
1 µF
0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
C12,C13,C16,C17
0.47 µF
0603
CAP, CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
C14,C15
0.68 µF
0805
CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
L1,L2
4.7 µH
C9,C10,C11
Inductor, Shielded, 4.7 μH, 8.7 A
R2, R5
1 kΩ
0402
RES, 1.0k, 1%, 0.063 W, 0402
R3,R4,R6
10 kΩ
0402
RES, 10.0 k, 1%, 0.063 W, 0402
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10.2.6 Application Curves
10
100
5 PV CC =24V
TA=25qC
2 PBTL Mode
1
90
80
70
Efficiency (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
60
50
40
30
0.01
20
0.005
0.002
Load=4:
Load=3:
0.001
0.1
0
1
10
20
100
Output Power (W)
PVDD = 18 V
Hybrid Modulation
0
10
D007
D408
Fsw = 384 kHz
Load = 4Ω
Figure 169. THD+N vs Output Power
86
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
TA=25qC
R L=4:
10
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20
30
40
50
Output Power (W)
Hybrid Modulation
60
70
80
D024
D120
Fsw = 384 kHz
Figure 170. Efficiency vs Output Power
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11 Power Supply Recommendations
The TAS5825P device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one lowvoltage power supply which is calls DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions
table. The two power supplies do not have a required powerup sequence. The power supplies can be powered
on in any order.
DVDD
1.8V/3.3V'
Internal Digital
Circuitry
Digital IO
VR_DIG
1.5V
External Filtering/Decoupling
LDO
DVDD
PVDD
4.5V~26.4V
Output Stage
Power Supply
Gate Drive
Voltage
GVDD
5V
External Filtering/Decoupling
LDO
Internal Analog
Circuitry
PVDD
LDO
AVDD
5V
External Filtering/Decoupling
Copyright © 2017, Texas Instruments Incorporated
Figure 171. Power Supply Function Block Diagram
11.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
Figure 171, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are
highlighted in the Application and Implementation section and the Layout Example section and must be followed
as closely as possible for proper operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5825P device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuity. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
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11.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TAS5825PEVM and must be followed as closely as possible for proper operation and
performance. Due to the high-voltage switching of the output stage, it is particularly important to properly
decouple the output power stages in the manner described in the TAS5825P device Application and
Implementation. Lack of proper decoupling, like that shown in the Application and Implementation, results in
voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5825P internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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12 Layout
12.1 Layout Guidelines
12.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the Layout Example section. These examples
represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These
designs can be modified slightly as needed to meet the needs of a given application. In some applications, for
instance, solution size can be compromised to improve thermal performance through the use of additional
contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by
routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it
is recommended to start from the guidance shown in the Layout Example section and work with TI field
application engineers or through the E2E community to modify it based upon the application specific goals.
12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the TAS5825P device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5825P device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the Layout Example section.
12.1.3 Optimizing Thermal Performance
Follow the layout example shown in the Figure 172 to achieve the best balance of solution size, thermal, audio,
and electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
12.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5825P device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5825P device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5825P device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5825P
device.
• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
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Layout Guidelines (continued)
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
12.1.3.2 Stencil Pattern
The recommended drawings for the TAS5825P device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
NOTE
The customer must verify that deviation from the guidance shown in the package
addendum, including the deviation explained in this section, meets the customer’s quality,
reliability, and manufacturability goals.
12.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5825P device is soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5825P
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5825P
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Layout Example section, this interface can benefit from improved thermal performance.
NOTE
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Layout Example section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5825P device to open up the current path
to and from the device.
12.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
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Layout Guidelines (continued)
manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the Layout Example section. It is important that the total area of the
aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the
thermal pad itself.
12.2 Layout Example
2
900mm
11cm2
From
System
Processor
Figure 172. 2.0 (Stereo BTL) 3-D View
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Layout Example (continued)
Figure 173. 2.0 (Stereo BTL) Top Copper View
92
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Device Nomenclature
The glossary listed in the Glossary section is a general glossary with commonly used acronyms and words which
are defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,
and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this
product and documentation, collateral, or support tools and software used with this product. For any additional
questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one halfbridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device
which serves as a central system controller, providing control information to devices connected to it as well as
gathering audio source data from devices upstream from it and distributing it to other devices. This device often
configures the controls of the audio processing devices (like the TAS5825P) in the audio path in order to
optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure
level, safe operating area of the system, and user preference.
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
13.1.2 Development Support
For RDGUI software, please consult your local field support engineer.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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13.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
94
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TAS5825PRHBR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RHB
32
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-25 to 85
5825P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5825PRHBR
Package Package Pins
Type Drawing
VQFN
RHB
32
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5825PRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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