Texas Instruments | TPA3255-Q1 315-W Stereo, 600-W mono PurePath™ ultra-HD analog-input (Rev. A) | Datasheet | Texas Instruments TPA3255-Q1 315-W Stereo, 600-W mono PurePath™ ultra-HD analog-input (Rev. A) Datasheet

Texas Instruments TPA3255-Q1 315-W Stereo, 600-W mono PurePath™ ultra-HD analog-input (Rev. A) Datasheet
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TPA3255-Q1
SLASEM8A – JANUARY 2019 – REVISED MARCH 2019
TPA3255-Q1 315-W Stereo, 600-W mono PurePath™ ultra-HD analog-input
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Temperature Grade 2: –40°C to +105°C, TA
Differential Analog Inputs
Total Output Power at 10% THD+N
– 315-W Stereo into 4 Ω in BTL Configuration
– 180-W Stereo into 8 Ω in BTL Configuration
– 600-W Mono into 2 Ω in PBTL Configuration
Total Output Power at 1% THD+N
– 255-W Stereo into 4 Ω in BTL Configuration
– 150-W Stereo into 8 Ω in BTL Configuration
– 495-W Mono into 2 Ω in PBTL Configuration
Advanced Integrated Feedback Design with Highspeed Gate Driver Error Correction
– Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources
– Ultra Low 0.006% THD+N at 1 W into 4 Ω and
<0.01% THD+N to Clipping
– >65 dB PSRR (BTL, 1 kHz, No Input Signal)
– <85 µV (A-Weighted) Output Noise
– >111 dB (A Weighted) SNR
Multiple Configurations Possible:
– Stereo, Mono, 2.1 and 4xSE
Click and Pop Free Startup and Stop
90% Efficient Class-D Operation (4 Ω)
Wide 18-V to 53.5V Supply Voltage Operation
Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short Circuit
Protection) With Error Reporting
Automotive External Amplifiers
Subwoofers
Actuators and Suspension
3 Description
TPA3255-Q1 is a high performance class-D power
amplifier that enables true premium sound quality
with class-D efficiency. It features an advanced
integrated feedback design and proprietary highspeed gate driver error correction (PurePath™ UltraHD). This technology allows ultra low distortion
across the audio band and superior audio quality.
The device is operated in AD-mode, and can drive up
to 2 x 315 W into 4-Ω load at 10% THD and 2 x 150
W unclipped into 8-Ω load and features a 2-VRMS
analog input interface that works seamlessly with high
performance DACs such as TI's PCM5242. In
addition to excellent audio performance, TPA3255-Q1
achieves both high power efficiency and very low
power stage idle losses below 2.5W. This is achieved
through the use of 85-mΩ MOSFETs and an
optimized gate driver scheme that achieves
significantly lower idle losses than typical discrete
implementations.
Device Information(1)
PART NUMBER
TPA3255-Q1
LC Filter
TAS5630
LEFT
LC Filter
/CLIP_OTW
/RESET
/FAULT
GVDD
Operation Mode Select
Switching Frequency Select
Master/Slave Synchronization
M1:M2
FREQ_ADJ
Power Supply
51V
OSC_IO
110VAC->240VAC
THD+N - Total Harmonic Distortion + Noise - %
Total Harmonic Distortion
TPA3255-Q1
Audio
Source
And Control
BODY SIZE (NOM)
6.10 mm x 14.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
RIGHT
PACKAGE
HTSSOP (44)
10
4:
8:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
1
10
Po - Output Power - W
100
400
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3255-Q1
SLASEM8A – JANUARY 2019 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
8
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Audio Characteristics (BTL) ...................................... 8
Audio Characteristics (SE) ....................................... 9
Audio Characteristics (PBTL) ................................... 9
Typical Characteristics, BTL Configuration............. 10
Typical Characteristics, SE Configuration............. 12
Typical Characteristics, PBTL Configuration ........ 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagrams ..................................... 15
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Applications ................................................ 22
10 Power Supply Recommendations ..................... 29
10.1
10.2
10.3
10.4
Power Supplies .....................................................
Powering Up..........................................................
Powering Down .....................................................
Thermal Design.....................................................
29
30
31
31
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Examples................................................... 34
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2019) to Revision A
•
2
Page
Changed the data sheet status From: Advanced Information To: Production data .............................................................. 1
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5 Pin Configuration and Functions
The TPA3255-Q1 is available in a thermally enhanced TSSOP package.
The package type contains a PowerPAD™ that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DDV Package
HTSSOP 44-Pin
(Top View)
GVDD_AB
1
44
BST_A
VDD
2
43
BST_B
M1
3
42
GND
M2
4
41
GND
INPUT_A
5
40
OUT_A
INPUT_B
6
39
OUT_A
OC_ADJ
7
38
PVDD_AB
FREQ_ADJ
8
37
PVDD_AB
OSC_IOM
9
36
PVDD_AB
OSC_IOP
10
35
OUT_B
DVDD
11
34
GND
GND
12
Thermal
Pad
33
GND
GND
13
32
OUT_C
AVDD
14
31
PVDD_CD
C_START
15
30
PVDD_CD
INPUT_C
16
29
PVDD_CD
INPUT_D
17
28
OUT_D
RESET
18
27
OUT_D
FAULT
19
26
GND
VBG
20
25
GND
CLIP_OTW
21
24
BST_C
GVDD_CD
22
23
BST_D
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Pin Functions
NAME
NO.
I/O
AVDD
14
P
Internal voltage regulator, analog section
BST_A
44
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B
43
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C
24
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D
23
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW
21
O
Clipping warning and Over-temperature warning; open drain; active low. Do not connect if not used.
C_START
15
O
Startup ramp, requires a charging capacitor to GND
DVDD
11
P
Internal voltage regulator, digital section
FAULT
19
O
Shutdown signal, open drain; active low. Do not connect if not used.
FREQ_ADJ
8
O
Oscillator freqency programming pin
12, 13, 25, 26,
33, 34, 41, 42
P
GVDD_AB
1
P
Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD
22
P
Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A
5
I
Input signal for half bridge A
INPUT_B
6
I
Input signal for half bridge B
INPUT_C
16
I
Input signal for half bridge C
INPUT_D
17
I
Input signal for half bridge D
M1
3
I
Mode selection 1 (LSB)
M2
4
I
Mode selection 2 (MSB)
OC_ADJ
7
I/O
Over-Current threshold programming pin
OSC_IOM
9
I/O
Oscillator synchronization interface. Do not connect if not used.
OSC_IOP
10
I/O
Oscillator synchronization interface. Do not connect if not used.
OUT_A
39, 40
O
Output, half bridge A
OUT_B
35
O
Output, half bridge B
OUT_C
32
O
Output, half bridge C
OUT_D
27, 28
O
Output, half bridge D
PVDD_AB
36, 37, 38
P
PVDD supply for half-bridge A and B
PVDD_CD
29, 30, 31
P
PVDD supply for half-bridge C and D
RESET
18
I
Device reset Input; active low
VDD
2
P
Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG
20
P
Internal voltage reference requires a 1-µF capacitor to GND for decoupling.
P
Ground, connect to grounded heat sink
GND
PowerPad™
DESCRIPTION
Ground
Table 1. Mode Selection Pins
MODE
PINS (1)
INPUT
MODE (2)
OUTPUT
CONFIGURATION
M2
M1
0
0
2N + 1
2 × BTL
0
1
2N/1N + 1
1 x BTL + 2 x SE
1
(1)
(2)
4
0
1
2.1 BTL + SE mode. Channel AB: BTL, channel C + D: SE
INPUT_C
INPUT_D
0
0
1 x BTL
Mono BTL configuration. BTL channel AB active,
channel CD not switching. Connect INPUT_C to DVDD
and INPUT_D to GND. (1)
1
0
4 x SE
Single ended output configuration
2N + 1
1N +1
Stereo BTL output configuration
Parallelled BTL configuration. Connect INPUT_C and
INPUT_D to GND. (1)
1 x PBTL
1
DESCRIPTION
1 refers to logic high (DVDD level), 0 refers to logic low (GND).
2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control (RESET) input pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Interface pins
(1)
MIN
MAX
BST_X to GVDD_X (2) (3) (4)
–0.3
69
V
VDD to GND
–0.3
11.4
V
GVDD_X to GND (2) (3)
–0.3
11.4
V
PVDD_X to GND (2) (3)
–0.3
69
V
DVDD to GND
–0.3
4.2
V
AVDD to GND
–0.3
8.5
V
VBG to GND
-0.3
4.2
V
OUT_X to GND (2) (4)
–0.3
69
V
BST_X to GND (2) (4)
–0.3
81.5
V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND
–0.3
4.2
V
RESET, FAULT, CLIP_OTW to GND
–0.3
4.2
V
INPUT_X to GND
–0.3
7
V
9
mA
Continuous sink current, RESET, FAULT, CLIP_OTW to GND
UNIT
TA
Operating ambient temperature
-40
105
°C
Tstg
Storage temperature range
–40
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
GVDD_X and PVDD_X represent a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD. PVDD_X is PVDD_AB
or PVDD_CD
OUT_X and BST_X represent a half bridge output node or bootstrap supply. OUT_X is OUT_A, OUT_B, OUT_C or OUT_D. BST_X is
BST_A, BST_B, BST_C or BST_D.
6.2 ESD Ratings
VESD
(1)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002 HBM ESD Classification
Level 2 (1)
±3000
V
Charged-device model (CDM), per AEC Q100-011 CDM ESD
Classification Level C4A
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage, RL = 4Ω
18
51
53.5
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
9.8
10.6
11.4
V
VDD
Digital regulator supply voltage
DC supply voltage
9.8
10.6
11.4
V
3.4
4
1.7
3
1.7
2
RL(BTL)
RL(SE)
Output filter inductance within recommended
value range
Load impedance
RL(PBTL)
LOUT(BTL)
LOUT(SE)
5
Output filter inductance
Minimum output inductance at IOC
5
LOUT(PBTL)
R(FREQ_ADJ)
CPVDD
μH
5
PWM frame rate programming resistor
Nominal; Master mode
29.7
30
30.3
AM1; Master mode
19.8
20
20.2
AM2; Master mode
9.9
10
10.1
Resistor tolerance = 5%, RL = 4Ω
22
PVDD close decoupling capacitors
1
ROC
Over-current programming resistor
ROC(LATCHED)
Over-current programming resistor
V(FREQ_ADJ)
Voltage on FREQ_ADJ pin for slave mode
operation
TJ
Junction temperature
Resistor tolerance = 5%, RL ≥ 6Ω, PVDD =
53.5V (1)
kΩ
μF
30
kΩ
30
Resistor tolerance = 5%, RL = 4Ω
(1)
Ω
47
64
Resistor tolerance = 5%, RL ≥ 6Ω, PVDD =
53.5V (1)
64
Slave mode
3.3
-40
kΩ
V
125
°C
For load impedance ≥ 6 Ω PVDD can be increased, provided a reduced over-current threshold is set
6.4 Thermal Information
TPA3255
THERMAL METRIC
DDV 44-PINS HTSSOP
(1)
UNIT
JEDEC STANDARD 4
LAYER PCB
FIXED 85°C HEATSINK
TEMPERATURE (2)
RθJA
Junction-to-ambient thermal resistance
50.7
2.4 (2)
RθJC(top)
Junction-to-case (top) thermal resistance
0.36
0.3
RθJB
Junction-to-board thermal resistance
24.4
n/a
ψJT
Junction-to-top characterization parameter
0.19
0.5
ψJB
Junction-to-board characterization parameter
24.2
n/a
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
(1)
(2)
6
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil
thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the
heatsink.
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6.5 Electrical Characteristics
PVDD_X = 51 V, GVDD_X = 10.6 V, VDD = 10.6 V, TC (Case temperature) = 75°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD
Voltage regulator, only used as reference
node
VDD = 10.6 V
AVDD
Voltage regulator, only used as reference
node
VDD = 10.6 V
IVDD
VDD supply current
IGVDD_X
Gate-supply current per full-bridge
IPVDD_X
PVDD idle current per full bridge
7.75
Operating, 50% duty cycle
30
Idle, reset mode
14
50% duty cycle
44
Reset mode
V
mA
mA
5
50% duty cycle with recommended output filter
V
24
mA
Reset mode, No switching
5
mA
VDD = 0V, GVDD_X = 0V
1.25
mA
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage swing, peak - peak
20
7
V
IIN
Maximum input current
1
mA
G
Inverting voltage Gain
VOUT/VIN
21.5
Nominal, Master Mode, 1% Resistor
450
AM1, Master Mode, 1% Resistor
500
AM2, Master Mode, 1% Resistor
600
kΩ
dB
OSCILLATOR
FPWM
PWM Output Frequency
PWM Output Frequency Variation
ΔFPWM
1% Resistor
5
Nominal, Master Mode, FPWM × 6
fOSC(IO+)
Oscillator Frequency
Oscillator Frequency Variation
VIH
High level input voltage
VIL
Low level input voltage
%
2.7
AM1, Master Mode, FPWM × 6
3
AM2, Master Mode, FPWM × 6
ΔfOSC(IO+)
kHz
3.45
3.6
MHz
3.75
5
%
1.86
V
1.45
V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, Includes metallization resistance,
GVDD = 10.6 V
85
mΩ
85
mΩ
8.7
V
0.6
V
14.5
V
I/O
PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,VDD,GVDD
Vuvp,VDD,
GVDD,hyst
Vuvp,PVDD
(1)
Undervoltage protection limit, PVDD_x
Vuvp,PVDD,hyst (1)
1.4
V
OTW
Overtemperature warning, CLIP_OTW (1)
OTWhyst (1)
Temperature drop needed below OTW
temperature for CLIP_OTW to be inactive
after OTW event.
OTE (1)
Overtemperature error
OTEhyst (1)
A reset needs to occur for FAULT to be
released following an OTE event
15
°C
OTEOTW(differential) (1)
OTE-OTW differential
30
°C
OLPC
Overload protection counter
fPWM = 450 kHz (1024 PWM cycles)
2.3
ms
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 22 kΩ
17
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 30 kΩ
13
IOC
(1)
Overcurrent limit protection
110
120
130
20
140
150
°C
°C
160
°C
A
Specified by design.
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Electrical Characteristics (continued)
PVDD_X = 51 V, GVDD_X = 10.6 V, VDD = 10.6 V, TC (Case temperature) = 75°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resistor – programmable, peak current in 1Ω load,
ROCP = 47kΩ
17
Resistor – programmable, peak current in 1Ω load,
ROCP = 64kΩ
13
DC Speaker Protection Current Threshold
BTL current imbalance threshold
1.5
A
IOCT
Overcurrent response time
Time from switching transition to flip-state induced
by overcurrent.
150
ns
IPD
Output pulldown current of each half
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
3
mA
IOC(LATCHED)
IDCspkr
Overcurrent limit protection
A
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
1.9
M1, M2, OSC_IOP, OSC_IOM, RESET
V
0.8
V
100
μA
OTW/SHUTDOWN (FAULT)
RINT_PU
Internal pullup resistance, CLIP_OTW to
DVDD, FAULT to DVDD
26
kΩ
ΔRINT_PU
Internal pullup resistance variation,
CLIP_OTW to DVDD, FAULT to DVDD
25
%
VOH
High level output voltage
Internal pullup resistor
3.3
3.6
V
VOL
Low level output voltage
IO = 4 mA
10
500
mV
Device fanout
CLIP_OTW, FAULT
No external pullup
30
3
devices
6.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V,
GVDD_X = 10.6 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 4 Ω, 10% THD+N
315
RL = 4 Ω, 1% THD+N
255
RL = 8 Ω, 10% THD+N
180
MAX
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor Grounded
85
|VOS|
Output offset voltage
Inputs AC coupled to GND
15
SNR
Signal-to-noise ratio (1)
112
dB
DNR
Dynamic range
113
dB
Pidle
Power dissipation due to Idle losses (IPVDD)
2.5
W
RL = 8 Ω, 1% THD+N
(1)
(2)
8
PO = 0, 4 channels switching (2)
W
150
0.006%
μV
60
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
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6.7 Audio Characteristics (SE)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V,
GVDD_X = 10.6 V, RL = 2 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 2 Ω, 10% THD+N
148
RL = 2 Ω, 1% THD+N
120
MAX
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
160
μV
Vn
(1)
W
0.04%
SNR
Signal to noise ratio
A-weighted
101
dB
DNR
Dynamic range
A-weighted
101
dB
Pidle
Power dissipation due to idle losses (IPVDD)
PO = 0, 4 channels switching (2)
2
W
(1)
(2)
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
6.8 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V,
GVDD_X = 10.6 V, RL = 2 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
TYP
605
RL = 2 Ω, 1% THD+N
495
RL = 3 Ω, 10% THD+N
455
RL = 3 Ω, 1% THD+N
370
RL = 4 Ω, 10% THD+N
360
RL = 4 Ω, 1% THD+N
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
(1)
MIN
RL = 2 Ω, 10% THD+N
MAX
UNIT
W
285
0.008%
70
μV
SNR
Signal to noise ratio
A-weighted
114
dB
DNR
Dynamic range
A-weighted
114
dB
Pidle
Power dissipation due to idle losses (IPVDD)
PO = 0, 4 channels switching (2)
2.5
W
(1)
(2)
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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6.9 Typical Characteristics, BTL Configuration
10
1
TC = 75qC
1W
25W
150W
0.1
0.01
0.001
0.0003
20
100
RL = 4 Ω
1k
f - Frequency - Hz
10k
20k
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 10.6 V, RL = 4 Ω, fS = 450 kHz, ROC = 22
kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless
otherwise noted.
TC = 75°C
PVDD = 51V
TC = 75qC
0.1
0.01
0.001
100
RL = 8 Ω
1k
f - Frequency - Hz
10k
20k
P = 1W, 25W,
100W
TC = 75°C
4:
6:
8:
1
0.1
0.01
TC = 75°C
100
400
1k
f - Frequency - Hz
PVDD = 51V
10k
40k
D002
TC = 75°C
PVDD = 51V
10
TC = 75qC
1W
25W
100W
1
0.1
0.01
0.001
20
100
1k
f - Frequency - Hz
P = 1W, 25W,
100W
AUX-0025 filter, 80 kHz analyzer BW
10k
40k
D004
TC = 75°C
PVDD = 53.5V
Figure 4. Total Harmonic Distortion+Noise vs Frequency
10
6:
8:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
D005
Figure 5. Total Harmonic Distortion + Noise vs Output
Power
10
100
RL = 8 Ω
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 4 Ω, 6 Ω, 8 Ω
0.001
20
Figure 2. Total Harmonic Distortion+Noise vs Frequency
Figure 3. Total Harmonic Distortion+Noise vs Frequency
1
10
Po - Output Power - W
0.01
D003
PVDD = 53.5V
TA = 75qC
0.001
10m
100m
0.1
P = 1W, 25W,
150W
AUX-0025 filter, 80 kHz analyzer BW
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
0.0002
20
1
RL = 4 Ω
Figure 1. Total Harmonic Distortion+Noise vs Frequency
1
TC = 75qC
1W
25W
150W
D001
P = 1W, 25W,
150W
1W
25W
100W
10
RL = 6 Ω, 8 Ω
1
10
Po - Output Power - W
TC = 75°C
100
300
D006
PVDD = 53.5V
Figure 6. Total Harmonic Distortion + Noise vs Output
Power
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Typical Characteristics, BTL Configuration (continued)
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 10.6 V, RL = 4 Ω, fS = 450 kHz, ROC = 22
kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless
otherwise noted.
300
360
4:
6:
8:
280
240
200
160
120
80
20
25
30
35
40
45
PVDD - Supply Voltage - V
RL = 4 Ω, 6 Ω, 8 Ω
50
200
150
100
50
THD+N = 10%
TC = 75qC
40
0
15
4:
6:
8:
250
PO - Output Power - W
PO - Output Power - W
320
55
THD+N = 1%
TC = 75qC
0
15
60
THD+N = 10%
TC = 75°C
25
30
35
40
45
PVDD - Supply Voltage - V
RL = 4 Ω, 6 Ω, 8 Ω
Figure 7. Output Power vs Supply Voltage
50
55
60
D008
THD+N = 1%
TC = 75°C
Figure 8. Output Power vs Supply Voltage
100
100
4:
6:
8:
4:
6:
8:
80
Power Loss - W
Efficiency - %
20
D007
10
60
40
20
TC = 75qC
TC = 75qC
0
1
10m
100m
1
10
2 Channel Output Power - W
RL = 4 Ω, 6 Ω, 8 Ω
THD+N = 10%
100
0
700
200
300
400
500
2 Channel Output Power - W
D009
TC = 75°C
RL = 4 Ω, 6 Ω, 8 Ω
Figure 9. System Efficiency vs Output Power
600 650
D010
THD+N = 10%
TC = 75°C
Figure 10. System Power Loss vs Output Power
0
350
Noise Amplitude - dB
300
PO - Output Power - W
100
250
200
150
100
4:
6:
8:
50
TC = 75qC
-20 Vref = 36.06 V
FFT size = 16384
-40
4:
-60
-80
-100
-120
-140
THD+N = 10%
-160
0
0
RL = 4 Ω, 6 Ω, 8 Ω
25
50
75
TC - Case Temperature - qC
THD+N = 10%
100
0
5k
D011
TC = 75°C
Figure 11. Output Power vs Case Temperature
10k
15k
20k 25k 30k
f - Frequency - Hz
4 Ω, VREF = 36.06 V
(1% Output power)
AUX-0025 filter, 80 kHz
analyzer BW
35k
40k
45k48k
D012
FFT =
16384
TC = 75°C
Figure 12. Noise Amplitude vs Frequency
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6.10 Typical Characteristics, SE Configuration
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 10.6 V, RL = 3 Ω, fS = 450 kHz, ROC = 22
kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
10
2:
3:
4:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
RL = 2Ω, 3Ω, 4Ω
1
10
Po - Output Power - W
100 200
1
0.1
0.01
0.001
20
100
10k
20k
D014
P = 1W, 20W, 50W
TC = 75°C
Figure 14. Total Harmonic Distortion+Noise vs Frequency
180
10
TC = 75qC
2:
3:
4:
160
PO - Output Power - W
1W
20W
50W
1
0.1
0.01
140
120
100
80
60
40
THD+N = 10%
TC = 75qC
20
0
15
0.001
20
100
1k
f - Frequency - Hz
10k 20k 40k
D015
30
35
40
45
PVDD - Supply Voltage - V
50
55
60
D016
THD+N = 10%
TC = 75°C
Figure 16. Output Power vs Supply Voltage
175
2:
3:
4:
PO - Output Power - W
150
100
80
60
40
20
0
15
25
TC = 75°C
140
120
20
RL = 2Ω, 3Ω, 4Ω
Figure 15. Total Harmonic Distortion+Noise vs Frequency
PO - Output Power - W
1k
f - Frequency - Hz
RL = 3Ω
TC = 75°C
RL = 3Ω
P = 1W, 20W, 50W
AUX-0025 filter, 80 kHz analyzer BW
125
100
75
50
2:
3:
4:
25
THD+N = 1%
TC = 75qC
THD+N = 10%
0
20
RL = 2Ω, 3Ω, 4Ω
25
30
35
40
45
PVDD - Supply Voltage - V
THD+N = 1%
50
55
60
0
D017
TC = 75°C
Figure 17. Output Power vs Supply Voltage
12
TC = 75qC
1W
20W
50W
D013
Figure 13. Total Harmonic Distortion+Noise vs Output
Power
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 2Ω, 3Ω, 4Ω
25
50
75
TC - Case Temperature - qC
THD+N = 10%
100
D018
TC = 75°C
Figure 18. Output Power vs Case Temperature
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6.11 Typical Characteristics, PBTL Configuration
10
2:
3:
4:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
RL = 2Ω, 3Ω, 4Ω
1
10
Po - Output Power - W
100
700
10
1
0.1
0.01
0.001
0.0003
20
TC = 75°C
100
RL = 2Ω
1k
f - Frequency - Hz
D020
P = 1W, 50W, 375W
TC = 75°C
2:
3:
4:
PO - Output Power - W
600
1
0.1
0.01
500
400
300
200
100
0.001
20
100
1k
f - Frequency - Hz
10k
0
15
40k
D021
TC = 75°C
THD+N = 10%
TC = 75qC
20
25
RL = 2Ω, 3Ω, 4Ω
30
35
40
45
PVDD - Supply Voltage - V
50
55
60
D022
THD+N = 10%
TC = 75°C
Figure 22. Output Power vs Supply Voltage
Figure 21. Total Harmonic Distortion+Noise vs Frequency
600
700
2:
3:
4:
PO - Output Power - W
600
400
300
200
100
0
15
20k
700
TC = 75qC
1W
50W
375W
500
10k
Figure 20. Total Harmonic Distortion+Noise vs Frequency
10
RL = 2Ω
P = 1W, 50W, 375W
AUX-0025 filter, 80 kHz analyzer BW
PO - Output Power - W
TC = 75qC
1W
50W
375W
D019
Figure 19. Total Harmonic Distortion+Noise vs Output
Power
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51V, GVDD_X = 10.6 V, RL = 2Ω, fS = 450 kHz, ROC = 22
kΩ, TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
500
400
300
200
2:
3:
4:
100
THD+N = 1%
TC = 75qC
THD+N = 10%
0
20
RL = 2Ω, 3Ω, 4Ω
25
30
35
40
45
PVDD - Supply Voltage - V
THD+N = 1%
50
55
60
0
D023
TC = 75°C
Figure 23. Output Power vs Supply Voltage
RL = 2Ω, 3Ω, 4Ω
25
50
75
TC - Case Temperature - qC
THD+N = 10%
100
D024
TC = 75°C
Figure 24. Output Power vs Case Temperature
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7 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions,
Typical Characteristics, BTL Configuration, Typical Characteristics, SE Configuration and Typical Characteristics,
PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
8 Detailed Description
8.1 Overview
To facilitate system design, the TPA3255-Q1 needs only a low-voltage analog and digital supply in addition to the
(typical) 51-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and
low-voltage analog circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that
is, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor
for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same source,
separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see application
diagram for details) is recommended. These RC filters provide the recommended high-frequency isolation.
Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible.
In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to the
device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3255-Q1 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The VDD, AVDD and DVDD supplies should be from a low-noise, low-output-impedance voltage regulator.
Likewise, the 51-V power-stage supply is assumed to have low output impedance and low noise. The powersupply sequence is not critical as facilitated by the internal power-on-reset circuit, but it is recommended to
release RESET after the power supply is settled for minimum turn on audible artefacts. Moreover, the TPA3255Q1 is fully protected against erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply
ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table
of this data sheet).
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8.2 Functional Block Diagrams
/CLIP_OTW
VDD
VBG
POWERUP
RESET
PROTECTION & I/O LOGIC
/FAULT
M1
M2
/RESET
C_START
VREG
AVDD
UVP
DVDD
GND
TEMP
SENSE
GVDD_AB
GND
GVDD_CD
DIFFOC
STARTUP
CONTROL
OVER-LOAD
PROTECTIO
N
CB3C
CURRENT
SENSE
OC_ADJ
OSC_IOM
OSC_IOP
OSCILLATO
R
PPSC
FREQ_ADJ
PVDD_X
OUT_X
GND
GVDD_AB
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_AB
INPUT_A
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND
GVDD_AB
BST_B
PVDD_AB
INPUT_B
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND
GVDD_CD
BST_C
PVDD_CD
INPUT_C
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_C
GND
GVDD_CD
BST_D
PVDD_CD
INPUT_D
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND
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Functional Block Diagrams (continued)
Capacitor for
External
Filtering
and
Startup/Stop
C_START
/FAULT
/RESET
/CLIP_OTW
System
microcontroller or
Analog circuitry
BST_A
OSC_IOP
Oscillator
Synchronization
BST_B
OSC_IOM
OUT_A
INPUT_B
Hardwire PWM
Frame Adjust and
Master/Slave
Mode
FREQ_ADJ
OUT_C
51V
PVDD
PVDD
Power Supply
Decoupling
SYSTEM Power
Supplies
GND
GVDD
GVDD, VDD,
DVDD and
AVDD
Power Supply
Decoupling
OC_ADJ
AVDD
VBG
DVDD
M2
OUT_D
2nd Order
L-C Output
Filter for
Each
H-Bridge
BST_C
GND
VDD
M1
GVDD_AB, CD
Hardwire
Mode
Control
Output
H-Bridge 2
Input
H-Bridge 2
GND
ANALOG_IN_D
INPUT_D
OUT_B
2nd Order
L-C Output
Filter for
Each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
INPUT_C
Input DC
Blocking
Caps
ANALOG_IN_C
Input
H-Bridge 1
PVDD_AB, CD
ANALOG_IN_B
Output
H-Bridge 1
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
Bootstrap
Capacitors
BST_D
Bootstrap
Capacitors
Hardwire
OverCurrent
Limit
GND
GVDD/VDD
VAC
*NOTE1: Logic AND in or outside microcontroller
Figure 25. System Block Diagram
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8.3 Feature Description
8.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see Table 2).
Table 2. Error Reporting
FAULT
CLIP_OTW
DESCRIPTION
0
0
Overtemperature (OTE), overload (OLP) or undervoltage (UVP) Junction temperature
higher than 125°C (overtemperature warning)
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
1
0
Junction temperature higher than 125°C (overtemperature warning)
1
1
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.
8.4 Device Functional Modes
8.4.1 Device Protection System
The TPA3255-Q1 contains advanced protection circuitry carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions
such as short circuits, overload, overtemperature, and undervoltage. The TPA3255-Q1 responds to a fault by
immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault
condition has been removed, that is, the supply voltage has increased.
The device will handle errors, as shown in Table 3.
Table 3. Device Protection
BTL MODE
LOCAL
ERROR IN
A
B
C
D
PBTL MODE
TURNS OFF
A+B
C+D
LOCAL
ERROR IN
TURNS OFF
A
B
C
SE MODE
LOCAL
ERROR IN
A
A+B+C+D
D
B
C
D
TURNS OFF
A+B
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).
8.4.1.1 Overload and Short Circuit Current Protection
TPA3255-Q1 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all highside and low-side FETs. To prevent output current from increasing beyond the programmed threshold, TPA3255Q1 has the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control,
CB3C) or to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown).
CB3C prevents premature shutdown due to high output current transients caused by high level music transients
and a drop of real speaker’s load impedance, and allows the output current to be limited to a maximum
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programmed level. If the maximum output current persists, i.e. the power stage being overloaded with too low
load impedance, the device will shut down the affected output channel and the affected output is put in a highimpedance (Hi- Z) state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an
over current event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning
of next PWM frame.
PWM_X
RISING EDGE PWM
SETS CB3C LATCH
HS PWM
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
Figure 26. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
R_Latch, max,
Latching OC, min level
R_Latch, min,
Latching OC, max level
R_OC, min,
CB3C, max level
R_OC, max,
CB3C, min level
ROC_ADJ
Figure 27. OC Threshold versus OC_ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
18
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Table 4. Device Protection
OC_ADJ Resistor Value
Protection Mode
OC Threshold
22kΩ
CB3C
17.0A
24kΩ
CB3C
15.7A
27kΩ
CB3C
14.2A
30kΩ
CB3C
12.9A
47kΩ
Latched OC
17.0A
51kΩ
Latched OC
15.7A
56kΩ
Latched OC
14.2A
64kΩ
Latched OC
12.9A
8.4.1.2 Signal Clipping and Pulse Injector
A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3255-Q1 is designed to drive
unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying
excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback loop of
the audio channel will respond to this condition with a saturated state, and the output PWM signals would stop if
the device did not have special circuitry implemented to handle this situation. To prevent the output PWM signals
from stopping in a clipping or CB3C situation, narrow pulses are injected to the gate drive to maintain output
activity. The injected narrow pulses are injected at every 4th PWM frame, and thus the effective switching
frequency during this state is reduced to 1/4 of the normal switching frequency.
Signal clipping is signalled on the CLIP_OTW pin and is self clearing when signal level reduces and the device
reverts to normal operation. The CLIP_OTW pulses start at the onset to output clipping, typically at a THD level
around 0.01%, resulting in narrow CLIP_OTW pulses starting with a pulse width of ~500 ns.
Figure 28. Signal Clipping PWM and Speaker Output Signals
8.4.1.3 DC Speaker Protection
The output DC protection scheme protects a speaker from excess DC current in case one terminal of the
speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short
circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current
levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in
the event of the unbalance exceeding a programmed threshold, the overload counter increments until its
maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in SE mode
operation.
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8.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup
does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all
half bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
typical duration is < 15ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will
not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes, and FAULT
is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL
output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection
system it is recommended not to insert a resistive load to GND_X or PVDD_X.
8.4.1.5 Overtemperature Protection OTW and OTE
TPA3255-Q1 has a two-level temperature-protection system that asserts an active-low warning signal
(CLIP_OTW) when the device junction temperature exceeds 120°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To
clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
8.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
The UVP and POR circuits of the TPA3255-Q1 fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit ensures that all circuits are fully operational when the GVDD_X and
VDD supply voltages reach values stated in the Electrical Characteristics table. Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
The device automatically resumes operation when all supply voltages have increased above the UVP threshold.
8.4.1.7 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires
resetting the device by toggling RESET. Deasserting RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the CLIP_OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity
of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present.
20
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Table 5. Error Reporting
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed to
Clear
Output
FETs
Voltage Fault
Global
FAULT pin
Self Clearing
Increase affected
supply voltage
HI-Z
Power On Reset
Global
FAULT pin
Self Clearing
Allow DVDD to
rise
HI-Z
Voltage Fault
Channel (Half
Bridge)
None
Self Clearing
Allow BST cap to
recharge (lowside
ON, VDD applied)
HighSide
off
OTW
Thermal Warning
Global
OTW pin
Self Clearing
Cool below OTW
threshold
Normal
operation
OTE
Thermal Shutdown Global
FAULT pin
Latched
Toggle RESET
HI-Z
Fault/Event
PVDD_X UVP
VDD UVP
AVDD UVP
POR (DVDD UVP)
BST_X UVP
OLP (CB3C>1.7ms)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
Latched OC
(47kΩ<ROC_ADJ<68k OC Shutdown
Ω)
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
CB3C
(22kΩ<ROC_ADJ<30k OC Limiting
Ω)
Channel
None
Self Clearing
Reduce signal
level or remove
short
Flip state,
cycle by
cycle at
fs/3
Global
None
Self Clearing
Resume OSC_IO
activity
HI-Z
Stuck at Fault (1)
(1)
No OSC_IO
activity in Slave
Mode
Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.
8.4.1.8 Device Reset
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is
forced high. A rising-edge transition on reset input allows the device to resume operation after a fault. To ensure
thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of FAULT.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
TPA3255-Q1 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1
mixed 1x BTL + 2x SE mode depending on output power conditions and system design.
9.2 Typical Applications
9.2.1 Stereo BTL Application
3R3
GVDD
470uF
100nF
100nF
33nF
1
2
3
4
10µF
5
INPUT_A
10µF
6
INPUT_B
22k
30k
7
8
9
10
1µF
11
12
13
1µF
47nF
14
15
10µF
16
INPUT_C
10µF
17
INPUT_D
18
/RESET
19
/FAULT
1µF
20
21
/CLIP_OTW
3R3
22
100nF
GVDD_AB
BST_A
VDD
BST_B
M1
GND
M2
GND
INPUT_A
OUT_A
INPUT_B
OUT_A
OC_ADJ
PVDD_AB
FREQ_ADJ
PVDD_AB
OSC_IOM
PVDD_AB
OSC_IOP
DVDD
GND
GND
AVDD
C_START
OUT_B
TPA3255-Q1
GND
GND
OUT_C
PVDD_CD
PVDD_CD
INPUT_C
PVDD_CD
INPUT_D
OUT_D
/RESET
OUT_D
/FAULT
GND
VBG
GND
/CLIP_OTW
BST_C
GVDD_CD
BST_D
44
10µH
43
10nF
42
33nF
1nF
1µF
41
3R3
40
1µF
39
1nF
38
37
3R3
10nF
1µF
10µH
470uF
36
PVDD
35
1µF
34
GND
33
1µF
32
31
10µH
30
1µF
470uF
10nF
29
1nF
28
1µF
3R3
27
1µF
26
1nF
25
3R3
10nF
33nF
24
10µH
23
33nF
Figure 29. Typical Differential (2N) BTL Application
22
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Typical Applications (continued)
9.2.1.1 Design Requirements
For this design example, use the parameters in Table 6.
Table 6. Design Requirements, BTL Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply
10.6 V
High Power Supply
18 - 51 V
M2 = L
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ± 3.9V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
3-8 Ω
9.2.1.2 Detailed Design Procedures
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used either to decrease
audio volume or to control an intelligent power supply nominally operating at a low rail adjusting to a higher
supply rail.
The device is inverting the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.
9.2.1.2.1 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
9.2.1.2.2 PVDD Capacitor Recommendation
The PVDD decoupling capacitors must be placed as close to the device pins a possible to insure short trace
length and low a low inductance path. Likewise the ground path for these capacitors must provide a good
reference and should be substantial. This will keep voltage ringing on PVDD to a minimum.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 100 V is required for use with a 51-V power
supply.
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 80 V supports most applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
9.2.1.2.3 PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3255-Q1. The use of
this material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
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9.2.1.2.4 Oscillator
The built in oscillator frequency can be trimmed by an external resistor from the FREQ_ADJ pin to GND.
Changes in the oscillator frequency should be made with resistor values specified in Recommended Operating
Conditions while RESET is low.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower or higher values. These values should be chosen such that the nominal
and the alternate switching frequencies together result in the fewest cases of interference throughout the AM
band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in
master mode.
For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the
OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter-channel
delay is automatically set up between the switching of the audio channels, which can be illustrated by no idle
channels switching at the same time. This will not influence the audio output, but only the switch timing to
minimize noise coupling between audio channels through the power supply. Inter-channel delay is needed to
optimize audio performance and to get better operating conditions for the power supply. The inter-channel delay
will be set up for a slave device depending on the polarity of the OSC_I/O connection as follows:
• Slave 1 mode has normal polarity (master + to slave + and master - to slave -)
• Slave 2 mode has reverse polarity (master + to slave - and master - to slave +)
The interchannel delay for interleaved channel idle switching is given in the table below for the master/slave and
output configuration modes in degrees relative to the PWM frame.
Table 7. Master/Slave Inter Channel Delay Settings
Master
M1 = 0, M2 = 0, 2 x M1 = 1, M2 = 0, 1 x M1 = 0, M2 = 1, 1 x M1 = 1, M2 = 1, 4 x
BTL mode
BTL + 2 x SE
PBTL mode
SE mode
mode
OUT_A
0°
0°
0°
0°
OUT_B
180°
180°
180°
60°
OUT_C
60°
60°
0°
0°
OUT_D
240°
120°
180°
60°
Slave 1
OUT_A
60°
60°
60°
60°
OUT_B
240°
240°
240°
120°
OUT_C
120°
120°
60°
60°
OUT_D
300°
180°
240°
120°
Slave 2
24
OUT_A
30°
30°
30°
30°
OUT_B
210°
210°
210°
90°
OUT_C
90°
90°
30°
30°
OUT_D
270°
150°
210°
90°
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9.2.2 Application Curves
Relevant performance plots for TPA3255-Q1 in BTL configuration are shown in Typical Characteristics, BTL
Configuration
Table 8. Relevant Performance Plots, BTL Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion+Noise vs Frequency
Figure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 2
Total Harmonic Distortion + Noise vs Output Power
Figure 5
Output Power vs Supply Voltage, 10% THD+N
Figure 7
Output Power vs Supply Voltage, 10% THD+N
Figure 9
System Efficiency vs Output Power
Figure 9
System Power Loss vs Output Power
Figure 10
Output Power vs Case Temperature
Figure 11
Noise Amplitude vs Frequency
Figure 12
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9.2.3 Typical Application, Single Ended (1N) SE
TPA3255-Q1 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1
mixed 1x BTL + 2x SE mode depending on output power conditions and system design.
GVDD
470uF
100nF
470uF
15µH
3R3
100nF
33nF
1
2
3
4
10µF
5
INPUT_A
10µF
6
INPUT_B
22k
7
30k
8
9
10
1µF
11
12
13
1µF
1µF
14
15
10µF
16
INPUT_C
10µF
17
INPUT_D
18
/RESET
19
/FAULT
1µF
20
21
/CLIP_OTW
3R3
22
100nF
GVDD_AB
BST_A
VDD
BST_B
GND
M1
GND
M2
INPUT_A
OUT_A
INPUT_B
OUT_A
OC_ADJ
PVDD_AB
FREQ_ADJ
PVDD_AB
OSC_IOM
PVDD_AB
OUT_B
OSC_IOP
DVDD
GND
GND
AVDD
TPA3255-Q1
GND
GND
OUT_C
PVDD_CD
C_START
PVDD_CD
INPUT_C
PVDD_CD
INPUT_D
OUT_D
/RESET
OUT_D
/FAULT
GND
VBG
GND
/CLIP_OTW
GVDD_CD
BST_C
BST_D
44
10nF
43
1µF
42
1nF
3R3
33nF
41
1µF
1nF
40
3R3
10nF
39
38
1µF
37
470uF
15µH
470uF
36
PVDD
35
34
1µF
GND
33
32
1µF
31
30
470uF
15µH
1µF
470uF
29
28
10nF
27
1µF
1nF
26
3R3
25
33nF
1µF
24
1nF
3R3
10nF
23
33nF
15µH
470uF
Figure 30. Typical Single Ended (1N) SE Application
9.2.3.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 9. Design Requirements, SE Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply
10.6 V
High Power Supply
18 - 51 V
M2 = H
Mode Selection
M1 = H
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output Filters
Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
Speaker Impedance
2-8Ω
9.2.3.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
26
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9.2.3.3 Application Curves
Relevant performance plots for TPA3255-Q1 in PBTL configuration are shown in Typical Characteristics, SE
Configuration
Table 10. Relevant Performance Plots, SE Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion+Noise vs Output Power
Figure 13
Total Harmonic Distortion+Noise vs Frequency
Figure 14
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 15
Output Power vs Supply Voltage, 10% THD+N
Figure 16
Output Power vs Supply Voltage, 1% THD+N
Figure 17
Output Power vs Case Temperature
Figure 18
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9.2.4 Typical Application, Differential (2N) PBTL
TPA3255-Q1 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1
mixed 1x BTL + 2x SE mode depending on output power conditions and system design.
3R3
GVDD
470uF
100nF
100nF
33nF
1
2
3
4
10µF
5
INPUT_A
10µF
6
INPUT_B
22k
7
30k
8
9
10
1µF
11
12
13
1µF
14
47nF
15
16
17
18
/RESET
19
/FAULT
1µF
20
21
/CLIP_OTW
3R3
22
100nF
GVDD_AB
BST_A
VDD
BST_B
M1
GND
M2
GND
INPUT_A
OUT_A
INPUT_B
OUT_A
OC_ADJ
PVDD_AB
FREQ_ADJ
PVDD_AB
OSC_IOM
PVDD_AB
OSC_IOP
DVDD
GND
GND
AVDD
OUT_B
TPA3255-Q1
GND
GND
OUT_C
PVDD_CD
C_START
PVDD_CD
INPUT_C
PVDD_CD
INPUT_D
OUT_D
/RESET
OUT_D
/FAULT
GND
VBG
GND
/CLIP_OTW
BST_C
GVDD_CD
BST_D
44
43
42
33nF
41
40
39
38
PVDD
1µF
37
10µH
470uF
36
10nF
1nF
35
34
1µF
470nF
470nF
470nF
3R3
33
32
470nF
1nF
1µF
3R3
10nF
31
30
10µH
1µF
470uF
29
GND
28
27
26
25
33nF
24
23
33nF
Figure 31. Typical Differential (2N) PBTL Application
9.2.4.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 11. Design Requirements, PBTL Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply
10.6 V
High Power Supply
18 - 51 V
M2 = H
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
Analog Inputs
INPUT_C = Grounded
INPUT_D = Grounded
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
2-4Ω
9.2.4.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
28
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9.2.4.3 Application Curves
Relevant performance plots for TPA3255-Q1 in PBTL configuration are shown in Typical Characteristics, PBTL
Configuration
Table 12. Relevant Performance Plots, PBTL Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion+Noise vs Output Power
Figure 19
Total Harmonic Distortion+Noise vs Frequency
Figure 20
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 21
Output Power vs Supply Voltage, 10% THD+N
Figure 22
Output Power vs Supply Voltage, 1% THD+N
Figure 23
Output Power vs Case Temperature
Figure 24
10 Power Supply Recommendations
10.1 Power Supplies
The TPA3255-Q1 device requires two external power supplies for proper operation. A high-voltage supply called
PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one
mid-voltage power supply for GVDD_X and VDD is required to power the gate-drive and other internal digital and
analog portions of the device. The allowable voltage range for both the PVDD and the GVDD_X/VDD supplies
are listed in the Recommended Operating Conditions table. Ensure both the PVDD and the GVDD_X/VDD
supplies can deliver more current than listed in the Electrical Characteristics table.
10.1.1 VDD Supply
The VDD supply required from the system is used to power several portions of the device. It provides power to
internal regulators DVDD and AVDD that are used to power digital and analog sections of the device,
respectively. Proper connection, routing, and decoupling techniques are highlighted in the TPA3255 device EVM
User's Guide (SLOU441) (as well as the Application Information section and Layout Examples section) and must
be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in
the TPA3255 device EVM User's Guide (SLOU441), which followed the same techniques as those shown in the
Application Information section, may result in reduced performance, errant functionality, or even damage to the
TPA3255-Q1 device. Some portions of the device also require a separate power supply which is a lower voltage
than the VDD supply. To simplify the power supply requirements for the system, the TPA3255-Q1 device
includes integrated low-dropout (LDO) linear regulators to create these supplies. These linear regulators are
internally connected to the VDD supply and their outputs are presented on AVDD and DVDD pins, providing a
connection point for an external bypass capacitors. It is important to note that the linear regulators integrated in
the device have only been designed to support the current requirements of the internal circuitry, and should not
be used to power any additional external circuitry. Additional loading on these pins could cause the voltage to
sag and increase noise injection, which negatively affects the performance and operation of the device.
10.1.2 GVDD_X Supply
The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges. Proper
connection, routing, and decoupling techniques are highlighted in the TPA3255 device EVM User's Guide
(SLOU441) (as well as the Application Information section and Layout Examples section) and must be followed
as closely as possible for proper operation and performance. Deviation from the guidance offered in the
TPA3255 device EVM User's Guide (SLOU441), which followed the same techniques as those shown in the
Application Information section, may result in reduced performance, errant functionality, or even damage to the
TPA3255-Q1 device.
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Power Supplies (continued)
10.1.3 PVDD Supply
The output stage of the amplifier drives the load using the PVDD supply. This is the power supply which provides
the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3255 device EVM User's Guide (SLOU441) (as well as the Application Information section
and Layout Examples section) and must be followed as closely as possible for proper operation and
performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple
the output power stages in the manner described in the TPA3255 device EVM User's Guide (SLOU441). The
lack of proper decoupling, like that shown in the EVM User's Guide (SLOU441), can results in voltage spikes
which can damage the device, or cause poor audio performance and device shutdown faults.
10.2 Powering Up
The TPA3255-Q1 does not require a power-up sequence, but it is recommended to hold RESET low for at least
250 ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance state
until the gate-drive supply voltage (GVDD_X) and VDD voltages are above the undervoltage protection (UVP)
voltage threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as
initiating a controlled ramp up sequence of the output voltage.
PVDD
VDD
GVDD
DVDD
/RESET
AVDD
C 70µs
tPrecharge
C 200ms
/FAULT
VIN_X
OUT_X
tStartup ramp
VOUT_X
V_CSTART
Figure 32. Startup Timing
When RESET is released to turn on TPA3255-Q1, FAULT signal will turn low and AVDD voltage regulator will be
enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the
Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the
input AC coupling capacitors, the ramp up sequence starts.
30
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10.3 Powering Down
The TPA3255-Q1 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by
initiating a controlled ramp down sequence of the output voltage.
10.4 Thermal Design
10.4.1 Thermal Performance
TPA3255-Q1 thermal performance is dependent on the design of the thermal system, which is the heatsink
design and surrounding conditions including system enclosure (closed box with no air flow, or a fanned system
etc.). As a result, the maximum continuous output power attainable will be influenced by the thermal design.
To mitigate thermal limitations in systems with the device operated at continuous high power it is advised to
increase the cooling capability of the thermal system, or to operate the device in PBTL operation mode.
10.4.2 Thermal Performance with Continuous Output Power
It is recommended to operate TPA3255-Q1 below the OTW threshold. In most systems normal use conditions
will safely keep the device temperature with margin to the OTW threshold. However in some systems and use
cases the device tempertaure can run high, dependent on the actual output power, operating voltage, and
thermal system. At high operating temperature some thermal limitations for continuous output power may occur
at low audio frequencies due to increased heating of the output MOSFETs. Figure 33 shows maximum attainable
continuous output power with a heatsink temperature of 75ºC and maximum 10% THD.
Max. Continuous Output Power (W)
320
300
280
260
240
220
200
20
60
80
100
120
150
200
Frequency (Hz)
500
1000
C026
Figure 33. Maximum Continuous Output Power vs Frequency, BTL, 4Ω Load, Each Channel, TC = 75°C
10.4.3 Thermal Performance with Non-Continuous Output Power
As audio signals often have a peak to average ratio larger than one (average level below maximum peak output),
the thermal performance for audio signals can be illustrated using burst signals with different burst ratios.
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Thermal Design (continued)
Figure 34. Example of audio signal
A burst signal is characterized by the high-level to low-level ratio as well as the duration of the high level and low
level, e.g. a burst 1:4 stimuli is a single period of high level followed by 4 cycles of low level.
High level
Low level
1cycle : 4cycles
Figure 35. Example of 1:4 Burst Signal
The following analysis of thermal performance for TPA3255-Q1 is made with the heatsink temperature controlled
to 75°C.
320
320
310
310
Output Power 10% THD (W)
Output Power 10% THD (W)
The device is not thermally limited with 8-Ω load, but depending on the burst stimuli for operation at 75ºC
heatsink temperature some thermal limitations may occur with a lower load impedance, depending on switching
frequency and average to maximum power ratio. The figure below shows burst performance with a signal power
ratio of 1:16 (low cycles power level 1/16 of the high cycles power level) and 1:8 .
300
20 Hz
290
60 Hz
280
80 Hz
270
100 Hz
260
120 Hz
300
20 Hz
290
60 Hz
280
80 Hz
270
100 Hz
260
120 Hz
150 Hz
150 Hz
250
250
2:1
2:2
2:4
2:8
1:1
Burst Ratio (High:Low)
1:4
1:8
2:1
32
2:4
2:8
1:1
Burst Ratio (High:Low)
C027
Figure 36. Maximum Burst Output Power vs Frequency,
BTL, 4Ω Load, Each Channel, TC = 75°C, Power Ratio 1:16
2:2
1:4
1:8
C028
Figure 37. Maximum Burst Output Power vs Frequency,
BTL, 4Ω Load, Each Channel, TC = 75°C, Power Ratio 1:8
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
PCB layout, audio performance and EMI are linked closely together.
Routing the audio input should be kept short and together with the accompanied audio source ground.
Route VBG decoupling capacitor to the VBG and GND pins with as short PCB traces as possible
The small bypass capacitors on the PVDD lines of the DUT should be placed as close the PVDD pins as
possible.
A local ground area underneath the device is important to keep solid to minimize ground bounce.
Orient the passive component so that the narrow end of the passive component is facing the TPA3255-Q1
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
Avoid placing other heat producing components or structures near the TPA3255-Q1 device.
Avoid cutting off the flow of heat from the TPA3255-Q1 device to the surrounding ground areas with traces or
via strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in Figure 38.
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11.2 Layout Examples
11.2.1 BTL Application Printed Circuit Board Layout Example
T3
10k
22k
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T2
T2
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 38. BTL Application Printed Circuit Board - Composite
34
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Layout Examples (continued)
11.2.2 SE Application Printed Circuit Board Layout Example
T3
10k
22k
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
T2
T2
20
25
21
24
22
23
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 39. SE Application Printed Circuit Board - Composite
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Layout Examples (continued)
11.2.3 PBTL Application Printed Circuit Board Layout Example
T3
10k
22k
T1
Grounded for PBTL
Grounded for PBTL
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
T2
T2
20
25
21
24
22
23
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 40. PBTL Application Printed Circuit Board - Composite
36
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12 Device and Documentation Support
12.1 Documentation Support
TPA3255EVM User's Guide, SLOU441
Multi-Device Configuration for TPA32xx Amplifiers
TPA3255 Setup Guide & Configuration Tool
Class-D LC Filter Designer and Application Note
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPA3255TDDVRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
DDV
44
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
3255T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPA3255-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2019
• Catalog: TPA3255
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA3255TDDVRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DDV
44
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA3255TDDVRQ1
HTSSOP
DDV
44
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDV0044D
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 1.250
PLASTIC SMALL OUTLINE
C
8.3
TYP
7.9
PIN 1 ID
AREA
A
SEATING PLANE
0.1 C
42X 0.635
44
1
2X (0.3)
NOTE 6
14.1
13.9
NOTE 3
2X
13.335
7.30
6.72
EXPOSED
THERMAL
PAD
(0.15) TYP
NOTE 6
2X (0.6)
NOTE 6
22
B
23
4.43
3.85
44X
0.27
0.17
0.08
C A B
6.2
6.0
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
1.2
1.0
0.75
0.50
0.15
0.05
DETAIL A
TYPICAL
4218830/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDV0044D
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
SEE DETAILS
SYMM
44X (1.45)
1
44
44X (0.4)
42X (0.635)
SYMM
(R0.05) TYP
23
22
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218830/A 08/2016
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDV0044D
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
44X (1.45)
SYMM
1
44
44X (0.4)
42X (0.635)
SYMM
23
22
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE :6X
4218830/A 08/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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