Texas Instruments | TAS5755M 2 × 50W (2 × 19W 1 × 50W) Digital Input Audio Amplifier With Integrated Audio Processor and 2.1 Mode Support (Rev. C) | Datasheet | Texas Instruments TAS5755M 2 × 50W (2 × 19W 1 × 50W) Digital Input Audio Amplifier With Integrated Audio Processor and 2.1 Mode Support (Rev. C) Datasheet

Texas Instruments TAS5755M 2 × 50W (2 × 19W   1 × 50W) Digital Input Audio Amplifier With Integrated Audio Processor and 2.1 Mode Support (Rev. C) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
TAS5755M 2 × 50W (2 × 19W + 1 × 50W) Digital Input Audio Amplifier With Integrated
Audio Processor and 2.1 Mode Support
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
Reduced Sol
– Single-chip 2.1, 2.0 and Mono Mode Capable
– Single-filter in Mono (PBTL) Mode.
– Pad-up Package and 80 mΩ RDSON Enhances
Thermal Performance
High Output Power capable:
– 2 × 19 W +1 × 50 W in 2.1 mode
(2 × 4 Ω + 1 × 6 Ω, 24 V)
– 2 × 50 W in 2.0 mode (2 × 6 Ω, 24 V)
– 1 × 100 W in Mono Mode (1 × 2 Ω, 24 V)
– Wide Voltage Range: 8 V to 26.4 V
Audio Performance Audio:
– THD+N ≤ 0.05% at 1 kHz (RSPK = 8 Ω, POUT
= 1 W, PVDD = 18 V)
– ICN ≤ 50 µVRMS
– Crosstalk ≤ - 67 dB
– SNR ≥ 104 dB
– BD Modulation Available, for Improved Audio
Performance and Efficiency.
Integrated Audio Processing:
– 2 × 8 + 1 × 2 Biquads
– Two-band + Single-band configurable Dynamic
Range Control (DRC)
– License-Free 3D Effects
– Signal Mixing and DC blocking filter
– Automatic Rate Detection
Integrated Self-protection
– Thermal Protection
– Over-current Limit Protection
– Under-voltage Protection
DTV, UHD and Multi-Purpose Monitors
Sounds Bars, PC Audio
General Purpose Audio Equipment
3 Description
The TAS5755M is a single-chip flexible digital audio
solution with integrated processing that supports 2.1
(2 speakers + subwoofer), 2.0 or stereo (2 speakers)
and mono (high power speaker) modes.
Its high efficiency, low 80 mΩ RDSON and pad-up
package allows the device to output up to 2 × 50 W
or 1 × 100 W.
TAS5755M leverages 2 full H-bridges which are used
for each channel in stereo mode. In 2.1 mode,
TAS5755M runs 2 independent speaker channels
using 2 half-bridges while using a full-bridge to drive
a subwoofer. Finally, in mono mode, TAS5755M
supports pre-filter parallel bridge tied load (PBTL)
using only one filter stage to reduce total system size
and cost.
TAS5755M has integrated audio processing. It
includes: signal mixing, DC blocking filters, 2 × 8 + 1
× 2 biquads for equalization. Power limiting is
implemented by leveraging a two-band log-style DRC
and a separate single-band DRC for the subwoofer
channel.
Device Information(1)
PART NUMBER
TAS5755M
Efficiency vs Total Output Power
Output Power vs Supply Voltage
90
80
Output Power (W)
Efficiency (%)
70
60
50
40
30
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
20
30
40
50
Output Power (W)
60
70
BODY SIZE (NOM)
14 mm × 6.1 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
20 BTL Mode
TA=25qC
10
R L=6:
0
0
10
PACKAGE
DFD
80
D024
D003
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
THD+N=1%, R L=4:
THD+N=10%, R L=4:
THD+N=1%, R L=6:
THD+N=10%, R L=6:
BTL Mode
TA=25qC
8
10
12
14
16
18
20
Supply Voltage (V)
22
24
26
D014
D002
D037
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
7
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
PWM Operation at Recommended Operating
Conditions .................................................................. 8
7.6 DC Electrical Characteristics .................................... 8
7.7 AC Electrical Characteristics (BTL, PBTL)................ 9
7.8 Electrical Characteristics - PLL External Filter
Components............................................................... 9
7.9 Electrical Characteristic - I2C Serial Control Port
Operation ................................................................... 9
7.10 Timing Requirements - PLL Input Parameters ..... 10
7.11 Timing Requirements - Serial Audio Ports Slave
Mode ........................................................................ 10
7.12 Timing Requirements - I2C Serial Control Port
Operation ................................................................ 10
7.13 Timing Requirements - Reset (RESET)................ 10
7.14 Typical Characteristics .......................................... 13
8
9
Parameter Measurement Information ................ 21
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
21
21
24
34
36
41
10 Application and Implementation........................ 59
10.1 Application Information.......................................... 59
10.2 Typical Applications .............................................. 59
11 Power Supply Recommendations ..................... 68
11.1 DVDD and AVDD Supplies ................................... 68
11.2 PVDD Power Supply ............................................. 68
12 Layout................................................................... 68
12.1 Layout Guidelines ................................................. 68
12.2 Layout Examples................................................... 69
13 Device and Documentation Support ................. 71
13.1
13.2
13.3
13.4
13.5
13.6
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
71
71
71
71
71
71
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2018) to Revision C
Page
•
Changed "DVSSO" in OSC_RES Pin Description to "DVSS_OSC ground." ........................................................................ 6
•
Added RθJA in Thermal Information Table............................................................................................................................... 8
•
Changed RθJC(top) in Thermal Information Table ..................................................................................................................... 8
•
Added RθJB in Thermal Information Table............................................................................................................................... 8
•
Added ΨJT in Thermal Information Table................................................................................................................................ 8
•
Added RθJC(bot) in Thermal Information Table ......................................................................................................................... 8
Changes from Revision A (November 2017) to Revision B
Page
•
Changed SE Mode, PVDD = 24 V, RL = 4Ω, 7% THD from 17.1 W to 17.6 W in AC Electrical Characteristics (BTL,
PBTL) ..................................................................................................................................................................................... 9
•
Changed SE Mode, PVDD = 24 V, RL = 4Ω, 10% THD from 18.1 W to 19 W in AC Electrical Characteristics (BTL,
PBTL) ..................................................................................................................................................................................... 9
•
Changed Figure 6 and Figure 7 .......................................................................................................................................... 13
•
Changed Figure 19, Figure 20, and Figure 21 ..................................................................................................................... 16
•
Changed Figure 33, Figure 34, and Figure 35 .................................................................................................................... 19
2
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Changes from Original (August 2017) to Revision A
•
Page
Released device as Production Data ..................................................................................................................................... 1
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
3
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
5 Device Comparison Table
TAS5755M
TAS5731M
Max Power to SingleEnded Load
19
18
Max Power to Bridge
Tied Load
50
37
20
15
Max Power to Parallel
Bridge Tied Load
100
70
40
30
40
Min Supported SingleEnded Load
2
2
4
4
Min Supported Bridge
Tied Load
4
4
4
8
Min Supported Parallel
Bridge Tied Load
2
2
4
4
Closed/Open Loop
Open
Open
Open
Open
Max Speaker Outputs
3
3
Headphone Channels
4
TAS5729MD
TAS5721
TAS5717
10
TAS5711
16
10
4
20
6
4
Open
Open
3
2
3
2
Yes
Yes
Yes
Architecture
Class D
Class D
Class D
Class D
Class D
Class D
Dynamic Range Control
(DRC)
2-Band
2-Band
2-Band AGL
2-Band
2-Band AGL
Single-Band
Biquads (EQ)
21
21
28
21
28
21
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
6 Pin Configuration and Functions
HTSSOP Package
56-Pin DFD
Top View
Pin Functions
PIN
TYPE (1)
DESCRIPTION
8
DIO
Dual function terminal which sets the LSB of the 7-bit I2C address to "0" if pulled to GND and to "1" if
pulled to DVDD. If configured to be a fault output by the methods described in I²C Address Selection
and Fault Output, this terminal is pulled low when an internal fault occurs. A pull-up or pull-down
resistor is required, as is shown in the Typical Application Circuit Diagrams. If pulled high (to DVDD), a
15-kΩ resistor must be used to minimize in-rush current at power up and to isolate the net if the pin is
used as a fault output, as described above.
AVDD
9
P
3.3-V analog power supply
AVSS
13,14
P
Analog 3.3-V supply ground
BST_A
17
P
High-side bootstrap supply for half-bridge A
BST_B
28
P
High-side bootstrap supply for half-bridge B
NAME
ADR/FAULT
(1)
NO.
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
5
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
BST_C
29
P
High-side bootstrap supply for half-bridge C
BST_D
40
P
High-side bootstrap supply for half-bridge D
DVDD
47
P
3.3-V digital power supply
DVSS
44,46
P
Digital ground
DVSS_OSC
3
P
Oscillator ground
GVDD
41
P
Gate drive internal regulator output
LRCLK
56
P
Input serial audio data left/right clock (sample-rate clock)
MCLK
5
DI
Master clock input
6,7,22,35,
43,45,50,5
1
–
No connect
4
AO
OUT_A
20,21
O
Output, half-bridge A
OUT_B
26,27
O
Output, half-bridge B
OUT_C
30,31
O
Output, half-bridge C
OUT_D
36,37
O
Output, half-bridge D
PBTL
15
DI
Low means BTL mode; high means PBTL mode. Information goes directly to power stage.
PDN
1
DI
Power down, active-low. PDN prepares the device for loss of power supplies by shutting down the
noise shaper and initiating the PWM stop sequence.
PGND
23,24,25,
32,33,34
P
Power ground for half-bridges A and B
FLTM
12
AO
PLL negative loop-filter terminal
FLTP
11
AO
PLL positive loop-filter terminal
PVDD_AB
18,19
P
Power-supply input for half-bridge output A and B
PVDD_CD
38,39
P
Power-supply input for half-bridge output C and D
RESET
49
DI
Reset, active-low. A system reset is generated by applying a logic low to this pin. RESET is an
asynchronous control signal that restores the DAP to its default conditions and places the PWM in the
hard-mute (high-impedance) state.
SCL
52
DI
I2C serial control clock input
SCLK
55
DI
Serial audio-data clock (shift clock). SCLK is the serial-audio-port input-data bit clock.
SDA
53
DIO
SDIN
54
DI
Serial audio data input. SDIN supports three discrete (stereo) data formats.
SSTIMER
16
AI
Controls ramp time of OUT_x to minimize pop. Leave this pin floating for BD mode. Requires capacitor
of 2.2 nF to GND in AD mode. The capacitor determines the ramp time.
STEST
48
DI
Factory test pin. Connect directly to DVSS.
VR_ANA
10
P
Internally regulated 1.8-V analog supply voltage. This pin must not be used to power external devices.
VR_DIG
2
P
Internally regulated 1.8-V digital supply voltage. This pin must not be used to power external devices.
VREG
42
P
Digital regulator output. Not to be used for powering external circuitry.
P
Connect to GND for best system performance. If not connected to GND, leave floating.
NC
OSC_RES
PowerPAD™
6
Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSS_OSC ground.
I2C serial control data interface input/output
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Input voltage
MIN
MAX
UNIT
DVDD, AVDD
–0.3
4.2
V
PVDD_x
–0.3
30
V
3.3-V digital input
–0.5
DVDD + 0.5
5-V tolerant (2) digital input (except MCLK)
–0.5
DVDD + 2.5 (3)
–0.5
(3)
5-V tolerant MCLK input
AVDD + 2.5
V
OUT_x to PGND_x
32 (4)
V
BST_x to PGND_x
39 (4)
V
Input clamp current, IIK
–20
20
mA
Output clamp current, IOK
–20
20
mA
Operating free-air temperature
0
85
°C
Operating junction temperature
0
150
°C
–40
125
°C
Storage temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage must not exceed 6 V.
DC voltage + peak ac waveform measured at the pin must be below the allowed limit for all conditions.
(2)
(3)
(4)
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Digital/analog supply voltage
DVDD, AVDD
MIN
NOM
MAX
3
3.3
3.6
V
(1)
V
Half-bridge supply voltage
PVDD_x
8
VIH
High-level input voltage
5-V tolerant
2
VIL
Low-level input voltage
5-V tolerant
TA
TJ
(2)
26.4
UNIT
V
0.8
V
Operating ambient temperature range
0
85
°C
Operating junction temperature range
0
125
°C
RL (PBTL)
Load impedance
Output filter: L = 15 μH, C = 680 nF
2
Ω
RL (BTL)
Load impedance
Output filter: L = 15 μH, C = 680 nF
4
Ω
RL (SE)
Load impedance
Output filter: L = 15 μH, C = 680 nF
2
Ω
Output-filter inductance
Minimum output inductance under shortcircuit condition
10
μH
LO
(1)
(2)
For operation at PVDD_x levels greater than 18 V, the modulation limit must be set to 93.8% through the control port register 0x10.
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
7
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
7.4 Thermal Information
TAS5755M
THERMAL METRIC (1)
DFD HTSSOP
UNIT
56-PIN
RθJA
Junction-to-ambient thermal resistance
50.9
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
1.3
°C/W
Junction-to-board thermal resistance
26.9
°C/W
ψJT
Junction-to-top characterization parameter
3.1
°C/W
ψJB
Junction-to-board characterization parameter
26.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 PWM Operation at Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
Output PWM switch frequency
VALUE
11.025/22.05/44.1-kHz data rate ±2%
352.8
48/24/12/8/16/32-kHz data rate ±2%
384
UNIT
kHz
7.6 DC Electrical Characteristics
TA = 25°, PVDD_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
ADR/FAULT and SDA
IOH = –4 mA
DVDD = 3 V
VOL
Low-level output voltage
ADR/FAULT and SDA
IOL = 4 mA
DVDD = 3 V
0.5
V
IIL
Low-level input current
VI < VIL;
DVDD = AVDD = 3.6 V
75
μA
IIH
High-level input current
VI > VIH;
DVDD = AVDD = 3.6 V
75 (1)
μA
IDD
3.3-V supply current
3.3-V supply voltage (DVDD,
AVDD)
IPVDD
Supply current
No load (PVDD_x)
Drain-to-source resistance, LS
TJ = 25°C, includes metallization resistance
80
Drain-to-source resistance, HS
TJ = 25°C, includes metallization resistance
80
6.4
rDS(on)
(2)
2.4
V
Normal mode
49
68
Reset (RESET = low,
PDN = high)
23
38
Normal mode
32
50
4
8
Reset (RESET = low,
PDN = high)
mA
mA
mΩ
I/O
PROTECTION
Vuvp
Undervoltage protection limit
PVDD falling
Vuvp,hyst
Undervoltage protection limit
PVDD rising
OTE (3)
Overtemperature error
OTEHYST
(3)
Extra temperature drop
required to recover from error
IOC
Overcurrent limit protection
IOCT
Overcurrent response time
(1)
(2)
(3)
8
Output to output short in BTL mode
V
7.1
V
150
°C
30
°C
6
A
150
ns
IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.
This does not include bond-wire or pin resistance.
Specified by design.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
7.7 AC Electrical Characteristics (BTL, PBTL)
PVDD_x = 18 V, BTL AD mode, fS = 48 kHz, RL = 8 Ω, CBST = 10 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating
conditions (unless otherwise noted).
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP
BTL mode, PVDD = 8 V, RL = 8 Ω, 7% THD
3.9
BTL mode, PVDD = 8 V, RL = 8 Ω,10% THD
4.2
BTL mode, PVDD = 12 V, RL = 8 Ω, 7% THD
8
BTL mode, PVDD = 12 V, RL = 8 Ω,10% THD
9.6
BTL mode, PVDD = 18 V, RL = 8 Ω, 7% THD
18.7
BTL mode, PVDD = 18 V, RL = 8 Ω, 10% THD
21.2
BTL mode, PVDD = 24 V, RL = 8 Ω, 7% THD
32.6
BTL mode, PVDD = 24 V, RL = 8 Ω, 10% THD
37.2
BTL mode, PVDD = 24 V, RL = 6 Ω, 10% THD
50
PBTL mode, PVDD = 12 V, RL = 4 Ω, 7% THD
16.5
PBTL mode, PVDD = 12 V, RL = 4 Ω, 10% THD
17.9
PBTL mode, PVDD = 18 V, RL = 4 Ω, 7% THD
Vn
SNR
(1)
W
39.6
PBTL mode, PVDD = 24 V, RL = 4 Ω, 10% THD
66
PBTL mode, PVDD = 24 V, RL = 4 Ω, 10% THD
69.6
SE Mode, PVDD = 12 V, RL = 4 Ω, 7% THD
4.2
SE Mode, PVDD = 12 V, RL = 4 Ω, 10% THD
4.6
SE Mode, PVDD = 18 V, RL = 4 Ω, 7% THD
9.6
SE Mode, PVDD = 18 V, RL = 4 Ω, 10% THD
10.2
SE Mode, PVDD = 24 V, RL = 4 Ω, 7% THD
17.6
SE Mode, PVDD = 24 V, RL = 4 Ω, 10% THD
Total harmonic distortion + noise
UNIT
37
PBTL mode, PVDD = 18 V, RL = 4 Ω, 10% THD
THD+N
MAX
19
PVDD = 8 V, PO = 1 W
0.15%
PVDD = 12 V, PO = 1 W
0.03%
PVDD = 18 V, PO = 1 W
0.04%
PVDD = 24 V, PO = 1 W
0.1%
Output integrated noise (rms)
A-weighted
46
μV
Cross-talk
PO = 0.25 W, f = 1 kHz (AD Mode)
–67
dB
Signal-to-noise ratio (1)
A-weighted, f = 1 kHz, maximum power at THD
< 1%
104
dB
SNR is calculated relative to 0-dBFS input level.
7.8 Electrical Characteristics - PLL External Filter Components
PARAMETER
TEST CONDITIONS
External PLL filter capacitor C1
SMD 0603 X7R
External PLL filter capacitor C2
External PLL filter resistor R
MIN
TYP
MAX
UNIT
47
nF
SMD 0603 X7R
4.7
nF
SMD 0603, metal film
470
Ω
7.9 Electrical Characteristic - I2C Serial Control Port Operation
for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
CL
TEST CONDITIONS
Load capacitance for each bus line
MIN
TYP
MAX
UNIT
400
pF
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
9
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
7.10 Timing Requirements - PLL Input Parameters
MIN
fMCLKI
tr/tf(MCLK)
MCLK frequency
2.8224
MCLK duty cycle
40%
NOM
50%
MAX
UNIT
24.576
MHz
60%
Rise/fall time for MCLK
5
ns
LRCLK allowable drift before LRCLK reset
4
MCLKs
7.11 Timing Requirements - Serial Audio Ports Slave Mode
over recommended operating conditions (unless otherwise noted)
MIN
CL = 30 pF
NOM
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
32
64
SCLK
edges
–1/4
1/4
SCLK
period
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
tr/tf
Rise/fall time for SCLK/LRCLK
kHz
8
ns
MAX
UNIT
400
kHz
7.12 Timing Requirements - I2C Serial Control Port Operation
for I2C Interface signals over recommended operating conditions (unless otherwise noted)
MIN
No wait states
NOM
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
μs
μs
100
ns
0
ns
Bus free time between stop and start conditions
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
μs
7.13 Timing Requirements - Reset (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted).
MIN
tw(RESET)
Pulse duration, RESET active
td(I2C_ready)
Time to enable I2C
10
NOM
MAX
100
μs
12
Submit Documentation Feedback
UNIT
ms
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
tr
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 1. Slave-Mode Serial Data-Interface Timing
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
11
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTES: On power up, it is recommended that the TAS5755M RESET be held LOW for at least 100 μs after DVDD has
reached 3 V.
If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after
PDN is deasserted (HIGH).
Figure 4. Reset Timing
12
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
7.14 Typical Characteristics
7.14.1 Typical Characteristics, 2.1 SE Configuration
30
10
5 2.1 SE Mode
PV DD =12V
2 f = 1kHz
1 TA=25qC
0.5
20
THD+N (%)
Output Power (W)
2.1 SE Mode
TA=25qC
25 R L=2u4: + 6:
15
0.2
0.1
0.05
10
0.02
5
0.005
0.01
THD+N=1%
THD+N=10%
0.001
0.01
0
8
10
12
14
16
18
20
Supply Voltage (V)
22
24
26
1
10
Output Power (W)
D007
D028
Figure 6. Total Harmonic Distortion + Noise vs Output
Power
10
10
5 2.1 SE Mode
PV DD =24V
2 f = 1kHz
1 TA=25qC
5 2.1 SE Mode
PV DD =18V
2 f = 1kHz
1 TA=25qC
0.5
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
RL = 2u4:+4:
RL = 2u4:+8:
RL = 2u8:+8:
0.005
0.002
0.001
0.01
0.1
1
RL = 2u4:+4:
RL = 2u4:+8:
RL = 2u8:+8:
0.005
0.002
10
Output Power (W)
0.001
0.1
1
10
20
100
Output Power (W)
D007
D029
Figure 7. Total Harmonic Distortion + Noise vs Output
Power
D007
D030
Figure 8. Total Harmonic Distortion + Noise vs Output
Power
10
10
2.1 SE Mode
PO = 1W
PVDD = 12V
TA = 25ƒC
RL = 2î8Ÿ
Ÿ
RL = 2î4Ÿ
Ÿ
RL = 2î4Ÿ
Ÿ
2.1 SE Mode
PO = 1W
PVDD = 18V
TA = 25ƒC
RL = 2î8Ÿ
Ÿ
RL = 2î4Ÿ
Ÿ
RL = 2î4Ÿ
Ÿ
1
THD+N (%)
1
THD+N (%)
0.1
D014
D001
D037
Figure 5. Output Power vs Supply Voltage
THD+N (%)
RL = 2u4:+4:
RL = 2u4:+8:
RL = 2u8:+8:
0.002
0.1
0.01
0.1
0.01
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C020
Figure 9. Total Harmonic Distortion + Noise vs Frequency
C021
Figure 10. Total Harmonic Distortion + Noise vs Frequency
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
13
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Typical Characteristics, 2.1 SE Configuration (continued)
10
100
2.1 SE Mode
PO = 1W
PVDD = 24V
TA = 25ƒC
RL = 2î8Ÿ
Ÿ
RL = 2î4Ÿ
Ÿ
RL = 2î4Ÿ
Ÿ
90
80
1
2.1 SE Mode
RL = 2î8+8Ÿ
TA = 25ƒC
Efficiency (%)
THD+N (%)
70
0.1
60
50
40
30
0.01
20
PVDD = 12V
PVDD = 18V
10
PVDD = 24V
0
0.001
20
200
2k
20k
0
20
Frequency (Hz)
40
60
80
Total Output Power (W)
C022
C023
Figure 11. Total Harmonic Distortion + Noise vs
Frequency
100
0
90
±10
80
±20
2.1 SE Mode
RL = 2î4+8Ÿ
TA = 25ƒC
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 12V
RL = 2î8+8Ÿ
TA = 25ƒC
Left-to-Right
±30
Crosstalk (dB)
70
Efficiency (%)
Figure 12. Efficiency vs Total Output Power
60
50
40
±40
±50
±60
±70
30
20
±80
PVDD = 12V
PVDD = 18V
10
±90
PVDD = 24V
±100
0
0
20
40
60
20
80
200
2k
C025
C024
Figure 14. Crosstalk vs Frequency
Figure 13. Efficiency vs Total Output Power
0
0
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 12V
RL = 2î4+4Ÿ
TA = 25ƒC
±10
±20
±20
Left-to-Right
±30
Crosstalk (dB)
Crosstalk (dB)
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 24V
RL = 2î8+8Ÿ
TA = 25ƒC
±10
Left-to-Right
±30
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20k
Frequency (Hz)
20
200
2k
20k
Frequency (Hz)
C026
Figure 15. Crosstalk vs Frequency
14
20k
Frequency (Hz)
Total Output Power (W)
Submit Documentation Feedback
C027
Figure 16. Crosstalk vs Frequency
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Typical Characteristics, 2.1 SE Configuration (continued)
0
Right-to-Left
2.1 SE Mode
PO = 1W
PVDD = 24V
RL = 2î4+4Ÿ
TA = 25ƒC
±10
±20
Left-to-Right
Crosstalk (dB)
±30
±40
±50
±60
±70
±80
±90
±100
20
200
2k
20k
Frequency (Hz)
C028
Figure 17. Crosstalk vs Frequency
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
15
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
5 2.0 BTL Mode
PV DD =12V
2 f = 1kHz
1 TA=25qC
THD+N=1%, R L=4:
THD+N=10%, R L=4:
THD+N=1%, R L=6:
THD+N=10%, R L=6:
0.5
THD+N (%)
Output Power (W)
7.14.2 Typical Characteristics, 2.0 BTL Configuration
0.2
0.1
0.05
0.02
0.01
BTL Mode
TA=25qC
8
10
12
14
16
18
20
Supply Voltage (V)
22
24
0.002
0.001
0.1
26
20
100
D007
D031
Figure 19. Total Harmonic Distortion + Noise vs Output
Power
10
5 2.0 BTL Mode
PV DD =18V
2 f = 1kHz
1 TA=25qC
5 2.0 BTL Mode
PV DD =24V
2 f = 1kHz
1 TA=25qC
0.5
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
RL = 4:
RL = 6:
RL = 8:
0.005
0.002
0.001
0.1
1
10
20
RL = 4:
RL = 6:
RL = 8:
0.005
0.002
100
Output Power (W)
0.001
0.1
1
10
20
100
Output Power (W)
D007
D032
Figure 20. Total Harmonic Distortion + Noise vs Output
Power
D007
D033
Figure 21. Total Harmonic Distortion + Noise vs Output
Power
10
10
RL = 4Ÿ
2.0 BTL Mode
PVDD = 12V
PO = 1W
TA = 25ƒC
RL = 4Ÿ
2.0 BTL Mode
PVDD = 18V
PO = 1W
TA = 25ƒC
RL = 6Ÿ
RL = 8Ÿ
RL = 6Ÿ
RL = 8Ÿ
1
THD+N (%)
1
THD+N (%)
10
Output Power (W)
10
0.1
0.01
0.1
0.01
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C006
Figure 22. Total Harmonic Distortion vs Frequency
16
1
D014
D002
D037
Figure 18. Output Power vs Supply Voltage
THD+N (%)
RL = 4:
RL = 6:
RL = 8:
0.005
C007
Figure 23. Total Harmonic Distortion vs Frequency
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Typical Characteristics, 2.0 BTL Configuration (continued)
10
100
RL = 4Ÿ
2.0 BTL Mode
PVDD = 24V
PO = 1W
TA = 25ƒC
RL = 6Ÿ
90
RL = 8Ÿ
80
1
2.0 BTL Mode
RL = 8Ÿ
TA = 25ƒC
60
Efficiency (%)
THD+N (%)
70
0.1
50
40
30
0.01
20
PVDD = 12V
PVDD = 18V
10
PVDD = 24V
0.001
0
20
200
2k
20k
0
20
Frequency (Hz)
40
60
C005
Figure 24. Total Harmonic Distortion vs Frequency
Figure 25. Efficiency vs Output Power
0
0
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 8Ÿ
TA = 25ƒC
±10
±20
±20
Left-to-Right
±30
Crosstalk (dB)
Crosstalk (dB)
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 24V
RL = 8Ÿ
TA = 25ƒC
±10
Left-to-Right
±30
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C010
C011
Figure 26. Crosstalk vs Frequency
Figure 27. Crosstalk vs Frequency
0
0
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 4Ÿ
TA = 25ƒC
±10
±20
Right-to-Left
2.0 BTL Mode
PO = 1W
PVDD = 24V
RL = 4Ÿ
TA = 25ƒC
±10
Left-to-Right
±20
Left-to-Right
±30
Crosstalk (dB)
±30
Crosstalk (dB)
80
Total Output Power (W)
C008
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20k
20
200
2k
20k
Frequency (Hz)
Frequency (Hz)
C012
Figure 28. Crosstalk vs Frequency
C015
Figure 29. Crosstalk vs Frequency
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
17
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Typical Characteristics, 2.0 BTL Configuration (continued)
100
70
2.0 BTL Mode
TA = 25°C
90
60
80
50
60
Idle Channel Noise (uV)
Efficiency (%)
70
50
40
30
20 BTL Mode
TA=25qC
10
R L=6:
0
0
10
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
20
30
40
50
Output Power (W)
60
70
40
30
20
80
RL = 4Ÿ
10
RL = 6Ÿ
D024
D003
RL = 8Ÿ
Figure 30. Power vs Supply Voltage
0
8
10
12
14
16
18
20
22
24
Supply Voltage (V)
C009
Figure 31. Idle Channel Noise vs Supply Voltage
18
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
7.14.3 Typical Characteristics, PBTL Configuration
120
10
90
80
0.5
THD+N (%)
100
Output Power (W)
5 PBTL Mode
PV DD =12V
2 f = 1kHz
1 TA=25qC
THD+N=1%, R L=4:
THD+N=10%, R L=4:
THD+N=1%, R L=6:
THD+N=10%, R L=6:
THD+N=1%, R L=2:
THD+N=10%, R L=2:
110
70
60
50
0.2
0.1
0.05
0.02
40
30
0.01
20
0.005
PBTL Mode
TA=25qC
10
8
10
12
14
16
18
Supply Voltage (V)
20
22
0.001
0.1
24 25
10
20
100
Output Power (W)
D007
D034
Figure 33. Total Harmonic Distortion + Noise vs Output
Power (PBTL Mode)
10
10
5 PBTL Mode
PV DD =18V
2 f = 1kHz
1 TA=25qC
5 PBTL Mode
PV DD =24V
2 f = 1kHz
1 TA=25qC
0.5
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
RL = 2:
RL = 4:
0.002
0.001
0.1
1
10
20
0.001
0.1
10
20
100
Output Power (W)
D007
D036
Figure 35. Total Harmonic Distortion + Noise vs Output
Power (PBTL Mode)
10
RL = 2Ÿ
PBTL Mode
PO = 1W
PVDD = 12V
TA = 25ƒC
1
D007
D035
Figure 34. Total Harmonic Distortion + Noise vs Output
Power (PBTL Mode)
10
RL = 2:
RL = 4:
0.002
100
Output Power (W)
RL = 2Ÿ
PBTL Mode
PO = 1W
PVDD = 18V
TA = 25ƒC
RL = 4Ÿ
RL = 6Ÿ
RL = 4Ÿ
RL = 6Ÿ
1
THD+N (%)
1
THD+N (%)
1
D014
D004
D037
Figure 32. Output Power vs Supply Voltage
THD+N (%)
RL = 2:
RL = 4:
0.002
0
0.1
0.01
0.1
0.01
0.001
0.001
20
200
2k
20k
20
Frequency (Hz)
200
2k
20k
Frequency (Hz)
C037
Figure 36. Total Harmonic Distortion vs Frequency (PBTL
Mode)
C038
Figure 37. Total Harmonic Distortion vs Frequency (PBTL
Mode)
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
19
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Typical Characteristics, PBTL Configuration (continued)
10
100
RL = 2Ÿ
PBTL Mode
PO = 1W
PVDD = 24V
TA = 25ƒC
RL = 4Ÿ
90
RL = 6Ÿ
80
1
PBTL Mode
RL = 4Ÿ
TA = 25ƒC
60
Efficiency (%)
THD+N (%)
70
0.1
50
40
30
0.01
20
PVDD = 12V
PVDD = 18V
10
PVDD = 24V
0.001
0
20
200
2k
20k
0
20
Frequency (Hz)
40
60
80
Total Output Power (W)
C041
C035
Figure 38. Total Harmonic Distortion vs Frequency (PBTL
Mode)
Figure 39. Efficiency vs Output Power (PBTL Mode)
90
100
PBTL Mode
80 R L = 4:
TA=25qC
70
90
PBTL Mode
RL = 6Ÿ
TA = 25ƒC
70
Efficiency (%)
Output Power (W)
80
60
50
60
50
40
30
40
20
30
THD+N=1%
THD+N=10%
10
20
0
PVDD = 12V
8
10
PVDD = 18V
10
PVDD = 24V
10
20
30
40
14
16
18
Supply Voltage (V)
20
22
24
D014
D007
D037
D005
Figure 41. Power vs Supply Voltage (PBTL Mode)
0
0
12
50
Total Output Power (W)
C034
Figure 40. Efficiency vs Output Power (PBTL Mode)
80
PBTL Mode
TA = 25ƒC
Idle Channel Noise ( V)
60
40
20
RL = 4Ÿ
RL = 6Ÿ
RL = 8Ÿ
0
8
10
12
14
16
18
20
22
24
Supply Voltage (V)
C036
Figure 42. Idle Channel Noise vs Supply Voltage (PBTL Mode)
20
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
9 Detailed Description
9.1 Overview
The TAS5755M is an efficient 50-W stereo I2S input Class-D audio power amplifier. The digital auto processor of
the device uses noise shaping and customized correction algorithms to achieve a great power efficiency and high
audio performance. Also, the device has up to eight Equalizers per channel and two -band configurable Dynamic
Range Control (DRC).
The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal
voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of
the device enables its use in a multitude of applications.
The TAS5755M is a slave-only device that is controlled by a bidirectional I2C interface that supports both 100kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control interface
is used to program the registers of the device and read the device status.
The PWM of this device operates with a carrier frequency between 384 kHz and 354 kHz, depending the
sampling rate. This device allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using
a sampling frequency of 44.1 kHz or 48 kHz.
This device can be used in three different modes of operation, Stereo BTL mode, Single filter PBTL mono mode,
and 2.1 mode.
9.2 Functional Block Diagrams
OUT_A
2´ HB
FET Out
SDIN
Serial
Audio
Port
Digital Audio Processor
(DAP)
S
R
C
th
4 -Order
Noise Shaper
and PWM
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Sample Rate
Autodetect
and PLL
Serial
Control
Click and Pop
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-14
Figure 43. Functional Block Diagram
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
21
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Functional Block Diagrams (continued)
Undervoltage
Protection
FAULT
4
4
Power
On
Reset
Protection
and
I/O Logic
AGND
Temp.
Sense
GND
VALID
Overcurrent
Protection
Isense
BST_D
PVDD_CD
PWM
Rcv
Ctrl
Timing
PWM Controller
PWM_D
Gate
Drive
OUT_D
Pulldown Resistor
PGND_CD
GVDD
Regulator
GVDD_OUT
BST_C
PVDD_CD
PWM_C
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_C
Pulldown Resistor
PGND_CD
BST_B
PVDD_AB
PWM_B
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_B
Pulldown Resistor
GVDD
Regulator
PGND_AB
BST_A
PVDD_AB
PWM_A
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_A
Pulldown Resistor
PGND_AB
B0034-08
Figure 44. Power-Stage Functional Block Diagram
22
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
2
I C Subaddress in Red
I2C:53 – V1IM
L
59
1
+
1BQ
+
29
1BQ
1
1BQ
6BQ
+
1
3A
–1
3A
0
Auto-lp
(0x46 Bit 5)
R
1
+
1BQ
+
30
1BQ
ealpha
5D
Log
Math
Attack
Decay
Master ON/OFF
(0x46[0])
1
1BQ
6BQ
+
Vol2
+
32–36, 5C
1
1BQ
52 V2OM
Input Muxing
5E
I2C:56
VDISTA
Vol2
+
I2C:57
VDISTB
31
+
1
ealpha
2B–2F, 58
Energy
MAXMUX
2A
51 V1OM
Vol1
55
I2C:54 – V2IM
3D
ealpha
L
R
+
1
0
3
1
1BQ
1BQ
5A
5B
½
Energy
MAXMUX
½
61
21 (D8, D9)
3D
Log
Math
Attack
Decay
Master ON/OFF
(0x46[1])
ealpha
+
Vol1
60 V6OM
B0321-14
Figure 45. DAP Process Structure
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
23
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.3 Feature Description
9.3.1 Power Supply
To facilitate system design, the TAS5755M needs only a 3.3-V supply in addition to the PVDD power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in
bootstrap circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical half-bridges with separate bootstrap pins (BST_x). The gate-drive voltage (GVDD_OUT) is
derived from the PVDD voltage. Special attention must be paid to placing all decoupling capacitors as close to
their associated pins as possible. Inductance between the power-supply pins and decoupling capacitors must be
avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 288 kHz to 384 kHz, it is recommended to use 10-nF, X7R ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 10-nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Special attention must be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is
decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.
The TAS5755M is fully protected against erroneous power-stage turnon due to parasitic gate charging.
9.3.2 I2C Address Selection and Fault Output
ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the
Typical Applications sections in order to set the I2C address. Pulling this pin HIGH through the resistor results in
setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the
address to 0011010 (0x34).
During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault
notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to its
default state when register 0x02 is cleared. The behavior of the pin in response to a fault condition is to be pulled
low immediately upon an error. The device then waits for a period of time determined by BKND_ERR Register
(0x1C) before attempting to resume playback. If the error has been cleared when the device attempts to resume
playback, playback will resume, the ADR/FAULT pin will remain high, and normal operation will resume. If the
error has not been removed, then the device will immediately re-enter the protected state and wait again for the
predetermined period of time to pass. The device will pull the fault pin low for over-current, over-temperature, and
under-voltage lock-out.
9.3.3 Single-Filter PBTL Mode
The TAS5755M supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected
before the LC filter. In addition to connecting OUT_A/OUT_B and OUT_C/OUT_D, BST_A/BST_B and
BST_C/BST_D must also be connected before the LC filter, as shown in the Figure 71. In order to put the part in
PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of half-bridges A and B (and similarly
C/D) if an overcurrent condition is detected in either half-bridge. There is a pulldown resistor on the PBTL pin that
configures the part in BTL mode if the pin is left floating.
PWM output multiplexers register (0x25) and PWM Shutdown Group Register (0x19) must be updated to set the
device in PBTL mode. Must follow one of below listed configurations for PBTL mode.
•
•
.
24
Register (0x25) be written with a value of 0x0110 3245, Register (0x19) be written with a value of 0x35
Register (0x25) be written with a value of 0x0101 2345, Register (0x19) be written with a value of 0x3A
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Feature Description (continued)
9.3.4 Device Protection System
9.3.4.1 Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by a protection system. If the high-current condition situation persists, that
is, the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power
stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (that is, a short circuit on the output) is removed. Current-limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D are shut down.
9.3.4.2 Overtemperature Protection
The TAS5755M has an overtemperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state. The TAS5755M recovers automatically once the temperature drops approximately 30°C.
9.3.4.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5755M fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD
and AVDD are independently monitored, a supply-voltage drop below the UVP threshold on AVDD or either
PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state.
9.3.5 SSTIMER Functionality
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor,
similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin
capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the
start-up time. The SSTIMER pin can be left floating for BD modulation.
9.3.6 Clock, Autodetection, and PLL
The TAS5755M is an I2S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the Clock Control Register (0x00).
The TAS5755M checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1
× fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock-control register.
The TAS5755M has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)
and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system autodetects the new rate and reverts to normal operation. During this process, the default volume is
restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly
(also called soft unmute) as defined in volume register (0x0E).
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
25
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Feature Description (continued)
9.3.7 PWM Section
The TAS5755M DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can
be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For a detailed description of using audio processing features like DRC and EQ, see the TAS5755EVM User's
Guide (SLOU481) and TAS570X GDE Software Setup development tool documentation (SLOC124).
9.3.8 2.1-Mode Support
The TAS5755M uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode
operation. To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05
bit D2 must be set to 1. The SSTIMER pin must be left floating in this mode.
9.3.9 I2C Compatible Serial Control Interface
The TAS5755M DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent. The serial control interface supports
both single-byte and multiple-byte read and write operations for status registers and the general control registers
associated with the PWM.
9.3.10 Audio Serial Interface
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5755M DAP accepts serial data
in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
9.3.10.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
26
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Feature Description (continued)
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 46. I2S 64-FS Format
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
27
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Feature Description (continued)
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 47. I2S 48-FS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
LSB
15 14 13 12
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 48. I2S 32-FS Format
28
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Feature Description (continued)
9.3.10.2 Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 49. Left-Justified 64-FS Format
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
29
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Feature Description (continued)
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 50. Left-Justified 48-FS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 51. Left-Justified 32-FS Format
30
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Feature Description (continued)
9.3.10.3 Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 52. Right-Justified 64-FS Format
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
31
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Feature Description (continued)
2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 53. Right-Justified 48-FS Format
Figure 54. Right-Justified 32-FS Format
32
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Feature Description (continued)
9.3.11 Dynamic Range Control (DRC)
The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left/right channels and one
DRC for the low-band left/right channels.
Output Level (dB)
The DRC input/output diagram is shown in Figure 55.
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0091-04
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each DRC has adjustable threshold levels.
• Programmable attack and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 55. Dynamic Range Control
a, w
T
aa, wa / ad, wd
DRC1
0x3C
0x3B
0x40
DRC2
0x3F
0x3E
0x43
Alpha Filter Structure
S
a
w
–1
Z
B0265-04
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 56. DRC Structure
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
33
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.4 Device Functional Modes
9.4.1 Stereo BTL Mode
The classic stereo mode of operation uses the TAS5755M device to amplify two independent signals, which
represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented
on differential output pairs shown as OUT_A and OUT_B for a channel and OUT_C and OUT_D for the other
one. The routing of the audio data which is presented on the OUT_x outputs can be changed according to the
PWM Output Mux Register (0x25). By default, the TAS5755M device is configured to output channel 1 to the
OUT_A and OUT_B outputs, and channel 2 to the OUT_C and OUT_D outputs. Stereo Mode operation outputs
are shown in Figure 57.
Figure 57. Stereo BTL Mode
9.4.2 Mono PBTL Mode
When this mode of operation is used, the two stereo outputs of the device are placed in parallel one with another
to increase the power sourcing capabilities of the device. The TAS5755M supports parallel BTL (PBTL) mode
with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter.
The merging of the two output channels in this device can be done before the inductor portion of the output filter.
This is called Single-Filter PBTL, and this mono operation is shown in Figure 58. More information about this can
be found in Single-Filter PBTL Mode section.
34
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Device Functional Modes (continued)
Figure 58. Pre-Filter PBTL
On the input side of the TAS5755M device, the input signal to the mono amplifier can be selected from a mix, left
or right frame from an I2S, LJ, or RJ signal. The routing of the audio data which is presented on the SPK_OUTx
outputs must be configured with the PWM Output Mux Register (0x25) and PWM Shutdown Group Register
(0x19).
Refer to the Mono Parallel Bridge Tied Load Application section for more details of the correct PBTL output
connection of the TAS5755M.
9.4.3 2.1 Mode
2.1 Mode is defined as the application of two Single ended channels and one BTL channel used in systems
where a third sub channel is required. Generally, both single-ended inputs drive the Left and Right channels,
while the BTL channel drives a low-frequency content channel called often Subwoofer. More information about
this can be found in the 2.1-Mode Support section.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
35
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Device Functional Modes (continued)
Figure 59. 2.1 Mode
Refer to 2.1 Application section for more details of the correct 2.1 output connection of the TAS5755M.
9.5 Programming
9.5.1 I2C Serial Control Interface
The TAS5755M DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
9.5.1.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 60. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5755M holds SDA low during the acknowledge
clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
36
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Programming (continued)
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
2
Figure 60. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 60.
The 7-bit address for TAS5755M is 0011 011 (0x36).
9.5.1.2 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received
when a stop command (or another start command) is received, the received data is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5755M also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by
data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS5755M. For I2C sequential-write
transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,
before a stop or start is transmitted, determines how many subaddresses are written. As was true for random
addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data
is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is
accepted; only the incomplete data is discarded.
9.5.1.3 Single-Byte Write
As shown in Figure 61, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5755M internal memory address being accessed. After receiving the address
byte, the TAS5755M again responds with an acknowledge bit. Next, the master device transmits the data byte to
be written to the memory address being accessed. After receiving the data byte, the TAS5755M again responds
with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte datawrite transfer.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
37
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Programming (continued)
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 61. Single-Byte Write Transfer
9.5.1.4 Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 62. After receiving each data byte, the
TAS5755M responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
A5
2
A4
A3
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
Other Data Bytes
First Data Byte
Subaddress
I C Device Address and
Read/Write Bit
Last Data Byte
Stop
Condition
T0036-02
Figure 62. Multiple-Byte Write Transfer
9.5.1.5 Single-Byte Read
As shown in Figure 63, a single-byte data-read transfer begins with the master device transmitting a start
condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5755M address
and the read/write bit, TAS5755M responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5755M
address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After
receiving the address and the read/write bit, the TAS5755M again responds with an acknowledge bit. Next, the
TAS5755M transmits the data byte from the memory address being read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read
transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A4
Subaddress
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
2
I C Device Address and
Read/Write Bit
D6
D1
Data Byte
D0 ACK
Stop
Condition
T0036-03
Figure 63. Single-Byte Read Transfer
9.5.1.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5755M to the master device as shown in Figure 64. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
38
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Programming (continued)
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
2
I C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 64. Multiple-Byte Read Transfer
9.5.2 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This
is shown in Figure 65.
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 65. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 65. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 66 applied to obtain the magnitude
of the negative number.
1
0
2 Bit
2 Bit
1
2
0
–1
Bit
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 66. Conversion Weighting Factors — 3.23 Format To Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 67.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
39
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Programming (continued)
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
2
Figure 67. Alignment of 3.23 Coefficient in 32-Bit I C Word
Table 1. Sample Calculation for 3.23 Format
db
LINEAR
DECIMAL
0
1
8,388,608
80 0000
5
1.77
14,917,288
00E3 9EA8
–5
0.56
4,717,260
0047 FACC
D = 8,388,608 × L
H = dec2hex (D, 8)
(X/20)
X
L = 10
HEX (3.23 Format)
Table 2. Sample Calculation for 9.17 Format
40
db
LINEAR
DECIMAL
HEX (9.17 Format)
0
1
131,072
2 0000
3 8A3D
5
1.77
231,997
–5
0.56
73,400
1 1EB8
X
L = 10(X/20)
D = 131,072 × L
H = dec2hex (D, 8)
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6 Register Maps
9.6.1 Register Map Summary
Table 3. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
CONTENTS (1)
INITIALIZATION VALUE
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x00
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
1
Reserved (2)
1
Description shown in subsequent section
1
Reserved (2)
0x0B–0x0D
0x0E
Volume configuration
register
0x0F
0x91
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
1
Reserved (2)
Description shown in subsequent section
0x15-0x18
0x19
PWM channel shutdown
group register
1
0x1A
Start/stop period register
1
0x0F
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x1D–0x1F
0x30
0x02
(2)
1
Reserved
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
0x22 -0x24
0x25
PWM MUX register
0x26-0x28
0x29
0x2A
(1)
(2)
NO. OF
BYTES
ch1_bq[0]
ch1_bq[1]
(2)
4
Reserved
4
Description shown in subsequent section
4
Reserved (2)
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
20
0x0102 1345
A u indicates unused bits.
Reserved registers must not be accessed.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
41
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
42
REGISTER NAME
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS (1)
INITIALIZATION VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x34
0x35
0x36
REGISTER NAME
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
0x37 - 0x39
0x3A
DRC1 ae (3)
NO. OF
BYTES
20
20
20
DRC1 aa
DRC1 ad
DRC2 ae
DRC2 aa
DRC2 ad
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
8
8
8
8
8
DRC2 (1 – ad)
u[31:26], (1 – ad)[25:0]
0x0000 0000
0x40
DRC1-T
4
T1[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC1-K
4
u[31:26], K1[25:0]
0x0384 2109
0x42
DRC1-O
4
u[31:26], O1[25:0]
0x0008 4210
0x43
DRC2-T
4
T2[31:0] (9.23 format)
0xFDA2 1490
0x44
DRC2-K
4
u[31:26], K2[25:0]
0x0384 2109
0x45
DRC2-O
4
u[31:26], O2[25:0]
0x0008 4210
0x46
DRC control
4
Description shown in subsequent section
0x0000 0000
4
Reserved (2)
0x47–0x4F
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
0x51
Ch 1 output mixer
12
Ch 1 output mix1[2]
0x0080 0000
Ch 1 output mix1[1]
0x0000 0000
0x52
(3)
0x0000 0000
u[31:26], b2[25:0]
0x0080 0000
DRC2 (1 – aa)
0x3F
u[31:26], b1[25:0]
u[31:26], ae[25:0]
DRC 2 (1 – ae)
0x3E
0x0080 0000
8
DRC1 (1 – ad)
0x3D
u[31:26], b0[25:0]
Reserved (2)
DRC1 (1 – aa)
0x3C
INITIALIZATION VALUE
4
DRC1 (1 – ae)
0x3B
CONTENTS (1)
Ch 2 output mixer
12
Ch 1 output mix1[0]
0x0000 0000
Ch 2 output mix2[2]
0x0080 0000
Ch 2 output mix2[1]
0x0000 0000
Ch 2 output mix2[0]
0x0000 0000
"ae" stands for ∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
43
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x53
0x54
0x55
Ch 1 input mixer
Ch 2 input mixer
Channel 3 input mixer
NO. OF
BYTES
16
16
12
CONTENTS (1)
INITIALIZATION VALUE
Ch 1 input mixer[3]
0x0080 0000
Ch 1 input mixer[2]
0x0000 0000
Ch 1 input mixer[1]
0x0000 0000
Ch 1 input mixer[0]
0x0080 0000
Ch 2 input mixer[3]
0x0080 0000
Ch 2 input mixer[2]
0x0000 0000
Ch 2 input mixer[1]
0x0000 0000
Ch 2 input mixer[0]
0x0080 0000
Channel 3 input mixer [2]
0x0080 0000
Channel 3 input mixer [1]
0x0000 0000
Channel 3 input mixer [0]
0x0000 0000
0x56
Output post-scale
4
u[31:26], post[25:0]
0x0080 0000
0x57
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
0x58
ch1 BQ[7]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x59
0x5A
0x5B
0x5C
0x5D
44
REGISTER NAME
ch1 BQ[8]
Subchannel BQ[0]
Subchannel BQ[1]
ch2 BQ[7]
ch2 BQ[8]
20
20
20
20
20
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
Register Maps (continued)
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x5E
REGISTER NAME
pseudo_ch2 BQ[0]
0x5F
NO. OF
BYTES
20
INITIALIZATION VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
4
Reserved (2)
Ch 4 output mixer[1]
0x0000 0000
Ch 4 output mixer[0]
0x0080 0000
Ch 4 input mixer[1]
0x0040 0000
Ch 4 input mixer[0]
0x0040 0000
Post-IDF attenuation register
0x0000 0080
0x60
Channel 4 (subchannel)
output mixer
8
0x61
Channel 4 (subchannel)
input mixer
8
IDF post scale
4
0x62
CONTENTS (1)
0x63–0xF7
Reserved
(2)
0x0000 0000
0xF8
Device address enable
register
4
Write F9 A5 A5 A5 in this register to enable write to
device address update (0xF9)
0x0000 0000
0xF9
Device address Update
Register
4
u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id
(7:1) defines the new device address
0X0000 0036
4
Reserved (2)
0x0000 0000
0xFA–0xFF
All DAP coefficients are 3.23 format unless specified otherwise.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
45
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.6.2 Register Maps
9.6.2.1 Clock Control Register (0x00)
The clocks and data rates are automatically determined by the TAS5755M. The clock control register contains
the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The
device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of
192 fS and 384 fS only.
Table 4. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved (1)
0
1
0
–
–
–
–
–
Reserved (1)
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate (2)
1
0
0
–
–
–
–
–
fS = 16-kHz sample rate
1
0
1
–
–
–
–
–
fS = 22.05/24-kHz sample rate
1
1
0
–
–
–
–
–
fS = 8-kHz sample rate
1
1
1
–
–
–
–
–
fS = 11.025/12-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (3)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS (4)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved (1)
–
–
–
1
1
1
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Reserved (1)
–
(1)
(2)
(3)
(4)
(5)
–
–
–
–
–
–
0
FUNCTION
Reserved
(2) (5)
(2)
(1) (2)
Reserved registers must not be accessed.
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates
Rate only available for 32/44.1/48-kHz sample rates
Not available at 8 kHz
9.6.2.2 Device ID Register (0x01)
The device ID register contains the ID code for the firmware revision.
Table 5. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
46
FUNCTION
Identification code
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6.2.3 Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
Table 6. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, or undervoltage errors
–
–
–
–
–
–
–
0
Reserved
0
0
0
0
0
0
0
–
No errors (1)
(1)
FUNCTION
Default values are in bold.
9.6.2.4 System Control Register 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).
Bit D5:
If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the
same time as the volume ramp defined in register 0x0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp
Bits D1–D0: Select de-emphasis
Table 7. System Control Register 1 (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
PWM high-pass (dc blocking) disabled
1
–
–
–
–
–
–
–
PWM high-pass (dc blocking) enabled (1)
–
0
–
–
–
–
–
–
Reserved (1)
–
–
0
–
–
–
–
–
Soft unmute on recovery from clock error
–
–
1
–
–
–
–
–
Hard unmute on recovery from clock error (1)
–
–
–
0
–
–
–
–
Reserved (1)
–
–
–
–
0
–
–
–
Reserved (1)
–
–
–
–
–
0
–
–
Reserved (1)
–
–
–
–
–
–
0
0
No de-emphasis (1)
–
–
–
–
–
–
0
1
De-emphasis for fS = 32 kHz
–
–
–
–
–
–
1
0
De-emphasis for fS = 44.1 kHz
–
–
–
–
–
–
1
1
De-emphasis for fS = 48 kHz
(1)
FUNCTION
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
47
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.6.2.5 Serial Data Interface Register (0x04)
As shown in Table 8, the TAS5755M supports 9 serial data modes. The default is 24-bit, I2S mode,
Table 8. Serial Data Interface Control Register (0x04)
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD
LENGTH
D7–D4
D3
D2
D1
D0
Right-justified
16
0000
0
0
0
0
Right-justified
20
0000
0
0
0
1
Right-justified
24
0000
0
0
1
0
I2S
16
000
0
0
1
1
I2S
20
0000
0
1
0
0
2
I S
(1)
24
0000
0
1
0
1
Left-justified
16
0000
0
1
1
0
Left-justified
20
0000
0
1
1
1
Left-justified
24
0000
1
0
0
0
Reserved
0000
1
0
0
1
Reserved
0000
1
0
1
0
Reserved
0000
1
0
1
1
Reserved
0000
1
1
0
0
Reserved
0000
1
1
0
1
Reserved
0000
1
1
1
0
Reserved
0000
1
1
1
1
(1)
Default values are in bold.
9.6.2.6 System Control Register 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs
are shut down (hard mute).
Table 9. System Control Register 2 (0x05)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
Mid-Z ramp disabled (1)
1
–
–
–
–
–
–
–
Mid-Z ramp enabled
–
0
–
–
–
–
–
–
Exit all-channel shutdown (normal operation)
–
1
–
–
–
–
–
–
Enter all-channel shutdown (hard mute) (1)
0
FUNCTION
Sub-channel in AD Mode
1
Sub-channel in BD Mode
–
–
–
–
–
0
–
–
2.0 mode [2.0 BTL] (1)
–
–
–
–
–
1
–
–
2.1 mode [2 SE + 1 BTL]
–
–
–
–
–
–
0
–
ADR/FAULT pin is configured as to serve as an address input only (1)
–
–
–
–
–
–
1
–
ADR/FAULT pin is configured as fault output
–
–
0
0
-
–
–
0
Reserved (1)
(1)
48
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6.2.7 Soft Mute Register (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 10. Soft Mute Register (0x06)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
–
–
–
Reserved (1)
–
–
–
–
–
0
–
–
Soft unmute channel 3 (1)
–
–
–
–
–
1
–
–
Soft mute channel 3
–
–
–
–
–
–
0
–
Soft unmute channel 2 (1)
–
–
–
–
–
–
1
–
Soft mute channel 2
–
–
–
–
–
–
–
0
Soft unmute channel 1 (1)
–
–
–
–
–
–
–
1
Soft mute channel 1
(1)
FUNCTION
Default values are in bold.
9.6.2.8 Volume Registers (0x07, 0x08, 0x09, 0x0A)
Step size is 0.5 dB.
Master volume
– 0x07 (default is mute)
Channel-1 volume
– 0x08 (default is 0 dB)
Channel-2 volume
– 0x09 (default is 0 dB)
Channel-3 volume
– 0x0A (default is 0 dB)
Table 11. Volume Registers (0x07, 0x08, 0x09, 0x0A)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
24 dB
0
0
1
1
0
0
0
0
0 dB (default for individual channel volume) (1)
1
1
1
1
1
1
1
0
–103 dB
1
1
1
1
1
1
1
1
Soft mute (default for master volume)
(1)
FUNCTION
(1)
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
49
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.6.2.9 Volume Configuration Register (0x0E)
Bits
D2–D0:
Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the
number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows
Sample Rate (KHz)
Approximate Ramp Rate
8/16/32
125 µs/step
11.025/22.05/44.1
90.7 µs/step
12/24/48
83.3 µs/step
Table 12. Volume Control Register (0x0E)
D7
D6
D5
D4
D3
D2
D1
D0
1
–
–
1
0
–
–
–
Reserved (1)
–
0
–
–
–
–
–
–
Subchannel (ch4) volume = ch1 volume
–
1
–
–
–
–
–
–
Subchannel volume = register 0x0A (2)
–
–
0
–
–
–
–
–
Ch3 volume = ch2 volume (1)
–
–
1
–
–
–
–
–
Ch3 volume = register 0x0A
–
–
–
–
–
0
0
0
Volume slew 512 steps (43-ms volume ramp time at 48 kHz)
–
–
–
–
–
0
0
1
Volume slew 1024 steps (85-ms volume ramp time at 48 kHz) (1)
–
–
–
–
–
0
1
0
Volume slew 2048 steps (171- ms volume ramp time at 48 kHz)
–
–
–
–
–
0
1
1
Volume slew 256 steps (21-ms volume ramp time at 48 kHz)
–
–
–
–
–
1
X
X
Reserved
(1)
(2)
FUNCTION
(2) (1)
Default values are in bold.
Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)].
9.6.2.10 Modulation Limit Register (0x10)
The modulation limit is the maximum duty cycle of the PWM output waveform.
Table 13. Modulation Limit Register (0x10)
(1)
50
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION LIMIT
–
–
–
–
–
0
0
0
99.2%
–
–
–
–
–
0
0
1
98.4%
–
–
–
–
–
0
1
0
97.7% (1)
–
–
–
–
–
0
1
1
96.9%
–
–
–
–
–
1
0
0
96.1%
–
–
–
–
–
1
0
1
95.3%
–
–
–
–
–
1
1
0
94.5%
–
–
–
–
–
1
1
1
93.8%
0
0
0
0
0
–
–
–
Reserved
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 14. Channel Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
BITS DEFINITION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
–
–
Minimum absolute delay, 0 DCLK cycles
FUNCTION
0
1
1
1
1
1
–
–
Maximum positive delay, 31 × 4 DCLK cycles
1
0
0
0
0
0
–
–
Maximum negative delay, –32 × 4 DCLK cycles
0
0
Reserved
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
0x11
1
0
1
0
1
1
–
–
Default value for channel 1 (1)
0x12
0
1
0
1
0
1
–
–
Default value for channel 2 (1)
0x13
1
0
1
0
1
1
–
–
Default value for channel 1
(1)
0x14
0
1
0
1
0
1
–
–
Default value for channel 2
(1)
(1)
DELAY = (VALUE) × 4 DCLKs
Default values are in bold.
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.). Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
REGISTER
AD MODE
BD MODE
0x11
AC
B8
0x12
54
60
0x13
AC
A0
0x14
54
48
9.6.2.12 PWM Shutdown Group Register (0x19)
Settings of this register determine which PWM channels are active. The value must be 0x30 for BTL mode and
0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the
state of bit D5 in the system control register.
This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group
register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is
set to 0 in system control register 2, 0x05).
Table 15. Shutdown Group Register (0x19)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
Reserved (1)
–
0
–
–
–
–
–
–
Reserved (1)
–
–
1
–
–
–
–
–
Reserved (1)
–
–
–
1
–
–
–
–
Reserved (1)
–
–
–
–
0
–
–
–
PWM channel 4 does not belong to shutdown group. (1)
–
–
–
–
1
–
–
–
PWM channel 4 belongs to shutdown group.
–
–
–
–
–
0
–
–
PWM channel 3 does not belong to shutdown group. (1)
–
–
–
–
–
1
–
–
PWM channel 3 belongs to shutdown group.
–
–
–
–
–
–
0
–
PWM channel 2 does not belong to shutdown group. (1)
–
–
–
–
–
–
1
–
PWM channel 2 belongs to shutdown group.
–
–
–
–
–
–
–
0
PWM channel 1 does not belong to shutdown group. (1)
–
–
–
–
–
–
–
1
PWM channel 1 belongs to shutdown group.
(1)
FUNCTION
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
51
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.6.2.13 Start/Stop Period Register (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times
are only approximate and vary depending on device activity level and I2S clock stability.
Table 16. Start/Stop Period Register (0x1A)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
SSTIMER enabled (1)
1
–
–
–
–
–
–
–
SSTIMER disabled
–
0
0
–
–
–
–
–
Reserved (1)
–
–
–
0
0
–
–
–
No 50% duty cycle start/stop period
–
–
–
0
1
0
0
0
16.5-ms 50% duty cycle start/stop period
–
–
–
0
1
0
0
1
23.9-ms 50% duty cycle start/stop period
–
–
–
0
1
0
1
0
31.4-ms 50% duty cycle start/stop period
–
–
–
0
1
0
1
1
40.4-ms 50% duty cycle start/stop period
–
–
–
0
1
1
0
0
53.9-ms 50% duty cycle start/stop period
–
–
–
0
1
1
0
1
70.3-ms 50% duty cycle start/stop period
–
–
–
0
1
1
1
0
94.2-ms 50% duty cycle start/stop period
–
–
–
0
1
1
1
1
125.7-ms 50% duty cycle start/stop period (1)
–
–
–
1
0
0
0
0
164.6-ms 50% duty cycle start/stop period
–
–
–
1
0
0
0
1
239.4-ms 50% duty cycle start/stop period
–
–
–
1
0
0
1
0
314.2-ms 50% duty cycle start/stop period
–
–
–
1
0
0
1
1
403.9-ms 50% duty cycle start/stop period
–
–
–
1
0
1
0
0
538.6-ms 50% duty cycle start/stop period
–
–
–
1
0
1
0
1
703.1-ms 50% duty cycle start/stop period
–
–
–
1
0
1
1
0
942.5-ms 50% duty cycle start/stop period
–
–
–
1
0
1
1
1
1256.6-ms 50% duty cycle start/stop period
–
–
–
1
1
0
0
0
1728.1-ms 50% duty cycle start/stop period
–
–
–
1
1
0
0
1
2513.6-ms 50% duty cycle start/stop period
–
–
–
1
1
0
1
0
3299.1-ms 50% duty cycle start/stop period
–
–
–
1
1
0
1
1
4241.7-ms 50% duty cycle start/stop period
–
–
–
1
1
1
0
0
5655.6-ms 50% duty cycle start/stop period
–
–
–
1
1
1
0
1
7383.7-ms 50% duty cycle start/stop period
–
–
–
1
1
1
1
0
9897.3-ms 50% duty cycle start/stop period
–
–
–
1
1
1
1
1
13,196.4-ms 50% duty cycle start/stop period
(1)
52
FUNCTION
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6.2.14 Oscillator Trim Register (0x1B)
The TAS5755M PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. Currently, TI recommends a reference
resistor value of 18.2 kΩ (1%). This must be connected between OSC_RES and DVSSO.
Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
NOTE
Trim must always be run following reset of the device.
Table 17. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
Reserved (1)
–
0
–
–
–
–
–
–
Oscillator trim not done (read-only) (1)
–
1
–
–
–
–
–
–
Oscillator trim done (read only)
–
–
0
0
0
0
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Select factory trim (Write a 0 to select factory trim; default is 1.)
–
–
–
–
–
–
1
–
Factory trim disabled (1)
–
–
–
–
–
–
–
0
Reserved (1)
(1)
FUNCTION
Default values are in bold.
9.6.2.15 BKND_ERR Register (0x1C)
When a back-end error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 18 before attempting
to re-start the power stage.
Table 18. BKND_ERR Register (0x1C) (1)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
X
Reserved
–
–
–
–
0
0
1
0
Set back-end reset period to 299 ms (2)
–
–
–
–
0
0
1
1
Set back-end reset period to 449 ms
–
–
–
–
0
1
0
0
Set back-end reset period to 598 ms
–
–
–
–
0
1
0
1
Set back-end reset period to 748 ms
–
–
–
–
0
1
1
0
Set back-end reset period to 898 ms
–
–
–
–
0
1
1
1
Set back-end reset period to 1047 ms
–
–
–
–
1
0
0
0
Set back-end reset period to 1197 ms
–
–
–
–
1
0
0
1
Set back-end reset period to 1346 ms
–
–
–
–
1
0
1
X
Set back-end reset period to 1496 ms
–
–
–
–
1
1
X
X
Set back-end reset period to 1496 ms
(1)
(2)
FUNCTION
This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
53
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
9.6.2.16 Input Multiplexer Register (0x20)
This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal
channels.
Table 19. Input Multiplexer Register (0x20)
D31
(1)
54
D30
D29
D28
D27
D26
D25
D24
FUNCTION
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
0
–
–
–
–
–
–
–
Channel-1 AD mode (1)
1
–
–
–
–
–
–
–
Channel-1 BD mode
–
0
0
0
–
–
–
–
SDIN-L to channel 1 (1)
–
0
0
1
–
–
–
–
SDIN-R to channel 1
–
0
1
0
–
–
–
–
Reserved
–
0
1
1
–
–
–
–
Reserved
–
1
0
0
–
–
–
–
Reserved
–
1
0
1
–
–
–
–
Reserved
–
1
1
0
–
–
–
–
Ground (0) to channel 1
–
1
1
1
–
–
–
–
Reserved
–
–
–
–
0
–
–
–
Channel 2 AD mode (1)
–
–
–
–
1
–
–
–
Channel 2 BD mode
–
–
–
–
–
0
0
0
SDIN-L to channel 2
–
–
–
–
–
0
0
1
SDIN-R to channel 2 (1)
–
–
–
–
–
0
1
0
Reserved
–
–
–
–
–
0
1
1
Reserved
–
–
–
–
–
1
0
0
Reserved
–
–
–
–
–
1
0
1
Reserved
–
–
–
–
–
1
1
0
Ground (0) to channel 2
–
–
–
–
–
1
1
1
Reserved
D15
D14
D13
D12
D11
D10
D9
D8
0
1
1
1
0
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
0
Reserved
(1)
FUNCTION
FUNCTION
Reserved
(1)
FUNCTION
Reserved (1)
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6.2.17 Channel 4 Source Select Register (0x21)
This register selects the channel 4 source.
Table 20. Subchannel Control Register (0x21)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved (1)
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Reserved
(1)
FUNCTION
0
1
0
0
0
0
1
1
Select SDIN path (third path), not available in
TAS5755M (1)
–
–
–
–
–
–
–
0
(L + R)/2
–
–
–
–
–
–
0
1
Left-channel post-BQ (1)
D7
D6
D5
D4
D3
D2
D1
D0
0
(1)
0
0
0
0
0
1
1
FUNCTION
Reserved
(1)
Default values are in bold.
9.6.2.18 PWM Output Mux Register (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D21–D20:
Selects which PWM channel is output to OUT_A
Bits D17–D16:
Selects which PWM channel is output to OUT_B
Bits D13–D12:
Selects which PWM channel is output to OUT_C
Bits D09–D08:
Selects which PWM channel is output to OUT_D
NOTE
Channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.
Table 21. PWM Output Mux Register (0x25)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
0
0
0
0
0
0
0
1
D23
D22
D21
D20
D19
D18
D17
D16
0
0
–
–
–
–
–
–
Reserved (1)
–
–
0
0
–
–
–
–
Multiplex PWM 1 to OUT_A (1)
–
–
0
1
–
–
–
–
Multiplex PWM 2 to OUT_A
–
–
1
0
–
–
–
–
Multiplex PWM 3 to OUT_A
–
–
1
1
–
–
–
–
Multiplex PWM 4 to OUT_A
–
–
–
–
0
0
–
–
Reserved (1)
–
–
–
–
–
–
0
0
Multiplex PWM 1 to OUT_B
–
–
–
–
–
–
0
1
Multiplex PWM 2 to OUT_B
–
–
–
–
–
–
1
0
Multiplex PWM 3 to OUT_B (1)
–
–
–
–
–
–
1
1
Multiplex PWM 4 to OUT_B
(1)
Reserved
(1)
FUNCTION
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
55
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Table 21. PWM Output Mux Register (0x25) (continued)
D15
D14
D13
D12
D11
D10
D9
D8
0
0
–
–
–
–
–
–
Reserved (1)
–
–
0
0
–
–
–
–
Multiplex PWM 1 to OUT_C
–
–
0
1
–
–
–
–
Multiplex PWM 2 to OUT_C (1)
–
–
1
0
–
–
–
–
Multiplex PWM 3 to OUT_C
–
–
1
1
–
–
–
–
Multiplex PWM 4 to OUT_C
–
–
–
–
0
0
–
–
Reserved (1)
–
–
–
–
–
–
0
0
Multiplex PWM 1 to OUT_D
–
–
–
–
–
–
0
1
Multiplex PWM 2 to OUT_D
–
–
–
–
–
–
1
0
Multiplex PWM 3 to OUT_D
–
–
–
–
–
–
1
1
Multiplex PWM 4 to OUT_D (1)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
1
FUNCTION
FUNCTION
Reserved
(1)
9.6.2.19 DRC Control Register (0x46)
Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.
Table 22. DRC Control Register (0x46)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved (1)
FUNCTION
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
–
–
–
–
–
–
Reserved (1)
–
–
0
–
–
–
–
–
Disable complementary (1 - H) low-pass filter generation
–
–
1
–
–
–
–
–
Enable complementary (1 - H) low-pass filter generation
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
–
0
0
(1)
56
Reserved
(1)
FUNCTION
Reserved (1)
FUNCTION
Reserved (1)
–
–
–
–
–
–
0
–
DRC2 turned OFF (1)
–
–
–
–
–
–
1
–
DRC2 turned ON
–
–
–
–
–
–
–
0
DRC1 turned OFF (1)
–
–
–
–
–
–
–
1
DRC1 turned ON
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
9.6.2.20 Bank Switch and EQ Control Register (0x50)
Table 23. Bank Switching Command Register (0x50)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
0
–
–
–
–
–
–
–
32 kHz, does not use bank 3 (1)
1
–
–
–
–
–
–
–
32 kHz, uses bank 3
–
0
–
–
–
–
–
–
Reserved (1)
–
–
0
–
–
–
–
–
Reserved (1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 3 (1)
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 3
–
–
–
–
0
–
–
–
16 kHz, does not use bank 3
–
–
–
–
1
–
–
–
16 kHz, uses bank 3 (1)
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 3
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 3 (1)
–
–
–
–
–
–
0
–
8 kHz, does not use bank 3
–
–
–
–
–
–
1
–
8 kHz, uses bank 3 (1)
–
–
–
–
–
–
–
0
11.025 kHz/12, does not use bank 3
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 3 (1)
D23
D22
D21
D20
D19
D18
D17
D16
0
–
–
–
–
–
–
–
32 kHz, does not use bank 2 (1)
1
–
–
–
–
–
–
–
32 kHz, uses bank 2
–
1
–
–
–
–
–
–
Reserved (1)
–
–
1
–
–
–
–
–
Reserved (1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 2
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 2 (1)
–
–
–
–
0
–
–
–
16 kHz, does not use bank 2 (1)
–
–
–
–
1
–
–
–
16 kHz, uses bank 2
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 2 (1)
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 2
–
–
–
–
–
–
0
–
8 kHz, does not use bank 2 (1)
–
–
–
–
–
–
1
–
8 kHz, uses bank 2
–
–
–
–
–
–
–
0
11.025/12 kHz, does not use bank 2 (1)
11.025/12 kHz, uses bank 2
FUNCTION
–
–
–
–
–
–
–
1
D15
D14
D13
D12
D11
D10
D9
D8
0
–
–
–
–
–
–
–
32 kHz, does not use bank 1
1
–
–
–
–
–
–
–
32 kHz, uses bank 1 (1)
–
0
–
–
–
–
–
–
Reserved (1)
–
–
0
–
–
–
–
–
Reserved (1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 1 (1)
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 1
–
–
–
–
0
–
–
–
16 kHz, does not use bank 1 (1)
–
–
–
–
1
–
–
–
16 kHz, uses bank 1
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 1 (1)
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 1
–
–
–
–
–
–
0
–
8 kHz, does not use bank 1 (1)
–
–
–
–
–
–
1
–
8 kHz, uses bank 1
–
–
–
–
–
–
–
0
11.025/12 kHz, does not use bank 1 (1)
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 1
(1)
FUNCTION
Default values are in bold.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
57
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Table 23. Bank Switching Command Register (0x50) (continued)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
–
–
–
–
–
–
–
EQ OFF (bypass BQ 0-7 of channels 1 and 2)
–
0
–
–
–
–
–
–
Reserved (1)
–
–
0
–
–
–
–
–
Ignore bank-mapping in bits D31–D8.Use default mapping. (1)
–
–
–
0
–
–
–
–
L and R can be written independently. (1)
–
–
–
1
–
–
–
–
L and R are ganged for EQ biquads; a write to left-channel BQ is also
written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also
0x58–0x59 is ganged to 0x5C–0x5D)
–
–
–
–
0
–
–
–
Reserved (1)
–
–
–
–
–
0
0
0
No bank switching. All updates to DAP (1)
–
–
–
–
–
0
0
1
Configure bank 1 (32 kHz by default)
–
–
–
–
–
0
1
0
Configure bank 2 (44.1/48 kHz by default)
–
–
–
–
–
0
1
1
Configure bank 3 (other sample rates by default)
–
–
–
–
–
1
0
0
Automatic bank selection
–
–
–
–
–
1
0
1
Reserved
–
–
–
–
–
1
1
X
Reserved
1
58
FUNCTION
EQ ON
Use bank-mapping in bits D31–D8.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Figure 68, Figure 71, and Figure 72 highlight the required external components and system level connections for
proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible
modules allow full evaluation of the device in the most common modes of operation. Any design variation can be
supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the
audio amplifier discussion forum for additional information.
10.2 Typical Applications
10.2.1 Stereo Bridge Tied Load Application
A stereo system generally refers to a system in which there are two full range speakers without a separate
amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are
presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two
separate speakers.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel.
The Stereo BTL Configuration with Headphone and Line Driver Amplifier application is shown in Figure 68.
3.3V
8V-24V
AVDD/DVDD
OUT_A
LRCLK
Digital
Audio
Source
PVDD
SCLK
BST_A
MCLK
SDIN
LCBTL
BST_B
2
IC
Control
Control
Inputs
SDA
OUT_B
SCL
RESET
PDN
OUT_A
BST_A
Loop
Filter
LCBTL
PLL_FLTP
PLL_FLTM
BST_B
OUT_B
Copyright © 2018, Texas Instruments Incorporated
Figure 68. Stereo Bridge Tied Load Application
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
59
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Typical Applications (continued)
10.2.1.1 Design Requirements
Table 24. Design Requirements
PARAMETER
EXAMPLE
Low Power Supply
3.3 V
High Power Supply
8 V to 24 V
I2S Compliant Master
Host Processor
I2C Compliant Master
Output Filters
Inductor-Capacitor Low Pass Filter
Speaker
4 Ω minimum
GPIO Control
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Component Selection and Hardware Connections
The typical connections required for proper operation of the device can be found in the TAS5755EVM User’s
Guide (SLOU481A). The device was tested with this list of components; deviation from this list of typical
application components, unless recommended by this document, may produce unwanted results, which could
range from degradation of audio performance to destructive failure of the device.
10.2.1.2.2 I2C Pullup Resistors
Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical
Application Circuits, because they are shared by all of the devices on the I2C bus and are considered to be part
of the associated passive components for the System Processor. These resistor values must be chosen per the
guidance provided in the I2C Specification.
10.2.1.2.3 Digital I/O Connectivity
The digital I/O lines of the TAS5755M are described in previous sections. As discussed, whenever a static digital
pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it must be connected to
DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not,
however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor
can be used to tie all static I/O lines HIGH to reduce BOM count.
60
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
10.2.1.2.4 Recommended Start-Up and Shutdown Procedures
Normal Operation
Initialization
AVDD/DVDD
Powerdown
Shutdown
3V
3V
0 ns
PDN
2 ms
0 ns
2
I C
SCL
SDA
Trim
DAP
Config
Other
Config
Exit
SD
Volume and Mute Commands
(2)
50 ms
1 ms + 1.3 tstart
Enter
SD
1 ms + 1.3 tstop
(2)
2 ms
0 ns
100 ms
RESET
13.5 ms
tPLL
(1)
2 ms
100 μs
10 ms
PVDD
8V
6V
8V
6V
(1) tPLL has to be greater than 240 ms + 1.3 tstart.
This constraint only applies to the first trim command following AVDD/DVDD power-up.
It does not apply to trim commands following subsequent resets.
(2) tstart/tstop = PWM start/stop time as defined in register 0X1A
T0419-06
Figure 69. Recommended Command Sequence
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
61
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
3V
AVDD/DVDD
0 ns
2 ms
PDN
0 ns
2
I C
2 ms
RESET
2 ms
0 ns
8V
PVDD
6V
T0420-05
Figure 70. Power-Loss Sequence
10.2.1.2.4.1 Initialization Sequence
Use the following sequence to power up and initialize the device:
1.
Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
2.
Initialize digital inputs and PVDD supply as follows:
•
Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that
all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1,
and wait at least another 13.5 ms.
•
Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs
after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
3.
Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
4.
Configure the DAP via I2C, see TAS5755EVM Evaluation Module User's Guide (SLOU481A) for
typical values.
5.
Configure remaining registers.
6.
Exit shutdown (sequence defined in Shutdown Sequence).
10.2.1.2.4.2 Normal Operation
The following are the only events supported during normal operation:
1.
Writes to master/channel volume registers
2.
Writes to soft-mute register
3.
Enter and exit shutdown (sequence defined in Shutdown Sequence)
NOTE
Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD powerup ramp (where tstart is specified by register 0x1A).
62
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
10.2.1.2.4.3 Shutdown Sequence
Enter:
1.
Write 0x40 to register 0x05.
2.
Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A).
3.
If desired, reconfigure by returning to step 4 of initialization sequence.
1.
Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms
after trim following AVDD/DVDD power-up ramp).
2.
Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A).
3.
Proceed with normal operation.
Exit:
10.2.1.2.4.4 Power-Down Sequence
Use the following sequence to power down the device and its supplies:
1.
If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of
sudden power loss, assert PDN = 0 and wait at least 2 ms.
2.
Assert RESET = 0.
3.
Drive digital inputs low and ramp down PVDD supply as follows:
4.
•
Drive all digital inputs low after RESET has been low for at least 2 µs.
•
Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at
least 2 µs.
Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and
that it is never more than 2.5 V below the digital inputs.
10.2.1.3 Application Curves
space
Table 25. Relevant Performance Curves
CURVE TITLE
FIGURE
Output Power vs Supply Voltage (2.0 BTL Mode)
With 4Ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V
Figure 18
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode)
Figure 19
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode)
Figure 20
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode)
Figure 21
Total Harmonic Distortion vs Frequency (2.0 BTL Mode)
Figure 22
Total Harmonic Distortion vs Frequency (2.0 BTL Mode)
Figure 23
Total Harmonic Distortion vs Frequency (2.0 BTL Mode)
Figure 24
Efficiency vs Output Power (2.0 BTL Mode)
Figure 25
Crosstalk vs Frequency (2.0 BTL Mode)
Figure 26
Crosstalk vs Frequency (2.0 BTL Mode)
Figure 27
Crosstalk vs Frequency (2.0 BTL Mode)
Figure 28
Crosstalk vs Frequency (2.0 BTL Mode)
Figure 29
Power vs Supply Voltage (2.0 BTL Mode)
Figure 30
Idle Channel Noise vs Supply Voltage (2.0 BTL Mode)
Figure 31
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
63
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
10.2.2 Mono Parallel Bridge Tied Load Application
A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge
Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the
loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5755M
device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the
amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while
the on-resistance is approximately halved.
The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an
audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed
together and sent through a low-pass filter in order to create a single audio signal which contains the low
frequency information of the two channels.
The Mono Parallel Bridge Tied Load application is shown in Figure 71.
3.3 V
8 V–24 V
AVDD/DVDD
PVDD
LRCLK
Digital
Audio
Source
OUT_A
SCLK
MCLK
SDIN
BST_A
BST_B
OUT_B
2
SDA
I C
Control
LCPBTL
SCL
OUT_C
RESET
Control
Inputs
PDN
BST_C
BST_D
PLL_FLTP
Loop
Filter
PLL_FLTM
OUT_D
Copyright © 2018, Texas Instruments Incorporated
Figure 71. Mono Parallel Bridge Tied Load Application
64
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
10.2.2.1 Design Requirements
Table 26. Design Requirements
PARAMETER
EXAMPLE
Low Power Supply
3.3 V
High Power Supply
8 V to 24 V
I2S Compliant Master
Host Processor
I2C Compliant Master
Output Filters
Inductor-Capacitor Low Pass Filter
Speaker
4 Ω minimum
GPIO Control
10.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure for information.
10.2.2.3 Application Curves
SPACE
Table 27. Relevant Performance Curves
CURVE TITLE
FIGURE
Output Power vs Supply Voltage (PBTL Mode)
With 2Ω Load on Typical 2 Layer PCB, Device May Be Thermally Limited Above 20 V
Figure 32
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)
Figure 33
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)
Figure 34
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)
Figure 35
Total Harmonic Distortion vs Frequency (PBTL Mode)
Figure 36
Total Harmonic Distortion vs Frequency (PBTL Mode)
Figure 37
Total Harmonic Distortion vs Frequency (PBTL Mode)
Figure 38
Efficiency vs Output Power (PBTL Mode)
Figure 39
Efficiency vs Output Power (PBTL Mode)
Figure 40
Power vs Supply Voltage (PBTL Mode)
Figure 41
Idle Channel Noise vs Supply Voltage (PBTL Mode)
Figure 42
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
65
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
10.2.3 2.1 Application
A 2.1 system generally refers to a system in which there are two full range speakers with a separate amplifier
path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to
the amplifier via the digital input signal, these are driven into two single-ended speakers and are mixed into a
third channel, conditioned to stream low-frequency content into a differentially connected speaker.
The 2.1 application is shown in Figure 72.
3.3 V
8 V–24 V
AVDD/DVDD
PVDD
LRCLK
Digital
Audio
Source
LCSE
OUT_A
SCLK
PVDD
BST_A
MCLK
SDIN
BST_B
2
LCSE
OUT_B
I C
Control
SDA
Control
Inputs
RESET
PVDD
SCL
PDN
OUT_C
PLL_FLTP
Loop
Filter
PLL_FLTM
BST_C
LCBTL
BST_D
OUT_D
Copyright © 2018, Texas Instruments Incorporated
Figure 72. Simplified 2.1 Application Diagram
10.2.3.1 Design Requirements
Table 28. Design Requirements
PARAMETER
EXAMPLE
Low Power Supply
3.3 V
High Power Supply
8 V to 24 V
I2S Compliant Master
Host Processor
I2C Compliant Master
Output Filters
Inductor-Capacitor Low Pass Filter
Speaker
4 Ω (BTL), 2 Ω (SE) minimum
GPIO Control
66
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
10.2.3.2 Detailed Design Procedure
Refer to Detailed Design Procedure for information.
10.2.3.3 Application Curves
Table 29. Relevant Performance Curves
CURVE TITLE
FIGURE
Output Power vs Supply Voltage (2.1 SE Mode)
With 2 × 4Ω + 4Ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V
Figure 5
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode)
Figure 6
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode)
Figure 7
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode)
Figure 8
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode)
Figure 9
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode)
Figure 10
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode)
Figure 11
Efficiency vs Total Output Power (2.1 SE Mode)
Figure 12
Efficiency vs Total Output Power (2.1 SE Mode)
Figure 13
Crosstalk vs Frequency (2.1 SE Mode)
Figure 14
Crosstalk vs Frequency (2.1 SE Mode)
Figure 15
Crosstalk vs Frequency (2.1 SE Mode)
Figure 16
Crosstalk vs Frequency (2.1 SE Mode)
Figure 17
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
67
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
11 Power Supply Recommendations
The TAS5755M requires two power supplies; a low voltage 3.3 V nominal for the pins DVDD and AVDD and a
high power supply, 8 V to 24 V for the pin PVDD. There is no requirement for power up sequencing of low and
high power supplies, however is recommended to put the PDN pin to low before removing the low voltage power
supplies in order to protect the outputs.
11.1 DVDD and AVDD Supplies
The AVDD Supply is used to power the analog internal circuit of the device, and needs a well regulated and
filtered 3.3-V supply voltage. The DVDD Supply is used to power the digital circuitry. DVDD needs a well
regulated and filtered 3.3-V supply voltage.
11.2 PVDD Power Supply
The TAS5755M class-D audio amplifier requires adequate power supply decoupling to ensure the output total
harmonic distortion (THD) and noise is as low as possible. A good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 µF, placed as close as possible to the device PVDD leads works best. For filtering
lower frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier is
recommended.
12 Layout
12.1 Layout Guidelines
Class-D switching edges are fast and switched currents are high so it is necessary to take care when planning
the layout of the printed circuit board. The following suggestions will help to meet audio, thermal and EMC
requirements.
• Decoupling capacitors: the high-frequency decoupling capacitors must be placed as close to the supply pins
as possible; on the TAS5755M a 1-µF high-quality ceramic capacitor is used. Large (10 μF or greater) bulk
power supply decoupling capacitors must be placed near the TAS5755M on the PVDD supplies.
• Keep the current loop from each of the outputs through the output inductor and the small filter cap and back
to GND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Grounding: A big common GND plane is recommended. The PVDD decoupling capacitors must connect to
GND. The TAS5755M PowerPAD must be connected to GND.
• Output filter: remember to select inductors that can handle the high short circuit current of the device. The LC
filter must be placed close to the outputs.
The EVM product folder (TAS5755EVM) and User’s Guide (SLOU481A) available on www.ti.com show
schematic, bill of material, gerber files, and more detailed layout plots.
68
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
12.2 Layout Examples
Figure 73. Top Layer Layout with Stereo BTL Mode
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
69
TAS5755M
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
www.ti.com
Layout Examples (continued)
Figure 74. Bottom Layer Layout with Stereo BTL Mode
70
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
TAS5755M
www.ti.com
SLOS982C – AUGUST 2017 – REVISED APRIL 2018
13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
TAS570X GDE Software Setup development tool documentation (SLOC124)
13.2 Documentation Support
EVM product folder (TAS5755MEVM)
13.2.1 Related Documentation
TAS5755MEVM User's Guide (SLOU481A)
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: TAS5755M
71
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TAS5755MDFD
ACTIVE
HTSSOP
DFD
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
0 to 125
5755M
TAS5755MDFDR
ACTIVE
HTSSOP
DFD
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
0 to 125
5755M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5755MDFDR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DFD
56
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5755MDFDR
HTSSOP
DFD
56
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising