Texas Instruments | TAS5806M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with Enhanced Processing and Low Power Dissipation | Datasheet | Texas Instruments TAS5806M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with Enhanced Processing and Low Power Dissipation Datasheet

Texas Instruments TAS5806M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with Enhanced Processing and Low Power Dissipation Datasheet
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TAS5806M
SLASEP9 – MAY 2019
TAS5806M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio
Amplifier with Enhanced Processing and Low Power Dissipation
1 Features
2 Applications
•
•
•
•
PACKAGE
BODY SIZE (NOM)
TSSOP (38) DCP
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
BST_B-
OUT_BLRCLK
SDIN
SCLK (BCLK)
BST_A-
BST_B+
Speaker
R Channel
OUT_B+
Speaker
L Channel
OUT_A-
•
PART NUMBER
TAS5806M
SCL
•
Device Information(1)
SDOUT
•
Featuring the TI proprietary Hybrid Modulation
scheme, the TAS5806M consumes low quiescent
current (16.5 mA at 13.5 V PVDD), extending battery
life in portable audio applications. With advanced EMI
suppression technology, for applications under 10 W
designers can leverage inexpensive ferrite bead
filters to reduce board space and system cost.
SDA
•
The TAS5806M is a high-efficiency, stereo, closedloop Class-D amplifier offering a cost-effective digital
input solution with low power dissipation and sound
enrichment. The device’s integrated audio processor
and 96 kHz architecture support advanced audio
process flow, including SRC, 15 BQs per channel,
volume control, audio mixing, 3-band 4th order DRC,
full-band AGL, THD manager and level meter.
PDN
•
3 Description
BST_A+
•
•
•
•
LCD TV, OLED TV
Wireless speaker, smart speaker with voice
assistant
Soundbar, wired speaker
Desktop PC, notebook PC
AV receiver, smart home and IoT appliance
OUT_A+
•
Supports multiple output configurations
– 2 × 23 W in 2.0 mode (8-Ω, 21 V, THD+N=1%)
– 45 W in mono mode (4-Ω, 21 V, THD+N=1%)
Excellent audio performance
– THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V
– SNR ≥ 107 dB (A-weighted), noise level < 40
µVRMS
Low quiescent current with hybrid modulation
– 16.5 mA at PVDD = 13.5 V , 22 μH + 0.68 μF
filter
Flexible power supply configurations
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
Flexible audio I/O
– I2S, LJ, RJ, TDM, 3-wire digital audio interface
(no MCLK required)
– Supports 32, 44.1, 48, 88.2, 96 kHz sample
rates
– SDOUT for audio monitoring, sub-channel or
echo cancellation
Enhanced audio processing
– Multi-band advanced DRC and AGL
– 2×15 BQs, thermal foldback, DC blocking
– Input mixer, output crossbar, level meter
– 5 BQs + 1 band DRC +THD manager for the
subwoofer channel
Integrated self-protection
– Adjacent pin-to-pin short without device
damage
– Over-current error (OCE)
– Over-temperature warning (OTW)
– Over-temperature error (OTE)
– Under or Over-Voltage Lock-out (UVLO/OVLO)
Easy system integration
– I2C software control
– Reduced solution size
– Fewer passives required compared to
open-loop devices
– Inductor-less operation (ferrite bead) for
most cases where PVDD ≤ 14V
Pin-to-pin compatible with TAS5806MD
ADR/FAULT
1
DVDD
System
Processor
Digital
Audio
Source
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5806M
SLASEP9 – MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
9.5 Programming and Control ....................................... 31
9.6 Register Maps ......................................................... 37
1
1
1
2
3
3
5
10 Application and Implementation........................ 69
10.1 Application Information.......................................... 69
10.2 Typical Applications ............................................. 71
11 Power Supply Recommendations ..................... 77
11.1 DVDD Supply ........................................................ 77
11.2 PVDD Supply ........................................................ 78
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ............................................... 9
Typical Characteristics ............................................ 10
12 Layout................................................................... 79
12.1 Layout Guidelines ................................................. 79
12.2 Layout Example .................................................... 81
13 Device and Documentation Support ................. 83
13.1
13.2
13.3
13.4
13.5
13.6
Parametric Measurement Information ............... 20
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
21
22
27
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
83
83
83
83
83
83
14 Mechanical, Packaging, and Orderable
Information ........................................................... 83
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
May 2019
*
Initial release
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5 Device Comparison Table
ORDERABLE PART
NUMBER
RECOMMENDED PVDD
RANGE
RDS(ON) OPTION
Package
Headphone/Line
Driver integrated
TAS5806M
4.5 V to 26.4 V
180 mΩ
TSSOP38 (DCP)
NO
TAS5805M
4.5 V to 26.4 V
180 mΩ
TSSOP28 (PWP)
NO
TAS5806MD
4.5 V to 26.4 V
180 mΩ
TSSOP38 (DCP)
YES
TAS5825M
4.5 V to 26.4 V
90 mΩ
QFN32 (RHB)
NO
6 Pin Configuration and Functions
DCP Package
38-Pin TSSOP
BST_A-
1
38
BST_B-
OUT_A-
2
37
OUT_B-
PGND
3
36
PGND
BST_A+
4
35
BST_B+
OUT_A+
5
34
OUT_B+
PVDD
6
33
PVDD
PVDD
7
32
PVDD
DG ND
8
31
AGND
DV DD
9
30
AVDD
29
PDN
11
28
SCL
ADR/FA ULT
10
VR_DIG
Th ermal
Pad
DG ND
12
27
SDA
LRCLK
13
26
SDOUT
SCLK
14
25
NC
SDIN
15
24
NC
NC
16
23
NC
NC
17
22
NC
NC
18
21
NC
NC
19
20
NC
No t to scale
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
DGND
8,12
G
Digital ground
DVDD
9
P
3.3-V or 1.8-V digital power supply
VR_DIG
11
P
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
ADR/FAULT
10
DIO
LRCLK
13
DI
(1)
Different I2 C device address can be set by selecting different pull up resistor to DVDD, see Table 3 for details.
After power up, ADR/FAULT can be redefine as FAULT, go to Page0, Book0, set register 0x61 = 0x0b first, then
set register 0x60 = 0x01
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
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Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
SCLK
14
DI
Bit clock for the digital signal that is active on the input data line of the serial data port.
SDIN
15
DI
Data line to the serial data port
SDOUT
26
DO
Serial Audio data output, the source data can select as Pre-DSP or Post DSP, by setting the register 0x30h.
SDA
27
DI/O
I2C serial control data interface input/output
SCL
28
DI
I2C serial control clock input
PDN
29
DI
Power Down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators. Low, Power Down
Device; High, Enable Device.
AVDD
30
P
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
AGND
31
G
Analog ground
6
P
7
P
32
P
PVDD
PVDD voltage input
33
P
3
G
36
G
OUT_A+
5
AO
BST_A+
4
P
OUT_A-
2
AO
BST_A-
1
P
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-
BST_B-
38
P
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-
OUT_B-
37
AO
BST_B+
35
P
OUT_B+
34
AO
PGND
NC
4
-
Positive pin for differential speaker amplifier output A+
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+
Negative pin for differential speaker amplifier output A-
Negative pin for differential speaker amplifier output B
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+
Positive pin for differential speaker amplifier output B+
Not connected inside the device (all "no connect" pins should be connected to ground for best thermal
performance, however they can be used as routing channels if required.)
16-25
PowerPAD™
Ground reference for power device circuitry. Connect this pin to system ground.
G
Connect to the system Ground
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SLASEP9 – MAY 2019
7 Specifications
7.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted)
(1)
MIN
MAX
DVDD
Low-voltage digital supply
–0.3
3.9
V
PVDD
PVDD supply
–0.3
30
V
VI(DigIn)
DVDD referenced digital inputs (2)
–0.5
VDVDD + 0.5
V
VI(SPK_OUTxx)
Voltage at speaker output pins
–0.3
32
V
TA
Ambient operating temperature
–25
85
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DVDD referenced digital pins include: ADR/FAULT, LRCLK, SCLK, SCL, SDA, SDIN,PDN
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V(POWER)
Power supply inputs
RSPK
Minimum speaker load
NOM
MAX
UNIT
DVDD
1.62
3.63
PVDD
4.5
26.4
BTL Mode (4.5V≤PVDD≤16V)
3.2
Ω
BTL Mode (16V<PVDD≤24V)
4.8
Ω
PBTL Mode (4.5V≤PVDD≤16V)
1.6
Ω
RSPK
Minimum speaker load
PBLT Mode (16V<PVDD≤24V)
2.4
LOUT
Minimum inductor value in LC filter under short-circuit condition
1
V
Ω
4.7
µH
7.4 Thermal Information
TSSOP (DCP)
38 PINS
THERMAL METRIC (1)
JEDEC
STANDARD
2-LAYER PCB
UNIT
JEDEC
STANDARD
4-LAYER PCB
TAS5806MEVM-4
4-LAYER PCB
RθJA
Junction-to-ambient thermal resistance
N/A
29
23.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
N/A
18.5
N/A
°C/W
RθJB
Junction-to-board thermal resistance
N/A
9.2
N/A
°C/W
ψJT
Junction-to-top characterization parameter
N/A
0.5
1.2
°C/W
ψJB
Junction-to-board characterization parameter
N/A
9.2
8.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
2.3
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Free-air room temperature 25°C ,DVDD=3.3V,1SPW mode withe LC filter, BD mode with Ferrite bead filter (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL I/O
|IIH|
Input logic high current level
for DVDD referenced digital
input pins
VIN(DigIn) = VDVDD
|IIL|
Input logic low current level
for DVDD referenced digital
input pins
VIN(DigIn) = 0 V
VIH(Digin)
Input logic high threshold for
DVDD referenced digital
inputs
VIL(Digin)
Input logic low threshold for
DVDD referenced digital
inputs
VOH(Digin)
Output logic high voltage
level
IOH = 2 mA
VOL(Digin)
Output logic low voltage level
IOH = –2 mA
10
µA
–10
µA
70%
VDVDD
30%
80%
VDVDD
VDVDD
20%
VDVDD
400
pF
I2C CONTROL PORT
CL(I2C)
Allowable load capacitance
for each I2C line
fSCL(fast)
Support SCL frequency
No wait states, fast mode
400
kHz
fSCL(slow)
Support SCL frequency
No wait states, slow mode
100
kHz
SERIAL AUDIO PORT
tDLY
Required LRCLK/FS to SCLK
rising edge delay
DSCLK
Allowable SCLK duty cycle
40%
60%
fS
Supported input sample rates
32
96
fSCLK
Supported SCLK frequencies
32
64
fSCLK
SCLK frequency
5
ns
24.576
kHz
fS
MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
Icc
Quiescent supply current on
DVDD
PDN=2V, DVDD=3.3V, Play mode
Icc
Quiescent supply current on
DVDD
Icc
18
mA
PDN=2V, DVDD=3.3V, Sleep mode
0.75
mA
Quiescent supply current on
DVDD
PDN=2V, DVDD=3.3V, Deep Sleep mode
0.75
mA
Icc
Quiescent supply current on
DVDD
PDN=0V, DVDD=3.3V, Shutdown mode
5.5
µA
Icc
Quiescent supply current on
PVDD
PDN=2V,, VPVDD=13.5V, LC filter=10uH+0.68uF,
Fsw=768kHz, BD Modulation, Play mode,BTL
mode
32.5
mA
Icc
Quiescent supply current on
PVDD
PDN=2V,, VPVDD=13.5V, LC filter=22uH+0.68uF,
Fsw=384kHz, Hybrid Modulation, Play mode,BTL
mode
16.5
mA
Icc
Quiescent supply current on
PVDD
PDN=2V, VPVDD=13.5V, Output Hiz Mode
10.4
mA
Icc
Quiescent supply current on
PVDD
PDN=2V, VPVDD=13.5V, Sleep Mode
7.2
mA
Icc
Quiescent supply current on
PVDD
PDN=2V, VPVDD=13.5V, Deep Sleep Mode
120
µA
Icc
Quiescent supply current on
PVDD
PDN=0V, VPVDD=13.5V, Shutdown Mode
7.2
µA
toff
Turn-off Time
Excluding volume ramp
AV(SPK_AMP)
Programmable Gain
Value represents the "peak voltage" disregarding
clipping due to lower PVDD.
Measured at 0 dB input(1FS)
ΔAV(SPK_AMP)
Amplifier gain error
Gain = 29.5 Vp/FS
fSPK_AMP
6
Switching frequency of the
speaker amplifier
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10
4.95
29.5
ms
V
0.5
dB
384
kHz
768
kHz
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Electrical Characteristics (continued)
Free-air room temperature 25°C ,DVDD=3.3V,1SPW mode withe LC filter, BD mode with Ferrite bead filter (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RDS(on)
Drain-to-source on resistance
of the individual output
FET + Metallization
MOSFETs
OCETHRES
Over-Current Error Threshold
5
A
OVETHRES(PVDD)
PVDD over voltage error
threshold
28
V
UVETHRES(PVDD)
PVDD under voltage error
threshold
4.2
V
OTETHRES
Over temperature error
threshold
160
°C
OTEHystersis
Over temperature error
hysteresis
10
°C
OTWTHRES
Over temperature warning
level
135
°C
180
OUTxx Overcurrent Error Threshold
Read by register 0x73 bit3
mΩ
SPEAKER AMPLIFIER (STEREO BTL)
|VOS|
PO(SPK)
Amplifier offset voltage
Continuous Output power
(per channel)
Measured differentially with zero input data,
programmable gain configured with 29.5 Vp gain,
VPVDD = 12 V, BD Mode
–6.5
6.5
VPVDD = 21V, RSPK = 8 Ω, f = 1 kHz, THD+N =
1%, 1SPW Mode
23
W
VPVDD = 21 V, RSPK = 8 Ω, f = 1 kHz, THD+N =
10%, 1SPW Mode
27.5
W
VPVDD = 18 V, RSPK = 6 Ω, f = 1 kHz, THD+N =
1%, BD Mode
21
W
VPVDD = 18 V, RSPK = 6 Ω, f = 1 kHz, THD+N =
10%, BD Mode
25
W
VPVDD = 12 V, RSPK = 6 Ω, f = 1 kHz THD+N =
1%, BD Mode
9.9
W
VPVDD = 12 V, RSPK = 6 Ω, f = 1 kHz THD+N =
10%, BD Mode
12
W
VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 kHz THD+N =
1%, BD Mode
12
W
VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 kHz THD+N =
10%, BD Mode
15
W
Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz, RSPK =
6 Ω)
VPVDD = 12 V, Fsw=768kHz, LC-filter, BD Mode
0.03%
THD+NSPK
VPVDD = 18 V, Fsw=768kHz, LC-filter, BD Mode
0.03%
ICN(SPK)
Idle channel noise(Aweighted)
VPVDD = 12 V, Fsw=768kHz, LC-filter, Load=6 Ω
37
VPVDD = 18 V, Fsw=768kHz, LC-filter, Load=6 Ω
38
DR
Dynamic range
SNR
mV
µVrms
A-Weighted, -60 dBFS method. VPVDD = 24 V,
SPK_GAIN = 29.5 Vp/FS
106
dB
A-Weighted, referenced to 1% THD+N output
level, VPVDD=24V
111
dB
107.5
dB
72
dB
100
dB
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N output
level, VPVDD=13.5V
PSRR
Power supply rejection ratio
Injected Noise = 1 KHz, 1 Vrms, VPVDD = 12 V,
input audio signal = digital zero
X-talkSPK
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
f = 1 kHz
SPEAKER AMPLIFIER (MONO PBTL)
|VOS|
Amplifier offset voltage
Measured differentially with zero input data,
programmable gain configured with 29.5 Vp gain,
VPVDD = 12 V, BD Mode
–8
8
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Electrical Characteristics (continued)
Free-air room temperature 25°C ,DVDD=3.3V,1SPW mode withe LC filter, BD mode with Ferrite bead filter (unless otherwise
noted)
PARAMETER
PO(SPK)
Continuous Output Power
TEST CONDITIONS
THD+NSPK
DR
SNR
PSRR
8
Dynamic range
Signal-to-noise ratio
Power supply rejection ratio
TYP
MAX
UNIT
15.4
W
VPVDD = 12 V, RSPK = 4 Ω, f = 1kHz, THD+N =
10%, BD Mode
18.5
W
VPVDD = 18V, RSPK = 4 Ω, f = 1kHz, THD+N = 1%,
BD Mode
33.6
W
41
W
VPVDD = 18 V,RSPK = 4 Ω, f = 1kHz, THD+N =
10%, BD Mode
Total harmonic distortion and
noise
(PO = 1 W, f = 1 kHz)
MIN
VPVDD = 12 V, RSPK = 4 Ω, f = 1kHz, THD+N =
1%, BD Mode
VPVDD = 12 V, 4.7uH + 0.68uF filter, RSPK = 4 Ω,
BD Mode
0.06%
VPVDD = 24 V,4.7uH + 0.68uF filter, RSPK = 4 Ω,
1SPW Mode
0.07%
A-Weighted, -60 dBFS method, VPVDD = 24V,
SPK_GAIN = 29.5 Vp/FS
106
dB
A-Weighted, referenced to 1% THD+N output
level, VPVDD=13.5V
107.7
dB
A-Weighted, referenced to 1% THD+N output
level, VPVDD=24V
111
dB
Injected Noise = 1 KHz, 1 Vrms, VPVDD = 19 V,
input audio signal = digital zero
72
dB
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7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Serial Audio Port Timing
fSCLK
SCLK frequency
tSCLK
SCLK period
1.024
40
MHz
ns
tSCLKL
SCLK pulse width, low
16
ns
tSCLKH
SCLK pulse width, high
16
ns
tSL
SCLK rising to LRCK/FS edge
8
ns
tLS
LRCK/FS Edge to SCLK rising edge
8
ns
tSU
Data setup time, before SCLK rising edge
8
ns
tDH
Data hold time, after SCLK rising edge
8
tDFS
Data delay time from SCLK falling edge
ns
15
ns
100
kHz
I2C Bus Timing – Standard
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
4.7
µs
tLOW
Low period of the SCL clock
4.7
µs
tHI
High period of the SCL clock
4
µs
tRS-SU
Setup time for (repeated) START condition
4.7
µs
tS-HD
Hold time for (repeated) START condition
4
µs
tD-SU
Data setup time
250
ns
tD-HD
Data hold time
0
900
ns
tSCL-R
Rise time of SCL signal
20 + 0.1CB
1000
ns
tSCL-R1
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
20 + 0.1CB
1000
ns
tSCL-F
Fall time of SCL signal
20 + 0.1CB
1000
ns
tSDA-R
Rise time of SDA signal
20 + 0.1CB
1000
ns
tSDA-F
Fall time of SDA signal
20 + 0.1CB
1000
tP-SU
Setup time for STOP condition
4
ns
µs
I2C Bus Timing –
Fast
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP and START condition
400
tLOW
tHI
kHz
1.3
µs
Low period of the SCL clock
1.3
µs
High period of the SCL clock
600
ns
tRS-SU
Setup time for (repeated)START condition
600
ns
tRS-HD
Hold time for (repeated)START condition
600
ns
tD-SU
Data setup time
100
tD-HD
Data hold time
tSCL-R
ns
0
900
ns
Rise time of SCL signal
20 + 0.1CB
300
ns
tSCL-R1
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
20 + 0.1CB
300
ns
tSCL-F
Fall time of SCL signal
20 + 0.1CB
300
ns
tSDA-R
Rise time of SDA signal
20 + 0.1CB
300
ns
tSDA-F
Fall time of SDA signal
20 + 0.1CB
300
ns
tP-SU
Setup time for STOP condition
tSP
Pulse width of spike suppressed
600
ns
50
ns
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7.7 Typical Characteristics
7.7.1 Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5806MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM Modulation mode set to 1 SPW mode
with Class D Bandwidth = 120 kHz for 576 kHz Fsw and Class D Bandwidth = 175 kHz for 768 kHz Fsw (Listed
in Register 0x53) unless otherwise noted.
10
10
5 PVcc=5V
TA=25qC
2 R L=4:
1
5 PVcc=7.4V
TA=25qC
2 R L=4:
1
P O=0.5W
P O =1W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 5 V
FSW = 576 kHz
1k
Frequency (Hz)
4.7uH+0.68uF
1SPW Modulation
10k
0.001
20
20k
PVDD = 7.4 V
FSW = 576 kHz
Load=4Ω
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
D003
D101
D004
D002
Load = 4 Ω
10
5 PVcc=12V
TA=25qC
2 R L=4:
1
5 PVcc=12V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
1k
Frequency (Hz)
Figure 2. THD+N vs Frequency-BTL
10
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 12 V
FSW = 768 kHz
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
0.001
20
20k
100
D002
D109
Load= 4 Ω
PVDD = 12 V
FSW = 768 kHz
Figure 3. THD+N vs Frequency-BTL
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
D002
D103
Load = 6 Ω
Figure 4. THD+N vs Frequency-BTL
10
10
5 PVcc=18V
TA=25qC
2 R L=6:
1
5 PVcc=24V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
P O=5W
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
0.5
THD+N(%)
100
D003
D102
D004
D002
Figure 1. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 18 V
FSW = 768 kHz
1k
Frequency (Hz)
10 µH + 0.68 µF
1 SPW Modulation
10k
20k
0.001
20
100
D002
D104
Load = 6 Ω
PVDD = 24 V
FSW = 768 kHz
Figure 5. THD+N vs Frequency-BTL
10
P O=0.5W
P O =1W
P O=2.5W
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1k
Frequency (Hz)
10 µH + 0.68 µF
1 SPW Modulation
10k
20k
D002
D105
Load = 6 Ω
Figure 6. THD+N vs Frequency-BTL
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SLASEP9 – MAY 2019
Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (continued)
10
10
5 PVcc=12V
TA=25qC
2 R L=8:
1
5 PVcc=18V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 12 V
FSW = 768 kHz
1k
Frequency (Hz)
10k
0.001
20
20k
4.7 µH + 0.68 µF
1 SPW Modulation
Load = 8 Ω
PVDD = 18 V
FSW = 768 kHz
1k
Frequency (Hz)
10 µH + 0.68 µF
1 SPW Modulation
10k
20k
D002
D107
Load = 8 Ω
Figure 8. THD+N vs Frequency-BTL
10
10
5 PVcc=24V
TA=25qC
2 R L=8:
1
5 PVcc=19V
TA=25qC
2 R L=6:
1
P O=1W
P O =2.5W
P O=5W
BD Mode
1SPW Mode
Hybrid Mode
0.5
THD+N(%)
0.5
THD+N(%)
100
D002
D106
Figure 7. THD+N vs Frequency-BTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 24 V
FSW = 768 kHz
1k
Frequency (Hz)
10k
0.001
20
20k
100
1k
Frequency (Hz)
D002
D108
10 µH + 0.68 µF
1 SPW Modulation
Load = 8 Ω
PVDD = 19 V
FSW = 384 kHz
10 µH + 0.68 µF
Hybrid/BD, 1 SPW
Modulation
10k
20k
D002
D110
PO= 5 W
Load = 6 Ω
Figure 10. THD+N vs Frequency-BTL
Figure 9. THD+N vs Frequency-BTL
10
10
5 PV CC =5V
TA=25qC
2 R L=4:
1
5 PV CC =12V
TA=25qC
2 R L=4:
1
0.5
THD+N (%)
0.5
THD+N (%)
P O=1W
P O =2.5W
P O=5W
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.001
0.01
0.002
0.1
1
Output Power (W)
PVDD = 5 V
FSW = 768 kHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
4.7 µH + 0.68 µF
1 SPW Modulation
10
0.001
0.01
D007
D112
Load = 4 Ω
PVDD = 12 V
FSW = 768 kHz
Figure 11. THD+N vs Output Power-BTL
0.1
1
Output Power (W)
4.7 µH + 0.68 µF
1 SPW Modulation
10
D007
D113
Load = 4 Ω
Figure 12. THD+N vs Output Power-BTL
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Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (continued)
10
10
5 PV CC =12V
TA=25qC
2 R L=6:
1
5 PV CC =18V
TA=25qC
2 R L=6:
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.001
0.01
0.002
0.1
PVDD = 12 V
FSW = 768 kHz
1
Output Power (W)
4.7 µH + 0.68 µF
1 SPW Modulation
0.001
0.01
10
Load = 6 Ω
PVDD = 18 V
FSW = 768 kHz
10
20
D007
D115
10 µH + 0.68 µF
1SPW Modulation
Load = 6 Ω
10
5 PV CC =24V
TA=25qC
2 R L=6:
1
5 PV CC =12V
TA=25qC
2 R L=8:
1
0.5
THD+N (%)
0.5
THD+N (%)
1
Output Power (W)
Figure 14. THD+N vs Output Power-BTL
10
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.001
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.1
PVDD = 24 V
FSW = 768 kHz
1
Output Power (W)
10 µH + 0.68 µF
1 SPW Modulation
10
0.001
0.01
20
0.1
Load = 6 Ω
1
10
Output Power (W)
D007
D116
PVDD = 12 V
FSW = 768 kHz
Figure 15. THD+N vs Output Power-BTL
10 µH + 0.68 µF
1 SPW Modulation
D007
D117
Load = 8 Ω
Figure 16. THD+N vs Output Power-BTL
10
10
5 PV CC =18V
TA=25qC
2 R L=8:
1
5 PV CC =24V
TA=25qC
2 R L=8:
1
0.5
THD+N (%)
0.5
THD+N (%)
0.1
D007
D114
Figure 13. THD+N vs Output Power-BTL
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.001
0.01
PVDD = 18 V
FSW = 768 kHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.002
0.1
1
Output Power (W)
10 µH + 0.68 µF
1 SPW Modulation
10
0.001
0.01
20
D004
D118
D010
D007
Load = 8 Ω
PVDD = 24 V
FSW = 768 kHz
Figure 17. THD+N vs Output Power-BTL
12
f= 20Hz
f= 1kHz
f= 10KHz
0.005
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0.1
1
Output Power (W)
10 µH + 0.68 µF
1 SPW Modulation
10
20
D007
D119
Load = 8 Ω
Figure 18. THD+N vs Output Power-BTL
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SLASEP9 – MAY 2019
Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (continued)
30
45
THD+N=1%, R L=4:
THD+N=10%, R L=4:
25
THD+N=1%, R L=6:
THD+N=10%, R L=6:
40
Output Power (W)
Output Power (W)
35
20
15
10
30
25
20
15
10
5
BTL Mode
TA=25qC
0
4.5
6.5
8.5
10.5
12.5
Supply Voltage (V)
14.5
BTL Mode
TA=25qC
5
0
4.5
16
6.5
8.5
D014
D120
D037
Dashed lines represent thermally limited region for continuous
output power
PVDD = 4.5V~16V
4.7 µH + 0.68 µF
FSW = 768 kHz
1 SPW Modulation
Load = 4 Ω
10.5 12.5 14.5 16.5 18.5 20.5 22.5 24
Supply Voltage (V)
D014
D121
D037
Dashed lines represent thermally limited region for continuous
output power
PVDD = 4.5V~24V
10 µH + 0.68 µF
FSW = 768 kHz
1 SPW Modulation
Load = 6 Ω
Figure 19. Output Power vs Supply Voltage
Figure 20. Output Power vs Supply Voltage
100
40
THD+N=1%, R L=8:
THD+N=10%, R L=8:
35
90
80
Power Efficiency (%)
Output Power (W)
30
25
20
15
10
0
4.5
6.5
8.5
10.5 12.5 14.5 16.5 18.5 20.5 22.5 24
Supply Voltage (V)
D014
D122
D037
Dashed lines represent thermally limited region for continuous
output power
PVDD = 4. 5 V ~ 24 V
10 µH + 0.68 µF
FSW = 768 kHz
1 SPW Modulation
Load = 8 Ω
60
50
40
30
20 TA=25qC
10 R L=4:
BTL Mode
0
0
BTL Mode
TA=25qC
5
70
90
80
80
Power Efficiency (%)
Power Efficiency (%)
100
40
30
20 TA=25qC
10 R L=6:
BTL Mode
0
0
5
10
15
20
25
30
Output Power (W)
35
PVDD = 7.4 V, 12 V, 18 V, 24 V
FSW = 768 kHz
1 SPW Modulation
PV CC
PV CC
PV CC
PV CC
= 7.4V
= 12 V
= 18 V
= 24 V
40
45
50
D024
D123
4.7 µH + 0.68 µF
Load = 4 Ω
70
60
50
40
30
20 TA=25qC
10 R L=8:
BTL Mode
0
0
5
10
D016
900
10 µH + 0.68 µF
Load = 6 Ω
30
Figure 22. Efficiency vs Supply Voltage
90
50
20
PVDD = 4.5 V, 7.4 V, 12 V
FSW = 768 kHz
1 SPW Modulation
100
60
10
Output Power (W)
Figure 21. Output Power vs Supply Voltage
70
PV CC = 7.4V
PV CC = 12 V
PV CC = 4.5V
15
20
25
30
Output Power (W)
35
PVDD = 7.4 V, 12 V, 18 V, 24 V
FSW = 768 kHz
1 SPW Modulation
Figure 23. Efficiency vs Supply Voltage
PV CC
PV CC
PV CC
PV CC
= 7.4V
= 12 V
= 18 V
= 24 V
40
45
50
D016
901
10 µH + 0.68 µF
Load = 8 Ω
Figure 24. Efficiency vs Supply Voltage
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Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (continued)
80
0
-20
PVDD=12V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
60
Crosstalk (dB)
Idle Channel Noise (PVrms)
Fsw=768kHz, Channel A
Fsw=768kHz, Channel B
40
-40
-60
-80
20
-100
0
5
10
15
18
Supply Voltage (V)
PVDD = 7.4 V ~ 24 V
FSW = 768 kHz
1SPW Modulation
-120
20
20
100
D126
D030
D007
10 µH + 0.68 µF
Load = 8 Ω
PVDD = 12 V
FSW = 768 kHz
Figure 25. Idle Channel Noise vs Supply Voltage
Crosstalk (dB)
Crosstalk (dB)
-20
-60
-80
-100
100
PVDD = 18 V
FSW = 768 kHz
PVDD=24V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-40
-60
-80
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
-120
20
20k
100
D129
D001
D003
PO = 1 W
Load = 6 Ω
PVDD = 24 V
FSW = 768 kHz
Figure 27. Crosstalk
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
D130
D001
D003
PO = 1 W
Load = 6 Ω
Figure 28. Crosstalk
0
0
PVDD=12V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-20
-40
Crosstalk (dB)
Crosstalk (dB)
D128
D001
D003
PO = 1 W
Load = 6 Ω
-100
-120
20
-60
-80
-100
-120
20
PVDD = 12 V
FSW = 768 kHz
PVDD=18V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-40
-60
-80
-100
100
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
-120
20
D131
D001
D003
PO = 1 W
Load = 8 Ω
PVDD = 18 V
FSW = 768 kHz
Figure 29. Crosstalk
14
20k
0
PVDD=18V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-40
-20
4.7 µH + 0.68 µF
1 SPW Modulation
10k
Figure 26. Crosstalk
0
-20
1k
Frequency (Hz)
100
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
D132
D001
D003
PO = 1 W
Load = 8 Ω
Figure 30. Crosstalk
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Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (continued)
0
Crosstalk (dB)
-20
PVDD=24V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-40
-60
-80
-100
-120
20
PVDD = 24V
FSW = 768 kHz
100
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
D133
D001
D003
PO = 1 W
Load = 8 Ω
Figure 31. Crosstalk
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7.7.2 Bridge Tied Load (BTL) Configuration Curves
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS806MDEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 384 kHz, with Class D
Bandwidth = 80 kHz (Listed in Register 0x53), Spread Spectrum Enable, Ferrite bead + Capacitor as the output
filter, BD Modulation, unless otherwise noted.
10
10
5 PVcc=12V
TA=25qC
2 R L=6:
1
5 PVcc=12V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 12 V
FSW = 384 kHz
1k
Frequency (Hz)
10k
0.001
20
20k
BD Modulation
Load = 6 Ω
Spread Spectrum Enable
10k
20k
D002
D136
Figure 33. THD+N vs Frequency
10
5 PV CC =7.4V
TA=25qC
2 R L=4:
1
THD+N=1%, R L=8:
THD+N=10%, R L=8:
15
0.5
THD+N (%)
Output Power (W)
1k
Frequency (Hz)
BD Modulation
Load = 8 Ω
Spread Spectrum Enable
PVDD = 12 V
FSW = 384 kHz
20
10
0.2
0.1
0.05
0.02
0.01
5
0.005
BTL Mode
TA=25qC
0
4.5
6.5
PVDD = 4.5V-16 V
FSW = 384 kHz
8.5
10.5
12.5
Supply Voltage (V)
14.5
0.002
BD Modulation
Load = 8 Ω
Spread Spectrum Enable
1
10
Output Power (W)
D004
D138
D010
D007
BD Modulation
Load = 4 Ω
Spread Spectrum Enable
PVDD = 7.4 V
FSW = 384 kHz
Figure 35. THD+N vs Output Power
10
5 PV CC =12V
TA=25qC
2 R L=8:
5 PV CC =12V
TA=25qC
2 R L=6:
1
1
0.5
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.002
0.1
D014
D137
D037
10
0.005
f= 20Hz
f= 1kHz
f= 10KHz
0.001
0.01
16
Figure 34. Output Power vs Supply Voltage
THD+N (%)
100
D002
D135
Figure 32. THD+N vs Frequency
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.001
0.01
0.005
0.002
0.1
PVDD = 12 V
FSW = 384 kHz
1
Output Power (W)
f= 20Hz
f= 10kHz
f= 1KHz
0.001
0.01
10
0.1
D007
D139
BD Modulation
Load = 6 Ω
Spread Spectrum Enable
PVDD = 12 V
FSW = 384 kHz
Figure 36. THD+N vs Output Power
16
P O=1W
P O =2.5W
P O=5W
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1
Output Power (W)
10
D007
D140
BD Modulation
Load = 8 Ω
Spread Spectrum Enable
Figure 37. THD+N vs Output Power
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Bridge Tied Load (BTL) Configuration Curves (continued)
0
0
PVDD=12V, Ferrite Bead + Capacitor
Ch A to Ch B
Ch B to Ch A
PVDD=12V, Ferrite bead + Capacitor
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
Crosstalk (dB)
Crosstalk (dB)
-20
-60
-80
-100
-40
-60
-80
-100
-120
20
100
PVDD = 12 V
FSW = 384 kHz
1k
Frequency (Hz)
10k
-120
20
20k
100
D141
D001
D003
Load = 6 Ω
PO = 1 W
BD Modulation
Spread Spectrum
Enable
PVDD = 12 V
FSW = 384 kHz
BD Modulation
Spread Spectrum
Enable
10k
20k
D142
D001
D003
Load = 8 Ω
PO = 1 W
Figure 39. Crosstalk
100
100
90
90
80
80
Power Efficiency (%)
Power Efficiency (%)
Figure 38. Crosstalk
1k
Frequency (Hz)
70
60
50
40
30
20
70
60
50
40
30
20
TA=25qC
R L=4:
10
PV CC = 5V
PV CC = 7.4V
TA=25qC
R L=8:
10
0
PV CC = 7.4V
PV CC = 12 V
0
0
10
Output Power (W)
PVDD = 5V/7.4V
FSW = 384 kHz
0
10
Output Power (W)
D024
D143
BD Modulation
Load = 4 Ω
Spread Spectrum Enable
PVDD = 7.4 V, 12
V
FSW = 384 kHz
BD Modulation
20
D024
D144
Load = 8 Ω
Spread Spectrum Enable
Figure 40. Efficiency vs Output Power
Figure 41. Efficiency vs Output Power
100
90
Power Efficiency (%)
80
70
60
50
40
30
20
TA=25qC
R L=6:
10
PV CC = 7.4V
PV CC = 12 V
0
0
10
20
30
Output Power (W)
PVDD = 7.4 V,12 V
FSW = 384 kHz
BD Modulation
D024
D145
Load = 6 Ω
Spread Spectrum Enable
Figure 42. Efficiency vs Output Power
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7.7.3 Parallel Bridge Tied Load (PBTL) Configuration
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5806MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 576 kHz, the LC filter
used was 4.7 μH / 0.68 μF, 1SPW modulation with Class D Bandwidth = 120 kHz (Listed in Register 0x53)
unless otherwise noted.
10
10
5 PVcc=7.4V
TA=25qC
2 R L=4:
1
5 PVcc=12V
TA=25qC
2 R L=4:
1
P O=1W
PO=2.5W
PO=4W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 7.4 V
FSW = 576 kHz
1k
Frequency (Hz)
10k
0.001
20
20k
1 SPW Modulation
Load = 4 Ω
4.7 µH + 0.68 µF
PVDD = 12 V
FSW = 576 kHz
D002
D147
1 SPW Modulation
Load = 4 Ω
4.7 µH + 0.68 µF
0.5
THD+N (%)
THD+N(%)
20k
5 PV CC =5V
TA=25qC
2 R L=2:
1
P O=1W
PO=2.5W
PO=5W
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 24 V
FSW = 576 kHz
1k
Frequency (Hz)
10k
f= 20Hz
f= 10kHz
f= 1KHz
0.001
0.01
20k
0.1
1 SPW Modulation
Load = 4 Ω
4.7 µH + 0.68 µF
1
10
Output Power (W)
D002
D148
PVDD = 5 V
FSW = 576 kHz
Figure 45. THD+N vs Frequency
1 SPW Modulation
Load = 2 Ω
D007
D149
4.7 µH + 0.68 µF
Figure 46. THD+N vs Output Power
10
10
5 PV CC =5V
TA=25qC
2 R L=4:
1
5 PV CC =12V
TA=25qC
2 R L=4:
1
0.5
THD+N (%)
0.5
THD+N (%)
10k
10
5 PVcc=24V
TA=25qC
2 R L=4:
1
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 10kHz
f= 1KHz
0.001
0.01
0.005
0.002
0.1
1
10
Output Power (W)
PVDD = 5 V
FSW = 576 kHz
1 SPW Modulation
Load = 4 Ω
f= 20Hz
f= 10kHz
f= 1KHz
0.001
0.01
0.1
D007
D150
4.7 µH + 0.68 µF
PVDD = 12 V
FSW = 576 kHz
Figure 47. THD+N vs Output Power
18
1k
Frequency (Hz)
Figure 44. THD+N vs Frequency
10
0.002
100
D002
D146
Figure 43. THD+N vs Frequency
0.005
P O=1W
P O =2.5W
P O=5W
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Output Power (W)
1 SPW Modulation
Load = 4 Ω
10
20
D007
D151
4.7 µH + 0.68 µF
Figure 48. THD+N vs Output Power
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Parallel Bridge Tied Load (PBTL) Configuration (continued)
10
10
5 PV CC =18V
TA=25qC
2 R L=4:
1
5 PV CC =24V
TA=25qC
2 R L=4:
1
0.5
THD+N (%)
THD+N (%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 10kHz
f= 1KHz
0.005
0.002
0.001
0.01
0.1
PVDD = 18 V
FSW = 576 kHz
0.002
1
Output Power (W)
1 SPW Modulation
Load = 4 Ω
10
0.001
0.01
20
0.1
1
Output Power (W)
D007
D152
4.7 µH + 0.68 µF
PVDD = 24 V
FSW = 576 kHz
Figure 49. THD+N vs Output Power
10
20
D007
D153
1 SPW Modulation
Load = 4 Ω
4.7 µH + 0.68 µF
Figure 50. THD+N vs Output Power
80
100
Fsw=768kHz, PBTL Mode
90
80
60
Power Efficiency (%)
Idle Channel Noise (PVrms)
f= 20Hz
f= 10kHz
f= 1KHz
0.005
40
20
PVDD = 4.5~24V
FSW = 576 kHz
10
15
18
Supply Voltage (V)
1 SPW Modulation
Load = 4 Ω
60
50
40
30
20 TA=25qC
10 R L=4:
PBTL Mode
0
0
5
10 15
0
5
70
20
D155
D030
D007
4.7 µH + 0.68 µF
PV CC
PV CC
PV CC
PV CC
PV CC
20
25 30 35 40
Output Power (W)
PVDD = 5 V, 7.4 V, 12 V, 18 V, 24 V
FSW = 576 kHz
Load = 4 Ω
Figure 51. Idle Channel Noise vs Supply Voltage
45
= 5V
= 7.4 V
= 12 V
= 18 V
= 24 V
50
D016
902
1 SPW Modulation
4.7 µH + 0.68 µF
Figure 52. Efficiency vs Output Power
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8 Parametric Measurement Information
LRCK/FS
(Input)
0.5 × DVDD
tSCLKH
tSCLKL
tLS
SCLK
(Input)
0.5 × DVDD
tSCLK
tSL
DATA
(Input)
0.5 × DVDD
tSU
tDH
tDFS
DATA
(Output)
0.5 × DVDD
Figure 53. Serial Audio Port Timing in Slave Mode
Repeated
START
START
tD-SU
SDA
STOP
tD-HD
tSDA-F
tSDA-R
tP-SU
tBUF.
tSCL-R.
tRS-HD
tSP
tLOW.
SCL
tHI.
tRS-SU
tS-HD.
tSCL-F.
Figure 54. I2C Communication Port Timing Diagram
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9 Detailed Description
9.1 Overview
The TAS5806M device integrates 4 main building blocks together into a single cohesive device that maximizes
sound quality, flexibility, and ease of use. These 4 main building blocks are listed as follows:
1. A stereo audio DAC.
2. An Audio DSP subsystem.
3. A flexible close-loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
4. An I2C control port for communication with the device
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, PVDD, is required to provide power to the output stage of the audio
amplifier. One internal LDO converts PVDD to 5 V for internal GVDD and AVDD, another LDO converts DVDD to
1.5V for internal digital core.
9.2 Functional Block Diagram
4.5-26.4V
3.3/1.8V
DVDD
VR_DIG
AVDD
LDO 1.5V
PVDD1/2/3/4
LDO 5V
BST_A+
Closed-Loop Feedback
IO
IO
ADR/ FAULT
PDN
SDIN
OUT_A+
I2S/TDM
OUT_A-
Audio DSP
Subsystem
Digital to PWM
Conversion
SCLK
LRCLK
SDOUT
PDM
Modulator
H Bridge
&
Gate Driver
&
OC/DC Protect
BST_A-
BST_BOUT_BBST_B+
SCL
SDA
OUT_B+
PLL & OSC
Closed-Loop Feedback
DGND
AGND
PGND 1/2
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9.3 Feature Description
9.3.1 Power Supplies
To facilitate system design, TAS5806M needs only a 3.3-V or 1.8-V supply in addition to the (typical) 12 V or 24
V power-stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry
and internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to
filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and
damage to the device. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive,
is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good
electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical,
independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive
voltages (AVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic
capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the
power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the
gate-drive regulator output pin (AVDD) and the bootstrap pin. When the power-stage output is high, the bootstrap
capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the highside gate driver.
9.3.2 Device Clocking
The TAS5806M devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
Audio In
LRCLK/FS
DSPCLK
Serial Audio
Interface (Input)
DSP
(Including
interpolator)
OSRCLK
DACCLK
Delta Sigma
Modulator
DAC
Figure 55. Audio Flow with Respective Clocks
Figure 55 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
• SCLK (Bit Clock)
• LRCLK/FS (Left/Right Word Clock and Frame Sync)
• SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP
and the DAC clock.
The TAS5806M device has an audio sampling rate detection circuit that automatically senses which frequency
the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96
kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
9.3.3 Serial Audio Port – Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the TAS5806M device on the rising edge of SCLK. The LRCK/FS pin is the
serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
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Feature Description (continued)
Table 1. Audio Data Formats, Bit Depths and Clock Rates
DATA BITS
MAXIMUM LRCLK/FS FREQUENCY
(kHz)
SCLK RATE (fS)
I S/LJ/RJ
32, 24, 20, 16
32 to 96
64, 32
32
128
TDM
32, 24, 20, 16
44.1,48
128,256,512
96
128,256
FORMAT
2
Before DSP register initialize with I2C during the startup , TAS5806M requires stable I2S ready. When Clock halt,
non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register 113 (Register
Address 0x71).
9.3.4 Clock Halt Auto-recovery
As some of host processor will Halt the I2S clock when there is no audio playing. When Clock halt, the device
puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio
clocks recovery, the device automatically returns to the previous state.
9.3.5 Sample Rate on the Fly Change
TAS5806M supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or
96kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 100us before changing to the
new sample rate.
9.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (P0-R51-D[5:4]). If the high width of LRCK/FS in
TDM/DSP mode is less than 8 cycles of SCK, the register (P0-R51-D[3:2]) should set to 01. All formats require
binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word
length and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 56
through Figure 60. The word length are selected via Register (P0-R51-D[1:0]). The offsets of data are selected
via Register (P0-R51-D[7]) and Register (P0-R52-D[7:0]). Default setting is I2S and 24 bit word length.
1 tS
LRCLK/FS
Right-channel
Left-channel
SCLK
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1 2
15 16
MSB
1 2
LSB
15 16
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1 2
1 2
23 24
MSB
LSB
23 24
MSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1 2
31 32 1 2
MSB
LSB
31 32
MSB
LSB
Figure 56. Left Justified Audio Data Format
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1 tS
LRCLK/FS
Right-channel
Left-channel
SCLK
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1 2
15 16
MSB
1 2
LSB
15 16
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1 2
1 2
23 24
MSB
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1 2
31 32 1 2
MSB
31 32
MSB
LSB
LSB
2
I S Data Format; L-channel = LOW, R-channel = HIGH
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 57. I2S Audio Data Format
1 tS
LRCLK/FS
Right-channel
Left-channel
SCLK
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1 2
15 16
MSB
1 2
LSB
15 16
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1 2
1 2
23 24
MSB
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1 2
31 32 1 2
MSB
LSB
31 32
MSB
LSB
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 58. Right Justified Audio Data Format
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1 /fS .
LRCK/FS
«
SCLK
«
«
«
«
Audio data word = 16-bit, Offset = 0
DATA
1
«
2
15 16 1
«
2
Data Slot 1
LSB
MSB
15 16
1
Data Slot 2
LSB
MSB
Audio data word = 24-bit, Offset = 0
- ,
«
1 2
DATA
23 24 1
«
2
23 24
1
Data Slot 1
LSB
MSB
LSB
MSB
Audio data word = 32-bit, Offset = 0
DATA
1
«
2
31 32 1
«
2
LSB
MSB
1
31 32
LSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 59. TDM 1 Audio Data Format
1 /fS .
LRCK/FS
OFFSET = 1
«
SCLK
«
«
«
«
Audio data word = 16-bit, Offset = 1
DATA
1
«
2
MSB
15 16 1
Data Slot 1
LSB
MSB
«
2
15 16
1
Data Slot 2
LSB
Audio data word = 24-bit, Offset = 1
DATA
1
«
2
23 24 1
Data Slot 1
23 24
1
Data Slot 2
LSB
MSB
«
2
LSB
MSB
Audio data word = 32-bit, Offset = 1
DATA
1
«
2
31 32 1
Data Slot 1
2
«
1
Data Slot 2
LSB
MSB
31 32
LSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 60. TDM 2 Audio Data Format
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9.3.7 Digital Audio Processing
TAS5806M DSP has a flexible process flows for different applications, refer to application note, TAS5805M
Process Flows for details.
9.3.8 Class D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker
amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and
increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D
amplifier section of the device.
9.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As seen
in Figure 61, the audio path of the TAS5806M consists of a digital audio input port, a digital audio path, a digital
to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds the
output information back into the DPC block to correct for distortion sensed on the output pins. The total amplifier
gain is comprised of digital gain in the digital audio path and the analog gain from the input of the analog
modulator to the output of the speaker amplifier power stage.
Analog
Analog Gain
Gain
Digital
Digital Gain
Gain
Closed
Closed Loop
Loop Class
Class DD Amplifier
Amplifier
Full
Full Bridge
Bridge Power
Power
Stage
Stage
AA
Gate
Gate
Drivers
Drivers
Serial
Serial
Audio
Audio In
In
Serial
Serial
Audio
Audio
Port
Port
Audio
Audio Processing
Processing
(Flexible
(FlexibleAudio
AudioProcess
ProcessFlows)
Flows)
Full
Full Bridge
Bridge Power
Power
Stage
Stage
BB
SCL
SDA
SPK_OUTASPK_OUTA-
Digital
Digital to
to PWM
PWM
Conversion
Conversion
Gate
Gate
Drivers
Drivers
I2C
I2C Interface
Interface
SPK_OUTA+
SPK_OUTA+
Control
Control Register
Register
SPK_OUTB+
SPK_OUTB+
SPK_OUTBSPK_OUTB-
Closed
Closed Loop
Loop Class
Class DD Amplifier
Amplifier
Copyright
Copyright©
©2017,
2017,Texas
TexasInstruments
InstrumentsIncorporated
Incorporated
Figure 61. Speaker Amplifier Gain
As shown in Figure 61, the first gain stage for the speaker amplifier is present in the digital audio path. It consists
of the volume control and the digital boost block. The volume control is set to 0dB by default, it does not change.
For all settings of the register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These gain settings
ensure that the output signal is not clipping at different PVDD levels. 0 dBFS output is 29.5-V peak output
voltage
Table 2. Analog Gain Setting
AGAIN <4:0>
26
GAIN (dBFS)
AMPLIFIER OUTPUT PEAK VOLTAGE (V)
00000
0
29.5
00001
-0.5
27.85
…….
……..
…….
11111
-15.5
4.95
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9.4 Device Functional Modes
9.4.1 Software Control
The TAS5806M device is configured via an I2 C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections.
9.4.2 Speaker Amplifier Operating Modes
The TAS5806M device can be used in two different amplifier configurations:
1. BTL Mode
2. PBTL Mode
9.4.2.1 BTL Mode
The familiar BTL mode of operation uses the TAS5806M device to amplify two independent signals, which
represent the left and right portions of a stereo signal. The amplified left signal is presented on differential output
pair shown as OUT_A+ and OUT_A-, the amplified right signal is presented on differential output pair shown as
OUT_B+ and OUT_B-.
9.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
TAS5806M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive
inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the TAS5806M device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
9.4.3 Low EMI Modes
TAS5806M employs several modes to minimize EMI during playing audio, and they can be used based on
different applications.
9.4.3.1 Minimize EMI with Spread Spectrum
This device supports spread spectrum with triangle mode, Spread spectrum is used to minimize the EMI noise.
User need configure register SS_CTRL0 (0x6B) to Enable triangle mode and enable spread spectrum, and
select spread spectrum frequency and range with SS_CTRL1 (0x6C). For 384kHz FSW which configured by
DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in Table 3.
Table 3. Spread Spectrum Setting
SS_TRI_CTR
L[3:0]
0
1
Triangle Freq
Spread
Spectrum
Range
2
3
4
5
24k
5%
10%
6
7
20%
25%
48k
20%
25%
5%
10%
User Application example-Central Switching Frequency is 384kHz, Triangle Frequency is 24kHz, take I2C device
address 0x58 as an example:
w 58 6b 03 //Enable Spread Spectrum.
w 58 6c 03 //SS_TRI_CTRL[3:0]0011, Triangle Frequency = 24 kHz, Spread Spectrum Range should be 25%
(336 kHz ~ 432 kHz).
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9.4.3.2 Channel to Channel Phase shift
This device support channel to channel 180 degree PWM phase shift to minimize the EMI. Bit 0 of Register 0x53
can be used to disable or enable the phase shift.
9.4.3.3 Multi-Devices PWM Phase Synchronization
This device support up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 devices, user can select phase 0/1/2/3 for each device by register PHASE_CTRL (0x6A),
which means there is a 45 degree phase shift between each device to minimize the EMI.
Recommend to do the Phase Synchronization with I2S clock during the Startup Phase.
1. Halt I2S clock.
2. Configure each device phase selection and enable the phase synchronization. For example: Register 0x6A =
0x03 for device 0; Register 0x6A = 0x07 for device 1; Register 0x6A = 0x0B for device 2; Register 0x6A =
0x0F for device 3. There should be a 45 degree PWM phase shift between each device to minimize the EMI.
3. Configure each device into HIZ mode.
4. Provide I2S to each device. Phase synchronization for all 4 devices will be automatically done by internal
sequence.
5. Initialize the DSP code. (This step can be skipped if only need to do the PWM Phase Synchronization).
6. Device to Device PWM phase shift should be fixed with 45 degree.
9.4.4 Thermal Foldback
The Thermal Foldback (TFB), is designed to protect TAS5806M from excessive die temperature increases, in
case the device operates beyond the recommended temperature/power limit, or with a weaker thermal system
design than recommended. It allows the TAS5806M to play as loud as possible without triggering unexpected
thermal shutdown. When the die temperature triggers the over-temperature warning (OTW) level (135C typ), an
internal AGL (Automatic Gain Limiter) will reduce the digital gain automatically. Once the die temperature drops
below the OTW, the device digital gain gradually returns to the former setting. Both the attenuation gain and
adjustable rate are programmable. The TFB gain regulation speed (attack rate and release rate) settings are the
same as a regular AGL, which is also configurable with TAS5806M App in PurePathTM Console3.
9.4.5 Device State Control
TAS5806M has 5 states with different power dissipation which listed in the Electrical Characteristics Table.
• Shutdown Mode. With PDN pin pull down to GND. All internal LDOs (1.5V for digital core, 5V for analog) are
disabled, all registers will be cleared to default value.
NOTE
Exit from Shutdown Mode and re-enter into Play mode, need reload all register
configurations (which generated by PurePath Console3) again.
•
•
•
•
28
Deep Sleep Mode. Deep Sleep Mode. Register 0x03h -D[1:0]=00, device stays in Deep Sleep Mode. In this
mode, I2C block and 1.5V LDO for digital core still working, but internal 5V LDO (For AVDD and MOSFET
gate driver) is disabled for low power dissipation. This mode can be used to extend the battery life in some
portable speaker applications. If the host processor stops playing audio for a long time, TAS5806M can be set
to Deep Sleep Mode to minimize power dissipation until host processor starts playing audio again. Unlike the
Shutdown Mode (Pulling PDN Low), entering or exiting Deep Sleep Mode, the DSP keeps active.
Sleep Mode. Register 0x03h -D[1:0]=01, device stays in Sleep Mode. In this mode, I2C block, Digital core,
DSP Memory , 5V Analog LDO are stilling working. Unlike the Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP is kept active. Exit from this mode and re-enter into play mode, only need to set Register
0x03h -D[1:0]=11.
Output Hiz Mode. Register 0x03h -D[1:0]=10, device stays in Hiz Mode. In this mode, only output driver is set
to be Hi-Z state, all other block operate normally. Exit from this mode and re-enter into play mode, only need
to set Register 0x03h -D[1:0]=11.
Play Mode. Register 0x03h -D[1:0]=11, device stays in Play Mode.
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9.4.6 Device Modulation
TAS5806M has 3 modulation schemes: BD Modulation, 1SPW modulation and Hybrid modulation. Select
modulation schemes for TAS5806M with Register 0x02 [1:0]-DAMP_MOD.
9.4.6.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
OUTP- OUTN
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP - OUTN
0V
- PVCC
Speaker
Current
0A
Figure 62. BD Mode Modulation
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9.4.6.2 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In Low Idle Current mode the
outputs operate at ~17% modulation during idle conditions. When an audio signal is applied one output will
decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio
modulation takes place through the rising output. The result is that only one output is switching during a majority
of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses.
OUTP
OUTN
OUTP -OUTN
No Output
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP -OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP -OUTN
0V
- PVCC
Speaker
Current
0A
Figure 63. 1SPW Mode Modulation
9.4.6.3 Hybrid Modulation
Hybrid Modulation is designed for minimized power loss without compromising the THD+N performance, and is
optimized for battery-powered applications. With Hybrid modulation, TAS5806MD will detect the input signal level
and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and
maintains the same audio performance level as the Hybrid Modulation.
30
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NOTE
To use the Hybrid Modulation, users need to enter the system's PVDD value on the
TAS5806M PPC3 App.
9.5 Programming and Control
I2 C Serial Communication Bus
9.5.1
The device has a bidirectional serial control interface that is compatible with the Inter IC ( I2)C bus protocol and
supports 100 and 400-kHz data transfer rates for random and sequential write and read operations as a slave
device. Because the TAS5806M register map and DSP memory spans multi pages, the user should change from
page to page before writing individual register or DSP memory. Changing from page to page is accomplished via
register 0 on each page. This register value selects the page address, from 0 to 255.
9.5.2 Slave Address
The TAS5806M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are
factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be userdefined by ADR/FAULT pin in Table 4.
Table 4. I2 C Slave Address Configuration
ADR/FAULT PIN
Configuration
MSBs
User Define
LSB
4.7k Ω to DVDD
0
1
0
1
1
0
0
R/W
15kΩ to DVDD
0
1
0
1
1
0
1
R/W
47kΩ to DVDD
0
1
0
1
1
1
0
R/W
120kΩ to DVDD
0
1
0
1
1
1
1
R/W
9.5.2.1 Random Write
As shown in Figure 64, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4 A3
A2
A1
A0 R/W ACK A7
I2C Device Address
and R/W Bit
Acknowledge
A6
A5
A4
A3
A2
A1
A0 ACK D7
Subaddress
Acknowledge
D6
D5 D4
D3
D2
D1
D0 ACK
Data Byte
Stop
Condition
Figure 64. Random Write Transfer
9.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in Figure 65. After receiving each data byte, the device
responds with an acknowledge bit and the I2C sub-address is automatically incremented by one.
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Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
I2C Device Address
and R/W Bit
A5
A4
A3
A1
Subaddress
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Byte
Last Data Byte
Stop
Condition
Figure 65. Sequential Write Transfer
9.5.2.3 Random Read
As shown in Figure 66, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the
device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the
master device transmits another start condition followed by the address and the read/write bit again. This time
the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device
again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop
condition to complete the single-byte data-read transfer.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address
and R/W Bit
A6
A5
Subaddress
A4
A0 ACK
A6
Not
Acknowledge
Acknowledge
A5
A1 A0 R/W ACK D7 D6
I2C Device Address
and R/W Bit
D0 D6 ACK
Data Byte
Stop
Condition
Figure 66. Random Read Transfer
32
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9.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in Figure 67. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C sub
address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed by a
stop condition to complete the transfer.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address
and R/W Bit
A6
A5
A0 ACK
A6
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I2C Device Address
and R/W Bit
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
Stop
Condition
Figure 67. Sequential Read Transfer
9.5.2.5 DSP Memory Book, Page and BQ update
The TAS5806M device supports the I2C serial bus and the data transmission protocol for standard and fast mode
as a slave device.
The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has
several registers.
Because the TAS5806M register map spans several books and pages, the user must select the correct book and
page before writing individual register bits or bytes.
To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.
On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book
number to register 0x7f on page 0. To change between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in Book 0xAA. The five coefficients of every Biquad Filter should
be written entirely and sequentially from the lowest address to the highest.
All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5805M Process Flows
9.5.2.6 Example Use
Example 1, The following is a sample script for configuring a device on I2C slave address 0x58 and set the
device switching frequency to 768 kHz with Class D loop bandwidth to 175 kHz, 1SPW Modulation:
w 58 00 00 #Go to Page0
w 58 7f 00 #Change the Book to 0x00
w 58 00 00 #Go to Page 0x00
w 58 02 01 #Set switching frequency to 768kHz with 1SPW Modulation
w 58 53 60 #Set Class D Loop Bandwidth to 175kHz
Example 2, The following is a sample script for configuring a device on I2C slave address 0x58 and using the
DSP host memory to change the digital volume to the default value of 0dB:
w 58 00 00 #Go to Page 0
w 58 7f 8c #Change the Book to 0x8C
w 58 00 2a #Go to Page 0x2a
w 58 24 00 80 00 00 #change digital volume to 0dB
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9.5.2.7 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers
will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.
The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register
locations.
9.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the
same register locations where the CRC checksum is valid.
9.5.2.7.2 Exclusive or (XOR) Checksum
The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with
the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all
registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book
0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register
location where it is read.
34
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9.5.3 Control via Software
• Startup Procedures
• Shutdown Procedures
9.5.3.1 Startup Procedures
1. Configure ADR/FAULT pin with proper setting for I2C device address.
2. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first).
3. Once power supplies are stable, bring up PDN to high and wait at least 5 ms, then start SCLK, LRCLK.
4. Once I2S clock are stable, set the device into HiZ state and enable DSP via the I2C control port.
5. Wait at least 5 ms. Then initialize the DSP Coefficient, then set the device to Play state.
6. The device is now in normal operation.
Normal Operation
Initialization
DVDD
0 ns
PVDD
0 ns
0 ns
PDN
5ms
I2S
I2S
I2S
I2S
Deep sleep
Set to HiZ state
(Enable DSP)
I2S
I2S
I2S
I2S
DSP Coeff
Play
I2S
I2S
I2C
5 ms for device settle down
Figure 68. Start-up Sequence
9.5.3.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]=10 (HiZ) via the I2C control port or Pull PDN low.
3. Wait at least 6ms (this time depends on the LRCLK rate, digital volume and digital volume ramp down rate).
4. Bring down power supplies.
5. The device is now fully shutdown and powered off.
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PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
(1)
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C.
(2)
At least 6 ms delay needed based on LRCLK (Fs) = 48 kHz. Digital volume ramp down update every sample period,
decreased by 0.5 dB for each update, digital volume = 24 dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
Figure 69. Power-down Sequence
9.5.3.3 Protection and Monitoring
9.5.3.3.1 Over-current Shutdown (OCSD)
Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,
and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends
on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The
user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2C fault register
saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not
severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the output
FETs, and operation returns to normal after the short is removed.
9.5.3.3.2 DC Detect
If the TAS5806M device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the
OUTxx outputs transition to high impedance, signifying a fault.
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9.6 Register Maps
9.6.1 CONTROL PORT Registers
Table 5 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in
Table 5 should be considered as reserved locations and the register contents should not be modified.
Table 5. CONTROL PORT Registers
Offset
Acronym
Register Name
1h
RESET_CTRL
Register 1
Section
Go
2h
DEVICE_CTRL_1
Register 2
Go
3h
DEVICE_CTRL_2
Register 3
Go
Fh
I2C_PAGE_AUTO_INC
Register 15
Go
28h
SIG_CH_CTRL
Register 40
Go
29h
CLOCK_DET_CTRL
Register 41
Go
30h
SDOUT_SEL
Register 48
Go
31h
I2S_CTRL
Register 49
Go
33h
SAP_CTRL1
Register 51
Go
34h
SAP_CTRL2
Register 52
Go
35h
SAP_CTRL3
Register 53
Go
37h
FS_MON
Register 55
Go
38h
BCK_MON
Register 56
Go
39h
CLKDET_STATUS
Register 57
Go
40h
CHANNEL_FORCE_HIZ
Register 58
Go
4Ch
DIG_VOL_CTRL
Register 76
Go
4Eh
DIG_VOL_CTRL2
Register 78
Go
4Fh
DIG_VOL_CTRL3
Register 79
Go
50h
AUTO_MUTE_CTRL
Register 80
Go
51h
AUTO_MUTE_TIME
Register 81
Go
53h
ANA_CTRL
Register 83
Go
54h
AGAIN
Register 84
Go
5Ch
BQ_WR_CTRL1
Register 92
Go
5Dh
DAC_CTRL
Register 93
Go
60h
ADR_PIN_CTRL
Register 96
Go
61h
ADR_PIN_CONFIG
Register 97
Go
66h
DSP_MISC
Register 102
Go
67h
DIE_ID
Register 103
Go
68h
POWER_STATE
Register 104
Go
69h
AUTOMUTE_STATE
Register 105
Go
6Ah
PHASE_CTRL
Register 106
Go
6Bh
SS_CTRL0
Register 107
Go
6Ch
SS_CTRL1
Register 108
Go
6Dh
SS_CTRL2
Register 109
Go
6Eh
SS_CTRL3
Register 110
Go
6Fh
SS_CTRL4
Register 111
Go
70h
CHAN_FAULT
Register 112
Go
71h
GLOBAL_FAULT1
Register 113
Go
72h
GLOBAL_FAULT2
Register 114
Go
73h
OT WARNING
Register 115
Go
74h
PIN_CONTROL1
Register 116
Go
75h
PIN_CONTROL2
Register 117
Go
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Table 5. CONTROL PORT Registers (continued)
Offset
Acronym
Register Name
76h
MISC_CONTROL
Register 118
Section
Go
78h
FAULT_CLEAR
Register 120
Go
Complex bit access types are encoded to fit into small table cells. Table 6 shows the codes that are used for
access types in this section.
Table 6. CONTROL PORT Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
38
Value after reset or the default
value
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9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in Figure 70 and described in Table 7.
Return to Summary Table.
Figure 70. RESET_CTRL Register
7
6
RESERVED
R/W
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
Table 7. RESET_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
RST_MOD
W
0
WRITE CLEAR BIT
4
Reset Modules
WRITE CLEAR BIT Reset full digital core This bit resets full digital
signal chain (Include DSP and Control Port Registers). Since the
DSP is also reset, the coeffient RAM content will also be cleared by
the DSP.
0: Normal
1: Reset modules
3-1
0
RESERVED
R
000
This bit is reserved
RST_CONTROL_REG
W
0
WRITE CLEAR BIT
Reset Registers
This bit resets the control port registers back to their initial values.
The RAM content is not cleared.
0: Normal
1: Reset control port registers
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9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in Figure 71 and described in Table 8.
Return to Summary Table.
Figure 71. DEVICE_CTRL_1 Register
7
RESERVED
R/W
6
5
FSW_SEL
R/W
4
3
RESERVED
R/W
2
DAMP_PBTL
R/W
1
0
DAMP_MOD
R/W
Table 8. DEVICE_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
FSW_SEL
R/W
000
SELECT FSW
000:768K
001:384K
011:480K
100:576K
010:Reserved
101:Reserved
110:Reserved
111:Reserved
3
RESERVED
R/W
0
This bit is reserved
2
DAMP_PBTL
R/W
0
0: SET DAMP TO BTL MODE
1: SET DAMP TO PBTL MODE
1-0
DAMP_MOD
R/W
00
00:BD MODE
7
6-4
01:1SPW MODE
10:HYBRID MODE
40
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9.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
DEVICE_CTRL_2 is shown in Figure 72 and described in Table 9.
Return to Summary Table.
Figure 72. DEVICE_CTRL_2 Register
7
6
RESERVED
R/W
5
4
DIS_DSP
R/W
3
MUTE
R/W
2
RESERVED
R/W
1
0
CTRL_STATE
R/W
Table 9. DEVICE_CTRL_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
4
DIS_DSP
R/W
1
DSP reset
When the bit is made 0, DSP will start powering up and send out
data. This needs to be made 0 only after all the input clocks are
settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute Both Left /Right Channel
This bit issues soft mute request for the left/right channel. The
volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2
RESERVED
R/W
0
This bit is reserved
CTRL_STATE
R/W
00
Device state control register
00: Deep Sleep
01: Sleep
10: Hiz (Set both A channel and B channel to Hiz)
Notes: For separate channel Hiz, see details in Table 21
11: PLAY
1-0
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9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in Figure 73 and described in Table 10.
Return to Summary Table.
Figure 73. I2C_PAGE_AUTO_INC Register
7
6
5
4
RESERVED
R/W
3
PAGE_AUTOIN
C_REG
R/W
2
1
RESERVED
0
R/W
Table 10. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
PAGE_AUTOINC_REG
R/W
0
Page auto increment disable
Disable page auto increment mode for non -zero books. When end
of page is reached it goes back to 8th address location of next page
when this bit is 0. When this bit is 1 it goes to 0th location of current
page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
RESERVED
R/W
000
This bit is reserved
3
2-0
9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in Figure 74 and described in Table 11.
Return to Summary Table.
Figure 74. SIG_CH_CTRL Register
7
6
5
BCK_RATIO_CONFIGURE
R/W
4
3
2
1
0
FS_MODE
R/W
Table 11. SIG_CH_CTRL Register Field Descriptions
42
Bit
Field
Type
Reset
Description
7-4
BCK_RATIO_CONFIGUR
E
R/W
0000
These bits indicate the configured BCK ratio, the number of BCK
clocks in one audio frame.
0011: 32FS
0101: 64FS
0111: 128FS
1001: 256FS
1011: 512FS
3-0
FS_MODE
R/W
0000
FS Speed Mode These bits select the FS operation mode, which
must be set according to the current audio sampling rate.
0000: Auto detection
0110: 32KHz
1000: 44.1KHz
1001: 48KHz
1010: 88.2KHz
1011: 96KHz
Others Reserved
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9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in Figure 75 and described in Table 12.
Return to Summary Table.
Figure 75. CLOCK_DET_CTRL Register
7
RESERVED
6
DIS_DET_PLL
R/W
R/W
5
DIS_DET_BCL
K_RANGE
R/W
4
DIS_DET_FS
R/W
3
DIS_DET_BCL
K
R/W
2
DIS_DET_MIS
S
R/W
1
RESERVED
0
RESERVED
R/W
R/W
Table 12. CLOCK_DET_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6
DIS_DET_PLL
R/W
0
Ignore PLL overate Detection
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150MHz or an error will be reported. When
ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_BCLK_RANGE
R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the BCK range detection. The
BCK must be stable between 256KHz and 50MHz or an error will be
reported. When ignored, a BCK range error will not cause a clock
error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
DIS_DET_FS
R/W
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error will not cause a clock error.But CLKDET_STATUS
will report fs error.
0: Regard FS detection
1: Ignore FS detection
3
DIS_DET_BCLK
R/W
0
Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK.
The BCK must be stable between 32FS and 512FS inclusive or an
error will be reported. When ignored, a BCK error will not cause a
clock error.
0: Regard BCK detection
1: Ignore BCK detection
2
DIS_DET_MISS
R/W
0
Ignore BCK Missing Detection
This bit controls whether to ignore the BCK missing detection. When
ignored an BCK missing will not cause a clock error.
0: Regard BCK missing detection
1: Ignore BCK missing detection
1
RESERVED
R/W
0
This bit is reserved
0
RESERVED
R/W
0
This bit is reserved
9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]
SDOUT_SEL is shown in Figure 76 and described in Table 13.
Return to Summary Table.
Figure 76. SDOUT_SEL Register
7
6
5
4
RESERVED
3
2
1
0
SDOUT_SEL
R/W
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Table 13. SDOUT_SEL Register Field Descriptions
Bit
Field
7-1
RESERVED
0
SDOUT_SEL
Type
R
Reset
Description
0
This bit is reserved
0
SDOUT Select. This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
44
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9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in Figure 77 and described in Table 14.
Return to Summary Table.
Figure 77. I2S_CTRL Register
7
6
RESERVED
R/W
5
BCK_INV
R/W
4
3
RESERVED
R/W
R
2
1
RESERVED
R
0
RESERVED
R/W
Table 14. I2S_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
BCK_INV
R/W
0
BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the
rising edge of the BCK. Normally they are assumed to be aligned to
the falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode
RESERVED
R/W
00000
This bit is reserved
5
4-0
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9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in Figure 78 and described in Table 15.
Return to Summary Table.
Figure 78. SAP_CTRL1 Register
7
I2S_SHIFT_MS
B
R/W
6
RESERVED
5
4
DATA_FORMAT
3
2
I2S_LRCLK_PULSE
1
0
WORD_LENGTH
R/W
R/W
R/W
R/W
Table 15. SAP_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2S_SHIFT_MSB
R/W
0
I2S Shift MSB
6
RESERVED
R/W
0
This bit is reserved
5-4
DATA_FORMAT
R/W
00
I2S Data Format
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
I2S_LRCLK_PULSE
R/W
00
01: lrclk pulse < 8 SCLK. If the high width of LRCLK/FS in TDM/DSP
mode is less than 8 cycles of SCK, these two bits need set to 01.
1-0
WORD_LENGTH
R/W
10
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in Figure 79 and described in Table 16.
Return to Summary Table.
Figure 79. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
Table 16. SAP_CTRL2 Register Field Descriptions
46
Bit
Field
Type
Reset
Description
7-0
I2S_SHIFT
R/W
00000000
I2S Shift LSB
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of BCK from
the starting (MSB) of audio frame to the starting of the desired audio
sample.
000000000: offset = 0 BCK (no offset)
000000001: ofsset = 1 BCK
000000010: offset = 2 BCKs
and
111111111: offset = 512 BCKs
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9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
SAP_CTRL3 is shown in Figure 80 and described in Table 17.
Return to Summary Table.
Figure 80. SAP_CTRL3 Register
7
6
RESERVED
R/W
5
4
LEFT_DAC_DPATH
R/W
3
2
1
0
RIGHT_DAC_DPATH
R/W
RESERVED
R/W
Table 17. SAP_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5-4
LEFT_DAC_DPATH
R/W
01
Left DAC Data Path. These bits control the left channel audio data
path connection.
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
3-2
RESERVED
R/W
00
This bit is reserved
1-0
RIGHT_DAC_DPATH
R/W
01
Right DAC Data Path. These bits control the right channel audio
data path connection.
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
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9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in Figure 81 and described in Table 18.
Return to Summary Table.
Figure 81. FS_MON Register
7
6
5
4
BCLK_RATIO_HIGH
R
RESERVED
R/W
3
2
1
0
FS
R
Table 18. FS_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5-4
BCLK_RATIO_HIGH
R
00
2 msbs of detected BCK ratio
3-0
FS
R
0000
These bits indicate the currently detected audio sampling rate.
0000: FS Error
0110: 32KHz
1000: Reserved
1001: 48KHz
1011: 96KHz
Others Reserved
9.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in Figure 82 and described in Table 19.
Return to Summary Table.
Figure 82. BCK_MON Register
7
6
5
4
3
BCLK_RATIO_LOW
R
2
1
0
Table 19. BCK_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BCLK_RATIO_LOW
R
00000000
These bits indicate the currently detected BCK ratio, the number of
BCK clocks in one audio frame.
BCK = 32 FS~512 FS
48
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9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in Figure 83 and described in Table 20.
Return to Summary Table.
Figure 83. CLKDET_STATUS Register
7
6
5
4
RESERVED
R/W
3
2
1
0
DET_STATUS
R
Table 20. CLKDET_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5
DET_STATUS
R
0
This bit indicates whether the BCLK is overrate or underrate
4
DET_STATUS
R
0
This bit indicates whether the PLL is overrate
3
DET_STATUS
R
0
This bit indicates whether the PLL is locked or not. The PLL will be
reported as unlocked when it is disabled.
2
DET_STATUS
R
0
This bit indicates whether the BCK is missing or not.
1
DET_STATUS
R
0
This bit indicates whether the BCK is valid or not. The BCK ratio
must be stable and in the range of 32-512FS to be valid.
0
DET_STATUS
R
0
In auto detection mode(reg_fsmode=0),this bit indicated whether the
audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag will be also asserted.
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9.6.1.15 CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]
CHANNEL_FORCE_HIZ is shown in Figure 84 and described in Table 21.
Return to Summary Table.
Figure 84. CHANNEL_FORCE_HIZ Register
7
6
RESERVED
R/W
5
4
CH_A_HIZ
R/W
3
CH_B_HIZ
R/W
2
1
RESERVED
R/W
0
Table 21. CHANNEL_FORCE_HIZ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
These bits are reserved
CH_A_HIZ
R/W
0
1: Force Channel A (L channel) to Hiz mode.
4
0: Exit Force Hi-Z mode, Channel A is now controlled by Register
0x03, see Table 9.
Notes: If channel has been forced to Hiz, only method to exit Force
Hi-Z mode is set this bit to 0. This function is disabled in PBTL
mode.
3
CH_B_HIZ
R/W
0
1: Force Channel B (R channel) to Hiz mode.
0: Exit Force Hi-Z mode, Channel B is now controlled by Register
0x03, see Table 9.
Notes: If channel has been forced to Hiz, only method to exit Force
Hi-Z mode is set this bit to 0. This function is disabled in PBTL
mode.
2-0
RESERVED
R/W
001
These bits are reserved.
9.6.1.16 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL_CTL is shown in Figure 85 and described in Table 22.
Return to Summary Table.
Figure 85. DIG_VOL_CTL Register
7
6
5
4
3
2
1
0
PGA
R/W
Table 22. DIG_VOL_CTR Register Field Descriptions
50
Bit
Field
Type
Reset
Description
7-0
PGA
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
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9.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL2 is shown in Figure 86 and described in Table 23.
Return to Summary Table.
Figure 86. DIG_VOL_CTRL2 Register
7
6
PGA_RAMP_DOWN_SPEED
R/W
5
4
PGA_RAMP_DOWN_STEP
R/W
3
2
PGA_RAMP_UP_SPEED
R/W
1
0
PGA_RAMP_UP_STEP
R/W
Table 23. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
Type
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
PGA_RAMP_DOWN_STE R/W
P
11
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-2
PGA_RAMP_UP_SPEED
R/W
00
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
1-0
PGA_RAMP_UP_STEP
R/W
11
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each updat
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
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9.6.1.18 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL3 is shown in Figure 87 and described in Table 24.
Return to Summary Table.
Figure 87. DIG_VOL_CTRL3 Register
7
6
FAST_RAMP_DOWN_SPEED
R/W
5
4
FAST_RAMP_DOWN_STEP
R/W
3
2
1
0
RESERVED
R/W
Table 24. DIG_VOL_CTRL3 Register Field Descriptions
Bit
Field
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
Type
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST
EP
R/W
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
9.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in Figure 88 and described in Table 25.
Return to Summary Table.
Figure 88. AUTO_MUTE_CTRL Register
7
6
5
RESERVED
R/W
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
Table 25. AUTO_MUTE_CTRL Register Field Descriptions
52
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000
This bit is reserved
2
REG_AUTO_MUTE_CTR
L
R/W
1
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted
1
REG_AUTO_MUTE_CTR
L
R/W
1
0: Disable right channel auto mute
1: Enable right channel auto mute
0
REG_AUTO_MUTE_CTR
L
R/W
1
0: Disable left channel auto mute
1: Enable left channel auto mute bit2: .
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9.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in Figure 89 and described in Table 26.
Return to Summary Table.
Figure 89. AUTO_MUTE_TIME Register
7
RESERVED
R/W
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
RESERVED
R/W
2
1
AUTOMUTE_TIME_RIGHT
R/W
0
Table 26. AUTO_MUTE_TIME Register Field Descriptions
Bit
7
6-4
3
2-0
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
AUTOMUTE_TIME_LEFT
R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
RESERVED
R/W
0
This bit is reserved
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
AUTOMUTE_TIME_RIGH R/W
T
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9.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]
ANA_CTRL is shown in Figure 90 and described in Table 27.
Return to Summary Table.
Figure 90. ANA_CTRL Register
7
6
5
4
3
2
1
0
ANA_CTRL
R/W
Table 27. ANA_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-5
ANA_CTRL
R/W
00
Class-D bandwidth control.
00: 80kHz;
01: 100kHz;
10: 120kHz;
11: 175kHz.
With Fsw=768kHz, 175kHz bandwidth should be selected for high
audio performance. With Fsw=384kHz, bandwidth should ≤ 120kHz.
4-0
54
RESERVED
R/W
0000
These bits are reserved
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9.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in Figure 91 and described in Table 28.
Return to Summary Table.
Figure 91. AGAIN Register
7
6
RESERVED
R/W
5
4
3
2
ANA_GAIN
R/W
1
0
1
0
BQ_WR_FIRST
_COEF
R/W
Table 28. AGAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
4-0
ANA_GAIN
R/W
00000
Analog Gain Control , with 0.5dB one step
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001: -0.5db
11111: -15.5 dB
9.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
BQ_WR_CTRL1 is shown in Figure 92 and described in Table 29.
Return to Summary Table.
Figure 92. BQ_WR_CTRL1 Register
7
6
5
4
RESERVED
3
2
R/W
Table 29. BQ_WR_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000000
This bit is reserved
BQ_WR_FIRST_COEF
R/W
0
Indicate the first coefficient of a BQ is starting to write.
0
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9.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
DAC_CTRL is shown in Figure 93 and described in Table 30.
Return to Summary Table.
Figure 93. DAC_CTRL Register
7
DAC_FREQUE
NCY_SEL
R/W
6
5
DAC_DITHER_EN
4
R/W
3
DAC_DITHER
2
1
0
DAC_CTRL_DEM_SEL
R/W
R/W
Table 30. DAC_CTRL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
DAC_FREQUENCY_SEL
R/W
1
DAC Frequency Select
0: 6.144MHz
1: 3.072MHz
6-5
DAC_DITHER_EN
R/W
11
DITHER_EN,
00: disable both stage dither
01: enable main stage dither
10: enable second stage dither
11: enbale both stage dither
4-2
DAC_DITHER
R/W
110
Dither level
100: -2^-7
101: -2^-8
110: -2^-9
111: -2^-10
000: -2^-13
001: -2^-14
010: -2^-15
011: -2^-16
1-0
DAC_CTRL_DEM_SEL
R/W
00
00: Enable DEM
11: Disable DEM
9.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
ADR_PIN_CTRL is shown in Figure 94 and described in Table 31.
Return to Summary Table.
Figure 94. ADR_PIN_CTRL Register
7
6
5
4
RESERVED
3
2
1
0
ADR_OE
R/W - 0x0
Table 31. ADR_PIN_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000000
This bit is reserved
ADR_OE
R/W
0
ADR Output Enable This bit sets the direction of the ADR pin
0
0: ADR is input
1: ADR is output
56
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9.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
ADR_PIN_CONFIG is shown in Figure 95 and described in Table 32.
Return to Summary Table.
Figure 95. ADR_PIN_CONFIG Register
7
6
RESERVED
5
4
3
2
ADR_PIN_CONFIG
R/W
1
0
Table 32. ADR_PIN_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
These bits are reserved
4-0
ADR_PIN_CONFIG
R/W
00000
00000: off (low)
00011: Auto mute flag (asserted when both L and R channels are
auto muted)
00100: Auto mute flag for left channel 0101: Auto mute flag for right
channel
00110: Clock invalid flag (clock error or clock missing)
00111: Reserved
01001: Reserved
01011: ADR as FAULTZ output
9.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]
DSP_MISC is shown in Figure 96 and described in Table 33.
Return to Summary Table.
Figure 96. DSP_MISC Register
7
6
5
4
3
BYPASS_CONTROL
R/W
2
1
0
Table 33. DSP_MISC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
These bits are reserved
3
BYPASS CONTROL
R/W
0
1: Left and Right will have use unique coef 0->Right channel will
share left channel coefficient
2
BYPASS CONTROL
R/W
0
1: bypass 128 tap FIR
1
BYPASS CONTROL
R/W
0
1: bypass DRC (Only bypass DRC in L/R channel)
0
BYPASS CONTROL
R/W
0
1: bypass EQ (Only bypass EQs in L/R channel)
9.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]
DIE_ID is shown in Figure 97 and described in Table 34.
Return to Summary Table.
Figure 97. DIE_ID Register
7
6
5
4
3
2
1
0
DIE_ID
R-0h
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Table 34. DIE_ID Register Field Descriptions
58
Bit
Field
Type
Reset
Description
7-0
DIE_ID
R
0h
DIE ID
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9.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in Figure 98 and described in Table 35.
Return to Summary Table.
Figure 98. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
Table 35. POWER_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
STATE_RPT
R
00000000
0: Deep sleep
1: Sleep
2: HIZ
3: Play
Others: reserved
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9.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in Figure 99 and described in Table 36.
Return to Summary Table.
Figure 99. AUTOMUTE_STATE Register
7
6
5
4
3
RESERVED
R
2
1
ZERO_RIGHT_
MON
R
0
ZERO_LEFT_
MON
R
Table 36. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000
This bit is reserved
ZERO_RIGHT_MON
R
0
This bit indicates the auto mute status for right channel.
1
0: Not auto muted
1: Auto muted
0
ZERO_LEFT_MON
R
0
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
60
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9.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
PHASE_CTRL is shown in Figure 100 and described in Table 37.
Return to Summary Table.
Figure 100. PHASE_CTR Register
7
6
RESERVED
5
4
3
2
RAMP_PHASE_SEL
R/W
R/W
1
PHASE_SYNC
_SEL
R/W
0
PHASE_SYNC
_EN
R/W
Table 37. PHASE_CTR Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
This bit is reserved
3-2
RAMP_PHASE_SEL
R/W
00
Select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current, it is
recomended set all devices the same RAMP frequency and same
spread spectrum. it must be set before driving device into PLAY
mode if this feature is needed.
00: phase0
01: phase1
10: phase2
11: phase3
1
I2S_SYNC_EN
R/W
0
Use I2S to synchronize output PWM phase
0: Disable
1: Enable
0
PHASE_SYNC_EN
R/W
0
0: RAMP phase sync disable
1: RAMP phase sync enable
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9.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
SS_CTRL0 is shown in Figure 101 and described in Table 38.
Return to Summary Table.
Figure 101. SS_CTRL0 Register
7
RESERVED
6
RESERVED
R/W
R/W
5
SS_PRE_DIV_
SEL
R/W
4
SS_MANUAL_
MODE
R/W
3
RESERVED
2
1
SS_RDM_EN
0
SS_TRI_EN
R/W
R/W
R/W
Table 38. SS_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6
RESERVED
R/W
0
This bit is reserved
5
SS_PRE_DIV_SEL
R/W
0
Select pll clock divide 2 as source clock in manual mode
4
SS_MANUAL_MODE
R/W
0
Set ramp ss controller to manual mode
RESERVED
R/W
0
This bit is reserved
1
SS_RDM_EN
R/W
0
Random SS enable
0
SS_TRI_EN
R/W
0
Triangle SS enable
3-2
9.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in Figure 102 and described in Table 39.
Return to Summary Table.
Figure 102. SS_CTRL1 Register
7
RESERVED
R/W
6
5
SS_RDM_CTRL
R/W
4
3
2
1
0
SS_TRI_CTRL
R/W
Table 39. SS_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-4
SS_RDM_CTRL
R/W
000
Random SS range control
3-0
SS_TRI_CTRL
R/W
0000
Triangle SS frequency and range control
7
62
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9.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
SS_CTRL2 is shown in Figure 103 and described in Table 40.
Return to Summary Table.
Figure 103. SS_CTRL2 Register
7
6
5
4
3
TM_FREQ_CTRL
R/W
2
1
0
Table 40. SS_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TM_FREQ_CTRL
R/W
01010000
Control ramp frequency in manual mode, F=61440000/N
9.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in Figure 104 and described in Table 41.
Return to Summary Table.
Figure 104. SS_CTRL3 Register
7
6
5
TM_DSTEP_CTRL
R/W
4
3
2
1
TM_USTEP_CTRL
R/W
0
Table 41. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
Control triangle mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
Control triangle mode spread spectrum rise step in ramp ss manual
mode
9.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in Figure 105 and described in Table 42.
Return to Summary Table.
Figure 105. SS_CTRL4 Register
7
RESERVED
R/W
6
5
TM_AMP_CTRL
R/W
4
3
2
1
SS_TM_PERIOD_BOUNDRY
R/W
0
Table 42. SS_CTRL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-5
TM_AMP_CTRL
R/W
01
Control ramp amp ctrl in ramp ss manual model
4-0
SS_TM_PERIOD_BOUN
DRY
R/W
00100
Control triangle mode spread spectrum boundary in ramp ss manual
mode
7
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9.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in Figure 106 and described in Table 43.
Return to Summary Table.
Figure 106. CHAN_FAULT Register
7
6
5
4
RESERVED
R
3
CH1_DC_1
R
2
CH2_DC_1
R
1
CH1_OC_I
R
0
CH2_OC_I
R
2
CLK_FAULT_I
1
PVDD_OV_I
0
PVDD_UV_I
R
R
R
Table 43. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000
This bit is reserved
3
CH1_DC_1
R
0
Left channel DC fault
2
CH2_DC_1
R
0
Right channel DC fault
1
CH1_OC_I
R
0
Left channel over current fault
0
CH2_OC_I
R
0
Right channel over current fault
9.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in Figure 107 and described in Table 44.
Return to Summary Table.
Figure 107. GLOBAL_FAULT1 Register
7
6
OTP_CRC_ER BQ_WR_ERRO
ROR
R
R
R
5
4
3
Table 44. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OTP_CRC_ERROR
R
0h
Indicate OTP CRC check error.
6
BQ_WR_ERROR
R
0h
The recent BQ is written failed
RESERVED
R
0h
This bit is reserved
2
CLK_FAULT_I
R
0h
Clock fault
1
PVDD_OV_I
R
0h
PVDD OV fault
0
PVDD_UV_I
R
0h
PVDD UV fault
5-3
64
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9.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in Figure 108 and described in Table 45.
Return to Summary Table.
Figure 108. GLOBAL_FAULT2 Register
7
6
5
RESERVED
R
4
3
2
1
RESERVED
R
0
OTSD_I
R
Table 45. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0000000
This bit is reserved
OTSD_I
R
0
Over temperature shut down fault
0
9.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]
OT_WARNING is shown in Figure 109 and described in Table 46.
Return to Summary Table.
Figure 109. OT_WARNING Register
7
6
5
RESERVED
R
4
RESERVED
R
3
R
2
OTW
R
1
0
RESERVED
R
R
Table 46. OT_WARNING Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
00
This bit is reserved
5-3
RESERVED
R
000
This bit is reserved
OTW
R
0
Over temperature warning ,135C
RESERVED
R
00
This bit is reserved
2
1-0
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9.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in Figure 110 and described in Table 47.
Return to Summary Table.
Figure 110. PIN_CONTROL1 Register
7
MASK_OTSD
R/W
6
MASK_DVDD_
UV
R/W
5
MASK_DVDD_
OV
R/W
4
MASK_CLK_F
AULT
R/W
3
MASK_PVDD_
UV
R/W
2
MASK_PVDD_
OV
R/W
1
MASK_DC
0
MASK_OC
R/W
R/W
Table 47. PIN_CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MASK_OTSD
R/W
0
Mask OTSD fault report
6
MASK_DVDD_UV
R/W
0
Mask DVDD UV fault report
5
MASK_DVDD_OV
R/W
0
Mask DVDD OV fault report
4
MASK_CLK_FAULT
R/W
0
Mask clock fault report
3
MASK_PVDD_UV
R/W
0
Mask PVDD UV fault report
2
MASK_PVDD_OV
R/W
0
Mask PVDD OV fault report
1
MASK_DC
R/W
0
Mask DC fault report
0
MASK_OC
R/W
0
Mask OC fault report
9.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in Figure 111 and described in Table 48.
Return to Summary Table.
Figure 111. PIN_CONTROL2 Register
7
6
5
CLKFLT_LATC
H_EN
R/W
RESERVED
4
OTSD_LATCH
_EN
R/W
3
OTW_LATCH_
EN
R/W
2
MASK_OTW
1
0
RESERVED
R/W
Table 48. PIN_CONTROL2 Register Field Descriptions
66
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
11
This bit is reserved
5
CLKFLT_LATCH_EN
R/W
1
Enable clock fault latch
4
OTSD_LATCH_EN
R/W
1
Enable OTSD fault latch
3
OTW_LATCH_EN
R/W
1
Enable OT warning latch
2
MASK_OTW
R/W
0
Mask OT warning report
1-0
RESERVED
R/W
00
This bit is reserved
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9.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in Figure 112 and described in Table 49.
Return to Summary Table.
Figure 112. MISC_CONTROL Register
7
DET_STATUS_
LATCH
R/W
6
5
RESERVED
R/W
4
OTSD_AUTO_
REC_EN
R/W
3
2
1
0
RESERVED
R/W
Table 49. MISC_CONTROL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
DET_STATUS_LATCH
R/W
0
1:Latch clock detection status
RESERVED
R/W
00
This bit is reserved
OTSD_AUTO_REC_EN
R/W
0
OTSD auto recovery enable
RESERVED
R/W
0000
This bit is reserved
0:Don't latch clock detection status
6-5
4
3-0
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9.6.1.44 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in Figure 113 and described in Table 50.
Return to Summary Table.
Figure 113. FAULT_CLEAR Register
7
ANALOG_FAU
LT_CLEAR
W
6
5
4
3
RESERVED
2
1
0
R/W
Table 50. FAULT_CLEAR Register Field Descriptions
Bit
7
Field
Reset
Description
ANALOG_FAULT_CLEAR W
Type
0
WRITE CLEAR BIT.
RESERVED
0000000
Once write this bit to 1, device will clear analog fault
6-0
68
R/W
This bit is reserved
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the TAS5806M device into the larger system.
10.1.1 Bootstrap Capacitors
The output stage of the TAS5806M uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.22-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.22-µF capacitor between OUT_A and BST_A for
bootstrapping the A channel. Similarly, connect another 0.22-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
10.1.2 Inductor Selections
It is required that the peak current is smaller than the OCP (Over current protection) value which is 5A, there are
3 cases which cause high peak current flow through inductor.
1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ.
I peak _ power _ up | PVDD u C / L u sin(1 / L u C u T / Fsw )
(1)
NOTE
θ=0.5 (BD Modulation), 0.14 (1SPW Modulation), 0.14 (Hybrid Modulation)
Table 51. Peak current during power up
PWM
Modulatio
n
BD
Modulation
(θ=0.5)
PVDD
L (uH)
C (uF)
Fsw (kHz)
Ipeak_power_up
24
4.7
0.68
384 (80kHz BW)
6.07A (>5A OCP)
24
10
0.68
384 (80kHz BW)
3A
12
4.7
0.68
384 (80kHz BW)
3.32A
12
10
0.68
384 (80kHz BW)
1.55A
24
4.7
0.68
768 (175kHz BW)
3.25A
Comments
1.
2.
3.
24
10
0.68
768 (175kHz BW)
1.55A
4.
Lower Switching Frequency only permits low
Class D Loop Bandwidth, which cause worse
THD+N.
Lower Switching Frequency cause higher
startup peak current, which needs Inductor
supports higher saturation current.
BD Mode has more switching loss than 1SPW
mode, so the thermal performance is worse
with high PVDD, recommend 1SPW mode for
high PVDD case (Typical >16V case).
Saturation
current
of
Inductor
needs
>Ipeak_power_up .
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Application Information (continued)
Table 51. Peak current during power up (continued)
PWM
Modulatio
n
1SPW
Modulation
(θ=0.14)
PVDD
L (uH)
C (uF)
Fsw (kHz)
Ipeak_power_up
24
4.7
0.68
384 (80kHz BW)
1.84A
24
10
0.68
384 (80kHz BW)
0.87A
12
4.7
0.68
384 (80kHz BW)
0.92A
12
10
0.68
384 (80kHz BW)
0.44A
12
4.7
0.68
768 (175kHz BW)
0.46A
24
4.7
0.68
768 (175kHz BW)
0.93A
24
10
0.68
768 (175kHz BW)
0.87A
Comments
1.
1SPW mode with smaller duty cycle during
start up cause smaller Ipeak_power_up
1.
Even with same Inductor value, higher
switching
frequency
cause
smaller
Ipeak_power_up which means some lower cost
inductor with less saturation current is
permitted.
768kHz switching frequency,175kHz Loop
Bandwidth with 1SPW mode is a good balance
for both thermal and audio performance.
2.
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping will cause
PWM duty cycle increase dramatically. This is the worst case and it rarely happens.
I peak _ clipping | PVDD u (1 T ) /( Fsw u L)
(2)
Table 52. Peak current during PVDD clipping with Burst
PWM
PVDD
Modulation
1SPW
BD
L (uH)
Fsw (kHz)
Ipeak_clipping
24
10
768
2.68A
24
10
576
3.58A
24
10
384
5.37A (>5A OCP)
12
10
768
1.34A
12
4.7
768
2.86A
24
10
768
1.56
24
10
384
3.12
12
10
768
0.78
12
4.7
768
1.66
Comments
For high PVDD case, 1SPW mode is a good option to improve
thermal performance, but switching frequency can't be too low.
3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.
I peak _ output _ power | 2 u Max _ Output _ Power / Rspea ker_ Load
(3)
Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
It is suggested that inductor saturation current ISAT, is larger than the amplifier's peak current during power-up
and play audio.
I SAT t max(I peak _ power _ up , I peak _ clipping, I peak _ output_ power )
(4)
In addition, the effective inductance at the peak current is required to be at least 80% of the inductance value in
Table 53 to meet datasheet specifications. The minimum inductance is given in Table 53 .
70
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Table 53. LC filter recommendation
PVDD (V)
Switching Frequency (kHz)
Modulation Scheme
384
BD
384
1SPW/Hybrid
≤12
>12
≤12
>12
Recommended Minimum Inductance (uH)
for LC filter design
4.7uH + 0.68uF
10uH + 0.68uF
10uH + 0.68uF
15uH + 0.68uF
For higher switching frequency (Fsw), select inductors with minimum inductance to be 384kHz/Fsw×L.
10.1.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
10.1.4 Output EMI Filtering
The TAS5806M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power and
film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design
(SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon
the desired load and response.
10.2 Typical Applications
10.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels are
amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based
upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
Figure 114 shows the 2.0 (Stereo BTL) system application.
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Typical Applications (continued)
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Figure 114. 2.0 (Stereo BTL with Inductor as output filter) System Application Schematic
72
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Typical Applications (continued)
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Figure 115. 2.0 (Stereo BTL with Ferrite bead as output filter) System Application Schematic
10.2.2 Design Requirements
• Power supplies:
– 3.3-V or 1.8-V supply for DVDD.
– 4.5-V to 24-V supply for PVDD.
• Communication: host processor serving as I2C compliant master.
• Externa memory (Such as EEPROM or FLASH) used for coefficients.
10.2.3 Detailed Design Procedure
The design procedure can be used for Stereo 2.0, Mono, 2.1 system
10.2.3.1 Step1:Hardware Integration
• Use the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Follow the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they
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Typical Applications (continued)
are given precedent as design trade-offs are made is recommended.
– For questions and support, go to the E2E forums (E2E.ti.com). If deviating from the recommended layout
is necessary, go to the E2E forum to request a layout review.
10.2.3.2 Step2: Speaker Tuning
Use the TAS5806MEVM board and the TAS5806M tuning software to configure the desired device settings.
10.2.3.3 Software Integration
Use the End System Integration feature of the TAS5806M tuning software app to generate a baseline
configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
10.2.3.4 Application Curves
10
10
5 PVcc=12V
TA=25qC
2 R L=6:
1
5 PVcc=18V
TA=25qC
2 R L=8:
1
P O=1W
P O =2.5W
P O=5W
0.5
THD+N(%)
THD+N(%)
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 12 V
FSW = 768 kHz
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
0.001
20
20k
Load = 6 Ω
PVDD = 18 V
FSW = 768 kHz
20k
D002
D107
Load = 8 Ω
5 PV CC =18V
TA=25qC
2 R L=8:
1
0.5
THD+N (%)
0.5
THD+N (%)
10 µH + 0.68 µF
1 SPW Modulation
10k
10
5 PV CC =12V
TA=25qC
2 R L=6:
1
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.001
0.01
0.005
0.002
0.1
PVDD = 12 V
FSW = 768 kHz
1
Output Power (W)
4.7 µH + 0.68 µF
1 SPW Modulation
f= 20Hz
f= 1kHz
f= 10KHz
0.001
0.01
10
0.1
D007
D114
Load = 6 Ω
PVDD = 18 V
FSW = 768 kHz
Figure 118. THD+N vs Output Power
74
1k
Frequency (Hz)
Figure 117. THD+N vs Frequency
10
0.002
100
D002
D103
Figure 116. THD+N vs Frequency
0.005
P O=1W
P O =2.5W
P O=5W
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1
Output Power (W)
4.7 µH + 0.68 µF
1 SPW Modulation
10
20
D004
D118
D010
D007
Load = 8 Ω
Figure 119. THD+N vs Output Power
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Typical Applications (continued)
10.2.4 Mono (PBTL) system
In MONO application, TAS5806M can be used as PBTL mode to drive sub-woofer with more output power.
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Figure 120. Mono (PBTL) System Application Schematic
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Typical Applications (continued)
10.2.5 Application Curves
10
10
5 PVcc=24V
TA=25qC
2 R L=4:
1
5 PV CC =24V
TA=25qC
2 R L=4:
1
P O=1W
PO=2.5W
PO=5W
0.5
THD+N (%)
THD+N(%)
0.5
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
100
PVDD = 24 V
FSW = 576 kHz
1k
Frequency (Hz)
4.7 µH + 0.68 µF
1 SPW Modulation
10k
20k
0.001
0.01
0.1
D002
D148
PBTL Mode
Load = 4 Ω
PVDD = 24 V
FSW = 576 kHz
Figure 121. THD+N vs Frequency
76
f= 20Hz
f= 10kHz
f= 1KHz
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1
Output Power (W)
4.7 µH + 0.68 µF
1 SPW Modulation
10
20
D007
D153
PBTL Mode
Load = 4 Ω
Figure 122. THD+N vs Output Power
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11 Power Supply Recommendations
The TAS5806M device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. One low-voltage power
supply which is calls DVDD is required to power the various low-power portions of the device. The allowable
voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions table.
These two power supplies do not have a required power-up sequence. The power supplies can be powered on in
any order. But once the device has been initialized, PVDD must keep within the normal operation voltage. Once
PVDD lower than 3.5V, all registers need re-initialize again. Recommends waiting 1 ms to 5 ms for the DVDD
power supplies to stabilize before starting I2C communication and providing stable I2S clock before enabling the
device outputs.
DVDD
Internal Digital
Circuitry
Digital IO
VR_DIG
1.8V/3.3VÅ
1.5V
LDO
External Filtering/Decoupling
DVDD
PVDD
4.5V~26.4V
Gate Drive/Internal
Analog Circuitry
Output Stage
Power Supply
AVDD
5V
LDO
External Filtering/Decoupling
PVDD
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Figure 123. Power Supply Function Block Diagram
11.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
Figure 123, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are
highlighted in the Application and Implementation section and the Layout Example section and must be followed
as closely as possible for proper operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5806M device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the VR_DIG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuity. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
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11.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TAS5806MEVM and must be followed as closely as possible for proper operation and
performance. Due to the high-voltage switching of the output stage, it is particularly important to properly
decouple the output power stages in the manner described in the TAS5806M device Application and
Implementation. Lack of proper decoupling, like that shown in the Application and Implementation, results in
voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. An AVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5806M internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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12 Layout
12.1 Layout Guidelines
12.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the Layout Example section. These examples
represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These
designs can be modified slightly as needed to meet the needs of a given application. In some applications, for
instance, solution size can be compromised to improve thermal performance through the use of additional
contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by
routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it
is recommended to start from the guidance shown in the Layout Example section and work with TI field
application engineers or through the E2E community to modify it based upon the application specific goals.
12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD and PVDD. However, the capacitors on the PVDD net for the TAS5806M device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5806M device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the Layout Example section.
12.1.3 Optimizing Thermal Performance
Follow the layout example shown in the Figure 124 to achieve the best balance of solution size, thermal, audio,
and electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
12.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5806M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5806M device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5806M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5782M
device.
• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
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Layout Guidelines (continued)
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
12.1.3.2 Stencil Pattern
The recommended drawings for the TAS5806M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
NOTE
The customer must verify that deviation from the guidance shown in the package
addendum, including the deviation explained in this section, meets the customer’s quality,
reliability, and manufacturability goals.
12.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5806M device will be soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5806M
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5806M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Layout Example section, this interface can benefit from improved thermal performance.
NOTE
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Layout Example section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5806M device to open up the current path
to and from the device.
12.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
80
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TAS5806M
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SLASEP9 – MAY 2019
Layout Guidelines (continued)
manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the Layout Example section. It is important that the total area of the
aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the
thermal pad itself.
12.2 Layout Example
Top Layer 3D layout
(Output Filter = Ferrite Bead + Capacitor)
Bot Layer 3D layout
(Output Filter = Ferrite Bead + Capacitor)
Figure 124. 2.0 (Stereo BTL with Ferrite bead as the output filter) 3-D View
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SLASEP9 – MAY 2019
www.ti.com
Layout Example (continued)
Top Layer 3D layout
(Output Filter = Inductor + Capacitor)
Bot Layer 3D layout
(Output Filter = Inductor + Capacitor)
Figure 125. 2.0 (Stereo BTL with Inductor as the output filter) 3-D View
82
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TAS5806M
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SLASEP9 – MAY 2019
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•
•
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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83
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TAS5806MDCPR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
DCP
38
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-25 to 85
TAS5806M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5806MDCPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DCP
38
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5806MDCPR
HTSSOP
DCP
38
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.22 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/A
www.ti.com
PACKAGE OUTLINE
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9.8
9.6
NOTE 3
9
19
20
38X
4.5
4.3
B
0.27
0.17
0.08
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
38X (1.5)
38X (0.3)
SYMM
SEE DETAILS
1
38
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(0.6) TYP
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
( 0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
SYMM
(4.7)
BASED ON
0.125 THICK
STENCIL
39
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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