Texas Instruments | TAS6424L-Q1 27-W,​​​ 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics | Datasheet | Texas Instruments TAS6424L-Q1 27-W,​​​ 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics Datasheet

Texas Instruments TAS6424L-Q1 27-W,​​​ 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics Datasheet
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TAS6424L-Q1
SLOS809 – MARCH 2017
TAS6424L-Q1 27-W, 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier
With Load-Dump Protection and I2C Diagnostics
1 Features
3 Description
•
•
The TAS6424L-Q1 device is a four-channel digitalinput Class-D audio amplifier designed for use in
automotive head units and external amplifier
modules. The device provides four channels at 27 W
into 4 Ω at 10% THD+N and 27 W into 2 Ω at 10%
THD+N from a 14.4 V supply . The Class-D topology
dramatically improves efficiency over traditional linear
amplifier solutions. The output switching frequency
can be set either above the AM band, which
eliminates the AM-band interference and reduces
output filtering and cost, or below AM band to
optimize efficiency.
•
•
•
•
•
Qualified for Automotive Applications
Audio Inputs
– 4 Channel I2S or 4/8-Channel TDM Input
– Input Sample Rates: 44.1 kHz, 48 kHz, 96 kHz
– Input Formats: 16-bit to 32-bit I2S, and TDM
Audio Outputs
– Four-Channel Bridge-Tied Load (BTL), With
Option of Parallel BTL (PBTL)
– Up to 2.1 MHz Output Switching Frequency
– 27 W, 10% THD Into 4 Ω at 14.4 V
– 27 W, 10% THD Into 2 Ω at 14.4 V
– 80 W, 10% THD Into 2 Ω at 18 V PBTL
Audio Performance Into 4 Ω at 14.4 V
– THD+N < 0.03% at 1 W
– 42 µVRMS Output Noise
– –90 dB Crosstalk
Load Diagnostics
– Output Open and Shorted Load
– Output-to-Battery or Ground Shorts
– Line Output Detection Up to 6 kΩ
– Runs Without Input Clocks
– AC Diagnostic for Tweeter detection
Protection
– Output Current Limiting
– Output Short Protection
– 40 V Load Dump
– Open Ground and Power Tolerant
– DC Offset
– Overtemperature
– Undervoltage and Overvoltage
General Operation
– EVM Passes CISPR25-L5 EMC Specification
– 4.5 V to 18 V Supply voltage
– I2C Control With 4 Address Options
– Clip Detection and Thermal Warning
The wide supply-voltage range from 4.5 V to 18 V
helps minimize audio artefacts in start-stop
applications
The device incorporates all the functionality required
to perform in the demanding OEM applications area.
The device has a built-in load diagnostic function for
detecting and diagnosing misconnected outputs as
well as detection AC-coupled tweeters to help to
reduce test time during the manufacturing process.
The device is offered in a 56-pin HSSOP
PowerPAD™ package with the exposed thermal pad
up.
For a pin compatible two-channel devices see the
TAS6422-Q1 device.
Device Information(1)
PART NUMBER
TAS6424L-Q1
PACKAGE
HSSOP (56)
BODY SIZE (NOM)
18.41 mm × 7.49 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
PCB AREA
22 mm
1
2 Applications
•
•
Automotive Head Units
Automotive External Amplifier Modules
27 mm
25-W 4-channel
5.9 cm2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS6424L-Q1
SLOS809 – MARCH 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
9.4 Device Functional Modes........................................ 25
9.5 Programming........................................................... 25
9.6 Register Maps ......................................................... 29
1
1
1
2
3
4
6
10 Application and Implementation........................ 45
10.1 Application Information.......................................... 45
10.2 Typical Applications .............................................. 46
11 Power Supply Recommendations ..................... 52
12 Layout................................................................... 52
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 11
12.1 Layout Guidelines ................................................. 52
12.2 Layout Example .................................................... 54
12.3 Thermal Considerations ........................................ 54
13 Device and Documentation Support ................. 55
13.1
13.2
13.3
13.4
13.5
13.6
Parameter measurement Information ................ 13
Detailed description............................................. 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 15
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
55
14 Mechanical, Packaging, and Orderable
Information ........................................................... 56
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2017
*
Initial release.
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5 Device Comparison Table
PART
NUMBER
INPUT TYPE
CHANNEL
COUNT
POWER-SUPPLY
VOLTAGE RANGE
OUTPUT CURRENT
LIMIT
MAXIMUM PWM
FREQUENCY
TAS6424L-Q1
Digital
4
4.5 V to 18 V
4.8 A
2.1 MHz
TAS6424-Q1
Digital
4
4.5 V to 26.4 V
6.5 A
2.1 MHz
TAS6422-Q1
Digital
2
4.5 V to 26.4 V
6.5 A
2.1 MHz
TAS5414C-Q1
Analog, Single-Ended
4
5.6 V to 24 V
12.7 A
500 kHz
TAS5424C-Q1
Analog, Differential
4
5.6 v to 24 V
12.7 A
500 kHz
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6 Pin Configuration and Functions
DKQ Package
56-Pin HSSOP With Exposed Thermal Pad
Top View
GND
1
56
PVDD
PVDD
2
55
PVDD
VBAT
3
54
BST_4P
AREF
4
53
OUT_4P
VREG
5
52
GND
VCOM
6
51
OUT_4M
AVSS
7
50
BST_4M
AVDD
8
49
GND
GVDD
9
48
BST_3P
GVDD
10
47
OUT_3P
GND
11
46
GND
MCLK
12
45
OUT_3M
SCLK
13
44
BST_3M
FSYNC
14
43
PVDD
42
PVDD
Thermal
SDIN1
15
SDIN2
16
41
BST_2P
GND
17
40
OUT_2P
GND
18
39
GND
VDD
19
38
OUT_2M
SCL
20
37
BST_2M
SDA
21
36
GND
I2C_ADDR0
22
35
BST_1P
I2C_ADDR1
23
34
OUT_1P
STANDBY
24
33
GND
MUTE
25
32
OUT_1M
FAULT
26
31
BST_1M
WARN
27
30
PVDD
GND
28
29
PVDD
Pad
Not to scale
4
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Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
AREF
4
PWR
VREG and VCOM bypass capacitor return
AVDD
8
PWR
Voltage regulator bypass
AVSS
7
PWR
AVDD bypass capacitor return
BST_1M
31
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_1P
35
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_2M
37
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_2P
41
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_3M
44
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_3P
48
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_4M
50
PWR
Bootstrap capacitor connection pins for high-side gate driver
BST_4P
54
PWR
Bootstrap capacitor connection pins for high-side gate driver
FAULT
26
DO
Reports a fault (active low, open drain), 100-kΩ internal pullup resistor
FSYNC
14
DI
Audio frame clock input
1
11
17
18
28
GND
33
GND
Ground
36
39
46
49
52
GVDD
9
10
I2C_ADDR0
22
I2C_ADDR1
23
MCLK
12
MUTE
OUT_1M
PWR
Gate drive voltage regulator for channel 3 and 4, derived from VBAT input pin.
Gate drive voltage regulator for channel 1 and 2, derived from VBAT input pin.
DI
I2C address pins
DI
Audio master clock input
25
DI
Mutes the device outputs (active low), 100-kΩ internal pulldown resistor
32
NO
Negative output for the channel
OUT_1P
34
PO
Positive output for the channel
OUT_2M
38
NO
Negative output for the channel
OUT_2P
40
PO
Positive output for the channel
OUT_3M
45
NO
Negative output for the channel
OUT_3P
47
PO
Positive output for the channel
OUT_4M
51
NO
Negative output for the channel
OUT_4P
53
PO
Positive output for the channel
2
29
30
PVDD
42
PWR
PVDD voltage input (can be connected to battery)
43
55
56
(1)
GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/O = digital input
and output, NC = no connection
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Pin Functions (continued)
PIN
NAME
TYPE (1)
NO.
DESCRIPTION
DI
I2C clock input
13
DI
Audio bit and serial clock input
21
DI/O
SDIN1
15
DI
TDM data input and audio I2S data input for channels 1 and 2
SDIN2
16
DI
Audio I2S data input for channels 3 and 4
STANDBY
24
DI
Enables low power standby state (active Low), 100-kΩ internal pulldown resistor
VBAT
3
PWR
Battery voltage input
VCOM
6
PWR
Bias voltage
VDD
19
PWR
3.3-V external supply voltage
VREG
5
PWR
Voltage regulator bypass
WARN
27
DO
Thermal Pad
—
GND
SCL
20
SCLK
SDA
I2C data input and output
Clip and overtemperature warning (active low, open drain), 100-kΩ internal pullup resistor
Provides both electrical and thermal connection for the device. Heatsink must be connected to
GND.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
–0.3
30
V
–1
40
V
75
V/ms
–0.3
3.5
V
Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND)
±8
A
IMAX_PULSED
Pulsed supply current per PVDD pin (one shot)
±12
A
VLOGIC
Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK, BCLK, LRCLK, MUTE,
STANDBY, I2C_ADDRx)
VDD + 0.5
V
VGND
Maximum voltage between GND pins
±0.3
V
TJ
Maximum operating junction temperature
–55
150
°C
Tstg
Storage temperature
–55
150
°C
PVDD, VBAT
DC supply voltage relative to GND
VMAX
Transient supply voltage: PVDD, VBAT
VRAMP
Supply-voltage ramp rate: PVDD, VBAT
VDD
DC supply voltage relative to GND
IMAX
t ≤ 400 ms exposure
t < 100 ms
–0.3
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100–002 (1)
V(ESD)
(1)
6
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100–011
UNIT
±3000
All pins
±500
Corner pins (1, 28, 29 and 56)
±1000
V
AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.
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7.3 Recommended Operating Conditions
MIN
PVDD
Output FET supply voltage
Relative to GND
4.5
VBAT
Battery supply voltage input
Relative to GND
4.5
VDD
DC logic supply
Relative to GND
3.0
TA
Ambient temperature
An adequate thermal design is
required
NOM
MAX
UNIT
18
V
14.4
18
V
3.3
3.5
V
–40
125
°C
–40
150
°C
TJ
Junction temperature
RL
Nominal speaker load impedance
RPU_I2C
I2C pullup resistance on SDA and SCL pins
CBypass
External capacitance on bypass pins
Pin 2, 3, 5, 6, 8, 9, 10, 19
1
COUT
External capacitance to GND on OUT pins
Limit set by DC-diagnostic timing
1
BTL Mode
2
4
PBTL Mode
1
2
1
4.7
Ω
10
kΩ
µF
3.3
µF
7.4 Thermal Information
THERMAL METRIC
(1)
TAS6424L-Q1 (2)
TAS6424L-Q1 (3)
DKQ (HSSOP)
DKQ (HSSOP)
56 PINS
56 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
—
—
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.7
1.1
°C/W
RθJB
Junction-to-board thermal resistance
—
—
°C/W
ψJT
Junction-to-top characterization parameter
—
—
°C/W
ψJB
Junction-to-board characterization parameter
10
10
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
JEDEC Standard 4 Layer PCB.
Measured using the TAS6424L-Q1 EVM layout and heat sink. The device is not intended to be used without a heat sink.
7.5 Electrical Characteristics
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 59 and Figure 62
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
IPVDD_IDLE
PVDD idle current
All channels playing, no audio input
75
90
mA
IVBAT_IDLE
VBAT idle current
All channels playing, no audio input
90
100
mA
IPVDD_STBY
PVDD standby current
STANDBYActive, VDD = 0 V
1
10
μA
IVBAT_STBY
VBAT standby current
STANDBYActive, VDD = 0 V
4
10
μA
IVDD
VDD supply current
All channels playing, –60-dB signal
15
18
mA
OUTPUT POWER
PO_BTL
PO_PBTL
EFFP
Output power per channel, BTL
Output power per channel in parallel mode,
PBTL
Power efficiency
4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
20
22
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
25
27
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
20
22
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
25
27
4 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C
30
33
4 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C
40
45
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
35
40
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
45
50
1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
50
52
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
60
62
2 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C
60
65
2 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C
75
80
4 channels operating, 25-W output power/ch 4-Ω load, PVDD
= 14.4 V, TC = 25°C, including indcutor losses(1)
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 59 and Figure 62
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
Vn
Output noise voltage
Zero input, A-weighting, gain level 1, PVDD = 14.4 V
42
Zero input, A-weighting, gain level 2, PVDD = 14.4 V
55
Zero input, A-weighting, gain level 3, PVDD = 18 V
67
Zero input, A-weighting, gain level 4, PVDD = 25 V
85
Gain level 1, Register 0x01, bit 1-0 = 00
7.5
Gain level 2, Register 0x01, bit 1-0 = 01
15
Gain level 3, Register 0x01, bit 1-0 = 10
21
GAIN
Peak output voltage/dBFS
Crosstalk
Channel crosstalk
PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz
-90
PSRR
Power-supply rejection ratio
PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz
75
Gain level 4, Register 0x01, bit 1-0 = 11
THD+N
Total harmonic distortion + noise
GCH
Channel-to-channel gain variation
μV
V/FS
29
–0.5
-75
dB
dB
0.02%
0.05
%
0
0.5
dB
LINE OUTPUT PERFORMANCE
Vn_LINEOUT
LINE output noise voltage
Zero input, A-weighting, channel set to LINE MODE
42
μV
VO_LINEOUT
LINE output voltage
0-dB input, channel set to LINE MODE
5.5
VRMS
THD+N
Line output total harmonic distortion + noise
VO = 2 VRMS , channel set to LINE MODE
0.01%
0.03
%
DIGITAL INPUT PINS
VIH
Input logic level high
VIL
Input logic level low
70
IIH
Input logic current, high
VI = VDD
IIL
Input logic current, low
VI = 0
%VDD
30
%VDD
15
µA
–15
µA
PWM OUTPUT STAGE
RDS(on)
FET drain-to-source resistance
Not including bond wire and package resistance
90
mΩ
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV
PVDD overvoltage shutdown
VPVDD_OV_HY
PVDD overvoltage shutdown hysteresis
19.3
20
22
0.8
V
V
S
VVBAT_OV
VBAT overvoltage shutdown
VVBAT_OV_HY
VBAT overvoltage shutdown hysteresis
19.3
20
22
0.6
V
V
S
UNDERVOLTAGE (UV) PROTECTION
VBATUV
VBAT undervoltage shutdown
4
VBATUV_HYS VBAT undervoltage shutdown hysteresis
PVDDUV
PVDD undervoltage shutdown
PVDDUV_HY
PVDD undervoltage shutdown hysteresis
4.5
0.2
4
V
V
4.5
V
0.2
V
S
BYPASS VOLTAGES
VGVDD
Gate drive bypass pin voltage
7
V
VAVDD
Analog bypass pin voltage
6
V
VVCOM
Common bypass pin voltage
2.5
V
VVREG
Regulator bypass pin voltage
5.5
V
POWER-ON RESET (POR)
VPOR
VDD voltage for POR
2.1
VPOR_HY
VDD POR recovery hysteresis voltage
0.5
2.7
V
V
OVERTEMPERATURE (OT) PROTECTION
OTW(i)
Channel overtemperature warning
150
°C
OTSD(i)
Channel overtemperature shutdown
175
°C
OTW
Global junction overtemperature warning
130
°C
8
Set by register 0x01 bit 5-6, default value
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 59 and Figure 62
PARAMETER
OTSD
Global junction overtemperature shutdown
OTHYS
Overtemperature hysteresis
TEST CONDITIONS
MIN
TYP
MAX
UNIT
160
°C
15
°C
LOAD OVER CURRENT PROTECTION
ILIM
Overcurrent cycle-by-cycle limit
ISD
Overcurrent shutdown
OC Level 1
3
3
OC Level 2
4.2
4.8
OC Level 1, Any short to supply, ground, or other channels
6
OC Level 2, Any short to supply, ground, or other channels
7
A
A
MUTE MODE
GMUTE
Output attenuation
100
dB
7
mV
CLICK AND POP
VCP
Output click and pop voltage
ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z
DC OFSET
VOFFSET
Output offset voltage
2
5
Output DC fault protection
2
2.5
mV
DC DETECT
DCFAULT
V
DIGITAL OUTPUT PINS
VOH
Output voltage for logic level high
I = ±2 mA
VOL
Output voltage for logic level low
I = ±2 mA
tDELAY_CLIPD
Signal delay when output clipping detected
90
%VDD
10
%VDD
20
μs
ET
LOAD DIAGNOSTICS
S2P
Maximum resistance to detect a short from
OUT pins to PVDD
500
Ω
S2G
Maximum resistance to detect a short from
OUT pins to ground
200
Ω
SL
Shorted load detection tolerance
Other channels in Hi-Z
±0.5
Ω
OL
Open load
Other channels in Hi-Z
TDC_DIAG
DC diagnostic time
All 4 Channels
LO
Line output
TLINE_DIAG
Line output diagnostic time
ACIMP
AC impedance accuracy
TAC_DIAG
AC diagnostic time
40
70
Ω
230
ms
6
40
kΩ
ms
Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω,
25%
Offset
±0.5
Ω
All 4 Channels
520
ms
300
μs
I2C_ADDR PINS
tI2C_ADDR
Time delay needed for I2C address set-up
(1) Tested with Output Inductor DFEG7030D-3R3M.
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7.6 Timing Requirements
Test conditions (unless otherwise noted): TC = 25 °C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, PO = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 59 and Figure 62
MIN
TYP
MAX
UNIT
I2C CONTROL PORT (See Figure 22)
tBUS
Bus free time between start and stop conditions
tHOLD1
Hold time, SCL to SDA
1.3
μs
0
tHOLD2
Hold time, start condition to SCL
ns
tSTART
I2C startup time after VDD power on reset
tRISE
tFALL
tSU1
Setup, SDA to SCL
100
ns
tSU2
Setup, SCL to start condition
0.6
μs
tSU3
Setup, SCL to stop condition
0.6
μs
tW(H)
Required pulse duration SCL High
0.6
μs
tW(L)
Required pulse duration SCL Low
1.3
μs
0.6
μs
12
ms
Rise time, SCL and SDA
300
ns
Fall time, SCL and SDA
300
ns
SERIAL AUDIO PORT (See Figure 16)
DMCLK,
DSCLK
Allowable input clock duty cycle
ƒMCLK
Supported MCLK frequencies: 128, 256, or 512
ƒMCLK_Max
Maximum frequency
tSCY
SCLK pulse cycle time
40
ns
tSCL
SCLK pulse-with LOW
16
ns
tSCH
SCLK pulse-with HIGH
16
ns
trise/fall
Rise and fall time
4
ns
tSF
SCLK rising edge to FSYNC edge
8
ns
tFS
FSYNC rising edge to SCLK edge
8
ns
tDS
DATA set-up time
8
ns
tDH
DATA hold time
8
ci
Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2
TLA
Latency from input to output measured in FSYNC
sample count
10
45%
128
50%
55%
512
xFS
25
MHz
ns
10
FSYNC = 44.1 kHz or 48 kHz
30
FSYNC = 96 kHz
12
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7.7 Typical Characteristics
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see Figure 59 and Figure 62 (unless otherwise noted)
0
0
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
PSRR (dB)
Crosstalk (dB)
-20
-60
-40
-60
-80
-80
-100
-120
20
100
1k
Frequency (Hz)
10k
-100
20
20k
100
D002
PO = 1 W
D068
Figure 2. PVDD PSRR vs Frequency
10
Total Harmonic Distortion + Noise (%)
0
-20
-40
PSRR (dB)
10k
PO = 1 W
Figure 1. Crosstalk vs Frequency
-60
-80
-100
-120
20
100
1k
Frequency
10k
2 : Load
4 : Load
1
0.1
0.01
0.001
20
20k
100
D070
PO = 1 W
PO = 1 W
Figure 3. VBAT PSRR vs Frequency
1k
Frequency (Hz)
10k
20k
D006
fSW = 2.1 MHz
Figure 4. THD+N vs Frequency
10
10
2 : Load
4 : Load
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
1k
Frequency
1
0.1
0.01
0.001
20
100
PO = 1 W
1k
Frequency (Hz)
10k
20k
2 : Load
4 : Load
1
0.1
0.01
0.001
10m
D008
18 V
fSW = 2.1 MHz
Figure 5. THD+N vs Frequency
100m
1
Output Power (W)
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fSW = 2.1 MHz
Figure 6. THD+N vs Power
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Typical Characteristics (continued)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see Figure 59 and Figure 62 (unless otherwise noted)
50
Idle Channel Noise (PVrms)
2 W Load
4 W Load
Output Power (W)
40
30
20
10
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
Gain Level 1
Gain Level 2
Gain Level 3
Gain Level 4
5
0
5
7
9
11
13
Supply Voltage (V)
15
D059
10% THD
7
9
17 18
A-weighted Noise
fSW = 2.1 MHz
11
13
Supply Voltage (V)
15
17 18
D062
fSW = 2.1 MHz
Figure 8. Noise vs Supply voltage
Figure 7. Output Power vs Supply Voltage
100
95
VBAT Idle Current (mA)
PVDD Idle Current (mA)
50
40
30
20
90
85
80
75
70
65
10
60
FPWM = 2.1 MHz
6
0
5
10
Supply Voltage (V)
15
8
18
10
12
14
Supply Voltage (V)
16
18
D026
D071
Figure 10. VBAT Idle Current vs Voltage
Figure 9. PVDD Idle Current vs Voltage
5
Total Harmonic Distortion + Noise (%)
10
PVDD Idle Current (PA)
4
3
2
1
0
5
10
Supply Voltage (V)
15
18
2 : Load
4 : Load
1
0.1
0.01
0.001
20
100
D073
PO = 1 W
Figure 11. PVDD Standby Current vs Voltage
12
1k
Frequency (Hz)
10k
20k
D029
fSW = 2.1 MHz
Figure 12. PBTL THD+N vs Frequency
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Typical Characteristics (continued)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see Figure 59 and Figure 62 (unless otherwise noted)
90
2 : Load
4 : Load
2 : Load
4 : Load
80
70
1
Output Power (W)
Total Harmonic Distortion + Noise (%)
10
0.1
0.01
60
50
40
30
20
10
0.001
10m
0
100m
1
Output Power (W)
10 20
100
10
Supply Voltage (V)
5
D033
fSW = 2.1 MHz
10 % THD
Figure 13. PBTL THD+N vs Power
15
18
D079
fSW = 2.1 MHz
Figure 14. PBTL Output Power vs Voltage
8 Parameter measurement Information
The parameters for the TAS6424L-Q1 device were measured using the circuit in Figure 59.
For measurements with 2.1 MHz switching frequency the 3.3 µH inductor from the TAS6424L-Q1 EVM is used.
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9 Detailed description
9.1 Overview
The TAS6424L-Q1 device is a four-channel digital-input Class-D audio amplifier for use in the automotive
environment. The device is designed for vehicle battery operation. The design uses ultra-efficient class-D
technology developed by Texas Instruments specifically tailored for the automotive industry. This technology
allows for reduced power consumption, reduced PCB area, reduced heat, and reduced peak currents in the
electrical system. The device realizes an audio sound-system design with smaller size and lower weight than
traditional class-AB solutions.
The core design blocks are as follows:
• Serial audio port
• Clock management
• High-pass filter and volume control
• Pulse width modulator (PWM) with output stage feedback
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
9.2 Functional Block Diagram
VDD
VCOM VREG
MUTE
VBAT
GVDD
PVDD
Gate Drive
Regulator
Reference
Regulators
STANDBY
Digital Core
WARN
Closed Loop Class D Amplifier
Channel 1
Powerstage
FAULT
OUT_1M
Digital to PWM
MCLK
SCLK
Serial
Audio
Port
FSYNC
SDIN1
Volume Control
-100 to +24 dB
0.5 dB steps
Gate
Drives
Clip
Detection
SDIN2
PLL and Clock
Management
SCL
SDA
OUT_1P
2
I C Control
Channel 2
Powerstage
OUT_2P
Channel 3
Powerstage
OUT_3P
Channel 4
Powerstage
OUT_4P
Protection
DC Load Diagnostics
Overcurrent Limit
Short to GND
Overcurrent
Short to Power
Overtemperature
Open Load
Overvoltage and Undervoltage
Shorted Load
OUT_2M
OUT_3M
OUT_4M
I2C_ADDR0
I2C_ADDR1
DC Detection
AC Load Diagnostics
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9.3 Feature Description
9.3.1 Serial Audio Port
The serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats.
Settings for the serial audio port are programmed in the SAP control register (address 0x03), see the SAP
Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04] section.
Figure 15 shows the digital audio data connections for I2S and TDM8 mode for an eight channel system.
i2S
TDM8
SOC
Device A
SOC
Device A
MCLK
MCLK
MCLK
MCLK
SCLK
SCLK
SCLK
SCLK
FSYNC
FSYNC
FSYNC
FSYNC
DATA1
SDIN1
DATA
SDIN1
DATA2
SDIN2
SDIN2
DATA3
Device B
DATA4
Device B
MCLK
MCLK
SCLK
SCLK
FSYNC
FSYNC
SDIN1
SDIN1
SDIN2
SDIN2
Figure 15. Digital-Audio Data Connection
9.3.1.1
I2S Mode
I2S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when the
data is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bit
clock, SCLK, runs at 32 × fS or 64 × fS and is used to clock in the data. A delay of one bit clock occurs from the
time the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in 2scomplement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.
9.3.1.2 Left-Justified Timing
Left-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel
and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the right
channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on the
data lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge of the bit
clock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the left-right
(L/R) frame with zeros.
9.3.1.3 Right-Justified Timing
Right-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left
channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the
right channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on
the data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is always
clocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on the
rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.
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Feature Description (continued)
9.3.1.4 TDM Mode
TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM
clocks are present. The device can be configured through I2C to use different stereo pairs in the TDM data
stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.
In TDM mode, the SCLK pin must be 128 or 256, depending on the TDM slot size. In TDM mode SCLK and
MCLK can be connected together. If SCLK and MCLK are connected together than FSYNC should be minimum
2 MCLK pulses long.
In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused
SDIN2 pin (pin 16) to ground. Table 1 lists register settings for the TDM channel selection.
Table 1. TDM Channel Selection
REGISTER SETTING
TDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
1
2
3
4
5
6
7
8
0
0
CH1
CH2
CH3
CH4
—
—
—
—
1
0
—
—
—
—
CH1
CH2
CH3
CH4
0
1
CH3
CH4
CH1
CH2
—
—
—
—
1
1
—
—
—
—
CH3
CH4
CH1
CH2
If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to Table 2.
Table 2. TDM Channel Selection in PBTL Mode
REGISTER SETTING
TDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
0x21
BIT 6
1
2
3
4
5
6
7
8
0
0
0
PBTL
CH1/2
—
PBTL
CH3/4
—
—
—
—
—
1
0
0
—
—
—
—
PBTL
CH1/2
—
PBTL
CH3/4
—
0
0
1
—
PBTL
CH1/2
—
PBTL
CH3/4
—
—
—
—
1
0
1
—
—
—
—
—
PBTL
CH1/2
—
PBTL
CH3/4
0
1
0
PBTL
CH3/4
—
PBTL
CH1/2
—
—
—
—
—
1
1
0
—
—
—
—
PBTL
CH3/4
—
PBTL
CH1/2
—
0
1
1
—
PBTL
CH3/4
—
PBTL
CH1/2
—
—
—
—
1
1
1
—
—
—
—
—
PBTL
CH3/4
—
PBTL
CH1/2
9.3.1.5 Supported Clock Rates
The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.
The device supports SCLK rates of 32 × fSor 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDM
mode.
The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.
The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is
256 × fS.
The MCLK clock must not be in phase to sync to SCLK. Duty cycle of 50% is required for 128x FSYNC, for 256x
and 512x 50% duty is not required.
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9.3.1.6 Audio-Clock Error Handling
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all
channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically
returns to the state it was in. See the Timing Requirements table for timing requirements.
FSYNC
(Input)
0.5 × DVDD
tSCH
tFS
tSCL
SCLK
(Input)
0.5 × DVDD
tSCY
tSF
DATA
(Input)
0.5 × DVDD
tDS
tDH
Figure 16. Serial Audio Timing
1/fS
FSYNC
L-channel
R-channel
SCLK
Audio data word = 16 bit, SCLK = 64 fS
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 fS
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 fS
0
1
30 31
0
1
30 31
SDIN
MSB
LSB
MSB
LSB
Figure 17. Left-Justified Audio Data Format
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1/fS
FSYNC
L-channel
R-channel
SCLK
Audio data word = 16 bit, SCLK = 64 fS
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 fS
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 fS
0
1
30 31
0
1
30 31
SDIN
MSB
LSB
MSB
LSB
Figure 18. I2S Audio Data Format
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1/Fs (256 sbclks)
FSYNC
SCLK
SDIN (Left justified)
SDIN (I2S mode)
23
22
23
1
22
0
1
32 sbclks
23
0
22
23
1
22
0
1
32 sbclks
23
0
22
23
1
22
0
1
32 sbclks
23
0
22
23
1
22
0
1
32 sbclks
23
0
22
23
1
22
0
1
23
0
32 sbclks
22
23
1
22
0
1
32 sbclks
23
0
22
23
1
22
0
1
32 sbclks
23
0
22
23
1
22
0
1
23
0
22
23
22
32 sbclks
Audio Data Format: TDM8 mode
Figure 19. TDM8 Audio Data Format
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9.3.2 High-Pass Filter
Direct-current (DC) content in the audio signal can damage speakers. The data path has a high-pass filter to
remove any DC from the input signal. The corner frequency is selectable from 4 Hz, 8 Hz, or 15 Hz to 30 Hz with
bits 0 through 3 in register 0x26. The default value of –3 dB is approximately 4 Hz for 44.1 kHz or 48 kHz and
approximately 8 Hz for 96 kHz sampling rates.
9.3.3 Volume Control and Gain
Each channel has a independent digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps.
The volume control is set through I2C. The gain-ramp rate is programmable through I2C to take one step every 1,
2, 4, or 8 FSYNC cycles.
The peak output-voltage swing is also configurable in the gain control register through I2C. The four gain settings
are 7.5 V, 15 V, 21 V, and 29 V. TI recommends selecting the lowest possible for the expected PVDD operation
to optimize output noise and dynamic range performance.
9.3.4 High-Frequency Pulse-Width Modulator (PWM)
The PWM converts the PCM input data into a switched signal of varying duty cycle. The PWM modulator is an
advanced design with high bandwidth, low noise, low distortion, and excellent stability. The output switching rate
is synchronous to the serial audio-clock input and is programmed through I2C to be between 8× and 48× the
input-sample rate. The option to switch at high frequency allows the use of smaller and lower cost external
filtering components. Table 3 lists the switch frequency options for bits 4 through 6 in the miscellaneous control 2
register (address 0x02).
Table 3. Output Switch Frequency Option
INPUT SAMPLE RATE
BIT 6:4 SETTINGS
000
001
010 to 100
101
110
111
44.1 kHz
352.8 kHz
441 kHz
RESERVED
1.68 MHz
1.94 MHz
2.12 MHz
48 kHz
384 kHz
480 kHz
RESERVED
1.82 MHz
2.11 MHz
Not supported
96 kHz
384 kHz
480 kHz
RESERVED
1.82 MHz
2.11 MHz
Not supported
9.3.5 Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, powerFET stage. The device uses proprietary techniques to optimize EMI and audio performance.
The gate-driver power-supply voltage, GVDD, is internally generated and a decoupling capacitor is connected at
pin 9 and pin 10.
The full H-bridge output stages use only NMOS transistors. Therefore, bootstrap capacitors are required for the
proper operation of the high side NMOS transistors. A 1 µF ceramic capacitor of quality X7R or better, rated for
at least 16 V, must be connected from each output to the corresponding bootstrap input (see the application
circuit diagram in Figure 59). The bootstrap capacitors connected between the BST pins and corresponding
output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During
each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high keeping the highside MOSFETs turned on.
9.3.6 Power FETs
The BTL output for each channel comprises four N-channel 90-mΩ FETs for high efficiency and maximum power
transfer to the load. These FETs are designed to handle the fast switching frequency and large voltage transients
during load dump.
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9.3.7 Load Diagnostics
The device incorporates both DC-load and AC-load diagnostics which are used to determine the status of the
load. The DC diagnostics are turned on by default but if a fast startup without diagnostics is required the DC
diagnostics can be bypassed through I2C. The DC diagnostics runs when any channel is directed to leave the HiZ state and enter the MUTE or PLAY state. The DC diagnostics can also be enabled manually to run on any or
all channels. DC Diagnostics can be started from any operating condition but if the channel is in play state then
the time to complete the diagnostic is longer because the device must ramp down the audio signal of that
channel before transitioning to the Hi-Z state. The DC diagnostics are available as soon as the device supplies
are within the recommended operating range. The DC diagnostics do not rely on the audio input clocks to be
available to function. DC Diagnostic results are reported for each channel separately through the I2C registers.
9.3.7.1 DC Load Diagnostics
The DC load diagnostics are used to verify the load connected. The DC diagnostics consists of four tests: shortto-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G tests trigger if
the impedance to GND or a power rail is below that specified in the Specifications section. The diagnostic
detects a short to vehicle battery even when the supply is boosted. The SL test has an I2C-configurable threshold
depending on the expected load to be connected. Because the speakers connected to each channel might be
different, each channel can be assigned a unique threshold value. The OL test reports if the select channel has a
load impedance greater than the limits in the Specifications section.
Open Load
Open Load Detected
OL Maximum
Open Load (OL)
Detection Threshold
Normal or Open Load
May Be Detected
OL Minimum
Normal Load
Play Mode
SL Maximum
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
SL Minimum
Shorted Load
Shorted Load Detected
Figure 20. DC Load Diagnostic Reporting Thresholds
9.3.7.2 Line Output Diagnostics
The device also includes an optional test to detect a line-output load. A line-output load is a high-impedance load
that is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OL
condition is detected on a channel, if the line output detection bit is also set, the channel checks if a line-output
load is present as well. This test is not pop free, so if an external amplifier is connected it should be muted.
9.3.7.3 AC Load Diagnostics
The AC load diagnostic is used to determine the proper connection of a capacitively coupled speaker or tweeter
when used with a passive crossover. The AC load diagnostic is controlled through I2C. The AC diagnostics
requires an external input signal and reports the approximate load impedance and phase. The selected signal
frequency should create current flow through the desired speaker for proper detection. If multiple channels must
be tested, the diagnostics should be run in series. The AC load-diagnostic test procedure is as follows.
For load-impedance detection, use the following test procedure:
1. Set the channels to be tested into the Hi-Z state.
2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
3. Apply a full-scale input signal from the DSP for the tested channels with the desired frequency
(recommended 10 kHz to 20 kHz).
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NOTE
The device ramps the signal up and down automatically to prevent pops and clicks.
4. Set the device into the AC diagnostic mode (set bits 3:0 in register 0x15 to 1 for CH1 to CH4, set bit 3 in
register 0x15 to 1, and set bit 1 in register 0x15 to 1 for PBTL12 and PBTL34).
5. Read back the AC impedance (register 0x17 through register 0x1A).
When the test is complete the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
For loopback delay detection, use the following test procedure for either BTL mode or PBTL mode:
• BTL mode
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Apply a 0-dBFS 19K signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop of
CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register
0x15 to 1)
3. Read back the AC_LDG_PHASE1 value (register 0x1B and register 0x1C).
•
When the test is complete, the channel reporting register indicates the status change from the AC
diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
PBTL mode
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL
mode only for load diagnostics.
3. Apply a 0 dBFS 19K signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing loop of
CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in
register 0x15 to 1).
4. Read back the AC_LDG_PHASE1 (register 0x1B and register 0x1C).
5. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 1 to go back to PBTL mode for load
diagnostics.
Table 4. AC Impedance Code to Magnitude
SETTING
GAIN AT 19 kHz
I(A)
MEASUREMENT RANGE
(Ω)
MAPPING FROM CODE
TO MAGNITUDE
(Ω/Code)
Gain = 4, I = 10 mA
(recommended)
4.28
0.01
12
0.05832
Gain = 4, I = 19 mA
4.28
0.019
6
0.0307
Gain = 1, I = 10 mA
(recommended)
1
0.01
48
0.2496
Gain = 1, I = 19 mA
1
0.019
24
0.1314
9.3.8 Protection and Monitoring
9.3.8.1 Overcurrent Limit (ILIMIT)
The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (ILIMIT) is
exceeded. Power is limited but operation continues without disruption and prevents undesired shutdown for
transient music events. ILIMIT is not reported as a fault condition to either registers or the FAULT pin. Each
channel is independently monitored and limited. The two programable levels can be set by bit 4 in the
miscellaneous control 1 register (address 0x01).
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9.3.8.2 Overcurrent Shutdown (ISD)
If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs which
shuts down the channel. The time to shutdown the channel varies depending on the severity of the short
condition. The affected channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT
pin is asserted. If the diagnostics are enabled then the device automatically starts diagnostics on the channel
and, if no load failure is found, the device restarts. If a load fault is found the device continues to rerun the
diagnostics once per second. Because this hiccup mode is using the diagnostics, no high current is created. If
the diagnostics are disabled the device sets the state for that channel to Hi-Z and requires the MCU to take the
appropriate action.
Two programable levels can be set by bit 4 in the miscellaneous control 1 register (address 0x01).
9.3.8.3 DC Detect
This circuit detects a DC offset continuously during normal operation at the output of the amplifier. If the DC
offset exceeds the threshold, that channel is placed in the Hi-Z state, the fault is reported to the I2C register, and
the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.
9.3.8.4 Clip Detect
The clip detect is reported on the WARN pin if 100% duty-cycle PWM if reached for a minimum of 20 cycles. If
any channel is clipping, the clipping is reported to the pin. The clip detect is latched and can be cleared by I2C .
Masking the clip reporting to the pin is possible through I2C.
9.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
Four overtemperature warning levels are available in the device that can be selected (see the Register Maps
section for thresholds). When the junction temperature exceeds the warning level, the WARN pin is asserted
unless the mask bit has been set to disable reporting. The device functions until the OTSD value is reached at
which point all channels are placed in the Hi-Z state and the FAULT pin is asserted. When the junction
temperature returns to normal levels, the device automatically recovers and places all channels into the state
indicated by the register settings.
9.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
In addition to the global OTW, each channel also has an individual overtemperature warning and shutdown. If a
channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted unless the
mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then that
channel goes to the Hi-Z state until the temperature drops below the OTW(i) threshold at which point the channel
goes to the state indicated by the state control register.
9.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV
condition, the FAULT pin is asserted and the I2C register is updated. A power-on reset (POR) on the VDD pin
causes the I2C to goes to the high-impedance (Hi-Z) state and all registers are reset to default values. At poweron or after a POR event, the POR warning bit and WARN pin are asserted.
9.3.8.8 Overvoltage (OV) and Load Dump
The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV
threshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40 V load-dump
voltage spikes.
9.3.9 Power Supply
The device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows:
VDD
This pin is a 3.3V supply pin that provides power to the low voltage circuitry.
VBAT
This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated
voltage rail in a boosted system within the recommended limits. For best performance, this rail
should be 10 V or higher. See the Recommended Operating Conditions table for the maximum
supply voltage. This supply rail is used for higher voltage analog circuits but not the output FETs.
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This pin is a high-voltage supply that can either be connected to the vehicle battery or to another
voltage rail in a boosted system. The PVDD pin supplies the power to the output FETs and can be
within the recommended operating limits, even if that is below the VBAT supply, to allow for
dynamic voltage systems.
Several on-chip regulators are included generating the voltages necessary for the internal circuitry. The external
pins are provided only for bypass capacitors to filter the supply and should not be used to power other circuits.
The device can withstand fortuitous open ground and power conditions within the absolute maximum ratings for
the device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a
second ground path through the body diode in the output FETs.
9.3.9.1 Vehicle-Battery Power-Supply Sequence
The device can accept any sequence of the VBAT, PVDD and VDD supply.
In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the
same time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommended
operating range. When removing power from the device, TI recommends to deassert the VDD supply first then
the VBAT, PVDD, or both supplies which provides the lowest click and pop performance.
9.3.10 Hardware Control Pins
The device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.
9.3.10.1 FAULT
The FAULT pin reports faults and is active low under any of the following conditions:
• Any channel faults (overcurrent or DC detection)
• Overtemperature shutdown
• Overvoltage or undervoltage conditions on the VBAT or PVDD pins
• Clock errors
The FAULT pin is deactivated when none of the previously listed conditions exist.
Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the
setting of the pin and do not affect the register reporting or protection of the device. By default all faults are
reported to the pin. See the Register Maps section for a description of the mask settings.
This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.
9.3.10.2 WARN
This active-low output pin reports audio clipping, overtemperature warnings, and POR events.
Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks which results in
a 10-µs delay to report the onset of clipping. The warning bit is sticky and can be cleared by the CLEAR FAULT
bit (bit 7) in register 0x21.
An overtemperature warning (OTW) is reported if the general temperature or any of the channel temperature
warnings are set. The warning temperature can be set through bits 5 and 6 in register 0x01.
Register bits are available to mask either clipping or OTW reporting to the pin. These bits only mask the setting
of the pin and do not affect the register reporting. By default both clipping and OTW are reported.
The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.
This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.
9.3.10.3 MUTE
This active-low input pin is used for hardware control of the mute and unmute function for all channels.
This pin has a 100 kΩ internal pulldown resistor.
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9.3.10.4 STANDBY
When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin
can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not
already in the Hi-Z state. The I2C bus goes into the high-impedance (Hi-Z) state when in STANDBY.
This pin has a 100 kΩ internal pulldown resistor.
9.4 Device Functional Modes
9.4.1 Operating Modes and Faults
The operating modes and faults are listed in the following tables.
Table 5. Operating Modes
STATE NAME
OUTPUT FETS
OSCILLATOR
I2C
STANDBY
Hi-Z
Stopped
Stopped
Hi-Z
Hi-Z
Active
Active
MUTE
Switching at 50%
Active
Active
PLAY
Switching with audio
Active
Active
Table 6. Global Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
RESULT
All
I2C + WARN pin
Standby
Hi-Z, mute, normal
I2C + FAULT pin
Hi-Z
POR
VBAT UV
Voltage fault
PVDD UV
VBAT or PVDD OV
OTW
Thermal warning
Hi-Z, mute, normal
I2C + WARN pin
None
OTSD
Thermal shutdown
Hi-Z, mute, normal
I2C + FAULT pin
Hi-Z
Table 7. Channel Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
Clipping
Warning
Overcurrent limiting
Protection
Overcurrent fault
DC detect
MONITORING
MODES
REPORTING
METHOD
WARN pin
Mute and play
I2C + FAULT pin
Output channel fault
ACTION
TYPE
None
Current limit
Hi-Z
9.5 Programming
9.5.1 I2C Serial Communication Bus
The device communicates with the system processor through the I2C serial communication bus as an I2C slaveonly device. The processor can poll the device through I2C to determine the operating status, configure settings,
or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.
The device includes two I2C address pins, so up to four devices can be used together in a system with no
additional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in Table 8.
Table 8. I2C Addresses
I2C ADDR1
I2C ADDR0
I2C Write
I2C Read
Device 0
0
0
0xD4
0xD5
Device 1
0
1
0xD6
0xD7
Device 2
1
0
0xD8
0xD9
Device 3
1
1
0xDA
0xDB
DESCRIPTION
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9.5.2 I2C Bus Protocol
The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. The
TAS6424L-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit
slave address and the read/write (R/W) bit to open communication with another device and then wait for an
acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and
SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start and
stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the
bus.
R/
A
W
7-Bit Slave Address
SDA
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data for
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data for
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
Figure 21. Typical I2C Sequence
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
Figure 22. SCL and SDA Timing
Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using
single-byte or multiple-byte data transfers.
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9.5.3 Random Write
As shown in Figure 23, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data
transfer. For a write data transfer, the R/W bit is a 0. After receiving the correct I2C device address and the R/W
bit, the device responds with an acknowledge bit. Next, the master transmits the address byte or bytes
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4 A3
A2
A1
A0 R/W ACK A7
Acknowledge
A6
A5
I2C Device Address
and R/W Bit
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
D5 D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
Figure 23. Random Write Transfer
9.5.4 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in Figure 24. After receiving each data byte, the device
responds with an acknowledge bit and the I2C subaddress is automatically incremented by one.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
I2C Device Address
and R/W Bit
A4
A5
A3
A1
Subaddress
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Byte
Last Data Byte
Stop
Condition
Figure 24. Sequential Write Transfer
9.5.5 Random Read
As shown in Figure 25, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by
a read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be
read. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an
acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1,
indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an
acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte data-read transfer.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address
and R/W Bit
A6
A5
A4
Subaddress
A0 ACK
A6
Not
Acknowledge
Acknowledge
A5
A1 A0 R/W ACK D7 D6
I2C Device Address
and R/W Bit
D0 D6 ACK
Data Byte
Stop
Condition
Figure 25. Random Read Transfer
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9.5.6 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in Figure 26. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge bit followed
by a stop condition to complete the transfer.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address
and R/W Bit
A6
A5
Subaddress
A0 ACK
A6
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I2C Device Address
and R/W Bit
First Data Byte
Other Data Byte
Last Data Byte
Stop
Condition
Figure 26. Sequential Read Transfer
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9.6 Register Maps
Table 9. I2C Address Register Definitions
Address
Type
0x00
R/W
Mode control
Register Description
Section
Go
0x01
R/W
Miscellaneous control 1
Go
0x02
R/W
Miscellaneous control 2
Go
0x03
R/W
SAP control (serial audio-port control)
Go
0x04
R/W
Channel state control
Go
0x05
R/W
Channel 1 volume control
Go
0x06
R/W
Channel 2 volume control
Go
0x07
R/W
Channel 3 volume control
Go
0x08
R/W
Channel 4 volume control
Go
0x09
R/W
DC diagnostic control 1
Go
0x0A
R/W
DC diagnostic control 2
Go
0x0B
R/W
DC diagnostic control 3l
Go
0x0C
R
DC load diagnostic report 1 (channels 1 and 2)
Go
0x0D
R
DC load diagnostic report 2 (channels 3 and 4)
Go
0x0E
R
DC load diagnostic report 3-line output
Go
0x0F
R
Channel state reporting
Go
0x10
R
Channel faults (overcurrent, DC detection)
Go
0x11
R
Global faults 1
Go
0x12
R
Global faults 2
Go
0x13
R
Warnings
Go
0x14
R/W
Pin control
Go
0x15
R/W
AC load diagnostic control 1
Go
0x16
R/W
AC load diagnostic control 2
Go
0x17
R
AC load diagnostic report channel 1
Go
0x18
R
AC load diagnostic report channel 2
Go
0x19
R
AC load diagnostic report channels 3
Go
0x1A
R
AC load diagnostic report channels 4
Go
0x1B
R
AC load diagnostic phase report high
Go
0x1C
R
AC load diagnostic phase report low
Go
0x1D
R
AC load diagnostic STI report high
Go
0x1E
R
AC load diagnostic STI report low
Go
0x1F
R
RESERVED
0x20
R
RESERVED
0x21
R/W
Miscellaneous control 3
Go
0x22
R/W
Clip control
Go
0x23
R/W
Clip window
Go
0x24
R/W
Clip warning
Go
0x25
R/W
ILIMIT status
Go
0x26
R/W
Miscellaneous control 4
Go
0x27
R
RESERVED
0x28
R/W
RESERVED
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9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
The Mode Control register is shown in Figure 27 and described in Table 10.
Figure 27. Mode Control Register
7
RESET
R/W-0
6
RESERVED
R/W-0
5
PBTL CH34
R/W-0
4
PBTL CH12
R/W-0
3
2
1
0
CH1 LO MODE CH2 LO MODE CH3 LO MODE CH4 LO MODE
R/W-0
R/W-0
R/W-0
R/W-0
Table 10. Mode Control Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0
0: Normal operation
6
RESERVED
R/W
0
RESERVED
5
PBTL CH34
R/W
0
0: Channels 3 and 4 are in BTL mode
4
PBTL CH12
R/W
0
3
CH1 LO MODE
R/W
0
2
CH2 LO MODE
R/W
0
1
CH3 LO MODE
R/W
0
1: Resets the device
1: Channels 3 and 4 are in parallel BTL mode
0: Channels 1 and 2 are in BTL mode
1: Channels 1 and 2 are in parallel BTL mode
0: Channel 1 is in normal/speaker mode
1: Channel 1 is in line output mode
0: Channel 2 is in normal/speaker mode
1: Channel 2 is in line output mode
0: Channel 3 is in normal/speaker mode
1: Channel 3 is in line output mode
0
CH4 LO MODE
R/W
0
0: Channel 4 is in normal/speaker mode
1: Channel 4 is in line output mode
9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
The Miscellaneous Control 1 register is shown in Figure 28 and described in Table 11.
Figure 28. Miscellaneous Control 1 Register
7
HPF BYPASS
R/W-0
6
5
OTW CONTROL
R/W-01
4
OC CONTROL
R/W-1
3
2
VOLUME RATE
R/W-00
1
0
GAIN
R/W-10
Table 11. Misc Control 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
HPF BYPASS
R/W
0
0: High pass filter eneabled
OTW CONTROL
R/W
01
1: High pass filter disabled
6–5
00: Global overtemperature warning set to 140°C
01: Global overtemperature warning set to 130C
10: Global overtemperature warning set to 120°C
11: Global overtemperature warning set to 110°C
4
OC CONTROL
R/W
1
3–2
VOLUME RATE
R/W
00
0: Overcurrent is level 1
1: Overcurrent is level 2
00: Volume update rate is 1 step / FSYNC
01: Volume update rate is 1 step / 2 FSYNCs
10: Volume update rate is 1 step / 4 FSYNCs
11: Volume update rate is 1 step / 8 FSYNCs
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Table 11. Misc Control 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1–0
GAIN
R/W
10
00: Gain level 1 = 7.6 V peak output voltage
01: Gain Level 2 = 15 V peak output voltage
10: Gain Level 3 = 21 V peak output voltage
11: Gain Level 4 = 29 V peak output voltage
9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
The Miscellaneous Control 2 register is shown in Figure 29 and described in Table 12.
Figure 29. Miscellaneous Control 2 Register
7
RESERVED
6
5
PWM FREQUENCY
R/W-110
4
3
RESERVED
2
SDM_OSR
R/W-0
1
0
OUTPUT PHASE
R/W-10
Table 12. Misc Control 2 Field Descriptions
Bit
7
6–4
Field
Type
Reset
R/W
110
RESERVED
Description
0
PWM FREQUENCY
000: 8 × fS (352.8 kHz / 384 kHz)
001: 10 × fS (441 kHz / 480 kHz)
010: RESERVED
011: RESERVED
100: RESERVED
101: 38 × fS (1.68 MHz / 1.82 MHz)
110: 44 × fS (1.94 MHz / 2.11 MHz)
111: 48 × fS (2.12 MHz / not supported)
3
RESERVED
2
SDM_OSR
OUTPUT PHASE
0
0
R/W
0
0: 64x OSR
R/W
10
1: 128x OSR
1–0
00: 0 degrees output-phase switching offset
01: 30 degrees output-phase switching offset
10: 45 degrees output-phase switching offset
11: 60 degrees output-phase switching offset
9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
The SAP Control (serial audio-port control) register is shown in Figure 30 and described in Table 13.
Figure 30. SAP Control Register
7
6
INPUT SAMPLING RATE
R/W-00
5
8 Ch TDM
SLOT SELECT
R/W-0
4
TDM SLOT
SIZE
R/W-0
3
TDM SLOT
SELECT 2
R/W-0
2
1
INPUT FORMAT
0
R/W-100
Table 13. SAP Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
INPUT SAMPLING RATE
R/W
00
00: 44.1 kHz
01: 48 kHz
10: 96 kHz
11: RESERVED
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Table 13. SAP Control Field Descriptions (continued)
Bit
5
Field
Type
Reset
Description
8 Ch TDM SLOT SELECT
R/W
0
0: First four TDM slots
1: Last four TDM slots
4
TDM SLOT SIZE
R/W
0
0: TDM slot size is 24-bit or 32-bit
1: TDM slot size is 16-bit
3
TDM SLOT SELECT 2
R/W
0
0: Normal
1: swap channel 1/2 with channel 3/4
2–0
INPUT FORMAT
R/W
100
000: 24-bit right justified
001: 20-bit right justified
010: 18-bit right justified
011: 16-bit right justified
100: I2S (16-bit or 24-bit)
101: Left justified (16-bit or 24-bit)
110: DSP mode (16-bit or 24-bit)
111: RESERVED
9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
The Channel State Control register is shown in Figure 31 and described in Table 14.
Figure 31. Channel State Control Register
7
6
CH1 STATE CONTROL
R/W-01
5
4
CH2 STATE CONTROL
R/W-01
3
2
CH3 STATE CONTROL
R/W-01
1
0
CH4 STATE CONTROL
R/W-01
Table 14. Channel State Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
CH1 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
5–4
CH2 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
3–2
CH3 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
1–0
CH4 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
32
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9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
The Channel 1 Through 4 Volume Control registers are shown in Figure 32 and described in Table 15.
Figure 32. Channel x Volume Control Register
7
6
5
4
3
2
1
0
CH x VOLUME
R/W-CF
Table 15. Ch x Volume Control Field Descriptions
Bit
Field
Type
Reset
Description
7–0
CH x VOLUME
R/W
CF
8-Bit Volume Control for each channel, register address for Ch1
is 0x05, Ch2 is 0x06, Ch3 is 0x07 and Ch4 is 0x08, 0.5 dB/step:
0xFF: 24 dB
0xCF: 0 dB
0x07: –100 dB
< 0x07: MUTE
9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
The DC Diagnostic Control 1 register is shown in Figure 33 and described in Table 16.
Figure 33. DC Load Diagnostic Control 1 Register
7
DC LDG
ABORT
R/W-0
6
2x_RAMP
5
2x_SETTLE
R/W-0
R/W-0
4
3
RESERVED
2
1
LDG LO
ENABLE
R/W-0
0
LDG BYPASS
R/W-0
Table 16. DC Load Diagnostics Control 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
DC LDG ABORT
R/W
0
0: Default state, clear after abort
1: Aborts the load diagnostics in progress
6
2x_RAMP
R/W
0
5
2x_SETTLE
R/W
0
4–2
RESERVED
0: Normal ramp time
1: Double ramp time
0: Normal Settle time
1: Double settling time
0
0
0: Line output diagnostics are disabled
1
LDG LO ENABLE
R/W
0
0
LDG BYPASS
R/W
0
1: Line output diagnostics are enabled
0: Automatic diagnostics when leaving Hi-Z and after
channel fault
1: Diagnostics are not run automatically
9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
The DC Diagnostic Control 2 register is shown in Figure 34 and described in Table 17.
Figure 34. DC Load Diagnostic Control 2 Register
7
6
5
CH1 DC LDG SL
R/W-0001
4
3
2
1
CH2 DC LDG SL
R/W-0001
0
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Table 17. DC Load Diagnostics Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7–4
CH1 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3–0
CH2 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
The DC Diagnostic Control 3 register is shown in Figure 35 and described in Table 18.
Figure 35. DC Load Diagnostic Control 3 Register
7
6
5
CH3 DC LDG SL
R/W-0001
4
3
2
1
CH4 DC LDG SL
R/W-0001
0
Table 18. DC Load Diagnostics Control 3 Field Descriptions
Bit
Field
Type
Reset
Description
7–4
CH3 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3–0
CH4 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
DC Load Diagnostic Report 1 register is shown in Figure 36 and described in Table 19.
Figure 36. DC Load Diagnostic Report 1 Register
7
CH1 S2G
R-0
6
CH1 S2P
R-0
5
CH1 OL
R-0
4
CH1 SL
R-0
3
CH2 S2G
R-0
2
CH2 S2P
R-0
1
CH2 OL
R-0
0
CH2 SL
R-0
Table 19. DC Load Diagnostics Report 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
CH1 S2G
R
0
0: No short-to-GND detected
1: Short-To-GND Detected
34
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Table 19. DC Load Diagnostics Report 1 Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
CH1 S2P
R
0
0: No short-to-power detected
1: Short-to-power detected
5
CH1 OL
R
0
0: No open load detected
1: Open load detected
4
CH1 SL
R
0
0: No shorted load detected
1: Shorted load detected
3
CH2 S2G
R
0
2
CH2 S2P
R
0
1
CH2 OL
R
0
0
CH2 SL
R
0
0: No short-to-GND detected
1: Short-to-GND detected
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
The DC Load Diagnostic Report 2 register is shown in Figure 37 and described in Table 20.
Figure 37. DC Load Diagnostic Report 2 Register
7
CH3 S2G
R-0
6
CH3 S2P
R-0
5
CH3 OL
R-0
4
CH3 SL
R-0
3
CH4 S2G
R-0
2
CH4 S2P
R-0
1
CH4 OL
R-0
0
CH4 SL
R-0
Table 20. DC Load Diagnostics Report 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3 S2G
R
0
0: No short-to-GND detected
6
CH3 S2P
R
0
5
CH3 OL
R
0
1: Short-to-GND detected
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
4
CH3 SL
R
0
0: No shorted load detected
1: Shorted load detected
3
CH4 S2G
R
0
0: No short-to-GND detected
1: Short-to-GND detected
2
CH4 S2P
R
0
1
CH4 OL
R
0
0
CH4 SL
R
0
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
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9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
The DC Load Diagnostic Report, Line Output, register is shown in Figure 38 and described in Table 21.
Figure 38. DC Load Diagnostics Report 3 Line Output Register
7
6
5
4
3
CH1 LO LDG
R-0
RESERVED
2
CH2 LO LDG
R-0
1
CH3 LO LDG
R-0
0
CH4 LO LDG
R-0
Table 21. DC Load Diagnostics Report 3 Line Output Field Descriptions
Bit
Field
7–4
RESERVED
Type
Reset
3
CH1 LO LDG
R
0
2
CH2 LO LDG
R
0
1
CH3 LO LDG
R
0
0
CH4 LO LDG
R
0
Description
0
0: No line output detected on channel 1
1: Line output detected on channel 1
0: No line output detected on channel 2
1: Line output detected on channel 2
0: No line output detected on channel 3
1: Line output detected on channel 3
0: No line output detected on channel 4
1: Line output detected on channel 4
9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
The Channel State Reporting register is shown in Figure 39 and described in Table 22.
Figure 39. Channel State-Reporting Register
7
6
CH1 STATE REPORT
R-01
5
4
CH2 STATE REPORT
R-01
3
2
CH3 STATE REPORT
R-01
1
0
CH4 STATE REPORT
R-01
Table 22. State-Reporting Field Descriptions
Bit
Field
Type
Reset
Description
7–6
CH1 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
5–4
CH2 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
3–2
CH3 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
1–0
CH4 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
36
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9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
The Channel Faults (overcurrent, DC detection) register is shown in Figure 40 and described in Table 23.
Figure 40. Channel Faults Register
7
CH1 OC
R-0
6
CH2 OC
R-0
5
CH3 OC
R-0
4
CH4 OC
R-0
3
CH1 DC
R-0
2
CH2 DC
R-0
1
CH3 DC
R-0
0
CH4 DC
R-0
Table 23. Channel Faults Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 OC
R
0
0: No overcurrent fault detected
6
CH2 OC
R
0
5
CH3 OC
R
0
4
CH4 OC
R
0
3
CH1 DC
R
0
2
CH2 DC
R
0
1
CH3 DC
R
0
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
0
CH4 DC
R
0
0: No DC fault detected
1: DC fault detected
9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
The Global Faults 1 register is shown in Figure 41 and described in Table 24.
Figure 41. Global Faults 1 Register
7
6
RESERVED
5
4
INVALID
CLOCK
R-0
3
PVDD OV
2
VBAT OV
1
PVDD UV
0
VBAT UV
R-0
R-0
R-0
R-0
Table 24. Global Faults 1 Field Descriptions
Bit
Field
7–5
RESERVED
Type
Reset
Description
0
0
0: No clock fault detected
4
INVALID CLOCK
R
0
3
PVDD OV
R
0
2
VBAT OV
R
0
1
PVDD UV
R
0
1: Clock fault detected
0: No PVDD overvoltage fault detected
1: PVDD overvoltage fault detected
0: No VBAT overvoltage fault detected
1: VBAT overvoltage fault detected
0: No PVDD undervoltage fault detected
1: PVDD undervoltage fault detected
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Table 24. Global Faults 1 Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
VBAT UV
R
0
0: No VBAT undervoltage fault detected
1: VBAT undervoltage fault detected
9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
The Global Faults 2 register is shown in Figure 42 and described in Table 25.
Figure 42. Global Faults 2 Register
7
6
RESERVED
5
4
OTSD
R-0
3
CH1 OTSD
R-0
2
CH2 OTSD
R-0
1
CH3 OTSD
R-0
0
CH4 OTSD
R-0
Table 25. Global Faults 2 Field Descriptions
Bit
Field
Type
7–5
RESERVED
Reset
Description
0
4
OTSD
R
0
3
CH1 OTSD
R
0
2
CH2 OTSD
R
0
1
CH3 OTSD
R
0
0
CH4 OTSD
R
0
0: No global overtemperature shutdown
1: Global overtemperature shutdown
0: No overtemperature shutdown on Ch1
1: Overtemperature shutdown on Ch1
0: No overtemperature shutdown on Ch2
1: Overtemperature shutdown on Ch2
0: No overtemperature shutdown on Ch3
1: Overtemperature shutdown on Ch3
0: No overtemperature shutdown on Ch4
1: Overtemperature shutdown on Ch4
9.6.17 Warnings Register (address = 0x13) [default = 0x20]
The Warnings register is shown in Figure 43 and described in Table 26.
Figure 43. Warnings Register
7
6
RESERVED
5
VDD POR
R-0
4
OTW
R-0
3
OTW CH1
R-0
2
OTW CH2
R-0
1
OTW CH3
R-0
0
OTW CH4
R-0
Table 26. Warnings Field Descriptions
Bit
Field
7 -6
RESERVED
5
VDD POR
Type
R
Reset
Description
00
0
0
0: No VDD POR has occurred
1 VDD POR occurred
4
OTW
R
0
0: No global overtemperature warning
1: Global overtemperature warning
3
OTW CH1
R
0
0: No overtemperature warning on channel 1
1: Overtemperature warning on channel 1
2
OTW CH2
R
0
0: No overtemperature warning on channel 2
1: Overtemperature warning on channel 2
38
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Table 26. Warnings Field Descriptions (continued)
Bit
1
Field
Type
Reset
Description
OTW CH3
R
0
0: No overtemperature warning on channel 3
1: Overtemperature warning on channel 4
0
OTW CH4
R
0
0: No overtemperature warning on channel 4
1: Overtemperature warning on channel 4
9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
The Pin Control register is shown in Figure 44 and described in Table 27.
Figure 44. Pin Control Register
7
MASK OC
R/W-1
6
MASK OTSD
R/W-1
5
MASK UV
R/W-1
4
MASK OV
R/W-1
3
MASK DC
R/W-1
2
MASK ILIMIT
R/W-1
1
MASK CLIP
R/W-1
0
MASK OTW
R/W-1
Table 27. Pin Control Field Descriptions
Bit
Field
Type
Reset
Description
7
MASK OC
R/W
0
0: Report overcurrent faults on the FAULT pin
6
MASK OTSD
R/W
0
5
MASK UV
R/W
0
4
MASK OV
R/W
0
3
MASK DC
R/W
0
2
MASK ILIMIT
R/W
0
1
MASK CLIP
R/W
0
0
MASK OTW
R/W
0
1: Do not report overcurrent faults on the FAULT Pin
0: Report overtemperature faults on the FAULT pin
1: Do not report overtemperature faults on the FAULT pin
0: Report undervoltage faults on the FAULT pin
1: Do not report undervoltage faults on the FAULT pin
0: Report overvoltage faults on the FAULT pin
1: Do not report overvoltage faults on the FAULT pin
0: Report DC faults on the FAULT pin
1: Do not report DC faults on the FAULT pin
0: Report Ilimit on the FAULT pin
1: Do not report Ilimit on the FAULT pin
0: Report clipping on the WARN pin
1: Do not report clipping on the WARN pin
0: Report overtemperature warnings on the WARN pin
1: Do not report overtemperature warnings on the WARN pin
9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
The AC Load Diagnostic Control 1 register is shown in Figure 45 and described in Table 28.
Figure 45. AC Load Diagnostic Control 1 Register
7
CH1 GAIN
R/W-0
6
RESERVED
R/W-0
5
CH3 GAIN
R/W-0
4
RESERVED
R/W-0
3
CH1 ENABLE
R/W-0
2
CH2 ENABLE
R/W-0
1
CH3 ENABLE
R/W-0
0
CH4 ENABLE
R/W-0
Table 28. AC Load Diagnostic Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1, CH2, PBTL12: GAIN
R/W
0
0: Gain 1
6
RESERVED
R/W
0
1: Gain 4
0
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Table 28. AC Load Diagnostic Control 1 Field Descriptions (continued)
Bit
5
Field
Type
Reset
Description
CH3, CH4, PBTL34: GAIN
R/W
0
0: Gain 1
1: Gain 4
4
RESERVED
R/W
0
0
3
CH1 ENABLE
R/W
0
0: AC diagnostics disabled
2
CH2 ENABLE
R/W
0
1
CH3 ENABLE
R/W
0
0
CH4 ENABLE
R/W
0
1: Enable AC diagnostics
0: AC diagnostics disabled
1: Enable AC diagnostics
0: AC diagnostics disabled
1: Enable AC diagnostics
0: AC diagnostics disabled
1: Enable AC diagnostics
9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
The AC Load Diagnostic Control 2 register is shown in Figure 46 and described in Table 29.
Figure 46. AC Load Diagnostic Control 2 Register
7
AC_DIAGS_LO
OPBACK
R/W-0
6
5
RESERVED
R/W-0
4
AC TIMING
3
R/W-0
R/W-0
R/W-0
2
1
AC CURRENT
0
RESERVED
R/W-0
R/W-0
R/W-0
Table 29. AC Load Diagnostic Control 2 Field Descriptions
Bit
7
Field
Type
Reset
Description
AC_DIAGS_LOOPBACK
R/W
0
0: disable AC Diag loopback
1: Enable AC Diag loopback
6-5
RESERVED
R/W
00
00
4
AC TIMING
R/W
0
0: 32 Cycles
AC CURRENT
R/W
00
1: 64 Cycles
3-2
00: 10mA
01: 19 mA
10: RESERVED
11: RESERVED
1-0
RESERVED
R/W
00
00
9.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A)
[default = 0x00]
The AC Load Diagnostic Report Ch1 through CH4 registers are shown in Figure 47 and described in Table 30.
Figure 47. AC Load Diagnostic Impedance Report Chx Register
7
40
6
5
4
3
CHx IMPEDANCE
R-00
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Table 30. Chx AC LDG Impedance Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
CH x IMPEDANCE
R
00
8-bit AC-load diagnostic report for each channel with a step size
of 0.2496 Ω/bit (control by register 0x15 and register 0x16)
0x00: 0 Ω
0x01: 0.2496 Ω
...
0xFF: 63.65 Ω
9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
The AC Load Diagnostic Phase High value registers are shown in Figure 48 and described in Table 31.
Figure 48. AC Load Diagnostic (LDG) Phase High Report Register
7
6
5
4
3
2
1
0
AC Phase High
R-00
Table 31. AC LDG Phase High Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC Phase High
R
00
Bit 15:8
9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
The AC Load Diagnostic Phase Low value registers are shown in Figure 49 and described in Table 32.
Figure 49. AC Load Diagnostic (LDG) Phase Low Report Register
7
6
5
4
3
2
1
0
AC Phase Low
R-00
Table 32. AC LDG Phase Low Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC Phase Low
R
00
Bit 7:0
9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
The AC Load Diagnostic STI High value registers are shown in Figure 50 and described in Table 33.
Figure 50. AC Load Diagnostic (LDG) STI High Report Register
7
6
5
4
3
2
1
0
AC STI High
R-00
Table 33. AC LDG STI High Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC STI High
R
00
Bit 15:8
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9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
The AC Load Diagnostic STI Low value registers are shown in Figure 51 and described in Table 34.
Figure 51. AC Load Diagnostic (LDG) STI Low Report Register
7
6
5
4
3
2
1
0
1
RESERVED
0
AC STI Low
R-00
Table 34. Chx AC LDG STI Low Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC STI Low
R
00
Bit 7:0
9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
The Miscellaneous Control 3 register is shown in Figure 52 and described in Table 35.
Figure 52. Miscellaneous Control 3 Register
7
CLEAR FAULT
6
PBTL_CH_SEL
R/W-0
R/W-0
5
MASK ILIMIT
WARNING
R/W-0
4
RESERVED
R/W-1
3
OTSD AUTO
RECOVERY
R/W-0
2
Table 35. Misc Control 3 Field Descriptions
Bit
7
Field
Type
Reset
Description
CLEAR FAULT
R/W
0
0: Normal operation
1: Clear fault
6
PBTL_CH_SEL
R/W
0
0: PBTL normal signal source
1: PBTL flip signal source
5
MASK ILIMIT WARNING
R/W
0
4
RESERVED
R/W
0
3
OTSD AUTO RECOVERY
R/W
0
0: Report ILIMIT on the WARN pin
1: Do not report ILIMIT on the WARN pin
0: OTSD is latched
0: OTSD is autorecovery
2–0
RESERVED
0
0
9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
The Clip Detect register is shown in Figure 53 and described in Table 36.
Figure 53. Clip Control Register
7
6
5
4
RESERVED
3
2
1
0
CLIPDET_EN
R/W-1
Table 36. Clip Control Field Descriptions
Bit
Field
7-1
RESERVED
0
CLIPDET_EN
Type
Reset
Description
0
R/W
1
0: Clip detect disable
1: Clip Detect Enable
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9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
The Clip Window register is shown in Figure 54 and described in Table 37.
Figure 54. Clip Window Register
7
6
5
4
3
CLIP_WINDOW_SEL[7:1]
R/W-00001110
2
1
0
1
CH2_CLIP
R-0
0
CH1_CLIP
R-0
Table 37. Clip Window Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CLIP_WINDOW_SEL[7:1]
R/W
00010100
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001110
00010100
9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
The Clip Window register is shown in Figure 55 and described in Table 38.
Figure 55. Clip Warning Register
7
6
5
4
3
CH4_CLIP
R-0
RESERVED
2
CH3_CLIP
R-0
Table 38. Clip Warning Field Descriptions
Bit
Field
7-4
RESERVED
3
CH4_CLIP
Type
R
Reset
Description
0
RESERVED
0
0: No Clip Detect
1: Clip Detect
2
CH3_CLIP
R
0
0: No Clip Detect
1: Clip Detect
1
CH2_CLIP
R
0
0: No Clip Detect
1: Clip Detect
0
CH1_CLIP
R
0
0: No Clip Detect
1: Clip Detect
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9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
The ILIMIT Status register is shown in Figure 56 and described in Table 39.
Figure 56. ILIMIT Status Register
7
6
5
4
3
2
1
0
CH4_ILIMIT_W CH3_ILIMIT_W CH2_ILIMIT_W CH1_ILIMIT_W
ARN
ARN
ARN
ARN
R-0
R-0
R-0
R-0
RESERVED
Table 39. ILIMIT Status Field Descriptions
Bit
Reset
Description
7
Field
RESERVED
Type
0
RESERVED
6
RESERVED
0
RESERVED
5
RESERVED
0
RESERVED
4
RESERVED
0
RESERVED
3
CH4_ILIMIT_WARN
R
0
0: No ILIMIT
2
CH3_ILIMIT_WARN
R
0
1: ILIMIT Warning
0: No ILIMIT
1: ILIMIT Warning
1
CH2_ILIMIT_WARN
R
0
0: No ILIMIT
1: ILIMIT Warning
0
CH1_ILIMIT_WARN
R
0
0: No ILIMIT
1: ILIMIT Warning
9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
The Miscellaneous Control 4 register is shown in Figure 57 and described in Table 40.
Figure 57. Miscellaneous Control 4 Register
7
6
5
RESERVED
R/W-00000
4
3
2
1
HPF_CORNER[2:0]
R/W-000
0
Table 40. Misc Control 4 Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
01000
01000: DEFAULT
2-0
HPF_CORNER[2:0]
R/W
000
000: 3.7 Hz
001: 7.4 Hz
010: 15 Hz
011: 30 Hz
100: 59 Hz
101: 118 Hz
110: 235 Hz
111: 463 Hz
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TAS6424L-Q1 is a four-channel class-D digital-input audio-amplifier design for use in automotive head units
and external amplifier modules. The TAS6424L-Q1 incorporates the necessary functionality to perform in
demanding OEM applications.
10.1.1 AM-Radio Band Avoidance
AM-radio frequency interference can be avoided by setting the switching frequency of the device above the AM
band. The switching frequency options available are 38 fs, 44 fs, and 48 fs. If the switch frequency cannot be set
above the AM band, then use the two options of 8 fs and 10 fs. These options should be changed to avoid AM
active channels.
10.1.2 Parallel BTL Operation (PBTL)
The device can drive more current-paralleling BTL channels on the load side of the LC output filter. For parallel
operation, the parallel BTL mode, PBTL, must be used and the paralleled channels must have the same state in
the state control register. If the two states are not aligned the device reports a fault condition.
To set the requested channels to PBTL mode the device must be in standby mode for the commands to take
effect.
A load diagnostic is supported for PBTL channels. Paralleling on the device side of the LC output filter is not
supported.
10.1.3 Demodulation Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal.
The filter attenuates the high-frequency components of the output signals that are out of the audio band. The
design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to
meet the system THD+N requirements, the selection of the inductors used in the output filter should be carefully
considered.
10.1.4 Line Driver Applications
In many automotive audio applications, the same head unit must drive either a speaker (with several ohms of
impedance) or an external amplifier input (with several kiloohms of impedance). The design is capable of
supporting both applications and has special line-drive gain and diagnostics. Coupled with the high switching
frequency, the device is well suited for this type of application. Set the desired channel in line driver mode
through I2C register 0x00, the externally connected amplifier must have a differential impedance from 600 Ω to
4.7 kΩ for the DC line diagnostic to detect the connected external amplifier. Figure 58 shows the recommended
external amplifier input configuration.
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Application Information (continued)
Output Filter
3.3 µH
1 …F
1 nF
1 …F
1 nF
3.3 µH
External Amplifier
1 …F
600
to
4.7 k
1 …F
100 k
100 k
Figure 58. External Amplifier Input Configuration for Line Driver
10.2 Typical Applications
10.2.1 BTL Application
Figure 59 shows the schematic of a typical 4-channel solution for a head-unit application.
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Typical Applications (continued)
PVDD
Input
PVDD
1 •F
470 •F
1
1 •F
2
PVDD
3
4
5
1 •F
1 •F
7
8
1 •F
9
2.2 •F
10
2.2 •F
11
12
13
14
15
16
17
18
19
VDD
2 k•
VBAT
BST_4P
AREF
OUT_4P
VREG
VCOM
OUT_4M
AVSS
BST_4M
AVDD
GND
GVDD
BST_3P
OUT_3P
GVDD
GND
GND
OUT_3M
MCLK
BST_3M
SCLK
PVDD
FSYNC
PVDD
SDIN1
SDIN2
BST_2P
GND
OUT_2P
GND
GND
VDD
OUT_2M
2 k•
20
21
22
23
Micro
PVDD
PVDD
GND
6
DSP
PVDD
GND
24
SCL
BST_2M
SDA
GND
I2C_ADDR0
BST_1P
I2C_ADDR1
OUT_1P
MUTE
25
GND
STANDBY
26
27
28
WARN
FAULT
GND
OUT_1M
BST_1M
PVDD
PVDD
56
PVDD
1 •F
L
53
52
C
1 nF
C
1 nF
C
1 nF
C
1 nF
4•
L
51
50
10 •F
0.1 •F
55
54
1 nF
1 •F
49
48
1 •F
L
47
46
4•
L
45
44
1 •F
43
PVDD
41
1 •F
L
40
39
C
1 nF
C
1 nF
C
1 nF
C
1 nF
4•
L
38
37
10 •F
0.1 •F
42
1 •F
36
35
1 •F
L
34
33
4•
L
32
31
1 •F
30
29
PVDD
0.1 •F
10 •F
Figure 59. TAS6424L-Q1 Typical 4-Channel BTL Application Schematic
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Typical Applications (continued)
10.2.1.1 Design Requirements
Use the following requirements for this design:
• This head-unit example is focused on the smallest solution size for 4 × 25 W output power into 4 Ω with a
battery supply of 14.4 V.
• The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
• The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
10.2.1.2 Communication
All communications to the TAS6424L-Q1 are through the I2C protocol. A system controller can communicate with
the device through the SDA pins and SCL pins. The TAS6424L-Q1 is an I2C slave device and requires a master.
The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the
device is 400 kHz. If multiple TAS6424L-Q1 devices are on the same I2C bus, the I2C address must be different
for each device. Up to four TAS6424L-Q1 devices can be on the same I2C bus.
The I2C bus is shared internally.
NOTE
Complete any internal operations, such as load diagnostics, before reading the registers
for the results.
10.2.1.3 Detailed Design Procedure
10.2.1.3.1 Hardware Design
Use the following procedure for the hardware design:
• Determine the input format. The input format can be either I2S or TDM mode. The mode determines the
correct pin connections and the I2C register settings.
• Determine the power output that is required into the load. The power requirement determines the required
power-supply voltage and current. The output reconstruction-filter components that are required are also
driven by the output power.
• With the requirements, adjust the typical application schematic in Figure 59 for the input connections.
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Typical Applications (continued)
10.2.1.3.2 Digital Input and the Serial Audio Port
The TAS6424L-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left
Justified, and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The
supported frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see Table 13 for the I2C register, SAP Control,
for the complete matrix to set up the serial audio port.
NOTE
Bits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting up
all the control registers to the system requirements should be done before the device is
placed in Mute mode or Play mode. After the registers are setup, use bit 7 in register 0x21
to clear any faults. Then read the fault registers to make sure no faults are present. When
no faults are present, use register 0x04 to place the device properly into play mode.
10.2.1.3.3 Bootstrap Capacitors
The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be
sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if the
capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less
than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for
driving subwoofers that require frequencies below 30 Hz may be necessary.
10.2.1.3.4 Output Reconstruction Filter
The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off or
fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the
audio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitor
to ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduces
electromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. refer to the Class-D
LC Filter Design, (SLOA119) for a detailed description of proper component description and design of the LC
filter based upon the specified load and frequency response. The recommended low-pass cutoff frequency of the
LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency can be as high as 100
kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass cutoff frequency should be
less than 40 kHz. Certain specifications must be understood for a proper inductor. The inductance value is given
at zero current, but the TAS6424L-Q1 device will have current. Use the inductance versus current curve for the
inductor to make sure the inductance does not drop below 2 µH (for fSW = 2.1 MHz) at the maximum current
provided by the system design. The DCR of the inductor directly affects the output power of the system design.
The lower the DCR, the more power is provided to the speakers. The typical inductor DCR for a 4 Ω system is 40
to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ.
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Typical Applications (continued)
10.2.1.4 Application Curves
10
2 : Load
4 : Load
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
10
1
0.1
0.01
0.001
10m
100m
1
Output Power (W)
1 kHz
10
50
2 : Load
4 : Load
1
0.1
0.01
0.001
20
D056
PVDD = 14.4 V
Figure 60. THD vs Output Power
100
1k
Frequency (Hz)
1W
10k
20k
D006
PVDD = 14.4 V
Figure 61. THD vs Frequency
10.2.2 PBTL Application
Figure 62 shows a schematic of a typical 2-channel solution for a head unit or external amplifier application
where high power into 2 Ω is required.
To operate in PBTL mode the output stage must be paralleled according to the schematic in Figure 62. The
device can operate in a mix of PBTL and BTL mode. This application can be set up for 3-channels, with one
channel in PBTL mode and two channels in BTL mode. The device does not support a parallel configuration of
all four channels for a one channel amplifier.
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Typical Applications (continued)
PVDD
Input
PVDD
1 •F
470 •F
1 nF
Chassis
GND
1
1 •F
2
PVDD
3
4
5
1 •F
6
7
8
1 •F
9
2.2 •F
10
2.2 •F
11
12
13
14
15
16
17
18
19
2 k•
VBAT
BST_4P
AREF
OUT_4P
VREG
VCOM
OUT_4M
AVSS
BST_4M
AVDD
GND
GVDD
BST_3P
OUT_3P
GVDD
GND
GND
OUT_3M
MCLK
BST_3M
SCLK
PVDD
FSYNC
PVDD
SDIN1
SDIN2
BST_2P
GND
OUT_2P
GND
GND
VDD
2 k•
20
22
23
24
SCL
BST_2M
SDA
GND
BST_1P
I2C_ADDR1
OUT_1P
MUTE
GND
STANDBY
26
27
28
WARN
FAULT
GND
PVDD
54
1 •F
L
53
C
52
L
51
50
10 •F
0.1 •F
55
C
1 •F
1 nF
49
2•
48
1 •F
L
47
C
46
L
45
44
C
1 •F
43
PVDD
41
1 •F
L
40
C
39
L
38
37
10 •F
0.1 •F
42
C
1 •F
1 nF
36
2•
1 nF
I2C_ADDR0
25
56
1 nF
OUT_2M
21
Micro
PVDD
PVDD
GND
1 •F
DSP
PVDD
GND
OUT_1M
BST_1M
PVDD
PVDD
36
1 •F
L
34
C
33
L
32
31
C
1 •F
30
29
PVDD
0.1 •F
10 •F
Figure 62. TAS6424L-Q1 Typical 2-Channel PBTL Application Schematic
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Typical Applications (continued)
10.2.2.1 Design Requirements
Use the following requirements for this design:
• This head-unit example is focused on the smallest solution size for 2 times 50 W output power into 2 Ω with a
battery supply of 14.4 V
• The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
• The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
.
10.2.2.1.1 Detailed Design Procedure
As a starting point, refer to the Detailed Design Procedure section for the BTL application. PBTL mode requires
schematic changes in the output stage as shown in Figure 62. The other required changes include setting up the
I2C registers correctly (see Table 13) and selecting which frame or channel to use on each output. Bit 6 in
register 0x21 controls the frame selection.
10.2.2.2 Application Curves
10
2 : Load
4 : Load
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
10
1
0.1
0.01
0.001
10m
100m
1
Output Power (W)
1 kHz
10 20
100
2 : Load
4 : Load
1
0.1
0.01
0.001
20
D033
PVDD = 14.4 V
Figure 63. THD vs Output Power
100
1k
Frequency (Hz)
1W
10k
20k
D031
PVDD = 14.4 V
Figure 64. Frequency Response
11 Power Supply Recommendations
The TAS6424L-Q1 requires three power supplies. The PVDD supply is the high-current supply in the
recommended supply range. The VBAT supply is lower current supply that must be in the recommended supply
range. The PVDD and VBAT pins can be connected to the same supply if the recommended supply range for
VBAT is maintained. The VDD supply is the 3.3 Vdc logic supply and must be maintained in the tolerance as
shown in the Recommended Operating Conditions table.
12 Layout
12.1 Layout Guidelines
The pinout of the TAS6424L-Q1 was selected to provide flowthrough layout with all high-power connections on
the right side, and all low-power signals and supply decoupling on the left side.
Figure 65 shows the area for the components in the application example (see the Typical Applications section).
The TAS6424L-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize power
loss.
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Layout Guidelines (continued)
The small value of the output filter provides a small size and, in this case, the low height of the inductor enables
double-sided mounting.
The EVM PCB shown in Figure 65 is the basis for the layout guidelines.
12.1.1 Electrical Connection of Thermal pad and Heat Sink
For the DKQ package, the heat sink connected to the thermal pad of the device should be connected to GND.
The heat slug must not be connected to any other electrical node.
12.1.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design. The design has minimal parasitic inductances because of the short leads on the package which reduces
the EMI that results from current passing from the die to the system PCB. Each channel also operates at a
different phase. The design also incorporates circuitry that optimizes output transitions that cause EMI.
For optimizing the EMI a solid ground layer plane is recommended, for a PCB design the fulfills the CISPR25
level 5 requirements, see the TAS6424L-Q1 EVM layout.
12.1.3 General Guidelines
The EVM layout is optimized for low noise and EMC performance.
The TAS6424L-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider an
external heat sink.
Refer to Figure 65 for the following guidelines:
• A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop
impedance for the high-frequency switching current.
• The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the
ground pins.
• The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also
the ground return for each channel is the shared. This direct path allows for improved common mode EMI
rejection.
• The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the
smallest loop of large switching currents.
• Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package to
ground.
• Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power
supply.
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12.2 Layout Example
Power Supply
and
Amplifier
Section
B
C
F
A
D
E
Figure 65. EVM Layout
12.3 Thermal Considerations
The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output
power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6424L-Q1
and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can be
continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier design
because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink,
therefore, RθJC will be used as the thermal resistance from junction to the exposed metal package. This
resistance will dominate the thermal management, so other thermal transfers will not be considered. The thermal
resistance of RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance
is comprised of the following components:
• RθJC of the TAS6424L-Q1
• Thermal resistance of the thermal interface material
• Thermal resistance of the heat sink
The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the
area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, a
typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The
TAS6424L-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance
by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of
the thermal grease is 0.094°C/W
Table 41 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be
115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease example
previously described is used for the thermal interface material. Use Equation 1 to design the thermal system.
54
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Product Folder Links: TAS6424L-Q1
TAS6424L-Q1
www.ti.com
SLOS809 – MARCH 2017
Thermal Considerations (continued)
RθJA = RθJC + thermal interface resistance + heat sink resistance
(1)
Table 41. Thermal Modeling
Description
Value
Ambient Temperature
25°C
Average Power to load
40W (4x 10w)
Power dissipation
8W (4x 2w)
Junction Temperature
115°C
ΔT inside package
5.6°C (0.7°C/W × 8W)
ΔT through thermal interface material
0.75°C (0.094°C/W × 8W)
Required heat sink thermal resistance
10.45°C/W ([115°C – 25°C – 5.6°C – 0.75°C] / 8W)
System thermal resistance to ambient RθJA
11.24°C/W
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• PurePath™ Console 3 User Manual (SLOU408)
• TAS6424-Q1 EVM User's Guide (SLOU453)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
E2E Audio Amplifier Forum TI's Engineer-to-Engineer (E2E) Community for Audio Amplifiers. Created to
foster collaboration among engineers. Ask questions and receive answers in real-time.
13.4 Trademarks
PowerPAD, PurePath, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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55
TAS6424L-Q1
SLOS809 – MARCH 2017
www.ti.com
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
56
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Product Folder Links: TAS6424L-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TAS6424LQDKQRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HSSOP
DKQ
56
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TAS
6424L
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS6424LQDKQRQ1
Package Package Pins
Type Drawing
SPQ
HSSOP
1000
DKQ
56
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
32.4
Pack Materials-Page 1
11.35
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
18.67
3.1
16.0
32.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS6424LQDKQRQ1
HSSOP
DKQ
56
1000
367.0
367.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
DKQ0056A
PowerPAD TM HSSOP - 2.475 mm max height
SCALE 1.000
PLASTIC SMALL OUTLINE
C
10.67
TYP
10.03
A
SEATING PLANE
PIN 1 ID AREA
0.1 C
54X 0.635
56
1
EXPOSED
THERMAL PAD
18.54
18.29
NOTE 3
8.661
8.611
2X
17.15
5.533
5.483
28
29
56X
B
2.29 0.05
7.59
7.39
NOTE 4
0.37
0.17
0.13
(2.29)
C A B
0.25
TYP
0.13
2.475
2.240
NOTE 6
0.25
GAGE PLANE
SEE DETAIL A
0 -8
0.08
0.00
1.02
0.51
DETAIL A
TYPICAL
4221870/D 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body
thickness dimension.
www.ti.com
EXAMPLE BOARD LAYOUT
DKQ0056A
PowerPAD TM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SEE DETAILS
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
METAL
0.05 MAX
AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
0.05 MIN
AROUND
EXPOSED METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221870/D 01/2019
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DKQ0056A
PowerPAD TM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
(R0.05) TYP
29
(9.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE:6X
4221870/D 01/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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