Texas Instruments | TPA3112D1 25-W Filter-Free Mono Class-D Audio Power Amplifier With SpeakerGuard™ (Rev. D) | Datasheet | Texas Instruments TPA3112D1 25-W Filter-Free Mono Class-D Audio Power Amplifier With SpeakerGuard™ (Rev. D) Datasheet

Texas Instruments TPA3112D1 25-W Filter-Free Mono Class-D Audio Power Amplifier With SpeakerGuard™ (Rev. D) Datasheet
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TPA3112D1
SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
TPA3112D1 25-W Filter-Free Mono Class-D Audio Power Amplifier With SpeakerGuard™
1 Features
3 Description
•
The TPA3112D1 is a 25-W efficient, Class-D audio
power amplifier for driving a bridge tied speaker.
Advanced EMI Suppression Technology enables the
use of inexpensive ferrite bead filters at the outputs
while meeting EMC requirements. SpeakerGuard
speaker protection system includes an adjustable
power limiter and a DC detection circuit. The
adjustable power limiter allows the user to set a
virtual voltage rail lower than the chip supply to limit
the amount of current through the speaker. The DC
detect circuit measures the frequency and amplitude
of the PWM signal and shuts off the output stage if
the input capacitors are damaged or shorts exist on
the inputs.
1
•
•
•
•
•
•
•
•
•
•
25-W into an 8-Ω Load at < 0.1% THD+N From a
24-V Supply
20-W into an 4-Ω Load at 10% THD+N From a
12-V Supply
94% Efficient Class-D Operation into 8-Ω Load
Eliminates Need for Heat Sinks
Wide Supply Voltage Range Allows Operation
from 8 to 26 V
Filter-Free Operation
SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter plus DC Protection
Flow Through Pin Out Facilitates Easy Board
Layout
Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection with Auto-Recovery Option
Excellent THD+N/ Pop Free Performance
Four Selectable, Fixed Gain Settings
Differential Inputs
2 Applications
•
•
The TPA3112D1 can drive a mono speaker as low as
4Ω. The high efficiency of the TPA3112D1, > 90%,
eliminates the need for an external heat sink when
playing music.
The outputs are fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an autorecovery feature.
Device Information(1)
Televisions
Consumer Audio Equipment
PART NUMBER
TPA3112D1
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
4.40 mm × 9.70 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
1uF
Audio
Source
OUT+
INP
OUT -
INN
TPA3112D1
OUTP
OUTN
FERRITE
BEAD
FILTER
25W
8Ω
GAIN0
GAIN1
PLIMIT
Fault
SD
PVCC
8 to 26V
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3112D1
SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1 Absolute Maximum Ratings .....................................
6.2 ESD Ratings ............................................................
6.3 Recommended Operating Conditions......................
6.4 Thermal Information .................................................
6.5 DC Characteristics, VCC = 24 V ...............................
6.6 DC Characteristics, VCC = 12 V ...............................
6.7 AC Characteristics, VCC = 24 V ...............................
6.8 AC Characteristics, VCC = 12 V ...............................
6.9 Typical Characteristics ..............................................
4
4
4
5
5
5
6
6
7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Recieving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2012) to Revision D
•
2
Page
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
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SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
PHP PowerPAD™ Package
28-Pin HTSSOP
Top View
SD
FAULT
1
28
2
27
GND
GND
GAIN0
GAIN1
3
26
4
25
5
24
6
23
AVCC
AGND
GVDD
PLIMIT
7
22
8
21
INN
INP
NC
AVCC
9
20
10
19
11
18
12
17
13
16
14
15
PVCC
PVCC
BSN
OUTN
PGND
OUTN
BSN
BSP
OUTP
PGND
OUTP
BSP
PVCC
PVCC
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
8
G
Analog supply ground. Connect to the thermal pad.
AVCC
7
P
Analog supply.
AVCC
14
P
Connect AVCC supply to this pin
BSN
22
I
Bootstrap I/O for negative high-side FET.
BSN
26
I
Bootstrap I/O for negative high-side FET.
BSP
21
I
Bootstrap I/O for positive high-side FET.
BSP
17
I
Bootstrap I/O for positive high-side FET.
FAULT
2
O
Open drain output used to display short circuit or dc detect fault status. Voltage
compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting
FAULT pin to SD pin. Otherwise, both the short circuit faults and dc detect faults
must be reset by cycling PVCC.
GAIN0
5
I
Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1
6
I
Gain select most significant bit. TTL logic levels with compliance to AVCC.
GND
3
G
Connect to local ground
GND
4
G
Connect to local ground
GVDD
9
O
High-side FET gate drive supply. Nominal voltage is 7 V. May also be used as
supply for PLILMIT divider. Add a 1-μF capacitor to ground at this pin.
INP
12
I
Positive audio input. Biased at 3 V.
INN
11
I
Negative audio input. Biased at 3 V.
NC
13
—
Not connected
OUTN
23
O
Class-D H-bridge negative output.
OUTN
25
O
Class-D H-bridge negative output.
OUTP
20
O
Class-D H-bridge positive output.
OUTP
18
O
Class-D H-bridge positive output.
PLIMIT
10
I
Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a
1-μF capacitor to ground at this pin.
PGND
19
G
Power ground for the H-bridges.
PGND
24
G
Power ground for the H-bridges.
PVCC
15
P
Power supply for H-bridge. PVCC pins are also connected internally.
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
PVCC
16
P
Power supply for H-bridge. PVCC pins are also connected internally.
PVCC
27
P
Power supply for H-bridge. PVCC pins are also connected internally.
PVCC
28
P
Power supply for H-bridge. PVCC pins are also connected internally.
SD
1
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs
enabled). TTL logic levels with compliance to AVCC.
6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC Supply voltage
VI
Interface pin voltage
TA
Operating free-air temperature
RL
Minimum Load Resistance
UNIT
V
AVCC, PVCC
–0.3
30
SD, FAULT,GAIN0, GAIN1, AVCC (Pin
14)
–0.3
VCC + 0.3
< 10
PLIMIT
–0.3
GVDD + 0.3
INN, INP
–0.3
6.3
V
–40
85
°C
150
°C
BTL
V
V/ms
3.2
Tstg DMD storage temperature
(1)
MAX
V
Ω
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
26
V
VCC
Supply voltage
PVCC, AVCC
8
VIH
High-level input voltage
SD, GAIN0, GAIN1
2
VIL
Low-level input voltage
SD, GAIN0, GAIN1
0.8
VOL
Low-level output voltage
FAULT, RPULLUP = 100 kΩ, VCC = 26 V
0.8
V
IIH
High-level input current
SD, GAIN0, GAIN1, VI = 2 V, VCC = 18 V
50
µA
IIL
Low-level input current
SD, GAIN0, GAIN1, VI = 0.8 V, VCC = 18 V
5
µA
4
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V
V
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6.4 Thermal Information
TPA3112D1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
30.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.5
°C/W
RθJB
Junction-to-board thermal resistance
17.5
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
7.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5
DC Characteristics, VCC = 24 V
TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOS |
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
ICC
Quiescent supply current
SD = 2 V, no load, PVcc=21 V
ICC(SD)
Quiescent supply current in shutdown mode
SD = 0.8 V, no load, PVcc=21 V
rDS(on)
IO = 500 mA,
TJ = 25°C
Drain-source on-state resistance
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
tON
Turn-on time
SD = 2 V
tOFF
Turn-off time
SD = 0.8 V
GVDD
Gate Drive Supply
IGVDD = 2 mA
6.6
MIN
TYP MAX
1.5
15
mV
40
mA
400
µA
High side
240
Low side
240
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
10
6.9
dB
dB
ms
2
6.5
UNIT
μs
7.3
V
DC Characteristics, VCC = 12 V
TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
| VOS |
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
1.5
ICC
Quiescent supply current
SD = 2 V, no load, PVcc=12 V
20
mA
ICC(SD)
Quiescent supply current in shutdown mode
SD = 0.8 V, no load, PVcc=12 V
200
µA
Drain-source on-state resistance
IO = 500 mA,
TJ = 25°C
rDS(on)
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
High side
240
Low side
240
15
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
tON
Turn-on time
SD = 2 V
tOFF
Turn-off time
SD = 0.8 V
GVDD
Gate Drive Supply
IGVDD = 2 mA
PLIMIT
Output Voltage maximum under PLIMIT
control
VPLIMIT= 2.0 V; VI= 6.0-V differential
10
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dB
dB
ms
2
μs
6.5
6.9
7.3
V
6.75
7.90
8.75
V
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5
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SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
6.7
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AC Characteristics, VCC = 24 V
TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
KSVR
Power Supply ripple rejection
200-mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs AC-coupled to AGND
PO
Continuous output power
THD+N ≤ 0.1%, f = 1 kHz, VCC = 24 V
THD+N
Total harmonic distortion + noise
VCC = 24 V, f = 1 kHz, PO = 12 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
SNR
Signal-to-noise ratio
fOSC
Oscillator frequency
MAX
UNIT
–70
dB
25
W
<0.05
%
65
µV
–80
dBV
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–70
dB
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
102
dB
250
Thermal trip point
Thermal hysteresis
6.8
TYP
310
350
kHz
150
°C
15
°C
AC Characteristics, VCC = 12 V
TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
KSVR
Supply ripple rejection
200-mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
PO
Continuous output power
THD+N ≤ 10%, f = 1 kHz , RL = 8 Ω
PO
Continuous output power
THD+N ≤ 10%, f = 1 kHz , RL = 4 Ω
THD+N
Total harmonic distortion + noise
RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
SNR
Signal-to-noise ratio
fOSC
Oscillator frequency
MAX
UNIT
–70
dB
10
W
20
W
<0.06
%
65
µV
–80
dBV
Po = 1 W, Gain = 20 dB, f = 1 kHz
–70
dB
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
102
dB
250
Thermal trip point
Thermal hysteresis
6
TYP
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310
350
kHz
150
°C
15
°C
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6.9 Typical Characteristics
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
10
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
10
1
0.1
PO = 1 W
0.01
PO = 5 W
1
PO = 1 W
0.1
0.01
PO = 10 W
PO = 5 W
PO = 2.5 W
0.001
20
100
1k
10k
0.001
20
20k
100
1k
10k
G002
G001
Gain = 20 dB
VCC = 12 V
ZL = 8 Ω + 66 µH
Figure 1. Total Harmonic Distortion vs Frequency
Gain = 20 dB
ZL = 8 Ω + 66 µH
10
THD+N − Total Harmonic Distortion + Noise − %
THD − Total Harmonic Distortion − %
VCC = 24 V
Figure 2. Total Harmonic Distortion vs Frequency
10
1
PO = 5 W
PO = 10 W
0.1
0.01
PO = 1 W
0.001
20
100
1k
10k
Gain = 20 dB
VCC = 12 V
ZL = 8 Ω + 66 µH
1
f = 1 kHz
0.01
f = 10 kHz
0.001
0.01
20k
0.1
VCC = 12 V
ZL = 4 Ω + 33 µH
Figure 3. Total Harmonic Distortion vs Frequency
1
10
PO − Output Power − W
G003
Gain = 20 dB
f = 20 Hz
0.1
f − Frequency − Hz
Gain = 20 dB
VCC = 12 V
30
G004
ZL = 8 Ω + 66 µH
Figure 4. Total Harmonic Distortion + Noise vs Output
Power
10
10
Gain = 20 dB
VCC = 24 V
ZL = 8 Ω + 66 µH
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
20k
f − Frequency − Hz
f − Frequency − Hz
1
f = 1 kHz
f = 20 Hz
0.1
0.01
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
Gain = 20 dB
VCC = 24 V
10
30
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH
1
0.1
Figure 5. Total Harmonic Distortion + Noise vs Output
Power
f = 20 Hz
0.01
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
G005
ZL = 8 Ω + 66 µH
f = 1 kHz
Gain = 20 dB
VCC = 12 V
10
30
G006
ZL = 4 Ω + 33 µH
Figure 6. Total Harmonic Distortion + Noise vs Output
Power
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Typical Characteristics (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
30
PO(Max) − Maximum Output Power − W
30
Gain = 20 dB
VCC = 24 V
ZL = 8 Ω + 66 µH
25
PO − Output Power − W
25
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH
20
15
10
20
15
10
5
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
0.0
Gain = 20 dB
0.5
1.5
2.0
2.5
3.0
3.5
VCC = 24 V
ZL = 8 Ω + 66 µH
Gain = 20 dB
40
100
35
50
4.0
G008
G007
VCC = 12 V
ZL = 4 Ω + 33 µH
Figure 8. Output Power vs Plimit Voltage
Figure 7. Maximum Output Power vs Plimit Voltage
100
90
VCC = 24 V
80
Phase
30
0
25
−50
Gain
h − Efficiency − %
Phase − °
70
Gain − dB
1.0
VPLIMIT − PLIMIT Voltage − V
VPLIMIT − PLIMIT Voltage − V
VCC = 12 V
60
50
20
−100
15
−150
10
−200
5
−250
10
−300
100k
0
40
30
20
0
10
100
1k
10k
Gain = 20 dB
ZL = 8 Ω + 66 µH
0
5
10
15
20
25
30
PO − Output Power − W
f − Frequency − Hz
G012
G009
Gain = 20 dB
CI = µF
VCC = 12 V
VI = 0.1 VRMS
ZL = 8 Ω + 66 µH
Gain = 20 dB
ZL = 8 Ω + 66 µH
Figure 10. Efficiency vs Output Power
Figure 9. Gain/Phase vs Frequency
1.2
100
Gain = 20 dB
ZL = 8 Ω + 66 µH
90
ICC − Supply Current − A
70
h − Efficiency − %
1.0
VCC = 24 V
80
VCC = 12 V
60
50
40
30
20
VCC = 24 V
0.6
0.4
0.2
Gain = 20 dB
ZL = 4 Ω + 33 µH
10
0
0.0
0
5
10
15
20
PO − Output Power − W
Gain = 20 dB
25
30
0
5
ZL = 4 Ω + 33 µH
10
15
20
PO(Tot) − Total Output Power − W
G013
Gain = 20 dB
Figure 11. Efficiency vs Output Power
8
VCC = 12 V
0.8
25
30
G014
ZL = 8 Ω + 66 µH
Figure 12. Supply Current vs Total Output Power
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Typical Characteristics (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
1.8
0
1.6
KSVR − Supply Ripple Rejection Ratio − dB
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH
ICC − Supply Current − A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
5
10
15
20
25
PO(Tot) − Total Output Power − W
Gain = 20 dB
VCC = 12 V
30
−20
−40
−60
−80
−100
−120
20
100
1k
10k
20k
f − Frequency − Hz
G015
ZL = 4 Ω + 33 µH
Figure 13. Supply Current vs Total Output Power
G016
Gain = 20 dB
VCC = 12 V
ZL = 8 Ω + 66 µH
Figure 14. Supply Ripple Rejection Ratio vs Frequency
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7 Detailed Description
7.1 Overview
To facilitate system design, the TPA3112D1 requires only a single power supply from 8 V to 26 V for operation.
An internal voltage regulator provides suitable voltage levels for the gate driver, digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate drive, is
accommodated by built-in bootstrap circuitry with integrated bootstrap diodes requiring only an external capacitor
for each half-bridge. The audio signal path, including the gate drive and output stage is designed as identical,
independent full-bridges. Place all decoupling capacitors as close to their associated pins as possible. In general,
the physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must
be kept as short as possible and with as little area as possible to minimize induction (see TPA3112D1 Evaluation
Module for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSx) to the power-stage output pin (OUTx). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching
frequencies approximately 310 kHz, TI recommends ceramic capacitors with at least 220-nF capacitance, size
0603 or 0805, for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped
low frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of its ON cycle. Pay special attention to the power-stage power supply; this includes component
selection, PCB placement, and routing. For optimal electrical performance, EMI compliance, and system
reliability, it is important that each PVCC pin is decoupled with ceramic capacitors placed as close as possible to
each supply pin. TI recommends following the PCB layout of the TPA3112D1 EVM. For additional information on
recommended power supply and required components, see the Application and Implementation and Power
Supply Recommendations sections. The PVCC power supply must have low output impedance and low noise.
The power-supply ramp and SD release sequence is not critical for device reliability as facilitated by the internal
power-on-reset circuit, but TI recommends releasing SD after the power supply is settled for minimum turnon
audible artifacts.
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7.2 Functional Block Diagram
GVDD
OUTP FB
+
PVCC
BSP
PVCC
OUTP FB
INP
INN
±
Gain
Control
+
±
+
±
±
+
PLIMIT
±
+
Gate
Drive
PWM
Logic
+
OUTP
OUTN FB
±
FAULT
PGND
SD
GAIN0
TTL
Buffer
Gain Control
GAIN1
Ramp
Generator
PLIMIT
Reference
PLIMIT
GVDD
AVCC
AVCC
BSN
PVCC
PVCC
LDO
Regulator
SC Detect
GVDD
Startup
Protection
Logic
Biases and
References
GVDD
Gate
Drive
DC Detect
Thermal
Detect
OUTN
OUTN FB
PGND
UVLO and
OVLO
AGND
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7.3 Feature Description
7.3.1 Gain Setting Via Gain0 And Gain1 Inputs
The gain of the TPA3112D1 is set by two input terminals, GAIN0 and GAIN1. The voltage slew rate of these gain
terminals, along with terminals 1 and 14, must be restricted to no more than 10V/ms. For higher slew rates, use
a 100-kΩ resistor in series with the terminals.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part
at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3112D1. At the lower gain
settings, the input impedance could increase as high as 72 kΩ
Table 1. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE (kΩ)
TYP
TYP
20
60
1
26
30
1
0
32
15
1
1
36
9
GAIN1
GAIN0
0
0
0
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7.3.2
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SD Operation
The TPA3112D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
7.3.3 PLIMIT
The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Also add a 1-μF capacitor from pin 10 to ground.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This limit can be thought of as a virtual
voltage rail which is lower than the supply connected to PVCC. This virtual rail is 4 times the voltage at the
PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input
voltage and speaker impedance.
TPA3112D1 PLimit Operation
Figure 15. Plimit Circuit Operation
The PLIMIT circuits sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to
calculate the maximum output power for a given maximum input voltage and speaker impedance.
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POUT
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ææ
ö
ö
RL
çç ç
÷ ´ VP ÷÷
è RL + 2 ´ RS ø
ø
=è
2 ´ RL
2
for unclipped power
(1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT(10%THD) = 1.25 × POUT(unclipped)
Table 2. Plimit Typical Operation
Test Conditions ()
PLIMIT Voltage
Output Power (W)
Output Voltage
Amplitude (VP-P)
PVCC=24V, Vin=1Vrms,
RL=4Ω, Gain=20dB
6.97
22.1
26.9
PVCC=24V, Vin=1Vrms,
RL=4Ω, Gain=20dB
1.92
10
15.0
PVCC=24V, Vin=1Vrms,
RL=4Ω, Gain=20dB
1.24
5
10.0
PVCC=12V, Vin=1Vrms,
RL=4Ω, Gain=20dB
6.95
17.2
20.9
PVCC=12V, Vin=1Vrms,
RL=4Ω, Gain=20dB
1.75
10
15.3
PVCC=12V, Vin=1Vrms,
RL=4Ω, Gain=20dB
1.20
5
10.3
7.3.4 GVDD Supply
The GVDD supply powers the gates of the output full bridge transistors and can also used to supply the PLIMIT
voltage divider circuit. Add a 1-μF capacitor to ground at this pin.
7.3.5 DC Detect
TPA3112D1 has circuitry that protects the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential duty-cycle exceeds 14% (for example, +57%, -43%) for
more than 420 ms at the same polarity. This feature protects the speaker from large DC currents or AC currents
less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the
signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative input
to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are shown in Table Table 3. The inputs
must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect.
Table 3. DC Detect Threshold
AV(dB)
Vin (mV, differential)
20
112
26
56
32
28
36
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7.3.6 Short-Circuit Protection And Automatic Recovery Feature
TPA3112D2 has protection from over-current conditions caused by a short circuit on the output stage. The short
circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z
state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through
the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This will allow the FAULT pin function to automatically drive the SD pin low which will clear the short circuit
protection latch.
7.3.7 Thermal Protection
Thermal protection on the TPA3112D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT terminal.
7.4 Device Functional Modes
7.4.1 TPA3112D1 Modulation Scheme
The TPA3112D1 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 V to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R
losses in the load.
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Device Functional Modes (continued)
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
-12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output > 0 V
+12 V
0V
-12 V
Current
Figure 16. The TPA3112D1 Output Voltage and Current Waveforms into an Inductive Load
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA3112D1 is designed for use in stereo speakers like in televisions, monitors and laptops, and consumer
audio equipment. The TPA3112D1 can either be configured in stereo or mono mode, depending on output power
conditions. Depending on output power requirements and necessity for (speaker) load protection, the built-in
PLIMIT circuit can be used to control system power.
8.2 Typical Application
PVCC
100 μF
0.1 μF
1000pF
100k Ω
Control
System
1
SD
PVCC
FAULT
PVCC
28
1 kΩ
2
3
4
5
6
AVCC
PVCC
7
10 Ω
1 uF
8
GND
BSN
GND
OUTN
GAIN0
PGND
GAIN1
OUTN
BSN
AVCC
TPA3112D1
AGND
BSP
GVDD
OUTP
PLIMIT
PGND
INN
OUTP
INP
BSP
NC
PVCC
AVCC
PVCC
27
26
0.47 μF
25
24
FB
23
1000 pF
22
21
1000 pF
9
1 uF
10
11
1 uF
Audio
Source
12
1 uF
AVCC
100 kW
13
(1)
20
FB
19
0.47 μF
18
17
16
100 μF
14
15
0.1 μF
1000pF
GND
29
PowerPAD
PVCC
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(1)
100 kΩ resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 17. Mono Class-D Amplifier With Btl Output
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
Table 4. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range PVDD
8 V to 26 V
Ferrite bead + capacitor
120 Ω to 600 Ω at 100 MHz + 1 nF / 2.2 nF
8.2.2 Detailed Design Procedure
8.2.2.1 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3112D1 amplifier it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. it is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead
current handling capability by measuring the resonant frequency of the filter output at very low power and at
maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable.
Examples of ferrite beads which have been tested and work well with the TPA3112D2 include 28L0138-80R-10
and HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics.
A high-quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPAD™ beneath the
chip.
8.2.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3112D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
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An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
8.2.2.3 When to Use an Output Filter for EMI Suppression
The TPA3112D1 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3112D1 EVM passes FCC Class B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are circuits near which are sensitive to noise. Therefore, a classic second
order Butterworth filter similar to those shown in Figure 18 through Figure 20 can be used.
33 mH
OUTP
L1
C2
1 mF
33 mH
OUTN
L2
C3
1 mF
Figure 18. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1
C2
2.2 mF
15 mH
OUTN
L2
C3
2.2 mF
Figure 19. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 20. Typical Ferrite Chip Bead Filter (Chip Bead Example: Steward Hi0805r800r-10)
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8.2.2.4 Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. If a single capacitor is used in the input high-pass filter, the –3 dB or cutoff frequency
may change when changing gain steps.
Zf
Ci
IN
Input
Signal
Zi
The -3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 1.
f =
1
2p Zi Ci
(2)
8.2.2.5 Input Capacitor, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a highpass filter with the corner frequency determined in Equation 3.
-3 dB
fc =
1
2p Zi Ci
fc
(3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
Ci =
1
2p Zi fc
(4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. If a
ceramic capacitor is used, use a high quality capacitor with good temperature and voltage coefficient. An X7R
type works well and if possible use a higher voltage rating than required. This will give a better C vs voltage
characteristic. When polarized capacitors are used, the positive side of the capacitor should face the amplifier
input in most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note
that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc
offset voltages and it is important to ensure that boards are cleaned properly.
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8.2.2.6 BSN and BSP Capacitors
The full H-bridge output stage uses only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 470-nF ceramic capacitor, rated for at least 16 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 470-nF capacitor must be
connected from OUTP to BSP, and one 470-nF capacitor must be connected from OUTN to BSN. See the
Simplified Application Diagram.
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power
supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle,
the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.
8.2.2.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3112D1 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3112D1 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input DC blocking capacitors to become completely charged during the 14 msec power-up time. If the
input capacitors are not allowed to completely charge, there will be some additional sensitivity to component
matching which can result in pop if the input components are not well matched.
8.2.2.8 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
8.2.3 Application Curves
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
1
f = 1 kHz
f = 20 Hz
0.1
0.01
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
Gain = 20 dB
VCC = 12 V
10
20
f = 1 kHz
f = 20 Hz
0.1
0.01
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
G004
ZL = 8 Ω + 66 µH
Figure 21. Total Harmonic Distortion + Noise
vs Output Power
20
1
Gain = 20 dB
VCC = 24 V
10
20
G005
ZL = 8 Ω + 66 µH
Figure 22. Total Harmonic Distortion + Noise
vs Output Power
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THD+N − Total Harmonic Distortion + Noise − %
10
1
f = 1 kHz
0.1
f = 20 Hz
0.01
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
Gain = 20 dB
VCC = 12 V
10
20
G006
ZL = 4 Ω + 33 µH
Figure 23. Total Harmonic Distortion + Noise
vs Output Power
9 Power Supply Recommendations
The TPA3112D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good-quality, low equivalent-seriesresistance (ESR) ceramic capacitor from 220 pF to 1000 pF works well. This capacitor must be placed as close
to the device PVCC pins and system ground (either PGND pins or PowerPAD) as possible. For mid-frequency
noise due to filter resonances or PWM switching transients as well as digital hash on the line, another goodquality capacitor typically 0.1 µF to 1 µF placed as close as possible to the device PVCC leads works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near
the audio power amplifier works well. The 220-µF capacitor also serves as a local storage capacitor for supplying
current during large signal transients on the amplifier outputs. The PVCC pins provide the power to the output
transistors, so a 220-µF or larger capacitor must be placed on each PVCC pin. A 10-µF capacitor on the AVCC
pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high
frequency, Class-D noise from entering the linear input amplifiers.
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10 Layout
10.1 Layout Guidelines
The TPA3112D1 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
because the Class-D switching edges are very fast, take care when planning the layout of the printed-circuit
board. The following suggestions help to meet EMC requirements.
• Decoupling capacitors: The high-frequency decoupling capacitors must be placed as close to the PVCC and
AVCC pins as possible. Large, 220-µF or greater, bulk power supply decoupling capacitors must be placed
near the TPA3112D1 on the PVCC supplies. Local, high-frequency bypass capacitors must be placed as
close to the PVCC pins as possible. These capacitors can be connected to the thermal pad directly for an
excellent ground connection. Consider adding a small, good-quality, low-ESR ceramic capacitor from 220 pF
to 1000 pF and a larger mid-frequency capacitor from 0.1 µF to 1 µF also of good quality to the PVCC
connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter capacitor and back
to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Output filter: The ferrite EMI filter (Figure 20) must be placed as close to the output pins as possible for the
best EMI performance. The LC filter (Figure 18 and Figure 19) must be placed close to the outputs. The
capacitors used in both the ferrite and LC filters must be grounded to power ground.
• Thermal Pad: The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land must be 6.46 mm by 2.35 mm. Seven rows of
solid vias, three vias per row, 0.33-mm or 13-mils diameter, must be equally spaced underneath the thermal
land. The vias must connect to a solid copper plane, either on an internal layer or on the bottom layer of the
PCB. The vias must be solid vias, not thermal relief or webbed vias. See PowerPAD™ Thermally Enhanced
package (SLMA002) for more information about using the HTSSOP thermal pad. For recommended PCB
footprints, see mechanical pages appended to the end of this data sheet.
For an example layout, see the TPA3112D1EVM Audio Amplifier Evaluation Board User's Guide (SLOU270).
The EVM documentation is available on the TI website at http://www.ti.com/tool/TPA3112D1EVM.
22
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: TPA3112D1
TPA3112D1
www.ti.com
SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
10.2 Layout Example
100PF
100nF
1nF
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
0.47µF
FB
1PF
1PF
1nF
1nF
FB
0.47µF
1nF
100nF
100PF
Top Layer Ground and Thermal Pad
Via to Bottom Ground Plane
Pad to Top Layer Ground Pour
Top Layer Signal Traces
Figure 24. BTL Layout Example
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Product Folder Links: TPA3112D1
23
TPA3112D1
SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support, see the following:
The TI PCB Thermal Calculator is designed to estimate the junction temperatures of components which use
exposed-pad packages.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• QFN/SON PCB Attachment (SLUA271)
• PowerPAD™ Thermally Enhanced package (SLMA002)
• TPA3112D1EVM Audio Amplifier Evaluation Board User's Guide (SLOU270)
11.3 Recieving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
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TPA3112D1
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SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPA3112D1
25
PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA3112D1PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3112D1
TPA3112D1PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3112D1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPA3112D1 :
• Automotive: TPA3112D1-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA3112D1PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA3112D1PWPR
HTSSOP
PWP
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.65 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/A
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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