Texas Instruments | TPA3244 60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier (Rev. A) | Datasheet | Texas Instruments TPA3244 60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier (Rev. A) Datasheet

Texas Instruments TPA3244 60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier (Rev. A) Datasheet
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TPA3244
SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
TPA3244 60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Differential Analog Inputs
Total Output Power at 10%THD+N
– 60-W Stereo Continuous into 8 Ω in BTL
Configuration at 30 V
– 110-W Stereo Peak into 4 Ω in BTL
Configuration at 30 V
Total Output Power at 1%THD+N
– 50-W Stereo Continuous into 8 Ω in BTL
Configuration at 30 V
– 90-W Stereo Peak into 4 Ω in BTL
Configuration at 30 V
Advanced Integrated Feedback Design with Highspeed Gate Driver Error Correction
(PurePath™ Ultra-HD)
– Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources
– Ultra Low 0.005% THD+N at 1 W into 4 Ω and
<0.01% THD+N to Clipping
– 60 dB PSRR (BTL, No Input Signal)
– <55 µV (A-Weighted) Output Noise
– >110 dB (A Weighted) SNR
Multiple Configurations Possible:
– Stereo, Mono, 2.1 and 4xSE
Click and Pop Free Startup and Stop
94% Efficient Class-D Operation (8 Ω)
Wide 12-V to 30-V Supply Voltage Operation
Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short Circuit
Protection) With Error Reporting
EMI Compliant When Used With Recommended
System Design
High End Soundbar
Mini Combo Systems
Blu-Ray Disc™ / DVD Receivers
Active Speakers
3 Description
The TPA3244 device is a high performance Class-D
power amplifier that enables true premium sound
quality with Class-D efficiency. It features an
advanced integrated feedback design and proprietary
high-speed gate driver error correction (PurePath™
Ultra-HD). This technology allows ultra low distortion
across the audio band and superior audio quality.
With a 30-V power supply the device can drive up to
2 x 110 W peak into 4-Ω load and 2 x 60 W
continuous into 8-Ω load and features a 2-VRMS
analog input interface that works seamlessly with high
performance DACs such as Burr-Brown PCM52xx
DAC Family from TI (that is, PCM5242 / PCM5252).
In addition to excellent audio performance, TPA3244
achieves both high power efficiency and very low
power stage idle losses below 0.45 W. This is
achieved through the use of 65 mΩ MOSFETs and
an optimized gate driver scheme that achieves
significantly lower idle losses than typical discrete
implementations.
Device Information(1)
PART NUMBER
TPA3244
LC Filter
TAS5630
LEFT
LC Filter
/CLIP_OTW
/RESET
/FAULT
12V
Operation Mode Select
Switching Frequency Select
Master/Slave Synchronization
M1:M2
FREQ_ADJ
Power Supply
30V
OSC_IOM/P
110VAC->240VAC
Copyright © 2016, Texas Instruments Incorporated
THD+N - Total Harmonic Distortion + Noise - %
Total Harmonic Distortion
TPA3244
Audio Source
And Control
BODY SIZE (NOM)
6.10mm x 14.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
RIGHT
PACKAGE
HTSSOP (44)
10
8:
1
0.1
0.01
TA = 25qC
0.001
10m
100m
1
Po - Output Power - W
10
100
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3244
SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
9
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Audio Characteristics (BTL) ...................................... 8
Audio Characteristics (SE) ....................................... 9
Audio Characteristics (PBTL) ................................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 14
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
14
15
17
17
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Applications .............................................. 22
10.3 Typical Application, Differential (2N), PBTL (Outputs
Paralleled after LC filter) .......................................... 30
11 Power Supply Recommendations ..................... 32
11.1
11.2
11.3
11.4
Power Supplies .....................................................
Powering Up..........................................................
Powering Down .....................................................
Thermal Design.....................................................
32
32
33
34
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Examples................................................... 38
13 Device and Documentation Support ................. 42
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
42
14 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2016) to Revision A
Page
•
Changed From: Preview To Production data ........................................................................................................................ 1
•
Changed pin 18 From: INPUT_B To: INPUT_A in the Pin Functions table ........................................................................... 4
•
Changed pin 17 From: INPUT_A To: INPUT_B in the Pin Functions table ........................................................................... 4
•
Changed Figure 23............................................................................................................................................................... 22
•
Changed Figure 24............................................................................................................................................................... 26
•
Changed Figure 25............................................................................................................................................................... 28
2
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
5 Device Comparison Table
DEVICE NAME
DESCRIPTION
TPA3245
100-W Stereo, 200-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
TPA3250
70-W Stereo, 130-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
TPA3251
175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
TPA3255
315-W Stereo, 600-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
6 Pin Configuration and Functions
The TPA3244 device is available in a thermally enhanced TSSOP package.
The package type contains a PowerPad™ that is located on the bottom side of the device for thermal connection
to the PCB.
DDW Package
HTSSOP 44-Pin
(Top View)
GVDD_CD
1
44
BST_D
CLIP_OTW
2
43
BST_C
VBG
3
42
GND
FAULT
RESET
INPUT_D
4
41
GND
5
6
40
39
OUT_D
OUT_D
INPUT_C
7
38
PVDD_CD
C_START
8
37
PVDD_CD
AVDD
9
36
PVDD_CD
GND
10
35
OUT_C
GND
11
34
GND
DVDD
12
33
GND
OSC_IOP
OSC_IOM
13
14
32
31
OUT_B
PVDD_AB
FREQ_ADJ
15
30
PVDD_AB
OC_ADJ
16
29
PVDD_AB
INPUT_B
17
28
OUT_A
INPUT_A
18
27
OUT_A
M2
19
26
GND
M1
VDD
20
21
25
24
GND
BST_B
GVDD_AB
22
23
BST_A
Thermal
Pad
Not to scale
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
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Pin Functions
PIN
I/O
NAME
DESCRIPTION
NO.
AVDD
9
P
Internal voltage regulator, analog section
BST_A
23
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B
24
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C
43
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D
44
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW
2
O
Clipping warning and Over-temperature warning; open drain; active low. Do not connect if not used.
C_START
8
O
Startup ramp, requires a charging capacitor to GND
DVDD
12
P
Internal voltage regulator, digital section
FAULT
4
O
Shutdown signal, open drain; active low. Do not connect if not used.
FREQ_ADJ
15
O
Oscillator frequency programming pin
10, 11, 25, 26,
33, 34, 41, 42
P
GVDD_AB
22
P
Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD
1
P
Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A
18
I
Input signal for half bridge A
INPUT_B
17
I
Input signal for half bridge B
INPUT_C
7
I
Input signal for half bridge C
INPUT_D
6
I
Input signal for half bridge D
M1
20
I
Mode selection 1 (LSB)
M2
19
I
Mode selection 2 (MSB)
OC_ADJ
16
I/O
Over-Current threshold programming pin
OSC_IOM
14
I/O
Oscillator synchronization interface. Do not connect if not used.
OSC_IOP
13
O
Oscillator synchronization interface. Do not connect if not used.
OUT_A
27, 28
O
Output, half bridge A
OUT_B
32
O
Output, half bridge B
OUT_C
35
O
Output, half bridge C
OUT_D
39, 40
O
Output, half bridge D
PVDD_AB
29, 30, 31
P
PVDD supply for half-bridge A and B
PVDD_CD
36, 37, 38
P
PVDD supply for half-bridge C and D
RESET
5
I
Device reset Input; active low
VDD
21
P
Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG
3
P
Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
P
Ground, connect to PCB copper pour. Placed on bottom side of device.
GND
PowerPAD™
Ground
Table 1. Mode Selection Pins
MODE PINS
INPUT MODE
OUTPUT
CONFIGURATION
M2
M1
0
0
2N + 1
2 × BTL
0
1
2N/1N + 1
1 x BTL + 2 x SE
1
0
2N + 1
1 x PBTL
1
1
1N +1
4 x SE
(1)
4
(1)
DESCRIPTION
Stereo BTL output configuration
2.1 BTL + SE mode. Channel AB: BTL, channel C + D: SE
Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
Single ended output configuration
1 refers to logic high (DVDD level), 0 refers to logic low (GND).
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MIN
MAX
UNIT
BST_X to GVDD_X (2)
–0.3
43
V
VDD to GND
–0.3
13.2
V
GVDD_X to GND (2)
–0.3
13.2
V
PVDD_X to GND (2)
–0.3
43
V
DVDD to GND
–0.3
4.2
V
AVDD to GND
–0.3
8.5
V
VBG to GND
-0.3
4.2
V
(2)
–0.3
43
V
BST_X to GND (2)
–0.3
55.5
V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND
–0.3
4.2
V
RESET, FAULT, CLIP_OTW, CLIP to GND
–0.3
4.2
V
INPUT_X to GND
–0.3
7
V
9
mA
0
150
°C
–40
150
°C
OUT_X to GND
Interface pins
(1)
Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to
GND
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
7.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±1000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
12
30
31.5
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
2.7
4
Load impedance
Output filter inductance within
recommended value range
1.5
3
1.6
2
RL(BTL)
RL(SE)
RL(PBTL)
LOUT(BTL)
LOUT(SE)
5
Output filter inductance
Minimum output inductance at IOC
5
LOUT(PBTL)
R(FREQ_ADJ)
μH
5
PWM frame rate selectable for AM
interference avoidance; 1% Resistor
tolerance
FPWM
Ω
PWM frame rate programming resistor
Nominal
430
450
470
AM1
475
500
525
AM2
575
600
625
Nominal; Master mode
29.7
30
30.3
AM1; Master mode
19.8
20
20.2
AM2; Master mode
9.9
10
10.1
1.0
kHz
kΩ
CPVDD
PVDD close decoupling capacitors
ROC
Over-current programming resistor
Resistor tolerance = 5%
22
30
kΩ
ROC(LATCHED)
Over-current programming resistor
Resistor tolerance = 5%
47
64
kΩ
V(FREQ_ADJ)
Voltage on FREQ_ADJ pin for slave
mode operation
Slave mode
TJ
Junction temperature
μF
3.3
0
V
125
°C
7.4 Thermal Information
TPA3244
THERMAL METRIC (1)
DDV 44-PINS HTSSOP
UNIT
JEDEC STANDARD 4 LAYER PCB
RθJA
Junction-to-ambient thermal resistance
23.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
9.1
°C/W
RθJB
Junction-to-board thermal resistance
3.9
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
3.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD
Voltage regulator, only used as reference
node
VDD = 12 V
AVDD
Voltage regulator, only used as reference
node
VDD = 12 V
7.8
IVDD
VDD supply current
Operating, 50% duty cycle
40
Idle, reset mode
13
IGVDD_X
Gate-supply current per full-bridge
50% duty cycle
15
Reset mode
2
IPVDD_X
PVDD idle current per full bridge
50% duty cycle with 10µH Output Filter Inductors
Reset mode, No switching
V
V
mA
mA
12.5
mA
1
mA
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage swing
24
7
V
IIN
Maximum input current
1
mA
G
Inverting voltage Gain
VOUT/VIN
kΩ
20
dB
OSCILLATOR
Nominal, Master Mode
2.58
2.7
2.82
2.85
3
3.15
AM2, Master Mode
3.45
3.6
3.75
VIH
High level input voltage
1.86
VIL
Low level input voltage
fOSC(IO+)
AM1, Master Mode
FPWM × 6
MHz
V
1.45
V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, Includes metallization resistance,
GVDD = 12 V
65
mΩ
65
mΩ
9.5
V
0.6
V
10
V
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,VDD,GVDD
Vuvp,VDD,
GVDD,hyst
(1)
Vuvp,PVDD
Undervoltage protection limit, PVDD_x
Vuvp,PVDD,hyst
(1)
Overtemperature warning, CLIP_OTW (1)
OTW
OTWhyst
0.6
(1)
OTE (1)
115
Temperature drop needed below OTW
temperature for CLIP_OTW to be inactive
after OTW event.
125
V
135
25
Overtemperature error
145
155
°C
°C
165
°C
A reset needs to occur for FAULT to be
released following an OTE event
25
°C
OTE-OTW(differential)
(1)
OTE-OTW differential
30
°C
OLPC
Overload protection counter
fPWM = 450 kHz
2.3
ms
IOC
Overcurrent limit protection
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 22 kΩ
14
A
IOC(LATCHED)
Overcurrent limit protection
Resistor – programmable, peak current in 1Ω load,
ROCP = 47kΩ
14
A
IDCspkr
DC Speaker Protection Current Threshold
BTL current imbalance threshold
1.5
A
IOCT
Overcurrent response time
Time from switching transition to flip-state induced
by overcurrent.
150
ns
IPD
Output pulldown current of each half
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
3
mA
OTEhyst
(1)
(1)
Specified by design.
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Electrical Characteristics (continued)
PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
1.9
M1, M2, OSC_IOP, OSC_IOM, RESET
V
0.8
V
100
μA
32
kΩ
OTW/SHUTDOWN (FAULT)
RINT_PU
Internal pullup resistance, CLIP_OTW to
DVDD, FAULT to DVDD
VOH
High level output voltage
Internal pullup resistor
3.3
3.6
V
VOL
Low level output voltage
IO = 4 mA
200
500
mV
Device fanout
CLIP_OTW, FAULT
No external pullup
30
20
3
26
devices
7.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
RL = 8 Ω, 10% THD+N
Power output per channel
THD+N
50
RL = 4 Ω, 1% THD+N, 3 seconds Peak
Power (1)
90
RL = 4 Ω, 1% THD+N, Single Channel, 40
seconds Peak Power (1)
90
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
|VOS|
Output offset voltage
Inputs AC coupled to GND
SNR
Signal-to-noise ratio (2)
DNR
Dynamic range
Pidle
Power dissipation due to Idle losses (IPVDD_X)
(1)
(2)
(3)
8
110
RL = 8 Ω, 1% THD+N
PO = 0, 4 channels switching (3)
UNIT
60
RL = 4 Ω, 10% THD+N, Single Channel, 20
seconds duration (1)
PO
TYP MAX
W
0.005%
60
20
μV
60
mV
111
dB
111
dB
0.38
W
Peak Power rating using TPA3244 EVM
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
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7.7 Audio Characteristics (SE)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 4 Ω, 10% THD+N
30
RL = 3 Ω, 10% THD+N
39
RL = 4 Ω, 1% THD+N
25
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
100
μV
A-weighted
100
dB
A-weighted
101
dB
0.38
W
RL = 3 Ω, 1% THD+N
SNR
Signal to noise ratio
DNR
Dynamic range
Pidle
(1)
(2)
(1)
Power dissipation due to idle losses (IPVDD_X)
W
32
0.01%
PO = 0, 4 channels switching
(2)
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
7.8 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
outputs paralleled before LC filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
THD+N
MIN
RL = 4 Ω, 10% THD+N
125
RL = 3 Ω, 10% THD+N
160
RL = 4 Ω, 1% THD+N
100
RL = 3 Ω, 1% THD+N
130
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
SNR
Signal to noise ratio (1)
DNR
Dynamic range
Pidle
Power dissipation due to idle losses (IPVDD_X)
(1)
(2)
TYP MAX
UNIT
W
0.005%
55
μV
A-weighted
112
dB
A-weighted
112
dB
PO = 0, 4 channels switching (2)
0.38
W
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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7.9 Typical Characteristics
7.9.1 BTL Configuration
10
TA = 25qC
1W
20W
60W
1
0.1
0.01
0.001
0.0003
20
100
RL = 4 Ω
1k
f - Frequency - Hz
10k
20k
10
P = 1W, 20W, 60W
TA = 25°C
TA = 25qC
1W
20W
60W
1
0.1
0.01
0.001
20
100
D001
Figure 1. Total Harmonic Distortion+Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz,
ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025
measurement filters,unless otherwise noted.
1k
f - Frequency - Hz
10k
40k
D002
RL = 4 Ω P = 1W, 20W, 60W
AUX-0025 filter, 80 kHz analyzer BW
TA = 25°C
Figure 2. Total Harmonic Distortion+Noise vs Frequency
120
10
4:
8:
4:
8:
PO - Output Power - W
100
1
0.1
0.01
80
60
40
20
TA = 25qC
0.001
10m
100m
RL =4 Ω, 8 Ω
1
10
Po - Output Power - W
THD+N = 10%
TA = 25qC
0
10
100 200
15
20
25
PVDD - Supply Voltage - V
30
33
D004
D003
RL = 4 Ω, 8 Ω
TA = 25°C
THD+N = 10%
TA = 25°C
Figure 4. Output Power vs Supply Voltage
Figure 3. Total Harmonic Distortion + Noise vs Output
Power
100
100
4:
8:
4:
8:
Efficiency - %
PO - Output Power - W
80
60
40
10
20
THD+N = 1%
TA = 25qC
0
10
15
RL = 4 Ω, 8 Ω
20
25
PVDD - Supply Voltage - V
THD+N = 1%
30
TA = 25qC
33
D005
TA = 25°C
Figure 5. Output Power vs Supply Voltage
10
1
10m
100m
1
10
2 Channel Output Power - W
RL = 4 Ω, 8 Ω
100
300
D006
TA = 25°C
Figure 6. System Efficiency vs Output Power
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BTL Configuration (continued)
30
0
Noise Amplitude - dB
Power Loss - W
4:
8:
20
10
TA = 25qC
-20 Vref = 21.21 V
FFT size = 16384
-40
4:
-60
-80
-100
-120
-140
TA = 25qC
0
-160
0
30
60
90
120
150
2 Channel Output Power - W
RL = 4 Ω, 8 Ω
180
210
0
D007
TA = 25°C
5k
10k
15k
20k 24k
30k
f - Frequency - Hz
8 Ω, VREF = 25.46 V (1% Output power)
AUX-0025 filter, 80 kHz analyzer BW
Figure 7. System Power Loss vs Output Power
35k
40k
45k48k
D008
FFT = 16384
TA = 25°C
Figure 8. Noise Amplitude vs Frequency
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7.9.2 SE Configuration
10
2:
3:
4:
1
0.1
0.01
TA = 25qC
0.001
10m
100m
RL = 2 Ω, 3Ω, 4Ω
1
Po - Output Power - W
10
100
10
TA = 25qC
1W
5W
20W
1
0.1
0.01
0.001
20
100
1k
f - Frequency - Hz
D009
TA = 25°C
RL = 4Ω
Figure 9. Total Harmonic Distortion+Noise vs Output
Power
20k
D010
P = 1W, 5W, 20W
TA = 25°C
60
10
2:
3:
4:
TA = 25qC
1W
5W
20W
50
1
0.1
0.01
40
30
20
10
0.001
20
10k
Figure 10. Total Harmonic Distortion+Noise vs Frequency
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz,
ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025
measurement filters, unless otherwise noted.
100
1k
f - Frequency - Hz
0
10
10k 20k
D011
RL = 4Ω
P = 1W, 5W, 20W
AUX-0025 filter, 80 kHz analyzer BW
THD+N = 10%
TA = 25qC
TA = 25°C
15
20
25
PVDD - Supply Voltage - V
RL = 2 Ω, 3Ω, 4Ω
THD+N = 10%
30
33
D012
TA = 25°C
Figure 11. Total Harmonic Distortion+Noise vs Frequency
Figure 12. Output Power vs Supply Voltage
50
PO - Output Power - W
40
2:
3:
4:
30
20
10
THD+N = 1%
TA = 25qC
0
10
15
20
25
PVDD - Supply Voltage - V
RL = 2 Ω, 3Ω, 4Ω
THD+N = 1%
30
33
D013
TA = 25°C
Figure 13. Output Power vs Supply Voltage
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7.9.3 PBTL Configuration
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 4Ω, fS = 450 kHz,
ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10, outputs paralleled before LC
filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.
10
2:
3:
4:
1
0.1
0.01
TA = 25qC
0.001
10m
100m
RL = 2 Ω, 3Ω, 8Ω
1
10
Po - Output Power - W
100
300
TA = 25qC
1W
40W
120W
1
0.1
0.01
0.001
0.0004
20
100
1k
f - Frequency - Hz
D014
TA = 25°C
RL = 2Ω
Figure 14. Total Harmonic Distortion+Noise vs Output
Power
20k
D015
P = 1W, 40W, 120W
TA = 25°C
220
10
TA = 25qC
1W
40W
120W
2:
3:
4:
200
180
1
0.1
0.01
160
140
120
100
80
60
40
THD+N = 10%
TA = 25qC
20
0.001
20
10k
Figure 15. Total Harmonic Distortion+Noise vs Frequency
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
100
1k
f - Frequency - Hz
10k
0
10
40k
D016
RL = 2Ω
P = 1W, 40W, 120W
AUX-0025 filter, 80 kHz analyzer BW
TA = 25°C
15
20
25
PVDD - Supply Voltage - V
RL = 2Ω, 3Ω, 4Ω
Figure 16. Total Harmonic Distortion+Noise vs Frequency
THD+N = 10%
30
33
D017
TA = 25°C
Figure 17. Output Power vs Supply Voltage
180
PO - Output Power - W
160
140
2:
3:
4:
120
100
80
60
40
THD+N = 1%
TA = 25qC
20
0
10
15
RL = 2Ω, 3Ω, 4Ω
20
25
PVDD - Supply Voltage - V
THD+N = 1%
30
33
D018
TA = 25°C
Figure 18. Output Power vs Supply Voltage
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions,
BTL Configuration, SE Configuration and PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3244 needs only a 12-V supply in addition to the (typical) 30-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V
source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see
application diagram for details) is recommended. These RC filters provide the recommended high-frequency
isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to
the device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3244 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power
supply is settled for minimum turn on audible artefacts. Moreover, the TPA3244 device is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within the specified range.
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9.2 Functional Block Diagrams
/CLIP_OTW
VDD
VBG
POWERUP
RESET
PROTECTION & I/O LOGIC
/FAULT
M1
M2
/RESET
C_START
VREG
AVDD
UVP
DVDD
GND
TEMP
SENSE
GVDD_AB
GND
GVDD_CD
DIFFOC
STARTUP
CONTROL
OVER-LOAD
PROTECTIO
N
CB3C
CURRENT
SENSE
OC_ADJ
OSC_IOM
OSC_IOP
OSCILLATO
R
PPSC
FREQ_ADJ
PVDD_X
OUT_X
GND
GVDD_AB
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_AB
INPUT_A
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND
GVDD_AB
BST_B
PVDD_AB
INPUT_B
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND
GVDD_CD
BST_C
PVDD_CD
INPUT_C
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_C
GND
GVDD_CD
BST_D
PVDD_CD
INPUT_D
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND
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Functional Block Diagrams (continued)
Capacitor for
External
Filtering
and
Startup/Stop
C_START
/CLIP_OTW
/RESET
/FAULT
System
microcontroller or
Analog circuitry
BST_A
OSC_IOP
Oscillator
Synchronization
BST_B
OSC_IOM
OUT_A
INPUT_B
FREQ_ADJ
PVDD
30V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GVDD, VDD,
DVDD and
AVDD
Power Supply
Decoupling
BST_D
Bootstrap
Capacitors
Hardwire
OverCurrent
Limit
GND
GND
12V
OC_ADJ
AVDD
VBG
M2
OUT_D
2nd Order
L-C Output
Filter for
Each
H-Bridge
BST_C
DVDD
M1
Output
H-Bridge 2
VDD
Hardwire
Mode
Control
GVDD_AB, CD
Input
H-Bridge 2
INPUT_D
GND
ANALOG_IN_D
OUT_C
INPUT_C
Input DC
Blocking
Caps
OUT_B
2nd Order
L-C Output
Filter for
Each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
GND
Hardwire PWM
Frame Adjust and
Master/Slave
Mode
ANALOG_IN_C
Input
H-Bridge 1
PVDD_AB, CD
ANALOG_IN_B
Output
H-Bridge 1
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
Bootstrap
Capacitors
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
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Figure 19. System Block Diagram
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9.3 Feature Description
9.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see Table 2).
Table 2. Error Reporting
FAULT
CLIP_OTW
DESCRIPTION
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction
temperature higher than 125°C (overtemperature warning)
0
0
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C
(overtemperature warning)
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
1
0
Junction temperature higher than 125°C (overtemperature warning)
1
1
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by, that is, turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.
9.4 Device Functional Modes
9.4.1 Device Protection System
The TPA3244 device contains advanced protection circuitry carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions
such as short circuits, overload, overtemperature, and undervoltage. The TPA3244 device responds to a fault by
immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault
condition has been removed, that is, the supply voltage has increased.
The device will handle errors, as shown in Table 3.
Table 3. Device Protection
BTL
LOCAL
ERROR IN
A
B
C
D
MODE
PBTL
TURNS OFF
LOCAL
ERROR IN
A+B
C+D
MODE
SE
MODE
TURNS OFF
LOCAL
ERROR IN
TURNS OFF
A
B
C
A
A+B+C+D
D
B
C
D
A+B
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).
9.4.1.1 Overload and Short Circuit Current Protection
The TPA3244 device has fast reacting current sensors with a programmable trip threshold (OC threshold) on all
high-side and low-side FETs. To prevent output current to increase beyond the programmed threshold, TPA3244
has the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control,
CB3C) or to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown).
CB3C prevents premature shutdown due to high output current transients caused by high level music transients
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and a drop of real speaker’s load impedance, and allows the output current to be limited to a maximum
programmed level. If the maximum output current persists, i.e. the power stage being overloaded with too low
load impedance, the device will shut down the affected output channel and the affected output is put in a highimpedance (Hi- Z) state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an
over current event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning
of next PWM frame.
PWM_X
RISING EDGE PWM
SETS CB3C LATCH
HS PWM
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
Figure 20. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
R_Latch, max,
Latching OC, min level
R_Latch, min,
Latching OC, max level
R_OC, min,
CB3C, max level
R_OC, max,
CB3C, min level
ROC_ADJ
Figure 21. OC Threshold versus OC_ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
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Table 4. Device Protection
OC_ADJ Resistor Value
Protection Mode
OC Threshold
22kΩ
CB3C
16.3A
24kΩ
CB3C
15.1A
27kΩ
CB3C
13.5A
30kΩ
CB3C
12.3A
47kΩ
Latched OC
16.3A
51kΩ
Latched OC
15.1A
56kΩ
Latched OC
13.5A
64kΩ
Latched OC
12.3A
9.4.1.2 Signal Clipping and Pulse Injector
A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3244 is designed to drive
unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying
excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback
loop of the audio channel will respond to this condition with a saturated state, and the output PWM signals
will stop unless special circuitry is implemented to handle this situation. To prevent the output PWM signals
from stopping in a clipping or CB3C situation, narrow pulses are injejcted to the gate drive to maintain output
activity. The injected narrow pulses are injected at every 4th PWM frame, and thus the effective switching
frequency during this state is reduced to 1/4 of the normal switching frequency.
Signal clipping is signalled on the CLIP_OTW pin and is self clearing when signal level reduces and the
device reverts to normal operation. The CLIP_OTW pulses starts at the onset to output clipping, typically at a
THD level around 0.01%, resulting in narrow CLIP_OTW pulses starting with a pulse width of ~500ns.
Figure 22. Signal Clipping PWM and Speaker Output Signals
9.4.1.3 DC Speaker Protection
The output DC protection scheme protects a speaker from excess DC current in case one terminal of the
speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short
circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current
levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in
the event of the unbalance exceeding a programmed threshold, the overload counter increments until its
maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in PBTL and
SE mode operation.
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9.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the
device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,
and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL
and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.
9.4.1.5 Overtemperature Protection OTW and OTE
The TPA3244 device has a two-level temperature-protection system that asserts an active-low warning signal
(CLIP_OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To
clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
9.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
The UVP and POR circuits of the TPA3244 device fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical
CharacteristicsElectrical Characteristics table. Although GVDD_X and VDD are independently monitored, a
supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs
immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device
automatically resumes operation when all supply voltages have increased above the UVP threshold.
9.4.1.7 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the
affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being
present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over
temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting
in device shutdown (OTE).
Table 5. Error Reporting
Fault/Event
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Output FETs
Voltage Fault
Global
FAULT pin
Self Clearing
Increase affected
supply voltage
HI-Z
Power On Reset
Global
FAULT pin
Self Clearing
Allow DVDD to
rise
HI-Z
Voltage Fault
Channel (Half
Bridge)
None
Self Clearing
Allow BST cap to
recharge (lowside HighSide off
ON, VDD 12V)
PVDD_X UVP
VDD UVP
AVDD UVP
POR (DVDD UVP)
BST_X UVP
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Table 5. Error Reporting (continued)
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Output FETs
OTW
Thermal Warning
Global
OTW pin
Self Clearing
Cool below OTW
threshold
Normal operation
OTE
Thermal
Shutdown
Global
FAULT pin
Latched
Toggle RESET
HI-Z
Fault/Event
OLP (CB3C>1.7ms)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
Latched OC
(47kΩ<ROC_ADJ<68 OC Shutdown
kΩ)
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
CB3C
(22kΩ<ROC_ADJ<30 OC Limiting
kΩ)
Channel
None
Self Clearing
Reduce signal
level or remove
short
Flip state, cycle
by cycle at fs/3
Global
None
Self Clearing
Resume OSC_IO
HI-Z
activity
Stuck at Fault (1)
(1)
No OSC_IO
activity in Slave
Mode
Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical
CharacteristicsElectrical Characteristics table of this data sheet.
9.4.1.8 Device Reset
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is
forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault.
To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of
FAULT.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
TPA3244 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
10.2 Typical Applications
10.2.1 Stereo BTL Application
This section provides an example for configuring the TPA3244 in bridge-tied load (BTL) mode.
3R3
100nF
33nF
1
2
/CLIP_OTW
100nF
3
4
/FAULT
5
/RESET
10µF
6
INPUT_C
10µF
7
INPUT_D
10nF
8
1µF
9
10
11
1µF
12
13
14
30k
15
22k
16
10µF
17
INPUT_A
10µF
18
INPUT_B
19
20
+12V
21
470uF
100nF
22
100nF
3R3
GVDD_CD
BST_D
/CLIP_OTW
BST_C
GND
VBG
/FAULT
GND
/RESET
OUT_D
INPUT_D
OUT_D
INPUT_C
PVDD_CD
C_START
PVDD_CD
AVDD
PVDD_CD
OUT_C
GND
GND
DVDD
TPA3244
GND
GND
OSC_IOP
OUT_B
OSC_IOM
PVDD_AB
FREQ_ADJ
PVDD_AB
OC_ADJ
PVDD_AB
INPUT_B
OUT_A
INPUT_A
OUT_A
M2
M1
GND
GND
VDD
BST_B
GVDD_AB
BST_A
44
10µH
43
10nF
42
33nF
1nF
1µF
41
3R3
40
1µF
39
38
1nF
37
3R3
10nF
1µF
10µH
470uF
36
PVDD
35
34
1µF
GND
33
32
1µF
31
30
10µH
1µF
470uF
10nF
29
1nF
28
1µF
3R3
27
1µF
26
1nF
25
3R3
10nF
33nF
24
10µH
23
33nF
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Figure 23. Typical Differential (2N) BTL Application
22
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Typical Applications (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters in Table 6.
Table 6. Design Requirements, BTL Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply 12 V
12 V
High Power Supply
12 - 30 V
M2 = L
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ± 3.9V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
3-8Ω
10.2.1.2 Detailed Design Procedures
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply nominally operating at a low rail adjusting to a higher supply rail.
The device is inverting the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.
10.2.1.2.1 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
10.2.1.2.2 PVDD Capacitor Recommendation
The PVDD decoupling capacitors must be placed as close to the device pins a possible to insure short trace
length and low a low inductance path. Likewise the ground path for these capacitors must provide a good
reference and should be substantial. This will keep voltage ringing on PVDD to a minimum.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50 V is required for use with a 30V power
supply.
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50 V supports most applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.2.3 PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3244 device. The
use of this material can provide for higher power output, improved thermal performance, and better EMI margin
(due to lower PCB trace inductance.
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10.2.1.2.4 Oscillator
The built in oscillator frequency can be trimmed by an external resistor from the FREQ_ADJ pin to GND.
Changes in the oscillator frequency should be made with resistor values specified in Recommended Operating
Conditions while RESET is low.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower or higher values. These values should be chosen such that the nominal
and the alternate switching frequencies together result in the fewest cases of interference throughout the AM
band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in
master mode.
For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the
OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter-channel
delay is automatically set up between the switching of the audio channels, which can be illustrated by no idle
channels switching at the same time. This will not influence the audio output, but only the switch timing to
minimize noise coupling between audio channels through the power supply. Inter-channel delay is needed to
optimize audio performance and to get better operating conditions for the power supply. The inter-channel delay
will be set up for a slave device depending on the polarity of the OSC_I/O connection as follows:
• Slave 1 mode has normal polarity (master + to slave + and master - to slave -)
• Slave 2 mode has reverse polarity (master + to slave - and master - to slave +)
The interchannel delay for interleaved channel idle switching is given in the table below for the master/slave and
output configuration modes in degrees relative to the PWM frame.
Table 7. Master/Slave Inter Channel Delay Settings
Master
M1 = 0, M2 = 0, 2 x M1 = 1, M2 = 0, 1 x M1 = 0, M2 = 1, 1 x M1 = 1, M2 = 1, 4 x
BTL mode
BTL + 2 x SE
PBTL mode
SE mode
mode
OUT_A
0°
0°
0°
0°
OUT_B
180°
180°
180°
60°
OUT_C
60°
60°
0°
0°
OUT_D
240°
120°
180°
60°
Slave 1
OUT_A
60°
60°
60°
60°
OUT_B
240°
240°
240°
120°
OUT_C
120°
120°
60°
60°
OUT_D
300°
180°
240°
120°
Slave 2
24
OUT_A
30°
30°
30°
30°
OUT_B
210°
210°
210°
90°
OUT_C
90°
90°
30°
30°
OUT_D
270°
150°
210°
90°
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10.2.1.3 Application Curves
Relevant performance plots for the TPA3244 device shown in are shown in BTL Configuration.
Table 8. Relevant Performance Plots, BTL Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion+Noise vs Frequency
Figure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 2
Total Harmonic Distortion + Noise vs Output Power
Figure 3
Output Power vs Supply Voltage, 10% THD+N
Figure 4
Output Power vs Supply Voltage, 10% THD+N
Figure 6
System Efficiency vs Output Power
Figure 6
System Power Loss vs Output Power
Figure 7
Output Power vs Case Temperature
Noise Amplitude vs Frequency
Figure 8
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10.2.2 Typical Application, Single Ended (1N) SE
This section provides an example for configuring the TPA3244 in single-ended output (SE) mode.
470uF
15µH
3R3
100nF
33nF
1
2
/CLIP_OTW
100nF
3
4
/FAULT
5
/RESET
10µF
6
INPUT_C
10µF
7
INPUT_D
470nF
8
1µF
9
10
11
1µF
12
13
14
30k
15
22k
16
10µF
17
INPUT_A
10µF
18
INPUT_B
19
20
+12V
21
470uF
100nF
22
GVDD_CD
BST_D
/CLIP_OTW
BST_C
VBG
GND
/FAULT
GND
/RESET
OUT_D
INPUT_D
OUT_D
INPUT_C
PVDD_CD
C_START
PVDD_CD
AVDD
PVDD_CD
OUT_C
GND
GND
DVDD
TPA3244
GND
GND
OSC_IOP
OUT_B
OSC_IOM
PVDD_AB
FREQ_ADJ
PVDD_AB
OC_ADJ
PVDD_AB
INPUT_B
OUT_A
INPUT_A
OUT_A
M2
GND
M1
GND
VDD
GVDD_AB
BST_B
BST_A
100nF
44
10nF
43
1µF
42
1nF
3R3
33nF
41
1µF
1nF
40
3R3
10nF
39
38
1µF
37
470uF
15µH
470uF
36
PVDD
35
34
1µF
GND
33
32
1µF
31
30
470uF
15µH
1µF
470uF
29
28
10nF
27
1µF
1nF
26
3R3
25
33nF
1µF
24
1nF
3R3
10nF
23
33nF
3R3
470uF
15µH
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Figure 24. Typical Single Ended (1N) SE Application
10.2.2.1 Design Requirements
For this design example, use the parameters in Table 9.
Table 9. Design Requirements, SE Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply 12 V
12 V
High Power Supply
12 - 30 V
M2 = H
Mode Selection
M1 = H
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
26
Output Filters
Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
Speaker Impedance
2-8Ω
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10.2.2.2 Application Curves
Relevant performance plots for TPA3244 shown in SE Configuration.
Table 10. Relevant Performance Plots, SE Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion + Noise vs Output Power
Figure 3
Total Harmonic Distortion+Noise vs Frequency
Figure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 2
Output Power vs Supply Voltage, 10% THD+N
Figure 4
Output Power vs Supply Voltage, 10% THD+N
Figure 6
Output Power vs Case Temperature
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10.2.3 Typical Application, Differential (2N), PBTL (Outputs Paralleled before LC filter)
TPA3244 can be configured in mono PBTL mode by paralleling the outputs before the LC filter or after the LC
filter (see Typical Application, Differential (2N), PBTL (Outputs Paralleled after LC filter)). Paralleled outputs
before the LC filter is recommended for better performance and limiting the number of output LC filter inductors,
only two inductors required. This sections shows an example of paralleled outputs before the LC filter.
3R3
100nF
33nF
1
2
/CLIP_OTW
100nF
3
4
/FAULT
5
/RESET
6
7
10nF
8
1µF
9
10
11
1µF
12
13
14
30k
15
22k
16
10µF
17
INPUT_A
10µF
18
INPUT_B
19
20
+12V
21
470uF
100nF
22
GVDD_CD
BST_D
/CLIP_OTW
BST_C
VBG
GND
/FAULT
GND
/RESET
OUT_D
INPUT_D
OUT_D
INPUT_C
PVDD_CD
C_START
PVDD_CD
AVDD
PVDD_CD
OUT_C
GND
GND
DVDD
TPA3244
OSC_IOP
GND
GND
OUT_B
OSC_IOM
PVDD_AB
FREQ_ADJ
PVDD_AB
OC_ADJ
PVDD_AB
INPUT_B
OUT_A
INPUT_A
OUT_A
M2
GND
M1
GND
VDD
BST_B
GVDD_AB
BST_A
44
43
42
33nF
41
40
39
38
PVDD
1µF
37
470uF
10µH
36
10nF
1nF
35
34
1µF
32
470nF
470nF
470nF
470nF
3R3
33
1nF
1µF
3R3
10nF
31
30
10µH
1µF
470uF
29
GND
28
27
26
25
33nF
24
23
100nF
33nF
3R3
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Figure 25. Typical Differential (2N) PBTL (Outputs Paralleled before LC filter) Application
10.2.3.1 Design Requirements
For this design example, use the parameters in Table 11.
Table 11. Design Requirements, PBTL (Outputs Paralleled before LC filter) Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply 1 2V
12 V
High Power Supply
12 - 30 V
M2 = H
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
28
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
2-4Ω
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10.2.3.2 Application Curves
Relevant performance plots for TPA3244 shown in PBTL Configuration.
Table 12. Relevant Performance Plots, PBTL (Outputs Paralleled before LC filter)
Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion + Noise vs Output Power
Figure 3
Total Harmonic Distortion+Noise vs Frequency
Figure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 2
Output Power vs Supply Voltage, 10% THD+N
Figure 4
Output Power vs Supply Voltage, 10% THD+N
Figure 6
Output Power vs Case Temperature
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10.3 Typical Application, Differential (2N), PBTL (Outputs Paralleled after LC filter)
TPA3244 can be configured in mono PBTL mode by paralleling the outputs before the LC filter (see Typical
Application, Differential (2N), PBTL (Outputs Paralleled before LC filter)) or after the LC filter. Paralleled outputs
after the LC filter may be preferred if: a single board design must support both PBTL and BTL, or in the case
multiple, smaller paralleled inductors are preferred due to size or cost. Paralleling after the LC filter requires four
inductors, one for each OUT_x. This section shows an example of paralleled outputs after the LC filter.
3R3
100nF
33nF
1
2
/CLIP_OTW
100nF
3
4
/FAULT
5
/RESET
6
7
10nF
8
1µF
9
10
11
1µF
12
13
14
30k
15
22k
16
10µF
17
INPUT_A
10µF
18
INPUT_B
19
20
+12V
21
470uF
100nF
22
GVDD_CD
BST_D
/CLIP_OTW
BST_C
GND
VBG
/FAULT
GND
/RESET
OUT_D
INPUT_D
OUT_D
INPUT_C
PVDD_CD
C_START
PVDD_CD
AVDD
PVDD_CD
OUT_C
GND
GND
DVDD
TPA3244
OSC_IOP
GND
GND
OUT_B
OSC_IOM
PVDD_AB
FREQ_ADJ
PVDD_AB
OC_ADJ
PVDD_AB
INPUT_B
OUT_A
INPUT_A
OUT_A
M2
GND
M1
GND
VDD
GVDD_AB
BST_B
BST_A
44
10µH
43
42
33nF
41
40
39
38
PVDD
1µF
37
10µH
470uF
36
10nF
1nF
35
34
680nF
1µF
3R3
33
32
680nF
1nF
1µF
3R3
10nF
31
30
10µH
1µF
470uF
29
GND
28
27
26
25
33nF
24
10µH
23
100nF
33nF
3R3
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Figure 26. Typical Differential (2N) PBTL (Outputs Paralleled after LC filter) Application
10.3.1 Design Requirements
For this design example, use the parameters in Table 13.
Table 13. Design Requirements, PBTL (Outputs Paralleled after LC filter) Application
DESIGN PARAMETER
EXAMPLE
Low Power (Pull-up) Supply
3.3 V
Mid Power Supply 12 V
12 V
High Power Supply
12 - 30 V
M2 = H
Mode Selection
M1 = L
INPUT_A = ±3.9V (peak, max)
INPUT_B = ±3.9V (peak, max)
Analog Inputs
INPUT_C = Grounded
INPUT_D = Grounded
30
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
2-4Ω
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10.3.2 Application Curves
Relevant performance plots for TPA3244 shown in PBTL Configuration.
Table 14. Relevant Performance Plots, PBTL (Outputs Paralleled before LC filter)
Configuration
PLOT TITLE
FIGURE NUMBER
Total Harmonic Distortion + Noise vs Output Power
Figure 3
Total Harmonic Distortion+Noise vs Frequency
Figure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Figure 2
Output Power vs Supply Voltage, 10% THD+N
Figure 4
Output Power vs Supply Voltage, 10% THD+N
Figure 6
Output Power vs Case Temperature
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11 Power Supply Recommendations
11.1 Power Supplies
The TPA3244 device requires two external power supplies for proper operation. A high-voltage supply called
PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one
mid-voltage power supply for GVDD_X and VDD is required to power the gate-drive and other internal digital and
analog portions of the device. The allowable voltage range for both the PVDD and the GVDD_X/VDD supplies
are listed in the Recommended Operating Conditions table. Ensure both the PVDD and the GVDD_X/VDD
supplies can deliver more current than listed in the Electrical Characteristics table.
11.1.1 VDD Supply
The VDD supply required from the system is used to power several portions of the device. It provides power to
internal regulators DVDD and AVDD that are used to power digital and analog sections of the device,
respectively. Proper connection, routing, and decoupling techniques are highlighted in the TPA3244 Evaluation
Module User's Guide (SLVUAT5) (as well as the Application Information section and Layout Examples section)
and must be followed as closely as possible for proper operation and performance. Deviation from the guidance
offered in the TPA3244 Evaluation Module User's Guide (SLVUAT5), which followed the same techniques as
those shown in the Application Information section, may result in reduced performance, errant functionality, or
even damage to the TPA3244 device. Some portions of the device also require a separate power supply which is
a lower voltage than the VDD supply. To simplify the power supply requirements for the system, the TPA3244
device includes integrated low-dropout (LDO) linear regulators to create these supplies. These linear regulators
are internally connected to the VDD supply and their outputs are presented on AVDD and DVDD pins, providing
a connection point for an external bypass capacitors. It is important to note that the linear regulators integrated in
the device have only been designed to support the current requirements of the internal circuitry, and should not
be used to power any additional external circuitry. Additional loading on these pins could cause the voltage to
sag and increase noise injection, which negatively affects the performance and operation of the device.
11.1.2 GVDD_X Supply
The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges. Proper
connection, routing, and decoupling techniques are highlighted in the TPA3244 Evaluation Module User's Guide
(SLVUAT5) (as well as the Application Information section and Layout Examples section) and must be followed
as closely as possible for proper operation and performance. Deviation from the guidance offered in the
TPA3244 device EVM User's Guide, which followed the same techniques as those shown in the Application
Information section, may result in reduced performance, errant functionality, or even damage to the TPA3244
device.
11.1.3 PVDD Supply
The output stage of the amplifier drives the load using the PVDD supply. This is the power supply which provides
the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3244 Evaluation Module User's Guide (SLVUAT5) (as well as the Application Information
section and Layout Examples section) and must be followed as closely as possible for proper operation and
performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple
the output power stages in the manner described in the TPA3244 Evaluation Module User's Guide (SLVUAT5).
The lack of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can
damage the device, or cause poor audio performance and device shutdown faults.
11.2 Powering Up
The TPA3244 device does not require a power-up sequence, but it is recommended to hold RESET low for at
least 250 ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltages are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit
to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as
initiating a controlled ramp up sequence of the output voltage.
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Powering Up (continued)
PVDD
VDD
GVDD
DVDD
/RESET
AVDD
C 70µs
tPrecharge
C 200ms
/FAULT
VIN_X
OUT_X
tStartup ramp
VOUT_X
V_CSTART
Figure 27. Startup Timing
When RESET is released to turn on the TPA3244 device, FAULT signal will turn low and AVDD voltage regulator
will be enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold
(see the Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage
across the input AC coupling capacitors, before the ramp up sequence starts.
11.3 Powering Down
The TPA3244 device does not require a power-down sequence. The device remains fully operational as long as
the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold. Although not specifically required, it is a good practice to hold RESET low during power down, thus
preventing audible artifacts including pops or clicks by initiating a controlled ramp down sequence of the output
voltage.
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11.4 Thermal Design
11.4.1 Thermal Performance
The TPA3244 device thermal performance is dependent on the thermal design of the PCB. As a result, the
maximum continuous output power attainable will be influenced by the PCB design. The continuous power rating
is lower than the peak output power capability of the device. The peak power rating of the TPA3244 deviceis
based on the burst capability of the device. The peak to average power ratio of the TPA3244 device is well
suited to handle even demanding audio playback without thermal shutdown. Thermal performance with typical
audio content (burst) versus sine wave content (continuous) should be considered when defining the thermal test
requirements for the end product.
11.4.2 Thermal Performance with Continuous Output Power
It is recommended to operate the TPA3244 device below the OTW threshold, which in most systems will require
the average output power to be below the maximum peak output power. The maximum continuous power, the
TPA3244 device will deliver depends directly on the thermal design of the PCB and for the entire system (closed
box with no air flow, or a fanned system etc.). Thermal performance is also impacted by PVDD voltage and
switching frequency. The best configuration for a given application will often depend on the continuous output
power requirements.
Table 15. Device and PCB Temperatures with 8-Ω Load, TA = 40°C
TA = 40°C, TPA3244 EVM, No Airflow. Steady State Temperatures.
PVDD
Switching
Frequency
Device Top
Temperature
Maximum PCB
Temperature
Comment
30V
450kHz
63W
30V
450kHz
31.5W
10% THD
128ºC
93ºC
OTW after 187 seconds.
1/2 of 10% THD power
111ºC
83ºC
30V
450kHz
30V
450kHz
15.75W
1/4 of 10% THD power
89ºC
71ºC
7.9W
1/8 of 10% THD power
76ºC
63ºC
30V
600kHz
62W
10% THD
141ºC
100ºC
OTW after 38 seconds. Not
recommended.
30V
30V
600kHz
31W
1/2 of 10% THD power
130ºC
94ºC
OTW after 205 seconds.
600kHz
15.5W
1/4 of 10% THD power
99ºC
77ºC
30V
600kHz
7.75W
1/8 of 10% THD power
84ºC
68ºC
Continuous Power [W]
Table 16. Device and PCB Temperatures with 4-Ω Load, TA = 40°C
TA = 40°C, TPA3244 EVM, No Airflow. Steady State Temperatures.
(1)
34
PVDD
Switching
Frequency
30V
450kHz
114W
10% THD
OTE (1)
OTW and OTE after less than 1
second. Not recommended.
30V
450kHz
57W
1/2 of 10% THD power
OTE (1)
OTW after 3 seconds and OTE
after 9 seconds. Not
recommended.
30V
450kHz
28.5W
1/4 of 10% THD power
OTE (1)
OTW after 44 seconds and OTE
after 327 seconds. Not
recommended.
30V
450kHz
14.25W
1/8 of 10% THD power
30V
600kHz
26V
450kHz
84W
10% THD
OTE (1)
OTW after 3 seconds and OTE
after 6 seconds. Not
recommended.
26V
450kHz
42W
1/2 of 10% THD power
OTE (1)
OTW after 15 seconds and OTE
after 56 seconds. Not
recommended.
26V
450kHz
21W
1/4 of 10% THD power
113ºC
84ºC
26V
450kHz
10.5W
1/8 of 10% THD power
87ºC
69ºC
Continuous Power [W]
Device Top
Temperature
Maximum PCB
Temperature
107ºC
Comment
82ºC
Not recommended
Steady state data is not available because device heats up to OTE in this condition.
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Table 16. Device and PCB Temperatures with 4-Ω Load, TA = 40°C (continued)
TA = 40°C, TPA3244 EVM, No Airflow. Steady State Temperatures.
10% THD
OTE (1)
OTW after 3 seconds and OTE
after 6 seconds. Not
recommended.
41.5W
1/2 of 10% THD power
OTE (1)
OTW after 9 seconds and OTE
after 30 seconds. Not
recommended.
600kHz
20.75W
1/4 of 10% THD power
129ºC
93ºC
600kHz
10.50W
1/8 of 10% THD power
97ºC
76ºC
26V
600kHz
83W
26V
600kHz
26V
30V
OTW after 301 seconds.
11.4.3 Thermal Performance with Non-Continuous Output Power
As audio signals often have a peak to average ratio larger than one (average level below maximum peak output),
the thermal performance for audio signals can be illustrated using burst signals with different burst ratios.
Figure 28. Example of audio signal
A burst signal is characterized by the high-level to low-level ratio as well as the duration of the high level and low
level, e.g. a burst 1:4 stimuli is a single period of high level followed by 4 cycles of low level.
High level
Low level
1cycle : 4cycles
Figure 29. Example of 1:4 Burst Signal
The following analysis of thermal performance for the TPA3244 device is made with the TPA3244 EVM
surrounded by still air (no airflow) with a controlled air temperature of 40°C. For 30 V operation the system is not
thermally limited with 8Ω load, but depending on the burst stimuli for operation at 30V some thermal limitations
may occur, depending on switching frequency and average to maximum power ratio. Low to maximum power
ratio of the burst stimuli is given in the plots as for example P1:8 which equals low level burst cycles of 1/8 power
of the high level cycles. The level of the high power cycles is set equal to 10% THD level.
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140
130
140
Device Top P1:8
PCB Max P1:8
Device Top P1:4
PCB Max P1:4
Device Top P1:2
PCB Max P1:2
130
120
Temperature (qC)
Temperature (qC)
120
110
100
90
90
80
70
70
Device Top P1:8
PCB Max P1:8
Device Top P1:4
PCB Max P1:4
Device Top P1:2
PCB Max P1:2
60
1:8
1:4
1:2
1
Burst Ratio (High:Low)
PVDD = 30 V, fs = 450kHz
1:8
TA = 40°C
140
130
130
Temperature (qC)
140
100
1
D033
RL = 8Ω
TA = 40°C
Figure 31. Device and PCB Temperatures vs. Burst Ratio
150
110
1:2
PVDD = 30 V, fs = 600kHz
150
120
1:4
Burst Ratio (High:Low)
D032
RL = 8Ω
Figure 30. Device and PCB Temperatures vs. Burst Ratio
Temperature (qC)
100
80
60
120
110
100
90
90
80
Device Top P1:8
PCB Max P1:8
80
Device Top P1:4
PCB Max P1:4
1:8
1:4
1:2
Burst Ratio (High:Low)
PVDD = 26 V, fs = 450kHz
RL = 4Ω
Device Top P1:8
PCB Max P1:8
Device Top P1:4
PCB Max P1:4
70
70
1:8
1
D034
TA = 40°C
Figure 32. Device and PCB Temperatures vs. Burst Ratio
36
110
1:4
1:2
Burst Ratio (High:Low)
PVDD = 26 V, fs = 600kHz
RL = 4Ω
1
D035
TA = 40°C
Figure 33. Device and PCB Temperatures vs. Burst Ratio
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12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
PCB layout, audio performance and EMI are linked closely together.
Routing the audio input should be kept short and together with the accompanied audio source ground.
The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible.
A local ground area underneath the device is important to keep solid to minimize ground bounce.
Orient the passive component so that the narrow end of the passive component is facing the TPA3244
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
Avoid placing other heat producing components or structures near the TPA3244 device.
Avoid cutting off the flow of heat from the TPA3244 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in Figure 34.
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12.2 Layout Examples
12.2.1 BTL Application Printed Circuit Board Layout Example
Pad to top layer ground pour
Top Layer Signal Traces
Bottom Layer Signal Traces
Bottom to top layer connection via
System Processor
10k
22k
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T1
T2
T2
T1
T3
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors placed close to the pins.
D.
Note T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 34. BTL Application Printed Circuit Board - Composite
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Layout Examples (continued)
12.2.2 SE Application Printed Circuit Board Layout Example
Pad to top layer ground pour
Top Layer Signal Traces
Bottom Layer Signal Traces
Bottom to top layer connection via
System Processor
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
T1
34
11
½
T2
10k
22k
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T2
T1
T3
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins.
D.
Note T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 35. SE Application Printed Circuit Board - Composite
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Layout Examples (continued)
12.2.3 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
Pad to top layer ground pour
Top Layer Signal Traces
Bottom Layer Signal Traces
Bottom to top layer connection via
System Processor
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
T1
Grounded for PBTL
Grounded for PBTL
T2
10k
22k
20
25
21
24
22
23
T2
T1
T3
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
ote T3: Heat sink needs to have a good connection to PCB ground.
Figure 36. PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board - Composite
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Layout Examples (continued)
12.2.4 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
Pad to top layer ground pour
Top Layer Signal Traces
Bottom Layer Signal Traces
Bottom to top layer connection via
System Processor
Grounded for PBTL
Grounded for PBTL
10k
22k
1
44
23
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
14
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T1
T2
T2
T3
T1
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins.
D.
ote T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 37. PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board - Composite
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13 Device and Documentation Support
13.1 Documentation Support
TPA3244 Evaluation Module User's Guide (SLVUAT5)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PurePath, PowerPad, PowerPAD, E2E are trademarks of Texas Instruments.
Blu-Ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DDW0044D
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 1.250
PLASTIC SMALL OUTLINE
8.3
TYP
7.9
PIN 1 ID
AREA
A
42X 0.635
44
1
14.1
13.9
NOTE 3
2X
13.335
22
23
B
44X
6.2
6.0
0.27
0.17
0.08
0.1 C
C A B
SEATING PLANE
C
(0.15) TYP
SEE DETAIL A
23
22
4.43
3.85
EXPOSED
THERMAL PAD
7.30
6.72
0.25
GAGE PLANE
45
0 -8
2X (0.6)
NOTE 5
2X (0.13)
NOTE 5
1
1.2 MAX
0.75
0.50
0.15
0.05
DETAIL A
TYPICAL
44
4223171/A 07/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DDW0044D
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 9
SOLDER MASK
DEFINED PAD
(4.43)
SEE DETAILS
SYMM
44X (1.45)
1
44
44X (0.4)
42X (0.635)
(1.3)
TYP
45
SYMM
(7.3)
(14)
NOTE 9
(R0.05) TYP
( 0.2) TYP
VIA
23
22
METAL COVERED
BY SOLDER MASK
(0.65) TYP
(1.3 TYP)
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223171/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DDW0044D
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(4.43)
BASED ON
0.125 THICK
STENCIL
44X (1.45)
1
44
44X (0.4)
42X (0.635)
45
SYMM
(7.3)
BASED ON
0.125 THICK
STENCIL
22
23
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SYMM
(7.5)
SOLDER PASTE EXAMPLE
PAD 45:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
4.95 X 8.16
4.43 X 7.30 (SHOWN)
4.04 X 6.66
3.74 X 6.17
4223171/A 07/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPA3244
45
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA3244DDW
ACTIVE
HTSSOP
DDW
44
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
3244
TPA3244DDWR
ACTIVE
HTSSOP
DDW
44
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
3244
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA3244DDWR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DDW
44
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA3244DDWR
HTSSOP
DDW
44
2000
350.0
350.0
43.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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