Texas Instruments | TPA0211 2-W Mono Audio Power Amplifier (Rev. E) | Datasheet | Texas Instruments TPA0211 2-W Mono Audio Power Amplifier (Rev. E) Datasheet

Texas Instruments TPA0211 2-W Mono Audio Power Amplifier (Rev. E) Datasheet
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TPA0211
SLOS275E – JANUARY 2000 – REVISED NOVEMBER 2016
TPA0211 2-W Mono Audio Power Amplifier
1 Features
3 Description
•
•
•
•
The TPA0211 is a 2-W mono bridge-tied-load (BTL)
amplifier designed to drive speakers with as low as
4-Ω impedance. The device is ideal for small wireless
communicators, notebook PCs, PDAs, anyplace a
mono speaker and stereo headphones are required.
From a 5-V supply, the TPA0211 can deliver 2 W of
power into a 4-Ω speaker.
1
•
•
•
•
2 W Into 4 Ω From 5-V Supply
0.6 W Into 4 Ω From 3-V Supply
Wide Power Supply Compatibility: 3 V to 5 V
Low Supply Current:
– 4 mA Typical at 5 V
– 4 mA Typical at 3 V
Shutdown Control: 1 µA Typical
Shutdown Pin Is TTL Compatible
–40°C to 85°C Operating Temperature Range
Space-Saving, Thermally-Enhanced MSOPPowerPAD™ Packaging
The gain of the input stage is set by the user-selected
input resistor and a 50-kΩ internal feedback resistor
(AV = –RF / RI). The power stage is internally
configured with a gain of –1.25 V/V in SE mode, and
–2.5 V/V in BTL mode. Thus, the overall gain of the
amplifier is –62.5 kΩ/RI in SE mode and –125 kΩ/RI
in BTL mode. The input terminals are high-impedance
CMOS inputs, and can be used as summing nodes.
2 Applications
•
•
•
•
The TPA0211 is available in the 8-pin thermallyenhanced MSOP-PowerPAD package (DGN) and
operates over an ambient temperature range of
–40°C to 85°C.
Wireless Communictors
Notebook PCs
PDAs
Other Small Portable Audio Devices
Device Information(1)
PART NUMBER
TPA0211
PACKAGE
MSOP-PowerPAD (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Schematic
To power supply
CS
CI
CC
VDD
RI
IN
Audio Input
Vo+
TPA0211
Bypass
CB
SE/BTL
Shutdown Control
Shutdown
VoGND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA0211
SLOS275E – JANUARY 2000 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics – 3 V .................................
Electrical Characteristics – 5 V .................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
8
Parameter Measurement Information ................ 11
9
Detailed Description ............................................ 12
8.1 Set-Up for Graphs................................................... 11
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ................................................ 19
11 Power Supply Recommendations ..................... 23
11.1 Power Supply Decoupling Capacitors................... 23
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 23
12.3 Thermal Considerations ........................................ 24
13 Device and Documentation Support ................. 25
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2002) to Revision E
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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5 Device Comparison Table
DEVICE NUMBER
SPEAKER AMP TYPE
SPECIAL FEATURE
OUTPUT POWER (W)
PSRR (dB)
TPA0211
Class AB
—
2
58
TPA0213
Class AB
—
2
65
TPA0233
Class AB
—
2
58
TPA0253
Class AB
—
1
65
6 Pin Configuration and Functions
DGN Package
8-Pin MSOP-PowerPAD
Top View
IN
1
SHUTDOWN
2
8
VO±
7
GND
6
SE/BTL
5
VO+
Thermal
VDD
3
BYPASS
4
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BYPASS is the tap to the voltage divider for internal mid-supply bias.
This terminal must be connected to a 0.1-µF to 1-µF capacitor.
BYPASS
4
I
GND
7
—
IN
1
I
IN is the audio input terminal.
SE/BTL
6
I
When SE/BTL is held low, the TPA0211 is in BTL mode.
When SE/BTL is held high, the TPA0211 is in SE mode.
SHUTDOWN
2
I
SHUTDOWN places the entire device in shutdown mode when held low. TTL compatible input.
VDD
3
—
VDD is the supply voltage terminal.
VO+
5
O
VO+ is the positive output for BTL and SE modes.
VO–
8
O
VO– is the negative output in BTL mode and a high-impedance output in SE mode.
GND is the ground connection.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
6
V
VDD + 0.3
V
Supply voltage, VDD
Input voltage, VI
–0.3
Continuous total power dissipation
Internally limited
(see Dissipation Ratings)
Lead temperature, 1.6 mm (1/16 inch) from case (10 s)
260
°C
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
VIH
SE/BTL
High-level input voltage
VDD = 3 V
2.7
VDD = 5 V
4.5
SHUTDOWN
VIL
Low-level input voltage
TA
Operating free-air temperature
NOM
2.5
SE/BTL
MAX
UNIT
5.5
V
V
2
VDD = 3 V
1.65
VDD = 5 V
2.75
SHUTDOWN
V
0.8
–40
85
°C
7.4 Thermal Information
TPA0211
THERMAL METRIC (1)
DGN (MSOPPowerPAD)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
51.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.9
°C/W
RθJB
Junction-to-board thermal resistance
30.5
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
30.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics – 3 V
VDD = 3 V and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOO|
Output offset voltage
(measured differentially)
SE/BTL = 0 V, SHUTDOWN = 2 V, RL = 8 Ω,
inputs floating
IDD(BTL)
Supply current, BTL mode
SE/BTL = 1.375 V, SHUTDOWN = 2 V, VDD = 2.5 V
IDD(SE)
Supply current, SE mode
SE/BTL = 2.25 V, SHUTDOWN = 2 V, VDD = 2.5 V
IDD(SD)
Supply current,
shutdown mode
SE/BTL = 3 V, SHUTDOWN = 0 V
|IIH|
High-level input current
VDD = 3.3 V, VI = VDD
|IIL|
Low-level input current
VDD = 3.3 V, VI = 0 V
RF
Feedback resistor
SE/BTL = 0 V, SHUTDOWN = 2 V, VDD = 2.5 V,
RL = 4 Ω
MIN
TYP
MAX
30
mV
4
6
mA
2
4
mA
1
10
µA
SHUTDOWN
1
SE/BTL
1
SHUTDOWN
1
SE/BTL
1
45
UNIT
50
µA
µA
60
kΩ
OPERATING CHARACTERISTICS, RL = 4 Ω
THD = 1%, BTL mode, f = 1 kHz
PO
Output power
THD+N
Total harmonic distortion
plus noise
PO = 500 mW, f = 20 Hz to 20 kHz
BOM
Maximum output power
bandwidth
Gain = 2, THD = 2%
SNR
Signal-to-noise ratio
Vn
Output noise voltage
THD = 0.1%, SE mode, f = 1 kHz, RL = 32 Ω
CB = 0.47 µF,
f = 20 Hz to 20 kHz
660
mW
33
0.3%
20
kHz
88
dB
BTL mode, RL = 8
Ω,AV = 8 dB
65
SE mode, RL = 32 Ω,
AV = 2 dB
25
µVRMS
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7.6 Electrical Characteristics – 5 V
VDD = 5 V and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOO|
Output offset voltage
(measured differentially)
SE/BTL = 0 V, SHUTDOWN = 2 V, RL = 8 Ω,
inputs floating
IDD(BTL)
Supply current, BTL mode
SE/BTL = 2.75 V, SHUTDOWN = VDD
IDD(SE)
Supply current, SE mode
SE/BTL = 4.5 V, SHUTDOWN = VDD
IDD(SD)
Supply current,
shutdown mode
SE/BTL = 5 V, SHUTDOWN = 0 V
|IIH|
High-level input current
VDD = 5.5 V, VI = VDD
|IIL|
Low-level input current
VDD = 5.5 V, VI = 0 V
MIN
TYP
MAX
UNIT
30
mV
4
6
mA
2
4
mA
1
10
µA
SHUTDOWN
1
SE/BTL
1
SHUTDOWN
1
SE/BTL
1
µA
µA
OPERATING CHARACTERISTICS, RL = 4 Ω
THD = 1%, BTL mode, f = 1 kHz
PO
Output power
THD+N
Total harmonic distortion
plus noise
PO = 1.5 W, f = 20 Hz to 20 kHz
BOM
Maximum output power
bandwidth
Gain = 2.5, THD = 2%
SNR
Signal-to-noise ratio
Vn
THD = 0.1%, SE mode, f = 1 kHz, RL = 32 Ω
CB = 0.47 µF,
f = 20 Hz to 20 kHz
Output noise voltage
2
W
92
mW
0.2%
20
kHz
93
dB
BTL mode, RL = 8 Ω,
AV = 8 dB
65
SE mode, RL = 32 Ω,
AV = 2 dB
25
µVRMS
7.7 Dissipation Ratings
PACKAGE
DGN
(1)
6
TA ≤ 25°C
2.14 W
(1)
DERATING FACTOR
TA = 70°C
TA = 85°C
17.1 mW/°C
1.37 W
1.11 W
See PowerPAD™ Thermally Enhanced Package (SLMA002) for more information on the PowerPAD™ package. The thermal data was
measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on
page 33 of that document.
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7.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
IDD
PO
Supply ripple rejection ratio
vs Frequency
Supply current
vs Supply voltage
Figure 3
vs Supply voltage
Figure 4, Figure 5
Output power
Figure 1, Figure 2
vs Load resistance
Figure 6, Figure 7
Figure 8, Figure 9,
Figure 10, Figure 11
vs Frequency
THD+N
Total harmonic distortion plus noise
Figure 12, Figure 13, Figure 14,
Figure 15, Figure 16, Figure 17
vs Output power
Vn
Output noise voltage
vs Frequency
Figure 18, Figure 19
Closed loop gain and phase
Figure 20, Figure 21
0
0
R L = 8 Ÿ,
C B = 1 µF
Mode = BTL
±20
±30
±40
±50
±60
±70
±80
±20
±30
±40
±50
±60
±70
±80
±90
±90
±100
± 100
20
50
R L = 32 Ÿ,
C B = 1 µF,
Mode = SE
±10
Supp ly Ri pple Reject ion Rat io ± dB
Su ppl y Ri pple Rejecti on Rati o ± dB
±10
100 200
500 1 k 2 k
5 k 10 k 20 k
20
50
100 200
f±Frequency±Hz
Figure 1. Supply Ripple Rejection Ratio
vs Frequency
5 k 10 k 20 k
Figure 2. Supply Ripple Rejection Ratio
vs Frequency
4
3
THD+N = 1%,
f = 1 kHz,
Mode = BTL,
AV = 8 dB
3.5
2.5
TA = 125 °C
3
PO ± Output Power ± W
I DD ± Supply Current ± mA
500 1 k 2 k
f -Frequency -Hz
TA = 25 °C
2.5
2
TA = ±40°C
1.5
SHUTDOWN = VDD,
VDD From Low to High,
Mode = SE,
RL = Open,
Temperature From Hot to Cold
1
0.5
0
2.5
3
3.5
4
4.5
VDD ± Supply Voltage ± V
5
RL = 4 Ÿ
2
RL = 8 Ÿ
1.5
1
0.5
5.5
0
Figure 3. Supply Current vs Supply Voltage
3
3.5
4
4.5
5
VDD ± Supply Voltage ± V
5.5
Figure 4. Output Power vs Supply Voltage
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2.5
500
THD+N = 1%,
f = 1 kHz,
Mode = SE,
AV = 2 dB
2
PO ± Output Power ± W
PO ± Output Power ± mW
400
THD+N = 1%,
f = 1 kHz,
Mode = BTL,
AV = 8 dB
RL = 8 Ÿ
300
200
1.5
VDD = 5 V
1
RL = 32 Ÿ
100
0.5
0
0
VDD = 3 V
3
3.5
4
4.5
VDD ± Supply Voltage ± V
5
5.5
PO ± Output Power ± mW
THD+N ± Total Harmonic Distortion Plus Noise ± %
THD+N = 1%,
f = 1 kHz,
Mode = SE,
AV = 2 dB
500
400
VDD = 5 V
200
100
VDD = 3 V
0
0
10
20
30
40
50
RL ± Load Resistance ±Ÿ
60
VDD = 5 V,
PO = 1 W,
RL = 8 Ÿ,
Mode = BTL
1
0.5
0.2
0.1
0.05
AV = 20 dB
0.02
0.01
0.005
AV = 8 dB
0.002
0.001
20
50 100 200
500 1 k 2 k
50
60
10
5
2
VDD = 3 V,
PO = 250 mW,
RL = 8 Ÿ,
Mode = BTL
1
0.5
0.2
0.1
0.05
AV = 20 dB
0.02
AV = 8 dB
0.01
0.005
0.002
0.001
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
5 k 10 k 20 k
10
5
2
VDD = 3 V,
PO = 25 mW,
RL = 32 Ÿ,
Mode = SE
1
0.5
0.2
0.1
0.05
AV = 14 dB
0.02
0.01
0.005
AV = 2 dB
0.002
0.001
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
f ± Frequency ± Hz
f ± Frequency ± Hz
Figure 9. Total Harmonic Distortion Plus Noise
vs Frequency
8
40
Figure 8. Total Harmonic Distortion Plus Noise
vs Frequency
THD+N ± Total Harmonic Distortion Plus Noise ± %
THD+N ± Total Harmonic Distortion Plus Noise ± %
10
2
30
f ± Frequency ± Hz
Figure 7. Output Power vs Load Resistance
5
20
Figure 6. Output Power vs Load Resistance
700
300
10
RL ± Load Resistance ±Ÿ
Figure 5. Output Power vs Supply Voltage
600
0
Figure 10. Total Harmonic Distortion Plus Noise
vs Frequency
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THD+N ± Total Harmonic Distortion Plus Noise ± %
THD+N ± Total Harmonic Distortion Plus Noise ± %
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VDD = 5 V,
PO = 75 mW,
RL = 32 Ÿ,
Mode = SE
5
2
1
0.5
0.2
0.1
AV = 14 dB
0.05
0.02
0.01
AV = 2 dB
0.005
0.002
0.001
20
50
500 1 k 2 k
100 200
5 k 10 k 20 k
10
20 kHz
2
1
0.5
15 kHz
1 kHz
0.2
0.1
20 Hz
0.05
0.02
0.01
0.005
0.002
0.001
0.01 0.02 0.05
f ± Frequency ± Hz
10
VDD = 3 V,
RL = 8 Ÿ ,
Mode = BTL,
AV = 8 dB
5
2
20 kHz
1
0.5
15 kHz
0.2
1 kHz
0.1
0.05
20 Hz
0.02
0.01
0.005
0.002
0.001
0.01 0.02 0.05
0.5 1
0.1 0.2
PO ± Out put Power ± W
2
5
2
15 kHz
0.5
0.2
0.1
1 kHz
20 Hz
20 kHz
0.05
0.02
0.01
0.005
0.002
0.001
0.01 0.02 0.05
VDD = 5 V,
RL = 4 Ÿ ,
Mode = BTL,
AV = 8 dB
0.5 1
0.1 0.2
PO ± Out put Power ± W
2
5
10
Figure 15. Total Harmonic Distortion Plus Noise
vs Output Power
10
1
0.5
20 kHz
0.2
0.1
0.05
15 kHz
0.02
20 Hz
0.01
1 kHz
0.005
0.002
0.001
10
20
40
PO ± Output Power ± mW
100
70
Figure 14. Total Harmonic Distortion Plus Noise
vs Output Power
THD+N ± Total Harmonic Distortion Plus Noise ± %
THD+N ± Total Harmonic Distortion Plus Noise ± %
2
1
5
VDD = 3 V,
RL = 32 Ÿ,
Mode = SE,
AV = 2 dB
5
Figure 13. Total Harmonic Distortion Plus Noise
vs Output Power
5
2
10
10
10
0.5 1
0.1 0.2
PO ± Output Power ± W
Figure 12. Total Harmonic Distortion Plus Noise
vs Output Power
THD+N ± Total Harmonic Distortion Plus Noise ± %
THD+N ± Total Harmonic Distortion Plus Noise ± %
Figure 11. Total Harmonic Distortion Plus Noise
vs Frequency
VDD = 3 V,
RL = 4 Ÿ ,
Mode = BTL,
AV = 8 dB
5
10
5
2
VDD = 5 V,
RL = 8 Ÿ ,
Mode = BTL,
AV = 8 dB
1
20 kHz
0.5
0.2
15 kHz
1 kHz
0.1
0.05
0.02
20 Hz
0.01
0.005
0.002
0.001
0.01 0.02 0.05
0.5 1
0.1 0.2
PO ± Out put Power ± W
2
5
10
Figure 16. Total Harmonic Distortion Plus Noise
vs Output Power
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1M
10
VDD = 5 V,
RL = 32 Ÿ,
Mode = SE,
AV = 2 dB
5
2
1
Vn ± Output Noise Voltage ± µV RMS
0.5
0.2
20 kHz
0.1
0.05
15 kHz
0.02
20 Hz
0.01
1 kHz
0.005
200
100
50
20
10
5
2
0.002
0.001
0.01
1
0.02
0.2
0.05
0.1
PO ± Out put Power ± W
20
1
0.5
50
100 200
500 1 k 2 k
f ± Frequency ± Hz
5 k 10 k 20 k
Figure 18. Output Noise Voltage vs Frequency
Figure 17. Total Harmonic Distortion Plus Noise
vs Output Power
1M
180°
30
VDD = 5 V,
RL = 32 Ÿ,
Mode = SE,
AV = 2 dB
500
200
20
10
VDD = 5 V,
RL = 4 Ÿ ,
Mode = BTL,
AV = 8 dB
135°
Gain
90°
100
0
50
20
10
5
2
20
50
100 200
500 1 k 2 k
f ± Frequency ± Hz
±10
0°
±20
±45°
±30
±90°
±40
±135°
±50
10
1
5 k 10 k 20 k
100
1k
10k
100k
1M
±180°
f ± Frequency ± Hz
Figure 19. Output Noise Voltage vs Frequency
Figure 20. Closed Loop Response
180°
30
20
10
Gain ± dB
45°
Phase
Phase
Gain ± dB
Vn ± Output Noise Voltage ± µV RMS
VDD = 5 V,
RL = 8 Ÿ ,
Mode = BTL,
AV = 8 dB
500
VDD = 5 V,
RL = 32 Ÿ,
Mode = SE,
AV = 2 dB
135°
Gain
90°
0
45°
Phase
±10
0°
±20
±45°
±30
±90°
±40
±135°
±50
10
100
1k
10k
100k
Phase
THD+N ± Total Harmonic Distortion Plus Noise ± %
SLOS275E – JANUARY 2000 – REVISED NOVEMBER 2016
±180°
1M
f ± Frequency ± Hz
Figure 21. Closed Loop Response
10
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8 Parameter Measurement Information
8.1 Set-Up for Graphs
All parameters are measured according to the conditions described in Specifications. Figure 22 shows the setup
used for the typical characteristics of the test device.
TPA0211
CI
Measurement
Output
RI
IN
Vo+
+
Measurement
Input
Load
VoVDD
_
GND
1uF
+
VDD
_
Copyright © 2016, Texas Instruments Incorporated
(1)
All other measurements were taken with 1-µF CI (unless otherwise noted).
(2)
A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
Figure 22. Test Set-Up for Graphs
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9 Detailed Description
9.1 Overview
The TPA0211 device is a Class AB audio power amplifier designed to drive speakers in applications like small
wireless communicators, cellphones, notebooks, and so forth. The TPA0211 can deliver 2 W (1% THD+N) of
power into a 4-Ω speaker.
This device is available in the 8-pin thermally-enhanced MSOP-PowerPAD package (DGN) and operates over an
ambient temperature range of –40°C to 85°C.
9.2 Functional Block Diagram
CB
4
BYPASS
V DD
3
V DD
GND
7
BYPASS
V DD
50 NŸ
1.25*R
Audio
Input
Ci
RI
1
IN
±
100 NŸ
R
±
+
CC
V O+
5
+
BYPASS
100 k Ÿ
BYPASS
1 NŸ
50 NŸ
SE/BTL
Control
SE/BTL
6
50 NŸ
1.25*R
±
R
±
+
V O±
8
+
BYPASS
BYPASS
From
System Control
12
2
SHUTDOWN
Shutdown
and Depop Circuitry
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9.3 Feature Description
9.3.1 Bridged-Tied Load Versus Single-Ended Mode
Figure 23 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA0211 BTL amplifier
consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this
differential drive configuration, but initially consider power to the load. The differential drive to the speaker means
that as one side is slewing up, the other side is slewing down, and vice versa. This, in effect, doubles the voltage
swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4 times the output power from the same supply rail and load impedance (see
Equation 1 and ).
V(RMS)
Power
VO(PP)
2 2
V(RMS)2
RL
(1)
V DD
V O(PP)
RL
2x V O(PP)
V DD
±V O(PP)
Figure 23. Bridge-Tied Load Configuration
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power, that is a 6-dB improvement —
which is loudness that can be heard. In addition to increased power, there are frequency response concerns.
Consider the single-supply SE configuration shown in Figure 24. A coupling capacitor is required to block the dc
offset voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF) so
they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting lowfrequency performance of the system. This frequency limiting effect is due to the high pass filter network created
with the speaker impedance and the coupling capacitance and is calculated with Equation 2.
fc
1
2SRLC(C)
)
(2)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
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Feature Description (continued)
VDD
±3dB
VO(PP)
C(C)
VO(PP)
RL
fc
Figure 24. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4 times the output power of the SE
configuration. Internal dissipation versus output power is discussed further in Crest Factor.
9.3.2 Single-Ended Operation
In SE mode (see Figure 23 and Figure 24), the load is driven from one amplifier output (VO+, terminal 5).
The amplifier switches to single-ended operation when the SE/BTL terminal is held high.
9.3.3 BTL Amplifier Efficiency
Class-AB amplifiers are inefficient. The primary cause of inefficiencies is the voltage drop across the output stage
transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage drop that
varies inversely to output power. The second component is due to the sinewave nature of the output. The total
voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage
drop multiplied by the RMS value of the supply current, IDDrms, determines the internal power dissipation of the
amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 25).
I DD
VO
IDD(avg)
V(LMRMS)
Figure 25. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
Equation 3 and Equation 4 are the basis for calculating amplifier efficiency.
14
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Feature Description (continued)
Efficiency of a BTL amplifier
PL
PSUP
where
VLRMS2
, and VLRMS
RL
PL
and PSUP
VDDIDDavg
VP
2
VP2
2RL
, therefore, PL
and IDDavg
1
S
³
S
0
VP
sin(t) dt
RL
2VP
1 VP
[cos(t)] S0
u
S RL
SRL
therefore,
2VDD VP
SRL
PSUP
substituting PL and PSUP int o equation 9,
Efficiency of a BTL amplifier
VP2
2 RL
2VDD VP
SRL
SVP
4VDD
where
VP
2PLRL
(3)
therefore,
KBTL
PL
S 2PLRL
4VDD
Power delivered to load
VP
Peak voltage on BTL load
PSUP Power drawn from power supply
IDDavg Average current drawn from the power supply
VLRMS RMS voltage on BTL load
VDD
Power supply voltage
RL
KBTL
Efficiency of a BTL amplifier
Load resist ance
(4)
Table 2 employs Equation 3 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design.
Table 2. Efficiency vs Output Power in 5-V 8-Ω BTL Systems
(1)
OUTPUT POWER
(W)
EFFICIENCY (%)
PEAK VOLTAGE (V)
INTERNAL
DISSIPATION (W)
0.25
31.4
2
0.55
0.5
44.4
2.83
0.62
1
62.8
4
0.59
1.25
70.2
4.47 (1)
0.53
High peak voltages cause the THD to increase.
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A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. Note that in Equation 3, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
9.3.4 Gain Setting Via Input Resistance
The gain of the input stage is set by the user-selected input resistor and a 50-kΩ internal feedback resistor.
However, the power stage is internally configured with a gain of –1.25 V/V in SE mode, and –2.5 V/V in BTL
mode. Thus, the feedback resistor (RF) is effectively 62.5 kΩ in SE mode and 125 kΩ in BTL mode. Therefore,
the overall gain can be calculated using Equation 5 and Equation 6.
125k:
RI
AV
(BTL)
(5)
62.5k:
(SE)
RI
AV
(SE)
(6)
The –3 dB frequency can be calculated using Equation 7.
f
1
2SRICi
3db
(7)
If the filter must be more accurate, the value of the capacitor should be increased while the value of the resistor
to ground should be decreased. In addition, the order of the filter could be increased.
9.3.5 Crest Factor
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power
output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest
factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. The TPA0211 data sheet shows that when the
TPA0211 is operating from a 5-V supply into a 4-Ω speaker 4-W peaks are available. Converting watts to dB with
Equation 8.
Pdb
10Log
PW
Pr ef
10Log
4W
1W
6 dB
Subtracting the headroom restriction to obtain the average listening level without distortion yields :
6 dB 15 db
9 dB(15 dB crest factor)
6 dB 12 db
6 dB(12 dB crest factor)
6 dB 9 db
3 dB (9 dB crest factor)
6 dB 6 db 0 dB (6 dB crest factor)
6 dB 3 db 3 dB (3 dB crest factor)
(8)
Converting dB back into watts with Equation 9.
PW
10PdB/10 u Pr ef
63 mW (18 dB crest factor)
125 mW (15 dB crest factor)
250 mW (9 dB crest factor)
500 mW (6 dB crest factor)
1000 mW (3 dB crest factor)
2000 mW (15 dB crest factor)
16
(9)
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This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the absolute worst case, which is 2 W of continuous power output with a 3 dB crest
factor, against 12 dB and 15 dB applications drastically affects maximum ambient temperature ratings for the
system. Table 3 shows maximum ambient temperatures and TPA0211 internal power dissipation for various
output-power levels.
Table 3. TPA0211 Power Rating, 5-V, 4–Ω, Mono
AVERAGE OUTPUT POWER
POWER DISSIPATION (W)
MAXIMUM AMBIENT
TEMPERATURE
4
2 W (3-dB crest factor)
1.7
–3°C
4
1000 mW (6-dB crest factor)
1.6
6°C
4
500 mW (9-dB crest factor)
1.4
24°C
4
250 mW (12-dB crest factor)
1.1
51°C
4
125 mW (15-dB crest factor)
0.8
78°C
4
63 mW (18-dB crest factor)
0.6
96°C
PEAK OUTPUT POWER (W)
As a result, Equation 10 for calculating PDmax may be used for an 4-Ω application.
PDmax
2V 2DD
S2RL
(10)
However, in the case of a 4-Ω load, the PDmax occurs at a point well above the normal operating power level. The
amplifier may therefore be operated at a higher ambient temperature than required by the PDmax formula for a 4Ω load.
9.4 Device Functional Modes
9.4.1 Shutdown Mode
The TPA0211 amplifier can be put in shutdown mode when asserting shutdown pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and the current consumption is very low.
9.4.2 SE/BTL (Stereo/Mono) Operation
The ability of the TPA0211 to easily switch between mono BTL and stereo SE modes is one of its most important
cost saving features. This feature eliminates the requirement for an additional headphone amplifier in
applications where an internal speaker is driven in BTL mode but an external headphone must be
accommodated. When SE/BTL is held high for SE mode, the VO– output goes into a high impedance state while
the VO+ output operates normally. When SE/BTL is held low, the VO– output operates normally, placing the
amplifier in BTL mode.
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Device Functional Modes (continued)
VDD
100 KŸ
CC
Vo+
TPA0211
1 KŸ
100 KŸ
SE/BTL
Vo-
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Figure 26. TPA0211 Resistor Divider Network Circuit
Using a readily available 1/8-in (3.5 mm) mono headphone jack, the control switch is closed when no plug is
inserted. When closed, the 100-kΩ, 1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ
resistor is disconnected and the SE/BTL input is pulled high.
18
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device. Each of these configurations can be realized using the Evaluation Modules
(EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of
operation. Any design variation can be supported by TI through schematic and layout reviews. Visit e2e.ti.com for
design assistance and join the audio amplifier discussion forum for additional information.
10.2 Typical Application
To power supply
0.1 uF
CI
Audio
Input
10 uF
IN
100 KŸ
CC
VDD
RI
Vo+
TPA0211
1K Ÿ
Bypass
100 KŸ
CB
SE/BTL
Shutdown Control
Shutdown
Vo±
GND
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Figure 27. TPA0211 With SE/BTL Operation
10.2.1 Design Requirements
For this example, Table 4 lists the design parameters.
Table 4. Design Parameters
PARAMETER
VALUE
Power supply
5V
Enable inputs
High > 2 V
Low < 0.8 V
Speaker
8Ω
10.2.2 Detailed Design Procedure
10.2.2.1 Surface Mount Capacitor
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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Temperature and applied DC voltage influence the actual capacitance of high-K materials. Table 5 shows the
relationship between the different types of high-K materials and their associated tolerances, temperature
coefficients, and temperature ranges. Notice that a capacitor made with X5R material can lose up to 15% of its
capacitance within its working temperature range.
In an application, the working capacitance of components made with high-K materials is generally much lower
than nominal capacitance. A worst case result with a typical X5R material might be –10% tolerance, –15%
temperature effect, and –45% DC voltage effect at 50% of the rated voltage. This particular case would result in
a working capacitance of 42% (0.9 × 0.85 × 0.55) of the nominal value.
Select high-K ceramic capacitors according to the following rules:
1. Use capacitors made of materials with temperature coefficients of X5R, X7R, or better.
2. Use capacitors with DC voltage ratings of at least twice the application voltage. Use minimum 10-V
capacitors for this device.
3. Choose a capacitance value at least twice the nominal value calculated for the application. Multiply the
nominal value by a factor of 2 for safety. If a 10-µF capacitor is required, use 20 µF.
The preceding rules and recommendations apply to capacitors used in connection with the device. This device
cannot meet its performance specifications if the rules and recommendations are not followed.
Table 5. Typical Tolerance and Temperature Coefficient of Capacitance by Material
MATERIAL
TYPICAL TOLERANCE
TEMPERATURE
TEMPERATURE RANGE (°C)
COG/NOP
±5%
±30 ppm
–55 to 125
X7R
±10%
±15%
–55 to 125
X5R
80% to –20%
22% to –82%
–30 to 85
10.2.2.2 Input Capacitor, Ci
In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input resistance of the amplifier, RI, form a highpass filter with the corner frequency determined in Equation 11.
±3 dB
fc(highpass)
1
2SRICi
fc
(11)
The value of Ci is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 40 Hz.
Equation 6 is reconfigured as Equation 12.
Ci
1
2SRIfc
(12)
In this example, CI is 0.4 µF so one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic
capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face
the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher than the
source dc level. Note that it is important to confirm the capacitor polarity in the application.
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10.2.2.3 Power Supply Decoupling, C(S)
The TPA0211 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by
using two capacitors of different types that target different types of noise on the power supply leads. For higher
frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1 µF placed as close as possible to the device VDD lead, works best. For filtering lowerfrequency noise signals, TI recommends a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier.
10.2.2.4 Midrail Bypass Capacitor, C(BYP)
The midrail bypass capacitor, C(BYP), is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, C(BYP) determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor, C(BYP), values of 0.47 µF to 1 µF ceramic or tantalum low-ESR capacitors are recommended
for the best THD and noise performance.
10.2.2.5 Output Coupling Capacitor, C(C)
In the typical single-supply SE configuration, an output coupling capacitor (C(C)) is required to block the dc bias at
the output of the amplifier thus preventing dc currents in the load. As with the input coupling capacitor, the output
coupling capacitor and impedance of the load form a high-pass filter governed by Equation 13.
±3 dB
fc(high)
1
2SRLC(c)
fc
(13)
The main disadvantage, from a performance standpoint, is that the load impedances are typically small, which
drives the low-frequency corner higher, degrading the bass response. Large values of C(C) are required to pass
low frequencies into the load. Consider the example where a C(C) of 330 µF is chosen and loads vary from 3 Ω, 4
Ω, 8 Ω, 32 Ω, 10 kΩ, to 47 kΩ. Table 6 summarizes the frequency response characteristics of each configuration.
Table 6. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
RL
C(C)
LOWEST FREQUENCY
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
32 Ω
330 µF
15 Hz
10,000 Ω
330 µF
0.05 Hz
47,000 Ω
330 µF
0.01 Hz
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As Table 6 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate,
headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
Furthermore, the total amount of ripple current that must flow through the capacitor must be considered when
choosing the component. As shown in the application circuit, one coupling capacitor must be in series with the
mono loudspeaker for proper operation of the stereo-mono switching circuit. For a 4-Ω load, this capacitor must
be able to handle about 700 mA of ripple current for a continuous output power of 2 W.
10.2.3 Application Curves
Table 7 lists the figures for the application curves.
Table 7. Table of Graphs
(1)
22
DESCRIPTION
FIGURE (1)
Supply current vs Supply voltage
Figure 3
Output power vs Load resistance
Figure 6
THD+N vs Frequency
Figure 8
THD+N vs Output power
Figure 12
All figures are located in Typical Characteristics.
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11 Power Supply Recommendations
The TPA0211 is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Therefore, the
output voltage range of the power supply must be within this range. The current capability of upper power must
not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA0211 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1-µF ceramic capacitor, is recommended to place a 2.2-µF
to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any droop in the supply voltage.
12 Layout
12.1 Layout Guidelines
12.1.1 Component Placement
Keeping the external components very close to the TPA0211 to limit noise pickup is very important to limit noise
pickup. Placing the decoupling capacitors as close as possible to the device is important for the performance of
the class-AB amplifier.
12.2 Layout Example
Input Resistor placed
as close as possible
to the device
Ci
Ri
IN
SHUTDOWN
0.1µF
10µF
Vo -
1
8
2
7
3
6
SE/ BTL
4
5
Vo+
1µF
TPA0211
Decoupling capacitor
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
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Figure 28. Layout Recommendation
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12.3 Thermal Considerations
The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor
for the DGN package is shown in the Dissipation Ratings. Converting this θJA can be done with Equation 14.
(14)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per
channel so the dissipated power needs to be doubled for two channel operation. Given RθJA, the maximum
allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be
calculated with Equation 15. The maximum recommended junction temperature for the TPA0211 is 150°C.
(15)
NOTE
Internal dissipation of 0.8 W is estimated for a 2-W system with 15-dB crest factor per
channel.
Table 3 shows that for some applications no airflow is required to keep junction temperatures in the specified
range. The TPA0211 is designed with thermal protection that turns the device off when the junction temperature
surpasses 150°C to prevent damage to the IC. Table 3 was calculated for maximum listening volume without
distortion. When the output level is reduced the numbers in the table change significantly. Also, using 8-Ω
speakers dramatically increases the thermal performance by increasing amplifier efficiency.
24
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package (SLMA002)
• Guidelines for Measuring Audio Power Amplifier Performance (SLOA068)
• TPA0211EVM - User Guide (SLOU092)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: TPA0211
25
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA0211DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AEG
TPA0211DGNG4
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AEG
TPA0211DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AEG
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA0211DGNR
HVSSOP
DGN
8
2500
330.0
12.4
TPA0211DGNR
HVSSOP
DGN
8
2500
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.3
3.4
1.4
8.0
12.0
Q1
5.3
3.4
1.4
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA0211DGNR
HVSSOP
DGN
8
2500
364.0
364.0
27.0
TPA0211DGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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