Texas Instruments | TPA2026D2 3.2-W/Ch Stereo Class-D Audio Amplifier With Fast Gain Ramp SmartGain Automatic Gain Control and Dynamic Range Compression (Rev. B) | Datasheet | Texas Instruments TPA2026D2 3.2-W/Ch Stereo Class-D Audio Amplifier With Fast Gain Ramp SmartGain Automatic Gain Control and Dynamic Range Compression (Rev. B) Datasheet

Texas Instruments TPA2026D2 3.2-W/Ch Stereo Class-D Audio Amplifier With Fast Gain Ramp SmartGain Automatic Gain Control and Dynamic Range Compression (Rev. B) Datasheet
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TPA2026D2
SLOS649B – MARCH 2010 – REVISED MAY 2016
TPA2026D2 3.2-W/Ch Stereo Class-D Audio Amplifier With Fast Gain Ramp SmartGain™
Automatic Gain Control and Dynamic Range Compression
1 Features
3 Description
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The TPA2026D2 device is a stereo, filter-free Class-D
audio power amplifier with volume control, dynamic
range compression (DRC), and automatic gain
control (AGC). It is available in a 2.2 mm × 2.2 mm
DSBGA package.
1
Fast AGC Start-Up Time: 5 ms
Pinout Compatible With TPA2016D2
Filter-Free Class-D Architecture
3.2 W/Ch Into 4 Ω at 5 V (10% THD+N)
750 mW/Ch Into 8 Ω at 3.6 V (10% THD+N)
Power Supply Range: 2.5 V to 5.5 V
Flexible Operation With or Without I2C
Programmable DRC and AGC Parameters
Digital I2C Volume Control
Selectable Gain from 0 dB to 30 dB in 1-dB Steps
Selectable Attack, Release, and Hold Times
4 Selectable Compression Ratios
Low Supply Current: 3.5 mA
Low Shutdown Current: 0.2 μA
High PSRR: 80 dB
AGC Enable or Disable Function
Limiter Enable or Disable Function
Short-Circuit and Thermal Protection
Space-Saving Package
– 2.2 mm × 2.2 mm Nano-Free™ DSBGA (YZH)
2 Applications
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Wireless or Cellular Handsets and PDAs
Portable Navigation Devices
Portable DVD Players
Notebook PCs
Portable Radios
Portable Games
Educational Toys
USB Speakers
The DRC and AGC function in the TPA2026D2 is
programmable through a digital I2C interface. The
DRC and AGC function can be configured to
automatically prevent distortion of the audio signal
and enhance quiet passages that are normally not
heard. The DRC and AGC can also be configured to
protect the speaker from damage at high power
levels and compress the dynamic range of music to fit
within the dynamic range of the speaker. The gain
can be selected from 0 dB to +30 dB in 1-dB steps.
The TPA2026D2 is capable of driving 3.2 W/Ch at 5
V into an 4-Ω load or 750 mW/Ch at 3.6 V into an 8-Ω
load. The device features independent software
shutdown controls for each channel and also provides
thermal and short-circuit protection. The TPA2026D2
has faster AGC gain ramp during start-up than
TPA2016D2.
In addition to these features, a fast start-up time and
small package size make the TPA2026D2 an ideal
choice for cellular handsets, PDAs, and other
portable applications.
Device Information(1)
PART NUMBER
PACKAGE
TPA2026D2
DSBGA (16)
BODY SIZE (NOM)
2.20 mm × 2.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
To Battery
10 mF
AVDD
PVDDL PVDDR
TPA2026D2
CIN 1 mF
INL–
Analog
Baseband
or
Codec
OUTL+
INL+
INR–
INR+
OUTL–
OUTR+
2
I C Clock
Digital
Baseband
2
I C Data
Master Shutdown
OUTR–
SCL
SDA
SDZ
AGND
PGND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2026D2
SLOS649B – MARCH 2010 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
4
5
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Timing Requirements..........................................
Dissipation Ratings ...................................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 22
9.5 Programming .......................................................... 23
9.6 Register Maps ......................................................... 25
10 Application and Implementation........................ 30
10.1 Application Information.......................................... 30
10.2 Typical Applications .............................................. 30
11 Power Supply Recommendations ..................... 33
11.1 Power Supply Decoupling Capacitors .................. 33
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
12.2 Layout Example .................................................... 35
12.3 Efficiency and Thermal Considerations ................ 35
13 Device and Documentation Support ................. 36
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
14 Mechanical, Packaging, and Orderable
Information ........................................................... 36
14.1 YZH Package Dimensions .................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2011) to Revision B
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Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Original (March 2010) to Revision A
Page
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Changed the Default values in Table 5 ............................................................................................................................... 26
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Changed the Default value of the IC Function Control Table (I2C BIT 0) From: 0 (disabled) To: 1 (enabled) ................... 26
2
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SLOS649B – MARCH 2010 – REVISED MAY 2016
5 Device Comparison Table
DEVICE
NUMBER
SPEAKER AMP TYPE
SPECIAL FEATURE
OUTPUT POWER (W)
PSRR (dB)
TPA2012D2
Class D
—
2.1
71
TPA2016D2
Class D
AGC/DRC
2.8
80
TPA2026D2
Class D
AGC/DRC
3.2
80
6 Pin Configuration and Functions
YZH Package
16-Pin DSBGA
Top View
1
2
3
4
A
INR–
INR+
INL+
INL–
B
AVDD
SCL
SDA
AGND
C
PVDDR
SDZ
D
OUTR+ OUTR– OUTL– OUTL+
PGND PVDDL
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
A1
INR–
I
Right channel negative audio input
A2
INR+
I
Right channel positive audio input
A3
INL+
I
Left channel positive audio input
A4
INL–
I
Left channel negative audio input
B1
AVDD
P
Analog supply (must be the same as PVDDR and PVDDL)
B2
SCL
I
I2C clock interface
B3
SDA
I/O
I2C data interface
B4
AGND
P
Analog ground (all GND pins need to be connected)
C1
PVDDR
P
Right channel power supply (must be the same as AVDD and PVDDL)
C2
SDZ
I
Shutdown terminal (active low)
C3
PGND
P
Power ground (all GND pins need to be connected)
C4
PVDDL
P
Left channel power supply (must be the same as AVDD and PVDDR)
D1
OUTR+
O
Right channel positive differential output
D2
OUTR–
O
Right channel negative differential output
D3
OUTL–
O
Left channel negative differential output
D4
OUTL+
O
Left channel positive differential output
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted).
VDD
Supply voltage
Input voltage
MIN
MAX
UNIT
AVDD, PVDDR, PVDDL
–0.3
6
V
SDZ, INR+, INR–, INL+, INL–
–0.3
VDD + 0.3
SDA, SCL
–0.3
6
Continuous total power dissipation
V
See Dissipation Ratings
RL
Minimum load resistance
3.2
Ω
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
5.5
VDD
Supply voltage
AVDD, PVDDR, PVDDL
2.5
VIH
High-level input voltage
SDZ, SDA, SCL
1.3
VIL
Low-level input voltage
SDZ, SDA, SCL
TA
Operating free-air temperature
–40
UNIT
V
V
0.6
V
+85
°C
7.4 Thermal Information
TPA2026D2
THERMAL METRIC
(1)
YZH (DSBGA)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
71
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
0.4
°C/W
Junction-to-board thermal resistance
14.4
°C/W
ψJT
Junction-to-top characterization parameter
1.9
°C/W
ψJB
Junction-to-board characterization parameter
13.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLOS649B – MARCH 2010 – REVISED MAY 2016
7.5 Electrical Characteristics
at TA = 25°C, VDD = 3.6 V, SDZ = 1.3 V, and RL = 8 Ω + 33 μH (unless otherwise noted).
PARAMETER
VDD
TEST CONDITIONS
MIN
TYP
MAX
2.5
Supply voltage range
ISDZ
Shutdown quiescent current
ISWS
IDD
Software shutdown quiescent
current
Supply current
3.6
5.5
SDZ = 0.35 V, VDD = 2.5 V
0.1
1
SDZ = 0.35 V, VDD = 3.6 V
0.2
1
SDZ = 0.35 V, VDD = 5.5 V
0.3
1
SDZ = 1.3 V, VDD = 2.5 V
35
50
SDZ = 1.3 V, VDD = 3.6 V
50
70
SDZ = 1.3 V, VDD = 5.5 V
75
110
VDD = 2.5 V
3.5
4.5
VDD = 3.6 V
3.7
4.7
VDD = 5.5 V
4.5
5.5
300
325
kHz
1
µA
fSW
Class-D switching frequency
IIH
High-level input current
VDD = 5.5 V, SDZ = 5.8 V
IIL
Low-level input current
VDD = 5.5 V, SDZ = –0.3 V
tSTART
Start-up time
2.5 V ≤ VDD ≤ 5.5 V no pop, CIN ≤ 1 μF
POR
Power on reset ON threshold
POR
Power on reset hysteresis
275
V
µA
µA
mA
–1
µA
5
2
CMRR
Input common-mode rejection
RL = 8 Ω, Vicm = 0.5 V and Vicm = VDD – 0.8 V,
differential inputs shorted
Voo
Output offset voltage
VDD = 3.6 V, AV = 6 dB, RL = 8 Ω, inputs AC
grounded
ZOUT
Output impedance in shutdown
mode
SDZ = 0.35 V
Gain accuracy
Compression and limiter disabled, Gain = 0 to 30 dB
Power supply rejection ratio
VDD = 2.5 V to 4.7 V
PSRR
UNIT
ms
2.3
V
0.2
V
–70
dB
2
10
mV
2
–0.5
kΩ
0.5
dB
–80
dB
7.6 I2C Timing Requirements
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
MIN
fSCL
Frequency, SCL
No wait states
tW(H)
Pulse duration, SCL high
tW(L)
tSU(1)
TYP
MAX
UNIT
400
kHz
0.6
μs
Pulse duration, SCL low
1.3
μs
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
10
ns
t(buf)
Bus free time between stop and start condition
1.3
μs
tSU2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tSU3
Setup time, SCL to stop condition
0.6
μs
7.7 Dissipation Ratings
PACKAGE
16-ball WCSP
(1)
(1)
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
1.25 W
10 mW/°C
0.8 W
0.65 W
Dissipations ratings are for a 2-side, 2-plane PCB.
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7.8 Operating Characteristics
at TA = 25°C, VDD = 3.6V, SDZ = 1.3 V, RL = 8 Ω +33 μH, and AV = 6 dB (unless otherwise noted).
MIN
kSVR
Power-supply ripple rejection ratio
VDD = 3.6 Vdc with AC of 200 mVPP at 217 Hz
TYP
MAX
–68
faud_in = 1 kHz, PO = 550 mW, VDD = 3.6 V
0.1%
faud_in = 1 kHz, PO = 1 W, VDD = 5 V
0.1%
UNIT
dB
THD+N
Total harmonic distortion + noise
NfonF
Output integrated noise
Av = 6 dB
44
μV
NfoA
Output integrated noise
Av = 6 dB floor, A-weighted
33
μV
FR
Frequency response
Av = 6 dB
Pomax
η
Maximum output power
Efficiency
faud_in = 1 kHz, PO = 630 mW, VDD = 3.6 V
1%
faud_in = 1 kHz, PO = 1.4 W, VDD = 5 V
1%
20
20000
Hz
THD+N = 10%, VDD = 5 V, RL = 8 Ω
1.72
W
THD+N = 10%, VDD = 3.6 V, RL = 8 Ω
750
mW
THD+N = 1%, VDD = 5 V, RL = 8 Ω
1.4
W
THD+N = 1% , VDD = 3.6 V, RL = 8 Ω
630
mW
THD+N = 1%, VDD = 3.6 V, RL = 8 Ω, PO= 0.63 W
90%
THD+N = 1%, VDD = 5 V, RL = 8 Ω, PO = 1.4 W
90%
tw(L)
tw(H)
SCL
t su1
th1
SDA
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
Start Condition
Stop Condition
SDA
Figure 2. Start and Stop Conditions Timing
6
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SLOS649B – MARCH 2010 – REVISED MAY 2016
7.9 Typical Characteristics
with C(DECOUPLE) = 1 μF, CI = 1 µF. All THD + N graphs are taken with outputs out of phase (unless otherwise noted). All data
is taken on left channel.
Table 1. Table of Graphs
FIGURE
Quiescent supply current
vs Supply voltage
Figure 3
Supply current
vs Supply voltage in shutdown
Figure 4
Output level
vs Input level
Figure 5
Output level
vs Input level
Figure 6
Output level
vs Input level
Figure 7
Output level
vs Input level
Figure 8
Output level
vs Input level
Figure 9
Supply ripple rejection ratio
vs Frequency, 8 Ω
Figure 10
Total harmonic distortion + noise
vs Frequency VSUPPLY = 2.5 V, 4 Ω
Figure 11
Total harmonic distortion + noise
vs Frequency VSUPPLY = 2.5 V, 8 Ω
Figure 12
Total harmonic distortion + noise
vs Frequency VSUPPLY = 3.6 V, 4 Ω
Figure 13
Total harmonic distortion + noise
vs Frequency VSUPPLY = 3.6 V, 8 Ω
Figure 14
Total harmonic distortion + noise
vs Frequency VSUPPLY = 5 V, 4 Ω
Figure 15
Total harmonic distortion + noise
vs Frequency VSUPPLY = 5 V, 8 Ω
Figure 16
Total harmonic distortion + noise
vs Output power, 4 Ω
Figure 17
Total harmonic distortion + noise
vs Output power, 8 Ω
Figure 18
Efficiency
vs Output power (per channel), 4 Ω
Figure 19
Efficiency
vs Output power (per channel), 8 Ω
Figure 20
Total power dissipation
vs Total output power, 4 Ω
Figure 21
Total power dissipation
vs Total output power, 8 Ω
Figure 22
Total supply current
vs Total output power, 4 Ω
Figure 23
Total supply current
vs Total output power, 8 Ω
Figure 24
Output power
vs Supply voltage, 4 Ω
Figure 25
Output power
vs Supply voltage, 8 Ω
Figure 26
TPA2026D2
vs TPA2016D2 Start-up gain ramp
Figure 27
TPA2026D2
vs TPA2016D2 Shutdown gain ramp
Figure 28
Figure 29
Start-up time
Figure 30
10
100
8
80
IDD − Supply Current − µA
IDD − Quiescent Supply Current − mA
Shutdown time
6
4
2
0
2.5
3.5
4.5
VDD − Supply Voltage − V
5.5
60
40
SDZ = 0 V
20
0
2.5
3.5
4.5
5.5
VDD − Supply Voltage − V
G001
Figure 3. Quiescent Supply Current vs Supply Voltage
SDZ = VDD, SWS = 1
G002
Figure 4. Supply Current Vs Supply Voltage in Shutdown
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20
20
10
10
Output Level − dBV
Output Level − dBV
SLOS649B – MARCH 2010 – REVISED MAY 2016
0
−10
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
−20
−30
−40
−50
−40
RL = 8 Ω + 33 µH
VSupply = 5 V
Fixed Gain = Max Gain = 30 dB
Compression Ratio = 1:1
−30
−20
−10
Level
Level
Level
Level
Level
Level
Level
Level
Level
= −6.5
= −4.5
= −2.5
= −0.5
= 1.5
= 3.5
= 5.5
= 7.5
=9
0
−30
Fixed Gain = −27
Fixed Gain = −24
Fixed Gain = −21
Fixed Gain = −18
−50
−70
−50
−30
Fixed Gain = −15
Fixed Gain = −12
Fixed Gain = −9
Fixed Gain = −6
Fixed Gain = −3
Fixed Gain = 0
Fixed Gain = 3
Fixed Gain = 6
−10
0
G004
−20
−30
Fixed Gain = −27
Fixed Gain = −24
Fixed Gain = −21
Fixed Gain = −18
Fixed Gain = −15
−50
−30
Fixed Gain = −12
Fixed Gain = −9
Fixed Gain = −6
Fixed Gain = −3
Fixed Gain = 0
Fixed Gain = 3
−10
10
Input Level − dBV
G006
Figure 8. Output Level vs Input level With 8:1 Compression
0
Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
VSupply = 5 V
Fixed Gain = 0 dB
Max Gain = 30 dB
−20
−30
Compression
Compression
Compression
Compression
−40
−50
−30
Ratio = 1:1
Ratio = 2:1
Ratio = 4:1
Ratio = 8:1
−10
10
−20
−40
−60
−80
−100
G007
Figure 9. Output Level vs Input level
VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
Gain = 6 dB
RL = 8 Ω + 33 µH
Left Channel
20
Input Level − dBV
8
10
−10
G005
−10
−50
−70
0
−50
−70
KSVR − Supply Ripple Rejection Ratio − dB
Output Level − dBV
10
−10
Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
VSupply = 5 V
Compression Ratio = 8:1
Max Gain = 30 dB
−40
10
Input Level − dBV
−30
Input Level − dBV
Figure 7. Output Level vs Input level With 4:1 Compression
20
−50
Figure 6. Output Level vs Input level With 2:1 Compression
10
−10
−40
−30
20
Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
VSupply = 5 V
Compression Ratio = 4:1
Max Gain = 30 dB
−20
Fixed Gain = −12
Fixed Gain = −9
Fixed Gain = −6
Fixed Gain = −3
Fixed Gain = 0
Fixed Gain = 3
Fixed Gain = 6
Fixed Gain = 9
Fixed Gain = 12
−20
G003
Output Level − dBV
Output Level − dBV
0
−10
−50
−70
10
Input Level − dBV
10
0
−40
Figure 5. Output Level vs Input level With Limiter Enabled
20
Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
VSupply = 5 V
Fixed Gain (2:1)
Compression Ratio = 2:1
Max Gain = 30 dB
100
1k
f − Frequency − Hz
10k
20k
Figure 10. Supply Ripple Rejection Ratio vs Frequency, 8 Ω
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10
PO = 25 mW
PO = 125 mW
PO = 300 mW
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
THD+N − Total Harmonic Distortion + Noise − %
Figure 11. Total Harmonic Distortion + Noise vs Frequency
VSUPPLY = 2.5 V, 4 Ω
10
PO = 50 mW
PO = 250 mW
PO = 700 mW
Gain = 6 dB
RL = 4 Ω + 33 µH
VSupply = 3.6 V
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
THD+N − Total Harmonic Distortion + Noise − %
10
PO = 100 mW
PO = 500 mW
PO = 1.75 W
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
20k
Figure 15. Total Harmonic Distortion + Noise vs Frequency
VSUPPLY = 5 V, 4 Ω
PO = 25 mW
PO = 125 mW
PO = 200 mW
Gain = 6 dB
RL = 8 Ω + 33 µH
VSupply = 2.5 V
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
20k
Figure 12. Total Harmonic Distortion + Noise vs Frequency
VSUPPLY = 2.5 V, 8 Ω
10
PO = 50 mW
PO = 250 mW
PO = 500 mW
Gain = 6 dB
RL = 8 Ω + 33 µH
VSupply = 3.6 V
1
0.1
0.01
0.001
20k
Figure 13. Total Harmonic Distortion + Noise vs Frequency
VSUPPLY = 3.6 V, 4 Ω
Gain = 6 dB
RL = 4 Ω + 33 µH
VSupply = 5.0 V
10
20k
THD+N − Total Harmonic Distortion + Noise − %
Gain = 6 dB
RL = 4 Ω + 33 µH
VSupply = 2.5 V
THD+N − Total Harmonic Distortion + Noise − %
SLOS649B – MARCH 2010 – REVISED MAY 2016
20
100
1k
f − Frequency − Hz
10k
20k
Figure 14. Total Harmonic Distortion + Noise Vs Frequency
VSUPPLY = 3.6 V, 8 Ω
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
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10
PO = 100 mW
PO = 500 mW
PO = 1 W
Gain = 6 dB
RL = 8 Ω + 33 µH
VSupply = 5.0 V
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
20k
Figure 16. Total Harmonic Distortion + Noise vs Frequency
VSUPPLY = 5 V, 8 Ω
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100
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
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VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
Gain = 6 dB
RL = 4 Ω + 33 µH
f = 1 kHz
10
1
0.1
0.01
10m
100m
1
4
100
10
1
0.1
0.01
10m
PO − Output Power (Per Channel) − W
80
80
Efficiency − %
Efficiency − %
100
60
Gain = 6 dB
RL = 4 Ω + 33 µH
f = 1 kHz
0.5
1.0
1.5
2.0
2.5
3.0
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
0.5
1.0
1.5
2.0
PO − Output Power (Per Channel) − W
PO − Output Power (Per Channel) − W
Figure 19. Efficiency vs Output Power (Per Channel), 4 Ω
Figure 20. Efficiency vs Output Power (Per Channel), 8 Ω
0.4
0.8
PD − Total Power Dissipation − W
Gain = 6 dB
RL = 4 Ω + 33 µH
f = 1 kHz
0.9
PD − Total Power Dissipation − W
40
0
0.0
3.5
1.0
0.7
0.6
0.5
0.4
0.3
0.2
VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
0.1
0.0
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
0.3
0.2
0.1
VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
0.0
0
1
2
3
4
5
6
7
0
PO − Total Output Power − W
1
2
3
4
PO − Total Output Power − W
Figure 21. Total Power Dissipation vs Total Output Power,
4Ω
10
3
60
20
VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
0
0.0
1
Figure 18. Total Harmonic Distortion + Noise vs Power,
8Ω
100
20
100m
PO − Output Power (Per Channel) − W
Figure 17. Total Harmonic Distortion + Noise vs Power,
4Ω
40
VSupply = 2.5 V
VSupply = 3.6 V
VSupply = 5.0 V
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
Figure 22. Total Power Dissipation vs Total Output Power,
8Ω
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1.6
1.0
IDD − Total Supply Current − A
1.4
IDD − Total Supply Current − A
Gain = 6 dB
RL = 4 Ω + 33 µH
f = 1 kHz
1.2
1.0
0.8
0.6
0.4
VSupply = 2.5 V
VSupply = 3.6V
VSupply = 5.0 V
0.2
0.0
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
0.8
0.6
0.4
0.2
VSupply = 2.5 V
VSupply = 3.6V
VSupply = 5.0 V
0.0
0
1
2
3
4
5
6
7
0
1
2
PO − Total Output Power − W
Figure 23. Total Supply Current vs Total Output Power, 4 Ω
4
Figure 24. Total Supply Current vs Total Output Power, 8 Ω
4.0
2.5
f = 1 kHz
Gain = 6 dB
RL = 4 Ω + 33 µH
WCSP
3.5
3.0
f = 1 kHz
Gain = 6 dB
RL = 8 Ω + 33 µH
WCSP
2.0
PO − Output Power − W
PO − Output Power − W
3
PO − Total Output Power − W
2.5
2.0
1.5
1.0
1.5
1.0
0.5
0.5
THD = 1%
THD = 10%
0.0
2.5
3.0
3.5
4.0
4.5
Vsupply − Supply Voltage − V
5.0
THD = 1%
THD = 10%
0.0
2.5
5.5
Figure 25. Output Power vs Supply Voltage, 4 Ω
Output
SWS
Disable
5.5
Output
0.75
SWS Enable
0.5
Voltage - V
0.5
Voltage - V
5.0
Figure 28. TPA2026D2 vs TPA2016D2 Shutdown Gain Ramp
1
0.75
3.5
4.0
4.5
Vsupply − Supply Voltage − V
Figure 26. Output Power vs Supply Voltage, 8 Ω
Figure 27. TPA2026D2 vs TPA2016D2 Start-Up Gain Ramp
1
3.0
0.25
0
-0.25
0.25
0
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1
0
200m
400m
600m
800m
1m
1.2m
1.4m
1.6m
1.8m
2m
0
1m
2m
3m
4m
5m
6m
7m
8m
9m
10m
t - Time - s
t - Time - s
Figure 30. Start-Up Time
Figure 29. Shutdown Time
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications. Figure 31 shows the setup
used for the typical characteristics of the test device.
TPA2026D2
CI
+
Measurement
Output
–
IN+
OUT+
Load
CI
IN–
VDD
+
OUT–
30 kHz
Low-Pass
Filter
+
Measurement
Input
–
GND
1 mF
VDD
–
(1)
All measurements were taken with a 1-μF CI (unless otherwise noted).
(2)
A 33-μH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3)
The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (1 kΩ
4.7 nF) is used on each output for the data sheet graphs.
Figure 31. Test Setup for Graphs
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9 Detailed Description
9.1 Overview
The TPA2026D2 is a stereo Class-D audio power amplifier capable of driving 750 mW/Ch into 8-Ω load at 3.6 V
and 3.2 W/Ch into 4-Ω load at 5 V. The device features independent software shutdown controls for each
channel and also provides thermal and short-circuit protection. In addition to these features, a fast start-up time
and small package size make the TPA2026D2 an ideal choice for cellular handsets, PDAs, and other portable
applications.
9.2 Functional Block Diagram
SDA
2
I C Interface
SCL
IC shutdown
2
I C Interface
& Control
SDZ
Bias and
References
AVDD
PVDDL
C IN
OUTL+
INL-
Differential
INL+
Input Left
Volume
Control
Class-D
Modulator
Power
Stage
OUTL-
1uF
AGC
Reference
AGC
PVDDR
C IN
OUTR+
INR-
Differential
INR+
Input Right
Volume
Control
Class-D
Modulator
Power
Stage
OUTR-
1uF
AGND
PGND
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9.3 Feature Description
9.3.1 Automatic Gain Control
The Automatic Gain Control (AGC) feature provides continuous automatic gain adjustment to the amplifier
through an internal PGA. This feature enhances the perceived audio loudness and at the same time prevents
speaker damage from occurring (Limiter function).
The AGC function attempts to maintain the audio signal gain as selected by the user through the Fixed Gain,
Limiter Level, and Compression Ratio variables. Other advanced features included are Maximum Gain and Noise
Gate Threshold. Table 2 describes the function of each variable in the AGC function.
Table 2. TPA2026D2 AGC Variable Descriptions
VARIABLE
Maximum Gain
DESCRIPTION
The gain at the lower end of the compression region.
The normal gain of the device when the AGC is inactive.
Fixed Gain
The fixed gain is also the initial gain when the device comes out of shutdown mode or when the AGC is
disabled.
Limiter Level
The value that sets the maximum allowed output amplitude.
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Feature Description (continued)
Table 2. TPA2026D2 AGC Variable Descriptions (continued)
VARIABLE
DESCRIPTION
Compression Ratio
The relation between input and output voltage.
Noise Gate Threshold
Below this value, the AGC holds the gain to prevent breathing effects.
Attack Time
The minimum time between two gain decrements.
Release Time
The minimum time between two gain increments.
Hold Time
The time it takes for the very first gain increment after the input signal amplitude decreases.
The AGC works by detecting the audio input envelope. The gain changes depending on the amplitude, the limiter
level, the compression ratio, and the attack and release time. The gain changes constantly as the audio signal
increases and/or decreases to create the compression effect. The gain step size for the AGC is 0.5 dB. If the
audio signal has near-constant amplitude, the gain does not change. Figure 32 shows how the AGC works.
INPUT SIGNAL
Limiter threshold
Limiter threshold
B
C
D
E
A
GAIN
OUTPUT SIGNAL
Limiter threshold
Release Time
Hold Time
Attack Time
Limiter threshold
A.
Gain decreases with no delay; attack time is reset. Release time and hold time are reset.
B.
Signal amplitude above limiter level, but gain cannot change because attack time is not over.
C.
Attack time ends; gain is allowed to decrease from this point forward by one step. Gain decreases because the
amplitude remains above limiter threshold. All times are reset
D.
Gain increases after release time finishes and signal amplitude remains below desired level. All times are reset after
the gain increase.
E.
Gain increases after release time is finished again because signal amplitude remains below desired level. All times
are reset after the gain increase.
Figure 32. Input and Output Audio Signal vs Time
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Gain - dB
Because the number of gain steps is limited the compression region is limited as well. Figure 33 shows how the
gain changes versus the input signal amplitude in the compression region.
VIN - dBV
Figure 33. Input Signal Voltage vs Gain
Thus the AGC performs a mapping of the input signal versus the output signal amplitude. This mapping can be
modified according to the variables from Table 2.
The following graphs and explanations show the effect of each variable to the AGC independently and which
considerations should be taken when choosing values.
9.3.1.1 Fixed Gain
The fixed gain determines the initial gain of the AGC. Set the gain using the following variables:
• Set the fixed gain to be equal to the gain when the AGC is disabled.
• Set the fixed gain to maximize SNR.
• Set the fixed gain such that it will not overdrive the speaker.
Increasing
Fixed Gain
G
xe
d
Decreasing
Fixed Gain
1:
1
Fi
VOUT - dBV
ai
n
=
3
Fi
xe
dB
d
G
ai
n
=
6
dB
Figure 34 shows how the fixed gain influences the input signal amplitude versus the output signal amplitude state
diagram. The dotted 1:1 line is displayed for reference. The 1:1 line means that for a 1-dB increase in the input
signal, the output increases by 1 dB.
VIN - dBV
Figure 34. Output Signal vs Input Signal State Diagram Showing Different Fixed Gain Configurations
If the Compression function is enabled, the Fixed Gain is adjustable from –28 dB to 30 dB. If the Compression
function is disabled, the Fixed gain is adjustable from 0 dB to 30 dB.
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9.3.1.2 Limiter Level
The Limiter level sets the maximum amplitude allowed at the output of the amplifier. The limiter should be set
with the following constraints in mind:
• Below or at the maximum power rating of the speaker
• Below the minimum supply voltage in order to avoid clipping
Figure 35 shows how the limiter level influences the input signal amplitude versus the output signal amplitude
state diagram.
Limiter Level= 630mW
Limiter Level= 500mW
VOUT - dBV
Limiter Level = 400 mW
Increasing
Limiter
Level
Decreasing
Limiter
Level
VIN - dBV
Figure 35. Output Signal vs Input Signal State Diagram Showing Different Limiter Level Configurations
The limiter level and the fixed gain influence each other. If the fixed gain is set high, the AGC has a large limiter
range. The fixed gain is set low, the AGC has a short limiter range. Figure 36 illustrates the two examples:
Small
Fixed
Gain
1:
1
VOUT - dBV
Large Fixed Gain
VIN - dBV
Figure 36. Output Signal vs Input Signal State Diagram Showing Same Limiter Level Configurations With
Different Fixed Gain Configurations
9.3.1.3 Compression Ratio
The compression ratio sets the relation between input and output signal outside the limiter level region. The
compression ratio compresses the dynamic range of the audio. For example if the audio source has a dynamic
range of 60 dB and compression ratio of 2:1 is selected, then the output has a dynamic range of 30 dB. Most
small form factor speakers have small dynamic range. Compression ratio allows audio with large dynamic range
to fit into a speaker with small dynamic range.
The compression ratio also increases the loudness of the audio without increasing the peak voltage. The higher
the compression ratio, the louder the perceived audio.
For example:
• A compression ratio of 4:1 is selected (meaning that a 4-dB change in the input signal results in a 1-dB signal
change at the output)
• A fixed gain of 0 dB is selected and the maximum audio level is at 0 dBV.
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When the input signal decreases to –32 dBV, the amplifier increases the gain to 24 dB in order to achieve an
output of –8 dBV. The output signal amplitude equation is:
Output signal amplitude =
Input signal initial amplitude - |Current input signal amplitude|
Compression ratio
(1)
In this example:
-8dBV =
0dBV - | - 32 dBV|
4
(2)
The gain change equation is:
æ
ö
1
Gain change = ç 1 ÷ × Input signal change
Compression ratio ø
è
(3)
1ö
æ
24 dB = ç 1 - ÷ × 32
4ø
è
(4)
Consider the following when setting the compression ratio:
• Dynamic range of the speaker
• Fixed gain level
• Limiter Level
• Audio Loudness vs Output Dynamic Range
Figure 37 shows different settings for dynamic range and different fixed gain selected but no limiter level.
Rotation
Point@
higher gain
8 :1
4 :1
Increasing
Fixed Gain
1
2:
VOUT - dBV
1
Rotation
Point@
lower gain
:1
8 :1
Decreasing
4 :1
2:
1
1
:1
VIN - dBV
Figure 37. Output Signal vs Input Signal State Diagram Showing Different Compression Ratio
Configurations With Different Fixed Gain Configurations
The rotation point is always at VIN = 10 dBV. The rotation point is not located at the intersection of the limiter
region and the compression region. By changing the fixed gain the rotation point will move in the y-axis direction
only, as shown in the previous graph.
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9.3.1.4 Interaction Between Compression Ratio and Limiter Range
The compression ratio can be limited by the limiter range.
NOTE
The limiter range is selected by the limiter level and the fixed gain.
For a setting with large limiter range, the amount of gain steps in the AGC remaining to perform compression are
limited. Figure 38 shows two examples, where the fixed gain was changed.
1. Small limiter range yielding a large compression region (small fixed gain).
2. Large limiter range yielding a small compression region (large fixed gain).
Large Limiter
Range
Rotation
Point @
higher gain
1
Rotation
Point @
lower gain
Small Limiter
Range
1:
VOUT - dBV
Small
Compression
Region
Large
Compression
Region
VIN - dBV
Figure 38. Output Signal vs Input Signal State Diagram Showing the Effects of the Limiter Range to the
Compression Region
9.3.1.5 Noise Gate Threshold
The noise gate threshold prevents the AGC from changing the gain when there is no audio at the input of the
amplifier. The noise gate threshold stops gain changes until the input signal is above the noise gate threshold.
Select the noise gate threshold to be above the noise but below the minimum audio at the input of the amplifier
signal. A filter is needed between delta-sigma CODEC/DAC and TPA2026D2 for effectiveness of the noise gate
function. The filter eliminates the out-of-band noise from delta-sigma modulation and keeps the CODEC/DAC
output noise lower than the noise gate threshold.
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Input Signal
Amplitude - Vrms
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No
Audio
Noise Gate Threshold
time
Gain - dB
Gain does not change
in this region
time
Figure 39. Time Diagram Showing the Relationship Between Input Signal Amplitude, Noise Gate
Threshold, and Gain Versus Time
9.3.1.6 Maximum Gain
This variable limits the number of gain steps in the AGC. This feature is useful in order to accomplish a more
advanced output signal versus input signal transfer characteristic.
For example, to prevent the gain from going above a certain value, reduce the maximum gain.
However, this variable will affect the limiter range and the compression region. If the maximum gain is
decreased, the limiter range and/or compression region is reduced. Figure 40 illustrates the effects.
1:
1
VOUT - dBV
Max Gain Max Gain
= 30dB
= 22dB
VIN - dBV
Figure 40. Output Signal vs Input Signal State Diagram Showing Different Maximum Gains
A particular application requiring maximum gain of 22 dB, for example. Thus, set the maximum gain at 22 dB.
The amplifier gain never has a gain higher than 22 dB; however, this reduces the limiter range.
9.3.1.7 Attack, Release, and Hold Time
• The attack time is the minimum time between gain decreases.
• The release time is the minimum time between gain increases.
• The hold time is the minimum time between a gain decrease (attack) and a gain increase (release). The hold
time can be deactivated. Hold time is only valid if greater than release time.
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Successive gain decreases are never faster than the attack time. Successive gain increases are never faster
than the release time.
All time variables (attack, release, and hold) start counting after each gain change performed by the AGC. The
AGC is allowed to decrease the gain (attack) only after the attack time finishes. The AGC is allowed to increase
the gain (release) only after the release time finishes counting. However, if the preceding gain change was an
attack (gain increase) and the hold time is enabled and longer than the release time, then the gain is only
increased after the hold time.
The hold time is only enabled after a gain decrease (attack). The hold time replaces the release time after a gain
decrease (attack). If the gain needs to be increased further, then the release time is used. The release time is
used instead of the hold time if the hold time is disabled.
The attack time must be at least 100 times shorter than the release and hold time. The hold time must be the
same or greater than the release time. It is important to select reasonable values for those variables in order to
prevent the gain from changing too often or too slow.
Figure 41 illustrates the relationship between the three time variables.
Input Signal
Amplitue (Vrms)
Gain dB
Time end
Attack time
Time reset
Release time
Hold time
Hold timer not used after
first gain increase
time
Figure 41. Time Diagram Showing the Relation Between the Attack, Release, and Hold Time vs Input
Signal Amplitude and Gain
Figure 42 shows a state diagram of the input signal amplitude versus the output signal amplitude and a summary
of how the variables from Table 2 described in the preceding pages affect them.
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Fixed
Gain
Rotation
Point
8:1
¥:1
1:
1
4:1
2:1
nR
sio
1
:1
A
tta
R
c
el
k
ea
Ti
se
m
e
Ti
m
e
Noise Gate Threshold
VOUT - dBV
r es
mp
o
C
Limiter
Level
ion
eg
Maximum
Gain
VIN - dBV
10 dBV
Figure 42. Output Signal vs Input Signal State Diagram
9.3.2 Operation With DACS and CODECS
In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor
from the audio amplifier. This occurs when output frequencies of the CODEC/DAC mix with the Class-D
switching frequency and create sum or difference components in the audio band. The noise increase can be
solved by placing an RC low-pass filter between the CODEC/DAC and audio amplifier. The filter reduces high
frequencies that cause the problem and allows proper performance.
If driving the TPA2016D2 input with 4th-order or higher ΔΣ DACs or CODECs, add an RC low-pass filter at each
of the audio inputs (IN+ and IN–) of the TPA2016D2 to ensure best performance. The recommended resistor
value is 100 Ω and the capacitor value of 47 nF.
9.3.3 Short-Circuit Auto-Recovery
When a short-circuit event happens, the TPA2026D2 goes to low duty cycle mode and tries to reactivate itself
every 110 µs. This auto-recovery continues until the short-circuit event stops. This feature can protect the device
without affecting the device's long-term reliability. FAULT bit (register 1, bit 3) still requires a write to clear.
9.3.4 Filter-Free Operation and Ferrite Bead Filters
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the
frequency-sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC
and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,
choose one with high impedance at high frequencies, and low impedance at low frequencies. In addition, select a
ferrite bead with adequate current rating to prevent distortion of the output signal.
Use an LC output filter if there are low frequency (< 1 MHz) EMI-sensitive circuits or there are long leads from
amplifier to speaker. Figure 43 shows typical ferrite bead and LC output filters.
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Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 43. Typical Ferrite Bead Filter (Chip Bead Example: TDK: MPZ1608S221A)
9.4 Device Functional Modes
9.4.1 TPA2026D2 AGC Operation
The TPA2026D2 is controlled by the I2C interface. The correct start-up sequence is:
1. Apply the supply voltage to the AVDD and PVDD (L, R) pins.
2. Apply a voltage above VIH to the SDZ pin. The TPA2026D2 powers up the I2C interface and the control logic.
By default, the device is in active mode (SWS = 0). After 5 ms the amplifier enables the class-D output stage
and become fully operational.
9.4.1.1 AGC Start-Up Condition
The amplifier gain at start-up depends on the following conditions:
1. Start-up from hardware reset (EN from 0 to 1): The amplifier starts up immediately at default fixed gain. AGC
starts controlling gain once the input audio signal exceeds noise gate threshold.
2. Start-up from software shutdown (SWS from 1 to 0): The amplifier starts up immediately at the latest fixed
gain during software shutdown, regardless the attack or release time. For example:
– Audio is playing at fixed gain 6 dB
– Devices goes to software shutdown (SWS = 1)
– Set fixed gain from 6 dB to 12 dB
– Remove software shutdown (SWS = 0)
– Amplifier starts up immediately at 12 dB
3. During audio playback with AGC on, gain changes according to attack or release time. For example:
– Audio is playing at fixed gain 6 dB and 1:1 compression ratio
– Set fixed gain from 6 dB to 12 dB, at release time 500 ms / 6 dB
– Amplifier takes 500 ms to ramp from 6 dB to 12 dB
4. When SPKR_EN_R = 0, SPKR_EN_L = 0 and SWS = 0, the amplifier is set at fixed gain. The amplifier will
start up at fixed gain when either SPKR_EN_R and SPKR_EN_L transitions from 0 to 1.
CAUTION
Do not interrupt the start-up sequence after changing SDZ from VIL to VIH.
Do not interrupt the start-up sequence after changing SWS from 1 to 0.
The default conditions of TPA2026D2 allows audio playback without I2C control. Refer to Table 5 for the entire
default conditions.
There are several options to disable the amplifier:
• Write SPK_EN_R = 0 and SPK_EN_L = 0 to the register (0x01, 6 and 0x01, 7). This write disables each
speaker amplifier, but leaves all other circuits operating.
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Device Functional Modes (continued)
•
•
Write SWS = 1 to the register (0x01, 5). This action disables most of the amplifier functions.
Apply VIL to SDZ. This action shuts down all the circuits and has very low quiescent current consumption.
This action resets the registers to its default values.
CAUTION
Do not interrupt the shutdown sequence after changing SDZ from VIH to VIL.
Do not interrupt the shutdown sequence after changing SWS from 0 to 1.
9.4.2 TPA2026D2 AGC Recommended Settings
Table 3. Recommended AGC Settings for Different Types of Audio Source (VDD = 3.6 V)
AUDIO
SOURCE
COMPRESSION
RATIO
ATTACK TIME
(ms/6 dB)
RELEASE TIME
(ms/6 dB)
HOLD TIME
(ms)
FIXED GAIN
(dB)
LIMITER LEVEL
(dBV)
Pop Music
4:1
1.28 to 3.84
986 to 1640
137
6
7.5
Classical
2:1
2.56
1150
137
6
8
Jazz
2:1
5.12 to 10.2
3288
—
6
8
Rap/Hip Hop
4:1
1.28 to 3.84
1640
—
6
7.5
Rock
2:1
3.84
4110
—
6
8
Voice/News
4:1
2.56
1640
—
6
8.5
9.5 Programming
9.5.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most
significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on
SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within
the low time of the clock period. Figure 44 shows a typical sequence. The master generates the 7-bit slave
address and the read/write (R/W) bit to open communication with another device, and then waits for an
acknowledge condition. The TPA2026D2 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals through a bidirectional bus using a wired-AND connection.
An external pullup resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 5 V, use pullup resistors between 1 kΩ and 2 kΩ.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 44. Typical I2C Sequence
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Programming (continued)
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 44.
9.5.2 Single and Multiple-Byte Transfers
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA2026D2 responds with data, one byte at a time, starting at the
register assigned, as long as the master device continues to respond with acknowledgments.
The TPA2026D2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of
data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.
9.5.3 Single-Byte Write
As Figure 45 shows, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C device
address and the read/write bit, the TPA2026D2 responds with an acknowledge bit. Next, the master transmits the
register byte corresponding to the TPA2026D2 internal memory address being accessed. After receiving the
register byte, the TPA2026D2 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2026D2
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
I2C Device Address and
Read/Write Bit
A5
A4
A3
A2
A1
A0 ACK D7
Acknowledge
D6
Register
D5
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
Figure 45. Single-Byte Write Transfer
9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA2026D2 as shown in Figure 46. After receiving each data byte,
the TPA2026D2 responds with an acknowledge bit.
Register
Figure 46. Multiple-Byte Write Transfer
9.5.5 Single-Byte Read
As Figure 47 shows, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a
read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
24
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Programming (continued)
After receiving the TPA2026D2 address and the read/write bit, the TPA2026D2 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA2026D2 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA2026D2 address and
the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA2026D2
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A4
Not
Acknowledge
Acknowledge
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
I2C Device Address and
Read/Write Bit
Register
D1
D0 ACK
Stop
Condition
Data Byte
Figure 47. Single-Byte Read Transfer
9.5.6 Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA2026D2 to the master device as shown in Figure 48. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A0 ACK
A6
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Register
Acknowledge
Not
Acknowledge
D0 ACK D7
D0 ACK
Acknowledge
Acknowledge
D0
ACK D7
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 48. Multiple-Byte Read Transfer
9.6 Register Maps
Table 4. TPA2026D2 Register Map
REGISTER
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
SPK_EN_R
SPL_EN_L
SWS
FAULT_R
FAULT_L
Thermal
1
NG_EN
2
0
0
ATK_time [5]
ATK_time [4]
ATK_time [3]
ATK_time [2]
ATK_time [1]
ATK_time [0]
3
0
0
REL_time [5]
REL_time [4]
REL_time [3]
REL_time [2]
REL_time [1]
REL_time [0]
4
0
0
Hold_time [5]
Hold_time [4]
Hold_tme [3]
Hold_time [2]
Hold_time [1]
Hold_time [0]
5
0
0
FixedGain [5]
FixedGain [4]
FixedGain [3] FixedGain [2]
FixedGain [1]
FixedGain [0]
6
Output
Limiter
Disable
NoiseGate
Threshold [1]
NoiseGate
Threshold [2]
Output Limiter
Level [4]
Output
Limiter Level
[3]
Output
Limiter Level
[2]
Output Limiter
Level [1]
Output Limiter
Level [0]
7
Max Gain [3]
Max Gain [2]
Max Gain [1]
Max Gain [0]
0
0
Compression
Ratio [1]
Compression
Ratio [0]
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The default register map values are given in Table 5.
Table 5. TPA2026D2 Default Register Values
REGISTER
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Default
C3h
05h
0Bh
00h
06h
3Ah
C2h
Any register above address 0x08 is reserved for testing and must not be written to because it may change the
function of the device. If read, these bits may assume any value.
Some of the default values can be reprogrammed through the I2C interface and written to the EEPROM. This
function is useful to speed up the turnon time of the device and minimizes the number of I2C writes. If this is
required, contact your local TI representative.
The TPA2026D2 I2C address is 0xB0 (binary 10110000) for writing and 0xB1 (binary 10110001) for reading. If a
different I2C address is required, contact your local TI representative. See General I2C Operation for more
details.
The following tables show the details of the registers, the default values, and the values that can be programmed
through the I2C interface.
9.6.1 IC Function Control (Address: 1)
Table 6. IC Function Control (Address: 1)
REGISTER
ADDRESS
01 (01H) – IC
Function Control
I2C BIT
LABEL
7
SPK_EN_R
1 (enabled)
Enables right amplifier
6
SPK_EN_L
1 (enabled)
Enables left amplifier
5
SWS
0 (enabled)
Shutdown IC when bit = 1
4
FAULT_R
0
Changes to a 1 when there is a short on the right channel. Reset by writing
a 0.
3
FAULT_L
0
Changes to a 1 when there is a short on the left channel. Reset by writing a
0
2
Thermal
0
Changes to a 1 when die temperature is above 150°C
1
UNUSED
1
0
NG_EN
1 (enabled)
DEFAULT
DESCRIPTION
Enables Noise Gate function
SPK_EN_R:
Enable bit for the right-channel amplifier. Amplifier is active when bit is high. This function is
gated by thermal and returns once the IC is below the threshold temperature.
SPK_EN_L:
Enable bit for the left-channel amplifier. Amplifier is active when bit is high. This function is
gated by thermal and returns once the IC is below the threshold temperature
SWS:
Software shutdown control. The device is in software shutdown when the bit is 1 (control, bias
and oscillator are inactive). When the bit is 0 the control, bias and oscillator are enabled.
FAULT_L:
This bit indicates that an over-current event has occurred on the left channel with a 1. This bit
is cleared by writing a 0 to it.
FAULT_R:
This bit indicates that an over-current event has occurred on the right channel with a 1. This bit
is cleared by writing a 0 to it.
Thermal:
This bit indicates a thermal shutdown that was initiated by the hardware with a 1. This bit is
deglitched and latched, and can be cleared by writing a 0 to it.
NG_EN:
Enable bit for the Noise Gate function. This function is enabled when this bit is high. This
function can only be enabled when the Compression ratio is not 1:1.
26
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9.6.2 AGC Attack Control (Address: 2)
Table 7. AGC Attack Control (Address: 2)
REGISTER
ADDRESS
02 (02H) –
AGC Control
I2C BIT
LABEL
DEFAULT
7:6
Unused
00
5:0
ATK_time
000101
(1.28 ms/6 dB)
DESCRIPTION
AGC Attack time (gain ramp down)
Per Step
Per 6 dB
000001
0.1067 ms
1.28 ms
90% Range
5.76 ms
000010
0.2134 ms
2.56 ms
11.52 ms
000011
0.3201 ms
3.84 ms
17.19 ms
000100
0.4268 ms
5.12 ms
23.04 ms
(time increases by 0.1067 ms with every step)
111111
ATK_time
6.722 ms
80.66 ms
362.99 ms
These bits set the attack time for the AGC function. The attack time is the minimum time
between gain decreases.
9.6.3 AGC Release Control (Address: 3)
Table 8. AGC Release Control (Address: 3)
REGISTER
ADDRESS
I2C BIT
03 (03H) – AGC
Release
Control
7:6
Unused
00
5:0
REL_time
001011
(0.9864 sec/6 dB)
LABEL
DEFAULT
DESCRIPTION
AGC Release time (gain ramp down)
Per Step
Per 6 dB
90% Range
000001
0.0137 s
0.1644 s
0.7398 s
000010
0.0274 s
0.3288 s
1.4796 s
000011
0.0411 s
0.4932 s
2.2194 s
000100
0.0548 s
0.6576 s
2.9592 s
(time increases by 0.0137 s with every step)
111111
REL_time
0.8631 s
10.36 s
46.6 s
These bits set the release time for the AGC function. The release time is the minimum time
between gain increases.
9.6.4 AGC Hold Time Control (Address: 4)
Table 9. AGC Hold Time Control(Address: 4)
REGISTER
ADDRESS
I2C BIT
04 (04H) –
AGC Hold
Time Control
7:6
Unused
00
5:0
Hold_time
000000 (disabled)
LABEL
DEFAULT
DESCRIPTION
AGC Hold time
Per Step
000000
Hold Time Disable
000001
0.0137 s
000010
0.0274 s
000011
0.0411 s
000100
0.0548 s
(time increases by 0.0137 s with every step)
111111
Hold_time
0.8631 s
These bits set the hold time for the AGC function. The hold time is the minimum time between
a gain decrease (attack) and a gain increase (release). The hold time can be deactivated.
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9.6.5 AGC Fixed Gain Control (Address: 5)
Table 10. AGC Fixed Gain Control (Address: 5)
REGISTER
ADDRESS
05 (05H) –
AGC Fixed
Gain Control
I2C BIT
LABEL
DEFAULT
7:6
Unused
00
5:0
Fixed Gain
000110 (6 dB)
DESCRIPTION
Sets the fixed gain of the amplifier: two's complement
Gain
100100
–28 dB
100101
–27 dB
100110
–26 dB
(gain increases by 1 dB with every step)
111101
–3 dB
111110
–2 dB
111111
–1 dB
000000
0 dB
000001
1 dB
000010
2 dB
000011
3 dB
(gain increases by 1dB with every step)
Fixed Gain
011100
28 dB
011101
29 dB
011110
30 dB
These bits are used to select the fixed gain of the amplifier. If compression is enabled, fixed
gain is adjustable from –28 dB to 30 dB. If compression is disabled, fixed gain is adjustable
from 0 dB to 30 dB.
9.6.6 AGC Control (Address: 6)
Table 11. AGC Control (Address: 6)
REGISTER
ADDRESS
06 (06H) –
AGC Control
I2C BIT
7
6:5
LABEL
DEFAULT
Output Limiter
Disable
0 (enable)
NoiseGate
Threshold
01 (4 mVrms)
DESCRIPTION
Disables the output limiter function. Can only be disabled when the AGC compression
ratio is 1:1 (off)
Select the threshold of the noise gate
Threshold
00
4:0
Output Limiter
Level
11010 (6.5 dBV)
1 mVrms
01
4 mVrms
10
10 mVrms
11
20 mVrms
Selects the output limiter level
Output Power (Wrms)
Peak Output Voltage
(Vp)
dBV
00000
0.03
0.67
–6.5
00001
0.03
0.71
–6
00010
0.04
0.75
–5.5
(Limiter level increases by 0.5dB with every step)
28
11101
0.79
3.55
8
11110
0.88
3.76
8.5
11111
0.99
3.99
9
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Output Limiter
Disable
This bit disables the output limiter function when set to 1. Can only be disabled when
the AGC compression ratio is 1:1
NoiseGate Threshold
These bits set the threshold level of the noise gate. NoiseGate Threshold is only
functional when the compression ratio is not 1:1
Output Limiter Level
These bits select the output limiter level. Output Power numbers are for 8-Ω load.
9.6.7 AGC Control (Address: 7)
Table 12. AGC Control (Address: 7)
REGISTER
ADDRESS
07 (07H) –
AGC Control
I2C BIT
7:4
LABEL
Max Gain
DEFAULT
1100 (30 dB)
DESCRIPTION
Selects the maximum gain the AGC can achieve
Gain
0000
18 dB
0001
19 dB
0010
20 dB
(gain increases by 1 dB with every step)
1100
3:2
Unused
00
1:0
Compression
Ratio
10 (4:1)
30 dB
Selects the compression ratio of the AGC
Ratio
00
1:1 (off)
01
2:1
10
4:1
11
8:1
Compression Ratio These bits select the compression ratio. Output Limiter is enabled by default when the
compression ratio is not 1:1.
Max Gain
These bits select the maximum gain of the amplifier. In order to maximize the use of the
AGC, set the Max Gain to 30 dB
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device. Each of these configurations can be realized using the Evaluation Modules
(EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of
operation. Any design variation can be supported by TI through schematic and layout reviews. Visit e2e.ti.com for
design assistance and join the audio amplifier discussion forum for additional information.
10.2 Typical Applications
10.2.1 TPA2026D2 With Differential Input Signals
To Battery
10 mF
AVDD
PVDDL PVDDR
TPA2026D2
CIN 1 mF
INL–
Analog
Baseband
or
Codec
OUTL+
INL+
INR–
INR+
OUTL–
OUTR+
2
I C Clock
Digital
Baseband
2
I C Data
Master Shutdown
OUTR–
SCL
SDA
SDZ
AGND
PGND
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Figure 49. Typical Application Schematic With Differential Input Signals
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 13.
Table 13. Design Procedure
PARAMETER
EXAMPLE VALUE
Power supply
5V
High > 1.3 V
Enable inputs
Low < 0.6 V
8Ω
Speaker
30
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Surface Mount Capacitor
Temperature and applied DC voltage influence the actual capacitance of high-K materials. Table 14 shows the
relationship between the different types of high-K materials and their associated tolerances, temperature
coefficients, and temperature ranges. Notice that a capacitor made with X5R material can lose up to 15% of its
capacitance within its working temperature range.
In an application, the working capacitance of components made with high-K materials is generally much lower
than nominal capacitance. A worst-case result with a typical X5R material might be –10% tolerance, –15%
temperature effect, and –45% DC voltage effect at 50% of the rated voltage. This particular case would result in
a working capacitance of 42% (0.9 × 0.85 × 0.55) of the nominal value.
Select high-K ceramic capacitors according to the following rules:
1. Use capacitors made of materials with temperature coefficients of X5R, X7R, or better.
2. Use capacitors with DC voltage ratings of at least twice the application voltage. Use minimum 10-V
capacitors for the TPA2026D2.
3. Choose a capacitance value at least twice the nominal value calculated for the application. Multiply the
nominal value by a factor of 2 for safety. If a 10-μF capacitor is required, use 20 µF.
The preceding rules and recommendations apply to capacitors used in connection with the TPA2026D2. The
TPA2026D2 cannot meet its performance specifications if the rules and recommendations are not followed.
Table 14. Typical Tolerance and Temperature Coefficient of Capacitance by Material
MATERIAL
COG/NPO
X7R
X5R
Typical tolerance
±5%
±10%
80/–20%
Temperature
±30 ppm
±15%
22/–82%
Temperature range
–55 to 125°C
–55 to 125°C
–30 to 85°C
10.2.1.2.2 Decoupling Capacitor, CS
The TPA2026D2 is a high-performance Class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) 1-μF ceramic capacitor
(typically) placed as close as possible to the device PVDD (L, R) lead works best. Placing this decoupling
capacitor close to the TPA2026D2 is important for the efficiency of the Class-D amplifier, because any resistance
or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lowerfrequency noise signals, a 4.7 μF or greater capacitor placed near the audio power amplifier would also help, but
it is not required in most applications because of the high PSRR of this device.
10.2.1.2.3 Input Capacitors, CI
The input capacitors and input resistors form a high-pass filter with the corner frequency, fC, determined in
Equation 5.
1
fC =
(2p ´ RI ´ CI )
(5)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase
output offset. Equation 6 is used to solve for the input coupling capacitance. If the corner frequency is within the
audio band, the capacitors must have a tolerance of ±10% or better, because any mismatch in capacitance
causes an impedance mismatch at the corner frequency and below.
1
CI =
(2p ´ RI ´ fC )
(6)
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10.2.1.3 Application Curves
For application curves, see the figures listed in Table 15.
Table 15. Table of Graphs
DESCRIPTION
FIGURE NUMBER
Output Level vs Input Level
Figure 6
THD+N vs Frequency
Figure 11
Total Power Dissipation vs Total Output Power
Figure 22
Output Power vs Supply Voltage
Figure 26
10.2.2 TPA2026D2 With Single-Ended Input Signal
To power supply
10uF
AVDD
CI
PVDDL
PVDDR
TPA2026D2
INL-
Analog
Baseband or
CODEC
INL+
OUTL+
OUTL-
INRINR+
Digital
Baseband
I2C Clock
SCL
I2C Data
SDA
Master Shutdown
OUTR+
OUTR-
SDZ
AGND
PGND
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Figure 50. Typical Application Schematic With Single-Ended Input Signal
10.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 13.
10.2.2.2 Detailed Design Procedure
For the design procedure see Detailed Design Procedure from the previous section
10.2.2.3 Application Curves
For application curves, see the figures listed in Table 15.
32
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11 Power Supply Recommendations
The TPA2026D2 is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. Therefore
the output voltage range of the power supply should be within this range. The current capability of upper power
must not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA2026D2 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,
within 2 mm of the VDD/VCCOUT pin. This choice of capacitor and placement helps with higher frequency
transients, spikes, or digital hash on the line. In addition to the 0.1-μF ceramic capacitor, is recommended to
place a 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir,
providing energy faster than the board supply, thus helping to prevent any droop in the supply voltage.
12 Layout
12.1 Layout Guidelines
12.1.1 Pad Size
In making the pad size for the WCSP balls, TI recommends that the layout use non solder mask-defined (NSMD)
land. With this method, the solder mask opening is made larger than the desired land area, and the opening size
is defined by the copper pad width. Figure 51 and Table 16 show the appropriate diameters for a WCSP layout.
The TPA2026D2 evaluation module (EVM) layout is shown in Layout Example.
Figure 51. Land Pattern Dimensions
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Layout Guidelines (continued)
Table 16. Land Pattern Dimensions (1)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
SOLDER PAD
DEFINITIONS
COPPER PAD
SOLDER MASK (5)
OPENING
COPPER
THICKNESS
Non solder mask
defined (NSMD)
275 μm
(+0.0, –25 μm)
375 μm
(+0.0, –25 μm)
1 oz max (32 μm)
(2) (3) (4)
STENCIL (6)
(7)
OPENING
275 μm × 275 μm Sq. (rounded
corners)
STENCIL
THICKNESS
125 μm thick
Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
Recommend solder paste is Type 3 or Type 4.
For a PWB using a Ni/Au surface finish, the gold thickness must be less 0.5 mm to avoid a reduction in thermal fatigue performance.
Solder mask thickness must be less than 20 μm on top of the copper circuit pattern
Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
Trace routing away from WCSP device must be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
12.1.2 Component Location
Place all external components very close to the TPA2026D2. Placing the decoupling capacitor, CS, close to the
TPA2026D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace
between the device and the capacitor can cause a loss in efficiency.
12.1.3 Trace Width
Recommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCB
traces. For high current pins (PVDD (L, R), PGND, and audio output pins) of the TPA2026D2, use 100-μm trace
widths at the solder balls and at least 500-μm PCB traces to ensure proper performance and output power for
the device. For the remaining signals of the TPA2026D2, use 75-μm to 100-μm trace widths at the solder balls.
The audio input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation.
34
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12.2 Layout Example
Decoupling capacitor
placed as close as
possible to the device
INR- INR+
CI
10µF
Input capacitors
placed as close as
possible to the device
INL+ INL-
CI
1µF
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
SCL
SDA
SDZ
TPA2026D2
OUTR+ OUTR-
10µF
OUTL- OUTL+
1µF
Decoupling capacitor
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Bottom Layer Traces
Via to Ground Plane
Via to Bottom Layer
Via to Power Supply Plane
Figure 52. Layout Recommendation
12.3 Efficiency and Thermal Considerations
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the package is shown in the dissipation rating table. Converting this to θJA for the DSBGA package:
100°C/W
(7)
Given θJA of 100°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.4 W (0.2 W per channel) for 1.5 W per channel, 8-Ω load, 5-V supply, from Figure 15, the
maximum ambient temperature can be calculated with the following equation.
TA Max = TJMax - qJA PDMAX = 150 - 100 (0.4) = 110°C
(8)
Equation 8 shows that the calculated maximum ambient temperature is 110°C at maximum power dissipation
with a 5-V supply and 8-Ω a load. The TPA2026D2 is designed with thermal protection that turns the device off
when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more
resistive than 8-Ω dramatically increases the thermal performance by reducing the output current and increasing
the efficiency of the amplifier.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
SmartGain, Nano-Free, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14.1 YZH Package Dimensions
The package dimensions for this YZH package are shown in the table below. See the package drawing at the
end of this data sheet for more details.
Packaged Devices
TPA2026D2YZH
36
D
E
Max = 2160 µm
Max = 2137 µm
Min = 2100 µm
Min = 2077 µm
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA2026D2YZHR
ACTIVE
DSBGA
YZH
16
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
NSV
TPA2026D2YZHT
ACTIVE
DSBGA
YZH
16
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
NSV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA2026D2YZHR
DSBGA
YZH
16
3000
180.0
8.4
TPA2026D2YZHT
DSBGA
YZH
16
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.35
2.35
0.81
4.0
8.0
Q1
2.35
2.35
0.81
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2026D2YZHR
DSBGA
YZH
16
3000
182.0
182.0
20.0
TPA2026D2YZHT
DSBGA
YZH
16
250
182.0
182.0
20.0
Pack Materials-Page 2
D: Max = 2.164 mm, Min =2.104 mm
E: Max = 2.142 mm, Min =2.082 mm
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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