Texas Instruments | TAS5421-Q1 22-W Mono Automotive Digital-Audio Amplifier With Load Dump and I2C Diagnostics (Rev. D) | Datasheet | Texas Instruments TAS5421-Q1 22-W Mono Automotive Digital-Audio Amplifier With Load Dump and I2C Diagnostics (Rev. D) Datasheet

Texas Instruments TAS5421-Q1 22-W Mono Automotive Digital-Audio Amplifier With Load Dump and I2C Diagnostics (Rev. D) Datasheet
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TAS5421-Q1
SLOS814D – MARCH 2014 – REVISED SEPTEMBER 2016
TAS5421-Q1 22-W Mono Automotive Digital-Audio Amplifier With Load Dump and I2C
Diagnostics
1 Features
2 Applications
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Mono BTL Digital Power Amplifier
22-W Output Power at 10% THD+N into 4 Ω
4.5-V to 18-V Operating Range
85% Efficiency into 4 Ω
Differential Analog Input
Speaker Guard™ Speaker Protection with
Adjustable Power Limiter
75-dB Power-Supply Rejection Ratio (PSRR)
Load Diagnostic Functions:
– Open and Shorted Output Load
– Output-to-Power and Output-to-Ground Shorts
Protection and Monitoring Functions:
– Short-Circuit Protection
– 40-V Load Dump Protection per ISO-7637-2
– Output DC Level Detection while Music is
Playing
– Overtemperature Protection
– Overvoltage and Undervoltage Protection
Thermally Enhanced 16-Pin HTSSOP (PWP)
Package with PowerPAD™ Package (Pad Down)
Designed for Automotive EMC Requirements
Qualified According to AEC-Q100 Grade 2
ISO9000: 2002 TS16949 Certified
–40°C to 125°C Ambient Temperature Range
Automotive Emergency Call (eCall) Amplifier
Telematics Systems
Instrument Cluster Systems
Infotainment Audio
3 Description
The TAS5421-Q1 is a mono digital audio amplifier,
ideal for use in automotive emergency call (eCall),
telematics, instrument cluster, and infotainment
applications. The device provides up to 22 W into 4 Ω
at less than 10% THD+N from a 14.4-Vdc automotive
battery. The wide operating voltage range and
excellent efficiency make the device ideal for startstop support or running from a backup battery when
required. The integrated load-dump protection
reduces external voltage clamp cost and size, and
the onboard load diagnostics report the status of the
speaker through I2C.
Device Information(1)
PART NUMBER
TAS5421-Q1
Output Power Efficiency
2
90
IC
80
OUTP
TAS5421-Q1
70
LC
OUTN
Efficiency (%)
IN_P
IN_N
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Block Diagram
System
µP
PACKAGE
HTSSOP (16)
60
50
40
30
20
2:
4:
10
0
0
5
10
15
Output Power (W)
20
25
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5421-Q1
SLOS814D – MARCH 2014 – REVISED SEPTEMBER 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements for I2C Interface Signals.........
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
17
7.5 Register Maps ......................................................... 18
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Examples................................................... 23
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2014) to Revision D
Page
•
Added the FAULT pin to the Input voltage parameters in the Absolute Maximum Ratings table ......................................... 5
•
Added the MUTE pin to the logic-level high and logic-level low parameters for the STANDBY in the Recommended
Operating Conditions table ..................................................................................................................................................... 5
•
Added the capacitance parameter to the Electrical Characteristics table for the SDA pin in STANDBY mode .................... 7
•
Added the Receiving Notification of Documentation Updates section ................................................................................ 26
Changes from Revision B (July 2014) to Revision C
Page
•
Moved Tstg from Handling Ratings table to Absolute Maximum Ratings table ...................................................................... 5
•
Changed Handling Ratings table to ESD Ratings ................................................................................................................. 5
•
In "1. Load Diagnostics" paragraph, changed "at start-up" to "on de-assertion of STANDBY" and appended two
new sentences ..................................................................................................................................................................... 13
•
Changed Section number of I2C Serial Communication Bus from 7.4 to 7.3.7 ................................................................... 14
•
Changed Table 3 .................................................................................................................................................................. 17
•
Added disclaimer to beginning of Application and Implementation section ......................................................................... 20
•
Added Power Supply Recommendations section and moved the contents of former Section 8.2.1.5 here........................ 23
•
Placed text ahead of graphics for Figure 18 through Figure 21........................................................................................... 23
•
Created a Layout Examples section to contain former sections 9.1.1 through 9.1.4........................................................... 23
•
Added third-party component disclaimer .............................................................................................................................. 26
Changes from Revision A (July 2014) to Revision B
•
2
Page
Changed data-sheet status from PRODUCT PREVIEW to PRODUCTION DATA ............................................................... 1
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Changes from Original (March 2014) to Revision A
•
Page
Added content to the preliminary data sheet to create the full PRODUCT PREVIEW data sheet ....................................... 4
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5 Pin Configuration and Functions
PWP Package
16-Pin TSSOP With Exposed Thermal Pad
Top View
GND
1
16
GND
STANDBY
2
15
PVDD
BYP
3
14
FAULT
SDA
4
13
BSTP
Thermal
Pad
SCL
5
12
OUTP
IN_P
6
11
OUTN
IN_N
7
10
BSTN
MUTE
8
9
GND
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
BSTN
10
AI
Bootstrap for negative-output high-side FET
BSTP
13
AI
Bootstrap for positive-output high-side FET
BYP
3
PBY
Voltage-regulator bypass-capacitor pin
FAULT
14
DO
Active-low open-drain output used to report faults
1
GND
9
GND
Ground
16
IN_N
7
AI
Inverting analog input
IN_P
MUTE
6
AI
Non-inverting analog input
8
DI
Mute input, active-high (no internal pullup or pulldown)
OUTN
11
PO
Output (–)
OUTP
12
PO
Output (+)
PVDD
15
PWR
SCL
5
DI
I2C clock
SDA
4
DI/DO
I2C data
STANDBY
2
DI
Active-low STANDBY pin (no internal pullup or pulldown)
Thermal pad
—
—
Must be soldered to ground
(1)
4
Power supply
DI = digital input, DO = digital output, AI = analog input, PWR = power supply, PBY = power bypass, PO = power output, GND = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
DC supply voltage range, V(PVDD)
Relative to GND
Pulsed supply voltage range, V(PVDD_MAX)
t ≤ 400 ms exposure
MIN
MAX
–0.3
30
–1
40
Supply voltage ramp rate, ΔV(PVDD_RAMP)
15
–0.3
5
For IN_N, IN_P, FAULT, and MUTE pins
Relative to GND
–0.3
6.5
Maximum current, on all input pins, I(IN_MAX)
V
±4
(2)
A
±1
mA
7
Storage temperature, Tstg
(2)
V/ms
Relative to GND
Maximum sink current for open-drain pin, I(IN_ODMAX)
(1)
V
For SCL, SDA, and STANDBY pins
DC current on PVDD, GND and OUTx pins, I(PVDD), IO
Current
UNIT
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the Application and Implementation section for information on analog input voltage and ac coupling.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±3500
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
4-Ω ±20% load (or higher)
V(PVDD_OP)
Supply voltage range relative to GND.
Includes ac transients, requires proper
decoupling. (1)
V(PVDD_RIPPLE)
Maximum ripple on PVDD
V(PVDD) < 8 V
V(AIN) (2)
Analog audio input-signal level
AC-coupled input voltage
V(IH_STANDBY)
MUTE and STANDBY pins input voltage for
logic-level high
V(IL_STANDBY)
MUTE and STANDBY pins input voltage for
logic-level low
V(IH_SCL)
SCL pin input voltage for logic-level high
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
V(IH_SDA)
SDA pin input voltage for logic-level high
V(IL_SCL)
2-Ω ±20% load
MIN
NOM
MAX
4.5
14.4
18
5
14.4
18
1
0.25–1 (3)
0
2
UNIT
V
Vpp
Vrms
V
0.7
V
2.1
5.5
V
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
2.1
5.5
V
SCL pin input voltage for logic-level low
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
–0.5
1.1
V
V(IL_SDA)
SDA pin input voltage for logic-level low
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
–0.5
1.1
V
TA
Ambient temperature
–40
125
°C
When using low-impedance loads, do not
exceed overcurrent limit.
R(L)
Nominal speaker load impedance
V(PU)
Pullup voltage supply (for open-drain logic
outputs)
R(PU_EXT)
External pullup resistor on open-drain logic
outputs
R(PU_I2C)
I2C pullup resistance on SDA and SCL pins
C(PVDD)
External capacitor on the PVDD pin, typical
value ± 20% (1)
(1)
(2)
(3)
Resistor connected between open-drain logic
output and V(PU) supply.
2
4
16
Ω
3
3.3
3.6
V
50
kΩ
10
kΩ
10
1
4.7
10
μF
See the Power Supply Recommendations section.
Signal input for full unclipped output with gains of 36 dB, 32 dB, 26 dB, and 20 dB
Maximum recommended input voltage is determined by the gain setting.
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Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
C(BYP)
External capacitor on the BYP pin, typical
value ± 10%
C(OUT)
External capacitance to GND on OUT_X pins
C(IN)
External capacitance to analog input pin in
series with input signal
1
μF
C(BSTN), C(BSTP)
External boostrap capacitor, typical value ±
20%
220
nF
1
μF
4
μF
6.4 Thermal Information
TAS5421-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
39.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.9
°C/W
RθJB
Junction-to-board thermal resistance
20
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
19.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
PVDD idle current
In PLAY mode, no audio present
PVDD standby current
STANDBY mode, MUTE = 0 V
16
5
mA
20
µA
OUTPUT POWER
Output power per channel
Power efficiency
4 Ω, THD+N ≤ 1%, 1 kHz, TC = 75°C
18
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C
22
4 Ω, P(O) = 22 W (10% THD)
W
85%
AUDIO PERFORMANCE
Noise voltage at output
G = 20 dB, zero input, and A-weighting
65
µV
Common-mode rejection ratio
f = 1 kHz, 100 mVrms referenced to GND, G = 20 dB
63
dB
Power-supply rejection ratio
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
75
Total harmonic distortion + noise
P(O) = 1 W, f = 1 kHz
0.05
%
Switching frequency
Switching frequency selectable for AM interference
avoidance
400
Internal common-mode input bias voltage
Internal bias applied to IN_N, IN_P pins
Voltage gain (VO / VIN)
Source impedance = 0 Ω, P(O) = 1 W
dB
kHz
500
3
V
19
20
21
25
26
27
31
32
33
35
36
37
dB
PWM OUTPUT STAGE
FET drain-to-source resistance
TJ = 25°C
Output offset voltage
Zero input signal, G = 20 dB
6
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180
mΩ
±25
mV
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Electrical Characteristics (continued)
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
21
22.5
V
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set
19.5
PVDD overvoltage-shutdown hysteresis
0.6
V
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set
3.6
PVDD undervoltage-shutdown hysteresis
4
4.4
0.25
V
V
BYP
BYP pin voltage
6.4
6.9
7.4
V
4.1
V
POWER-ON RESET (POR)
PVDD voltage for POR
PVDD recovery hysteresis voltage for POR
0.3
V
170
°C
15
°C
3.5
A
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown
155
Junction temperature overtemperature shutdown
hystersis
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current)
STANDBY PIN
STANDBY pin current
0.1
0.2
µA
700
ms
DC DETECT
DC detect threshold
2.9
DC detect step response time
V
FAULT REPORT
FAULT pin output voltage for logic-level high (open-drain
logic output)
External 47-kΩ pullup resistor to 3.3 V
FAULT pin output voltage for logic-level low (open-drain
logic output)
External 47-kΩ pullup resistor to 3.3 V
2.4
V
0.5
V
200
Ω
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pin(s) to PVDD or
ground
Open-circuit detection threshold
Including speaker wires
70
95
120
Ω
Short-circuit detection threshold
Including speaker wires
0.9
1.2
1.5
Ω
SDA pin output voltage for logic-level high
R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V
2.4
SDA pin output voltage for logic-level low
3-mA sink current
2
IC
V
Capacitance for SCL and SDA pins
Capacitance for SDA pin
STANDBY mode
0.4
V
10
pF
30
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6.6 Timing Requirements for I2C Interface Signals
over recommended operating conditions (unless otherwise noted)
MIN
NOM
MAX
UNIT
f(SCL)
SCL clock frequency
400
kHz
tr
Rise time for both SDA and SCL signals
300
ns
tf
Fall time for both SDA and SCL signals
300
tw(H)
SCL pulse duration, high
0.6
µs
tw(L)
SCL pulse duration, low
1.3
µs
tsu(2)
Setup time for START condition
0.6
µs
th(2)
START condition hold time before generation of first clock pulse
0.6
µs
tsu(1)
Data setup time
100
ns
th(1)
Data hold time
0 (1)
ns
tsu(3)
Setup time for STOP condition
0.6
µs
C(B)
Load capacitance for each bus line
(1)
400
ns
pF
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu(1)
th(1)
SDA
T0027-03
Figure 1. SCL and SDA Timing
SCL
t(buf)
th(2)
tsu(2)
tsu(3)
SDA
Start
Condition
Stop
Condition
T0028-02
Figure 2. Timing for Start and Stop Conditions
8
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6.7 Typical Characteristics
PVDD = 14.4 V, TA = 25ºC, P(O) = 1 W, 1-kHz input, default I2C settings (unless otherwise noted)
90
10
2:
4:
80
60
1
THD+N (%)
Efficiency (%)
70
50
40
30
0.1
20
2:
4:
10
0
0
5
10
15
Output Power (W)
Gain = 26 dB
V(PVDD) = 14.4 V
20
0.01
0.01
25
0.1
D001
f(SW) = 400 kHz
10
30
D002
TA = 25ºC
Figure 3. Efficiency vs Output Power
Figure 4. THD+N vs Output Power
30
1
2 :, 1% THD
2 :, 10% THD
4 :, 1% THD
4 :, 10% THD
25
2 :, 1 W
2 :, 5 W
4 :, 1 W
4 :, 5 W
20
0.1
THD+N (%)
Output Power (W)
1
Output Power (W)
15
10
0.01
5
0
5
6
7
8
9
10 11 12
Supply Voltage (V)
13
14
15
0.001
20
16
100
D003
0
-20
-20
-40
-40
-60
-60
-80
-100
20k
D004
-80
-100
-120
-120
-140
-140
-160
-160
-180
10k
Figure 6. THD+N vs Frequency
0
Noise (dBV)
Noise (dBV)
Figure 5. Output Power vs PVDD
1k
Frequency (Hz)
-180
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
D005
0
2k
Figure 7. Noise FFT With –60-dB Output
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
D006
Figure 8. Noise FFT With 1-W Output
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Typical Characteristics (continued)
PVDD = 14.4 V, TA = 25ºC, P(O) = 1 W, 1-kHz input, default I2C settings (unless otherwise noted)
4
Overcurrent Threshold (A)
3.5
3
2.5
2
1.5
1
0.5
0
25
35
45
55
65
75
85
95
Ambient Temperature (ºC)
105
115
125
D007
Figure 9. Overcurrent Threshold vs Temperature
10
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7 Detailed Description
7.1 Overview
The TAS5421-Q1 is a mono analog-input audio amplifier for use in the automotive environment. The design uses
an ultra-efficient class-D technology developed by Texas Instruments, but with features added for the automotive
industry. The class-D technology allows for reduced power consumption, reduced heat, and reduced peak
currents in the electrical system. The device realizes an audio sound system design with smaller size and lower
weight than traditional class-AB solutions.
The TAS5421-Q1 device has seven core design blocks:
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
7.2 Functional Block Diagram
Overcurrent Detection
SDA
2
I C
Protection
Control
SCL
DC Detection
Thermal Protection
Biases
and
References
Voltage Protection
GVDD
LDO
Regulator
BYP
GVDD
Short-to-Ground
Control
PVDD
Diagnostics
Control
FAULT
PVDD
BSTN
Short-to-Power
Shorted Load
Open Load
MUTE
STANDBY
IN_N
Gain
Control
Speaker
Guard
Preamplifier
IN_P
Pulse
Width
Modulator
(PWM)
Gate
Drive
OUTN
GVDD
GND
BSTP
PVDD
GND
Gate
Drive
OUTP
GND
7.3 Feature Description
7.3.1 Analog Audio Input and Preamplifier
The differential input stage of the amplifier cancels common-mode noise that appears on the inputs. For a
differential audio source, connect the positive lead to IN_P and the negative lead to IN_N. The inputs must be
ac-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages. For good
transient performance, the impedance seen at each of the two differential inputs should be the same.
The gain setting impacts the analog input impedance of the amplifier. See Table 1 for typical values.
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Table 1. Input Impedance and Gain
Gain
Input Impedance
20 dB
60 kΩ ± 20%
26 dB
30 kΩ ± 20%
32 dB
15 kΩ ± 20%
36 dB
9 kΩ ± 20%
7.3.2 Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5421-Q1, the modulator is an advanced design
with high bandwidth, low noise, low distortion, and excellent stability.
The pulse-width modulation scheme allows increased efficiency at low power. Each output is switching from 0 V
to PVDD. The OUTP and OUTN pins are in phase with each other with no input so that there is little or no
current in the speaker. The duty cycle of OUTP is greater than 50% and the duty cycle OUTN is less than 50%
for positive output voltages. The duty cycle of OUTN is greater than 50% and the duty cycle of OUTP is less than
50% for negative output voltages. The voltage across the load is at 0 V through most of the switching period,
reducing power loss.
OUTP
OUTN
No Output
0V
OUTP – OUTN
Speaker
Current
0A
OUTP
OUTN
Positive Output
OUTP – OUTN
PVDD
0V
Speaker
Current
0A
OUTP
OUTN
Negative Output
OUTP – OUTN
0V
–PVDD
0A
Speaker
Current
Figure 10. BD Mode Modulation
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7.3.3 Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts the signal to drive a high-current, full-bridge,
power FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
7.3.4 Power FETs
The BTL output comprises four matched N-channel FETs for high efficiency and maximum power transfer to the
load. By design, the FETs withstand large voltage transients during a load-dump event.
7.3.5 Load Diagnostics
The device incorporates load diagnostic circuitry designed for detecting and determining the status of output
connections. The device supports the following diagnostics:
• Short to GND
• Short to PVDD
• Short across load
• Open load
The device reports the presence of any of the short or open conditions to the system via I2C register read.
1. Load Diagnostics—The load diagnostic function runs on de-assertion of STANDBY or when the device is in
a fault state (dc detect, overcurrent, overvoltage, undervoltage, and overtemperature). During this test, the
outputs are in a Hi-Z state. The device determines whether the output is a short to GND, short to PVDD,
open load, or shorted load. The load diagnostic biases the output, which therefore requires limiting the
capacitance value for proper functioning; see the Recommended Operating Conditions. The load diagnostic
test takes approximately 229 ms to run. Note that the check phase repeats up to five times if a fault is
present or a large capacitor to GND is present on the output. On detection of an open load, the output still
operates. On detection of any other fault condition, the output goes into a Hi-Z state, and the device checks
the load continuously until removal of the fault condition. After detection of a normal output condition, the
audio output starts. The load diagnostics run after every other overvoltage (OV) event. The load diagnostic
for open load only has I2C reporting. All other faults have I2C and FAULT pin assertion.
The device performs load diagnostic tests as shown in Figure 11.
Figure 12 illustrates how the diagnostics determine the load based on output conditions.
Discharge
(75 ms)
Ramp Up
(52 ms)
Check
(50 ms)
Ramp Down
(52 ms)
Figure 11. Load Diagnostics Sequence of Events
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Output Conditions
Load Diagnostics
Open Load
Open Load Detected
OL Max
Normal or Open Load
Open Load (OL)
May Be Detected
Detection Threshold
OL Min
Normal
Load
Play Mode
SL Max
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
SL Min
Shorted
Load
Shorted Load
Detected
Figure 12. Load Diagnostic Reporting Thresholds
2. Faults During Load Diagnostics—If the device detects a fault (such as overtemperature, overvoltage, or
undervoltage) during the load diagnostics test, the device exits the load diagnostics, which can result in a
pop or click on the output.
7.3.6 Protection and Monitoring
• Overcurrent Shutdown (OCSD)—The overcurrent shutdown forces the output into Hi-Z. The device asserts
the FAULT pin and updates the I2C register.
• DC Detect—This circuit checks for a dc offset continuously during normal operation at the output of the
amplifier. If a dc offset occurs, the device asserts the FAULT pin and updates the I2C register. Note that the
dc detection threshold follows PVDD changes.
• Overtemperature Shutdown (OTSD)—The device shuts down when the die junction temperature reaches
the overtemperature threshold. The device asserts the FAULT pin asserts and updates I2C register. Recovery
is automatic when the temperature returns to a safe level.
• Undervoltage (UV)—The undervoltage (UV) protection detects low voltages on PVDD. In the event of an
undervoltage condition, the device asserts the FAULT pin and resets the I2C register.
• Power-On Reset (POR)—Power-on reset (POR) occurs when PVDD drops below the POR threshold. A POR
event causes the I2C bus to go into a high-impedance state. After recovery from the POR event, the device
restarts automatically with default I2C register settings. The I2C is active as long as the device is not in POR.
• Overvoltage (OV) and Load Dump—OV protection detects high voltages on PVDD. If PVDD reaches the
overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. The device can
withstand 40-V load-dump voltage spikes.
• SpeakerGuard—This protection circuitry limits the output voltage to the value selected in I2C register 0x03.
This value determines both the positive and negative limits. The user can use the SpeakerGuard feature to
improve battery life or protect the speaker from exceeding its excursion limits.
• Adjacent-Pin Shorts—The device design is such that shorts between adjacent pins do not cause damage.
7.3.7 I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions
and detections are via I2C. The system can also set numerous features and operating conditions via I2C. The I2C
interface is active approximately 1 ms after the STANDBY pin is high.
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The I2C interface controls the following device features:
• Changing gain setting to 20 dB, 26 dB, 32 dB, or 36 dB.
• Controlling peak voltage value of SpeakerGuard protection circuitry
• Reporting load diagnostic results
• Changing of switching frequency for AM radio avoidance
7.3.7.1 I2C Bus Protocol
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only
device that does not support a multimaster bus environment or wait-state insertion. The master device uses the
I2C control interface to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-toLOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. Figure 13 shows these conditions. The master
generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and
then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to
indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The address
for each device is a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of an
external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the
communicating devices can transmit between start and stop conditions. After transfer of the last word, the master
generates a stop condition to release the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-02
2
Figure 13. Typical I C Sequence
To communicate with the device, the I2C master uses addresses shown in Figure 13. Transmission of read and
write data can be by single-byte or multiple-byte data transfers.
7.3.7.2 Random Write
As shown in Figure 14, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
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Start
Condition
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Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
A4
2
I C Device Address and
Read/Write Bit
A3
A2
A1
Acknowledge
A0 ACK D7
D6
D5
Subaddress
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-05
Figure 14. Random Write Transfer
7.3.7.3 Random Read
As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, the master device
performs both a write and a following read. Initially, the master device performs a write to transfer the address
byte of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address
and the read/write bit, the device responds with an acknowledge bit. In addition, after sending the internal
memory address byte, the master device transmits another start condition followed by the device address and
the read/write bit again. This time, the read/write bit is a 1, indicating a read transfer. After receiving the address
and the read/write bit, the device again responds with an acknowledge bit. Next, the device transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a notacknowledge followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
I C Device Address and
Read/Write Bit
A5
A4
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
D6
2
Subaddress
D1
D0 ACK
Stop
Condition
Data Byte
I C Device Address and
Read/Write Bit
T0036-03
Figure 15. Random Read Transfer
7.3.7.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that the TAS5421-Q1
transmits multiple data bytes to the master device as shown in Figure 16. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte and automatically increments the
I2C subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Subaddress
A0 ACK
A6
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-07
Figure 16. Sequential Read Transfer
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7.4 Device Functional Modes
7.4.1 Hardware Control Pins
Three discrete hardware pins are available for real-time control and indication of device status.
1. FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition which requires
the device to go into the Hi-Z mode. On assertion of this pin, the device has protected itself and the system
from potential damage. The system can read the exact nature of the fault via I2C with the exception of PVDD
undervoltage faults below POR, in which case the I2C bus is no longer operational.
2. STANDBY pin: Assertion of this active-low pin sends the device goes into a complete shutdown, limiting the
current draw.
3. MUTE pin: On assertion of this active-high pin, the device is in mute mode. The output pins stop switching
and audio does not pass from the input to the output. To place the device back into play mode, deassert this
pin.
7.4.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
The design has minimal parasitic inductances due to the short leads on the package, which dramatically reduces
the EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that
optimizes output transitions that cause EMI.
7.4.3 Operating Modes and Faults
The following tables list operating modes and faults.
Table 2. Operating Modes
STATE NAME
OUTPUT
OSCILLATOR
I2C
STANDBY
Hi-Z, floating
Stopped
Stopped
Load diagnostic
DC biased
Active
Active
Fault and mute
Hi-Z, floating
Active
Active
Play
Switching with audio
Active
Active
Table 3. Faults and Actions
FAULT
EVENT
FAULT EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
Voltage fault
All
I2C + FAULT pin
OTSD
Thermal fault
Hi-Z, mute, play
OC fault
Output channel
fault
Play
POR
UV or OV
Not applicable
Load dump (1)
DC detect
ACTION
TYPE
FAULT pin
(1)
CLEARING
Standby
Hard mute (no ramp)
Hi-Z
Self-clearing
I2C + FAULT pin
Load diagnostic short
Load diagnostic open
ACTION
RESULT
Hi-Z, re-run
diagnostics
Diagnostic
Hi-Z
None
I2C
None
Clears on next
diagnostic
cycle
Tested in accordance with ISO7637-1
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7.5 Register Maps
Table 4. I2C Address
FIXED ADDRESS
DESCRIPTION
READ/WRITE BIT
I2C ADDRESS
MSB
6
5
4
3
2
1
LSB
1
1
0
1
1
0
0
0
0xD8
1
1
0
1
1
0
0
1
0xD9
I2C write
2
I C read
7.5.1 I2C Address Register Definitions
Table 5. I2C Address Register Definitions
ADDRESS
R/W
REGISTER DESCRIPTION
0x01
R
Latched fault register
0x02
R
Status and load diagnostics register
0x03
R/W
Control register
Table 6. Fault Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
No protection-created faults, default value
–
–
–
–
–
–
–
1
Reserved
–
–
–
–
–
–
1
–
Reserved
–
–
–
–
–
1
–
–
A load-diagnostics fault has occurred.
–
–
–
–
1
–
–
–
Overcurrent shutdown has occurred.
–
–
–
1
–
–
–
–
PVDD undervoltage has occurred.
–
–
1
–
–
–
–
–
PVDD overvoltage has occurred.
–
1
–
–
–
–
–
–
DC offset protection has occurred.
1
–
–
–
–
–
–
–
Overtemperature shutdown has occurred.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No speaker-diagnostic-created faults, default value
–
–
–
–
–
–
–
1
Output short to PVDD is present.
–
–
–
–
–
–
1
–
Output short to ground is present.
–
–
–
–
–
1
–
–
Open load is present.
–
–
–
–
1
–
–
–
Shorted load is present.
–
–
–
1
–
–
–
–
In a fault condition
–
–
1
–
–
–
–
–
Performing load diagnostics
–
1
–
–
–
–
–
–
In mute mode
1
–
–
–
–
–
–
–
In play mode
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
1
0
0
0
26-dB gain, switching frequency set to 400 kHz , SpeakerGuard
protection circuitry disabled
–
–
–
–
–
–
–
1
Switching frequency set to 500 khz
–
–
–
–
–
1
1
-
Reserved
–
–
1
1
0
–
–
–
SpeakerGuard protection circuitry set to 14-V peak output
–
–
1
0
1
–
–
–
SpeakerGuard protection circuitry set to 11.8-V peak output
–
–
1
0
0
–
–
–
SpeakerGuard protection circuitry set to 9.8-V peak output
–
–
0
1
1
–
–
–
SpeakerGuard protection circuitry set to 8.4-V peak output
Table 7. Status and Load Diagnostic Register (0x02)
FUNCTION
Table 8. Control Register (0x03)
18
FUNCTION
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Table 8. Control Register (0x03) (continued)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
0
1
0
–
–
–
SpeakerGuard protection circuitry set to 7-V peak output
FUNCTION
–
–
0
0
1
–
–
–
SpeakerGuard protection circuitry set to 5.9-V peak output
–
–
0
0
0
–
–
–
SpeakerGuard protection circuitry set to 5-V peak output
0
0
–
–
–
–
–
–
Gain set to 20 dB
1
0
–
–
–
–
–
–
Gain set to 32 dB
1
1
–
–
–
–
–
–
Gain set to 36 dB
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a mono high-efficiency class-D audio amplifier. Typical use of the device is to amplify an audio
input to drive a speaker. The intent of its use is for a bridge-tied load (BTL) application, not for support of singleended configuration. This section presents how to use the device in the application, including what external
components are necessary and how to connect unused pins.
8.2 Typical Application
PVDD
2.2nF 82nF 4.7µF 4.7µF 10µH
330µF 10µF 0.1µF
+
PVDD
FAULT
FAULT
SDA
0.22µF
SDA
22µH
OUTP
BSPP
3.3µF
SCL
0.01µF
SCL
OUTP
IN_P
1µF
5.6
IN_P
470pF
49.9k
IN_N
TAS5421-Q1
49.9k
5.6
470pF
0.22µF
22µH
IN_N
1µF
OUTN
MUTE
MUTE
OUTN
BSPN
3.3µF
0.01µF
BYP
GND
GND
STANDBY
GND
STANDBY
1.0µF
Figure 17. TAS5421-Q1 Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Use the following for the design requirements:
• Power supplies
The device requires only a single power supply compliant with the recommended operation range. The device
is designed to work with either a vehicle battery or regulated power supply such as from a backup battery.
• Communication
The device communicates with the system controller with both discrete hardware control pins and with I2C.
The device is an I2C slave and thus requires a master. If a master I2C-compliant device is not present in the
system, the device can still be used, but only with the default settings. Diagnostic information is limited to the
discrete reporting FAULT pin.
• External components
Table 9 lists the components required for the device.
Table 9. Supporting Components
EVM DESIGNATOR
QUANITY
VALUE
SIZE
DESCRIPTION
USE IN APPLICATION
C7
1
10 μF ± 10%
1206
X7R ceramic capacitor, 25-V
Power supply
C8
1
330 μF ± 20%
10 mm
Low-ESR aluminum capacitor, 25-V
Power supply
C9, C16, C20
3
1 μF ± 10%
0805
X7R ceramic capacitor, 25-V
Analog audio input filter, bypass
C10, C14
2
0.22 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Bootstrap capacitors
C11, C17
2
3.3 μF ± 10%
0805
X7R ceramic capacitor, 25-V
Amplifier output filtering
C13, C15
2
470 pF ± 10%
0603
X7R ceramic capacitor, 250-V
Amplifier output snubbers
C6
1
0.1 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Power supply
C2
1
2200 pF ± 10%
0603
X7R ceramic capacitor, 50-V
Power supply
C3
1
0.082 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Power supply
C4, C5
2
4.7 μF ± 10%
1206
X7R ceramic capacitor, 25-V
Power supply
C12, C18
2
0.01 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Output EMI filtering
L1
1
10 μH ± 20%
13.5 mm ×13.5
mm
Shielded ferrite inductor
Power supply
L2
1
22 μH ± 20%
8 mm × 8 mm
Coupled inductor
Amplifier output filtering
R5, R6
2
49.9 kΩ ± 1%
0805
Resistors, 0.125-W
Analog audio input filter
R4, R7
2
5.6 Ω ± 5%
0805
Resistors, 0.125-W
Output snubbers
8.2.1.1 Amplifier Output Filtering
Output FETs drive the amplifier outputs in an H-bridge configuration. These transistors are either fully off or on.
The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio
signal. The amplifier outputs require a low-pass filter to filter out the PWM modulation carrier frequency. People
frequently call this filter the L-C filter, due to the presence of an inductive element L and a capacitive element C
to make up the 2-pole low-pass filter. The L-C filter attenuates the carrier frequency, reducing electromagnetic
emissions and smoothing the current waveform which the load draws from the power supply. See Class-D LC
Filter Design for a detailed description on proper component selection and design of an L-C filter based upon the
desired load and response.
8.2.1.2 Amplifier Output Snubbers
A snubber is an RC network placed at the output of the amplifier to dampen ringing or overshoot on the PWM
output waveform. Overshoot and ringing has several negative impacts including: potential EMI sources,
degraded audio performance, and overvoltage stress of the output FETs or board components. For more
information on the use and design of output snubbers, see Class-D Output Snubber Design Guide.
8.2.1.3 Bootstrap Capacitors
The output stage uses dual NMOS transistors; therefore, the circuit requires bootstrap capacitors for the high
side of each output to turn on correctly. The required capacitor connection is from BSTN to OUTN and from
BSTP to OUTP as shown in Figure 17.
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8.2.1.4 Analog Audio Input Filter
The circuit requires an input capacitor to allow biasing of the amplifier put to the proper dc level. The input
capacitor and the input impedance of the amplifier form a high-pass filter with a –3-dB corner frequency
determined by the equation: f = 1 / (2πR(i)C(i)), where R(i) is the input impedance of the device based on the gain
setting and C(i) is the input capacitor value. Table 10 lists largest recommended input capacitor values. Use a
capacitor which matches the application requirement for the lowest frequency but does not exceed the values
listed.
Table 10. Recommended Input AC-Coupling Capacitors
GAIN (dB)
TYPICAL INPUT IMPEDANCE
(kΩ)
20
60
26
30
INPUT CAPACITANCE (µF)
HIGH-PASS FILTER (Hz)
1
2.7
1.5
1.8
1
5.3
3.3
1.6
32
15
5.6
2.3
36
9
10
1.8
8.2.2 Detailed Design Procedure
Use the following steps for the design procedure:
• Step 1: Hardware Schematic Design: Using the Figure 17 as a guide, integrate the hardware into the system
schematic.
• Step 2: Following the layout guidelines recommended in the Layout Guidelines section, integrate the device
and its supporting components into the system PCB file.
• Step 3: Thermal Design: The device has an exposed thermal pad which requires proper soldering. For more
information, see Semiconductor and IC Package Thermal Metrics and PowerPAD Thermally Enhanced
Package.
• Step 4: Develop software: The EVM User's Guide has detailed instructions for how to set up the device,
interpret diagnostic information, and so forth. For information about control registers, see the Register Maps
section.
• For questions and support, go to the E2E forums.
8.2.2.1 Unused Pin Connections
Even if unused, always connect pins to a fixed rail; do not leave them floating. Floating input pins represent an
ESD risk, therefore the user must adhere to the following guidance for each pin.
8.2.2.1.1 MUTE Pin
If the MUTE pin is unused in the application, connect it to GND through a high-impedance resistor.
8.2.2.1.2 STANDBY Pin
If the STANDBY pin is unused in the application, connect it to a low-voltage rail such as 3.3 V or 5 V through a
high-impedance resistor.
8.2.2.1.3 I2C Pins (SDA and SCL)
If there is no microcontroller in the system, use of the device without I2C communication is possible. In this
situation, connect the SDA and SCL pins to 3.3 V.
8.2.2.1.4 Terminating Unused Outputs
If the FAULT pin does not report to a system microcontroller in the application, connect it to GND.
22
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8.2.2.1.5 Using a Single-Ended Audio Input
When using a single-ended audio source, ac-ground the negative input through a capacitor equal in value to the
input capacitor on the positive input, and apply the audio source to the positive input. For best performance, the
ac ground should be at the audio source instead of at the device input if possible.
8.2.3 Application Curves
See the Typical Characteristics section for application performance plots.
Table 11. Table of Graphs
GRAPH
FIGURE NO.
Efficiency vs Output Power
Figure 3
THD+N vs Output Power
Figure 4
Output Power vs PVDD
Figure 5
THD+N vs Frequency
Figure 6
Noise FFT With –60-dB Output
Figure 7
Noise FFT With 1-W Output
Figure 8
Overcurrent Threshold vs Temperature
Figure 9
9 Power Supply Recommendations
A car battery that can have a large voltage range most commonly provides power for the device. PVDD, a filtered
battery voltage, is the supply for the output FETs and the low-side FET gate driver. Good power-supply
decoupling is necessary, especially at low voltage and temperature levels. To meet the PVDD specifications in
the Electrical Characteristics section, TI uses 10-µF and 0.1-µF ceramic capacitors near the PVDD pin along with
a larger bulk 330-µF electrolytic decoupling capacitor.
An internal linear regulator, which powers the analog circuitry, provides the voltage on the BYP pin. This supply
requires an external bypass ceramic capacitor at the BYP pin.
10 Layout
10.1 Layout Guidelines
The EVM layout optimizes for thermal dissipation and EMC performance. The TAS5421-Q1 device has a thermal
pad down, and good thermal conduction and dissipation require adequate copper area. Layout also affects EMC
performance. TAS5421Q1EVM illustrations form the basis for the layout discussions.
10.2 Layout Examples
10.2.1 Top Layer
The red boxes around number 1 are the copper ground on the top layer. Soldered directly to the thermal pad, the
ground is the first significant thermal dissipation required. There are vias that go to the other layers for further
thermal relief, but vias have high thermal resistance. TI recommends that use of the top layer be mostly for
thermal dissipation. A further recommendation is short routes from output pins to the second-order LC filter for
EMC suppression. The number 2 arrow indicates these short routes. The shorter the distance, the less EMC
radiates. A short route from the PVDD pin to the LC filter from the battery or power source, as indicated by the
number 3 arrow, also improves EMC suppression. The red box around number 4 indicates the ground plane that
is common to both OUTP and OUTN. Place the capacitors of the LC filter in the common ground plane to help
with common-mode noise and short ground loops.
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Layout Examples (continued)
Figure 18. Top Layer
10.2.2 Second Layer – Signal Layer
If possible, route the I2C and the positive and negative input traces close together and cover with ground plane,
keeping the signals from noise.
Figure 19. Signal Layer
24
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Layout Examples (continued)
10.2.3 Third Layer – Power Layer
There is no requirement for a power plane, but TI recommends a wide single PVDD trace to keep the switching
noise to a minimum and provide enough current to the device. The wide trace provides a low-impedance path
from the power source to the PVDD pin and from the GND pin to the source return. Suppression of switching
noise (ripple voltage) on both the positive and return (ground) paths requires a low impedance.
Figure 20. Power Layer
10.2.4 Bottom Layer – Ground Layer
The device has an exposed thermal pad on the bottom side for improved thermal performance. Conducting heat
from the thermal pad to other layers requires thermal vias. Because the bottom layer is the secondary heat
exchange surface to ambient, the thermal vias area must have low thermal resistance, that is, no signal vias or
traces that can increase thermal resistance from the thermal vias to the bottom copper.
Figure 21. Bottom Layer
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SLOS814D – MARCH 2014 – REVISED SEPTEMBER 2016
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• AN-1737 Managing EMI in Class D Audio Applications (SNAA050)
• AN-1849 An Audio Amplifier Power Supply Design (SNAA057)
• Class-D LC Filter Design (SLOA119)
• Class-D Output Snubber Design Guide (SLOA201)
• Filter-Free™ Class-D Audio Amplifiers (SLOA145)
• Guidelines for Measuring Audio Power Amplifier Performance (SLOA068)
• Power Rating in Audio Amplifiers (SLEA047)
• PowerPAD Thermally Enhanced Package (SLMA002)
• TAS5421EVM User's Guide (SLOU365)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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27
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
TAS5421QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TAS5421
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5421QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
16
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5421QPWPRQ1
HTSSOP
PWP
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016B
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
16
1
0.1 C
14X 0.65
2X
4.55
5.1
4.9
NOTE 3
8
4.5
4.3
B
9
16X
0.30
0.19
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X 0.15 MAX
NOTE 5
2X 0.95 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.0
2.4
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
(1)
3.0
2.4
DETAIL A
TYPICAL
4218971/A 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
SYMM
(3)
(5)
NOTE 9
14X (0.65)
8
9
( 0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218971/A 01/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3)
BASED ON
0.125 THICK
STENCIL
SYMM
14X (0.65)
9
8
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.35 X 3.35
3 X 3 (SHOWN)
2.74 X 2.74
2.54 X 2.54
4218971/A 01/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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