Texas Instruments | Ultra Low Power Stereo Audio Codec With Embedded miniDSP . (Rev. A) | Datasheet | Texas Instruments Ultra Low Power Stereo Audio Codec With Embedded miniDSP . (Rev. A) Datasheet

Texas Instruments Ultra Low Power Stereo Audio Codec With Embedded miniDSP . (Rev. A) Datasheet
TLV320AIC3254-Q1
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SLAS894A – MAY 2013 – REVISED AUGUST 2013
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
Check for Samples: TLV320AIC3254-Q1
FEATURES
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Qualified for Automotive Applications
AEC-Q100 Qualified with the Following
Results:
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Programmable PLL
Integrated LDO
5 mm x 5 mm 32-pin QFN Package
APPLICATIONS
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Stereo Audio DAC with 100dB SNR
4.1mW Stereo 48ksps DAC Playback
Stereo Audio ADC with 93dB SNR
6.1mW Stereo 48ksps ADC Record
PowerTune™
Extensive Signal Processing Options
Embedded miniDSP
Six Single-Ended or Three Fully-Differential
Analog Inputs
Stereo Analog and Digital Microphone Inputs
Stereo Headphone Outputs
Stereo Line Outputs
Very Low-Noise PGA
Low Power Analog Bypass Mode
Programmable Microphone Bias
Automotive
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing
Acoustic Echo Cancellation (AEC)
Active Noise Cancellation (ANC)
Advanced DSP algorithms
DESCRIPTION
The TLV320AIC3254-Q1 (also called the AIC3254Q1) is a flexible, low-power, low-voltage stereo audio
codec with programmable inputs and outputs,
PowerTune capabilities, fully-programmable miniDSP,
fixed predefined and parameterizable signal
processing blocks, integrated PLL, integrated LDOs
and flexible digital interfaces.
IN1_L
IN2_L
IN3_L
0…+47.5 dB
+
Left
ADC
tpl
+
´
AGC
DRC
ADC
Signal
Proc.
DAC
Signal
Proc.
Vol . Ctrl
-72...0dB
´
-6...+29dB
HPL
+
Left
DAC
1dB steps
Gain Adj.
0.5 dB
steps
-6...+29dB
-30...0 dB
LOL
+
Data
Interface
miniDSP
1dB steps
miniDSP
-6...+29dB
-30...0 dB
LOR
+
1dB steps
0…
+47.5 dB
+
Gain Adj.
Right
ADC
IN3_R
+
tpr
´
0.5 dB steps
IN2_R
ADC
Signal
Proc.
DAC
Signal
Proc.
AGC
DRC
-6...+29dB
Right
DAC
´
Vol . Ctrl
HPR
+
1dB steps
-72...0dB
IN1_R
SPI_Select
SPI / I2C
Control Block
Reset
Digital Interrupt Secondary
Mic.
Ctrl
I2S IF
PLL
Primary
I2S Interface
HPVdd
MicBias
Mic
Bias
ALDO
Ref
Ref
DLDO
Supplies
Pin Muxing/ Clock Routing
BCLK
WCLK
DIN
DOUT
GPIO
MCLK
SCLK
MISO
SDA/MOSI
SCL/SSZ
IOVss
DVss
AVss
IOVdd
DVdd
AVdd
LDO Select
LDO in
Figure 1. Simplified Block Diagram
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerTune is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The TLV320AIC3254-Q1 features two fully-programmable miniDSP cores that support application-specific
algorithms in the record and-or the playback path of the device. The miniDSP cores are fully software controlled.
Target algorithms, like active noise cancellation, acoustic echo cancellation or advanced DSP filtering are loaded
into the device after power-up.
Extensive register-based control of power, IO channel configuration, gains, effects, pin-multiplexing and clocks
allows the device to be precisely targeted to its application. Combined with the advanced PowerTune technology,
the device can cover operations from 8kHz mono voice playback to audio stereo 192kHz DAC playback, making
it ideal for portable battery-powered audio and telephony applications.
The record path of the TLV320AIC3254-Q1 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations covering single-ended and differential setups, as well as
floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by
mechanical coupling, such as optical zooming in a digital camera.
The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC
and analog input signals as well as programmable volume controls. The playback path contains two high-power
output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways,
including stereo and mono BTL.
The integrated PowerTune technology allows the device to be tuned to an optimum power-performance trade-off.
Mobile applications frequently have multiple use cases requiring very low power operation while being used in a
mobile environment. When used in a docked environment power consumption typically is less of a concern, while
minimizing noise is important. With PowerTune, the TLV320AIC3254-Q1 addresses both cases.
The voltage supply range for the TLV320AIC3254-Q1 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V.
To ease system-level design, LDOs are integrated to generate the appropriate analog or digital supply from input
voltages ranging from 1.8V to 3.6V. Digital IO voltages are supported in the range of 1.1V–3.6V.
The required internal clock of the TLV320AIC3254-Q1 can be derived from multiple sources, including the MCLK
pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be
derived from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable
clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can
accept available input clocks in the range of 512kHz to 50MHz.
The device is available in the 5-mm × 5-mm, 32-pin QFN package.
2
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Package and Signal Descriptions
Packaging and Ordering Information
For the most-current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Pin Assignments
IOVSS
8
1
GPIO/MFP5
SCLK/MFP3
IOVDD
DOUT/MFP2
DIN/MFP1
BCLK
WCLK
MCLK
This document describes signals that take on different names depending on how they are configured. In such
cases, the different names are placed together and separated by slash (/) characters. For example, "SCL/SS".
Active low signals are represented by overbars.
32
9
RESET
SCL/SS
SDA/MOSI
LDO_SELECT
MISO/MFP4
DVDD
SPI_SELECT
DVSS
IN1_L
HPR
IN1_R
LDOIN
IN2_L
25
16
IN2_R
MICBIAS
IN3_L
LOL
IN3_R
17
LOR
AVDD
24
REF
AVSS
HPL
Figure 2. QFN (RHB) Package, Bottom View
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Table 1. Terminal Functions
TERMINAL
NAME
TYPE
1
MCLK
I
DESCRIPTION
2
BCLK
IO
Audio serial data bus (primary) bit clock
3
WCLK
IO
Audio serial data bus (primary) word clock
4
DIN
I
Master Clock Input
Primary function:
Audio serial data bus data input
MFP1
Secondary function:
Digital Microphone Input
General Purpose Clock Input
General Purpose Input
5
DOUT
O
Primary function:
Audio serial data bus data output
MFP2
Secondary function:
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
6
IOVDD
Power
IO voltage supply 1.1V – 3.6V
7
IOVSS
Ground
IO ground supply
8
SCLK
I
/
Primary function: (SPI_Select = 1)
SPI serial clock
MFP3
Secondary function: (SPI_Select = 0)
Headphone-detect input
Digital microphone input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC or common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
9
SCL/SS
I
I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
10
SDA/MOSI
I
I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
11
MISO
O
Primary function: (SPI_Select = 1)
/
Serial data output
MFP4
Secondary function: (SPI_Select = 0)
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Digital microphone clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
12
4
SPI_ SELECT
I
Control mode select pin ( 1 = SPI, 0 = I2C )
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Table 1. Terminal Functions (continued)
TERMINAL
NAME
TYPE
13
IN1_L
I
DESCRIPTION
Multifunction Analog Input,
or Single-ended configuration: MIC 1 or Line 1 left
or Differential configuration: MIC or Line right, negative
14
IN1_R
I
Multifunction Analog Input,
or Single-ended configuration: MIC 1 or Line 1 right
or Differential configuration: MIC or Line right, positive
15
IN2_L
I
Multifunction Analog Input,
or Single-ended configuration: MIC 2 or Line 2 right
or Differential configuration: MIC or Line left, positive
16
IN2_R
I
Multifunction Analog Input,
or Single-ended configuration: MIC 2 or Line 2 right
or Differential configuration: MIC or Line left, negative
17
AVSS
Ground
18
REF
O
Reference voltage output for filtering
19
MICBIAS
O
Microphone bias voltage output
20
IN3_L
I
Multifunction Analog Input,
or Single-ended configuration: MIC3 or Line 3 left,
or Differential configuration: MIC or Line left, positive,
or Differential configuration: MIC or Line right, negative
21
IN3_R
I
Multifunction Analog Input,
or Single-ended configuration: MIC3 or Line 3 right,
or Differential configuration: MIC or Line left, negative,
or Differential configuration: MIC or Line right, positive
22
LOL
O
Left line output
23
LOR
O
Right line output
24
AVDD
Power
Analog ground supply
Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
25
HPL
O
26
LDOIN/HPVDD
Power
Left high power output driver
27
HPR
O
28
DVSS
Ground
Digital Ground and Chip-substrate
29
DVDD
Power
If LDO_SELECT Pin = 0 (D-LDO disabled)
LDO Input supply and Headphone Power supply 1.9V– 3.6V
Right high power output driver
Digital voltage supply 1.26V – 1.95V
If LDO_SELECT Pin = 1 (D-LDO enabled)
Digital voltage supply filtering output
30
LDO_ SELECT
I
connect to DVss.
31
RESET
I
Reset (active low)
32
GPIO
I
Primary function:
General Purpose digital IO
MFP5
Secondary function:
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
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Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
AVDD to AVSS
–0.3 to 2.2
V
DVDD to DVSS
–0.3 to 2.2
V
IOVDD to IOVSS
–0.3 to 3.9
V
LDOIN to AVSS
–0.3 to 3.9
V
Digital Input voltage to ground
–0.3 to IOVDD + 0.3
V
Analog input voltage to ground
–0.3 to AVDD + 0.3
V
Operating temperature range
–40 to 85
°C
Storage temperature range
–55 to 125
°C
Junction temperature (TJ Max)
Electrostatic discharge
(ESD) ratings
(1)
105
°C
2
kV
750
V
Human-body model (HBM) AEC-Q100 Classification Level H2
Charged-device model (CDM) AEC-Q100 Classification Level C4B
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM
LDOIN
Power Supply Voltage Range
Referenced to AVSS (1)
1.9
AVDD
1.5
IOVDD
DVDD
(2)
PLL Input Frequency
MCLK
Master Clock Frequency
SCL
SCL Clock Frequency
LOL,
LOR
Stereo line output load resistance
HPL,
HPR
Stereo headphone output load
resistance
Headphone output load resistance
CLout
Digital output load capacitance
TOPR
Operating Temperature Range
(1)
(2)
6
Referenced to IOVSS (1)
1.1
Referenced to DVSS (1)
1.26
MAX
3.6
1.8
1.95
1.8
1.95
UNIT
V
3.6
Clock divider uses fractional divide
(D > 0), P = 1, DVDD ≥ 1.65V (See table in SLAU497,
Maximum TLV320AIC3254-Q1 Clock Frequencies)
10
20
MHz
Clock divider uses integer divide
(D = 0), P = 1, DVDD ≥ 1.65V (See table in SLAU497,
Maximum TLV320AIC3254-Q1 Clock Frequencies)
0.512
20
MHz
MCLK; Master Clock Frequency; DVDD ≥ 1.65V
50
MHz
MCLK; Master Clock Frequency; DVDD ≥ 1.26V
25
400
kHz
0.6
10
kΩ
Single-ended configuration
14.4
16
Ω
Differential configuration
24.4
32
Ω
10
pF
–40
85
°C
All grounds on board are tied together to prevent voltage differences of more than 0.2V maximum for any combination of ground signals.
At DVDD values lower than 1.65V, the PLL does not function. Please see the Maximum TLV320AIC3254-Q1 Clock Frequencies table in
the TLV320AIC3254-Q1 Application Reference Guide (SLAU497) for details on maximum clock frequencies.
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THERMAL INFORMATION
THERMAL METRIC (1)
TLV320AIC3254-Q1
RHB (32 PINS)
θJA
Junction-to-ambient thermal resistance
31.4
θJCtop
Junction-to-case (top) thermal resistance
21.4
θJB
Junction-to-board thermal resistance
5.4
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
5.4
θJCbot
Junction-to-case (bottom) thermal resistance
0.9
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Electrical Characteristics, ADC
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
AUDIO ADC
TEST CONDITIONS
MIN
Input signal level (0dB)
Single-ended, CM = 0.9V
Device Setup
1kHz sine wave input
Single-ended Configuration
IN1R to Right ADC and IN1L to Left ADC,
Rin = 20K, fs = 48kHz,
AOSR = 128, MCLK = 256 * fs,
PLL Disabled; AGC = OFF,
Channel Gain = 0dB,
Processing Block = PRB_R1,
Power Tune = PTM_R4
MAX
0.5
Inputs ac-shorted to ground
SNR
TYP
UNIT
(1) (2)
IN2R, IN3R routed to Right ADC and ac-shorted to
ground
IN2L, IN3L routed to Left ADC and ac-shorted to
ground
Signal-to-noise ratio, Aweighted (1) (2)
(1) (2)
DR
Dynamic range A-weighted
THD+N
Total Harmonic Distortion plus
Noise
80
VRMS
93
93
–40°C
76
85°C
68
dB
–60dB full-scale, 1-kHz input signal
92
–3 dB full-scale, 1-kHz input signal
–85
IN2R,IN3R routed to Right ADC
IN2L, IN3L routed to Left ADC
–3dB full-scale, 1-kHz input signal
–85
85°C
dB
–70
dB
–68
AUDIO ADC
Input signal level (0dB)
Single-ended, CM = 0.75V, AVDD = 1.5V
Device Setup
1kHz sine wave input
Single-ended Configuration
IN1R, IN2R, IN3R routed to Right ADC
IN1L, IN2L, IN3L routed to Left ADC
Rin = 20kΩ, fs = 48kHz,
AOSR = 128, MCLK = 256* fs,
PLL Disabled, AGC = OFF,
Channel Gain = 0dB,
Processing Block = PRB_R1
Power Tune = PTM_R4
SNR
Signal-to-noise ratio, A-weighted
Inputs ac-shorted to ground
DR
Dynamic range A-weighted (1) (2)
THD+N
Total Harmonic Distortion plus
Noise
(1)
(2)
8
(1) (2)
0.375
VRMS
91
dB
–60dB full-scale, 1-kHz input signal
90
dB
–3dB full-scale, 1-kHz input signal
–80
dB
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher
THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-ofband noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, ADC (continued)
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC
ICN
Input signal level (0dB)
Differential Input, CM = 0.9V
Device Setup
1kHz sine wave input
Differential configuration
IN1L and IN1R routed to Right ADC
IN2L and IN2R routed to Left ADC
Rin = 10K, fs = 48kHz, AOSR = 128
MCLK = 256* fs PLL Disabled
AGC = OFF, Channel Gain = 40dB Processing Block =
PRB_R1,
Power Tune = PTM_R4
Idle-Channel Noise, Aweighted (3) (4)
Inputs ac-shorted to ground, input referred noise
10
mV
2
μVRMS
AUDIO ADC
Gain Error
1kHz sine wave input
Single-ended configuration
Rin = 20kΩ fs = 48kHz, AOSR = 128,
MCLK = 256 * fs, PLL Disabled
AGC = OFF, Channel Gain = 0dB
Processing Block = PRB_R1,
Power Tune = PTM_R4, CM = 0.9V
–0.05
dB
108
dB
Input Channel Separation
1kHz sine wave input at -3dBFS
Single-ended configuration
IN1L routed to Left ADC
IN1R routed to Right ADC, Rin = 20kΩ
AGC = OFF, AOSR = 128,
Channel Gain = 0dB, CM = 0.9V
1kHz sine wave input at –3dBFS on IN2L, IN2L internally
not routed.
IN1L routed to Left ADC
ac-coupled to ground
115
dB
Input Pin Crosstalk
55
dB
1kHz sine wave input at –3dBFS on IN2R,
IN2R internally not routed.
IN1R routed to Right ADC
ac-coupled to ground
Single-ended configuration Rin = 20kΩ,
AOSR = 128 Channel, Gain = 0dB, CM = 0.9V
PSRR
217Hz, 100mVpp signal on AVDD,
Single-ended configuration, Rin = 20kΩ,
Channel Gain = 0dB; CM = 0.9V
Single-Ended, Rin = 10kΩ, PGA gain set to 0dB
0
dB
47.5
dB
–6
dB
Single-Ended, Rin = 20kΩ, PGA gain set to 47.5dB
41.5
dB
Single-Ended, Rin = 40kΩ, PGA gain set to 0dB
–12
dB
Single-Ended, Rin = 40kΩ, PGA gain set to 47.5dB
35.5
dB
0.5
dB
Single-Ended, Rin = 10kΩ, PGA gain set to 47.5dB
ADC programmable gain
amplifier gain
ADC programmable gain
amplifier step size
(3)
(4)
Single-Ended, Rin = 20kΩ, PGA gain set to 0dB
1-kHz tone
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher
THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-ofband noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Bypass Outputs
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Device Setup
Load = 16Ω (single-ended), 50pF;
Input and Output CM = 0.9V;
Headphone Output on LDOIN Supply;
IN1L routed to HPL and IN1R routed to HPR;
Channel Gain = 0dB
Gain Error
THD
–0.8
Noise, A-weighted (1)
Idle Channel, IN1L and IN1R ac-shorted to
ground
Total Harmonic Distortion
446mVrms, 1kHz input signal
3
–89
dB
μVRMS
dB
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Device Setup
Load = 10kΩ (single-ended), 56pF;
Input and Output CM = 0.9V;
LINE Output on LDOIN Supply;
IN1L routed to ADCPGA_L and IN1R routed
to ADCPGA_R; Rin = 20kΩ
ADCPGA_L routed to LOL and ADCPGA_R
routed to LOR; Channel Gain = 0dB
Gain Error
0.6
Idle Channel,
IN1L and IN1R ac-shorted to ground
Noise, A-weighted (1)
(1)
10
Channel Gain = 40dB,
Input Signal (0dB) = 5mVrms
Inputs ac-shorted to ground, Input Referred
dB
7
μVRMS
3.4
μVRMS
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in
higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Microphone Interface
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
Bias voltage
Bias voltage CM = 0.9V, LDOIN = 3.3V
Micbias Mode 0, Connect to AVDD or LDOIN
1.25
V
Micbias Mode 1, Connect to LDOIN
1.7
V
Micbias Mode 2, Connect to LDOIN
2.5
V
Micbias Mode 3, Connect to AVDD
AVDD
V
LDOIN
V
Micbias Mode 0, Connect to AVDD or LDOIN
1.04
V
Micbias Mode 1, Connect to AVDD or LDOIN
1.425
V
Micbias Mode 2, Connect to LDOIN
2.075
V
AVDD
V
LDOIN
V
Micbias Mode 3, Connect to LDOIN
CM = 0.75V, LDOIN = 3.3V
Micbias Mode 3, Connect to AVDD
Micbias Mode 3, Connect to LDOIN
Output Noise
Current Sourcing
Inline Resistance
CM = 0.9V, Micbias Mode 2, A-weighted,
20Hz to 20kHz bandwidth,
Current load = 0mA.
Micbias Mode 2, Connect to LDOIN
Micbias Mode 3, Connect to AVDD
Micbias Mode 3, Connect to LDOIN
10
μVRMS
3
140
87
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Electrical Characteristics, Audio DAC Outputs
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
VRMS
87
100
dB
100
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Device Setup
Load = 10kΩ (single-ended), 56pF
Line Output on AVDD Supply
Input and Output CM = 0.9V
DOSR = 128, MCLK = 256 * fs,
Channel Gain = 0dB, word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio A-weighted (1) (2)
All zeros fed to DAC input
–40°C
84
85°C
78
DR
Dynamic range, A-weighted (1) (2)
–60dB 1kHz input full-scale signal, Word
length = 20 bits
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1kHz input signal
DAC Gain Error
0 dB, 1kHz input full scale signal
0.3
dB
DAC Mute Attenuation
Mute
119
dB
DAC channel separation
–1 dB, 1kHz signal, between left and right
HP out
113
dB
100mVpp, 1kHz signal applied to AVDD
73
dB
100mVpp, 217Hz signal applied to AVDD
77
dB
DAC PSRR
–83
85°C
–68
–70
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Device Setup
Load = 10kΩ (single-ended), 56pF
Line Output on AVDD Supply
Input and Output CM = 0.75V; AVDD = 1.5V
DOSR = 128
MCLK = 256 * fs
Channel Gain = –2dB
word length = 20 bits
Processing Block = PRB_P1
Power Tune = PTM_P4
Full scale output voltage (0dB)
0.375
VRMS
SNR
Signal-to-noise ratio, A-weighted (1) (2)
All zeros fed to DAC input
99
dB
DR
Dynamic range, A-weighted (1) (2)
–60dB 1 kHz input full-scale signal
97
dB
THD+N
Total Harmonic Distortion plus Noise
–1 dB full-scale, 1-kHz input signal
–85
dB
0.5
VRMS
100
dB
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT
Device Setup
Load = 16Ω (single-ended), 50pF
Headphone Output on AVDD Supply,
Input and Output CM = 0.9V, DOSR = 128,
MCLK = 256 * fs, Channel Gain = 0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Full scale output voltage (0dB)
SNR
(1)
(2)
12
Signal-to-noise ratio A-weighted (1) (2)
All zeros fed to DAC input
87
–40°C
84
85°C
78
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in
higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Audio DAC Outputs (continued)
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DR
Dynamic range, A-weighted (1) (2)
–60dB 1kHz input full-scale signal, Word
Length = 20 bits, Power Tune = PTM_P4
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1kHz input signal
DAC Gain Error
0dB, 1kHz input full scale signal
–0.3
dB
DAC Mute Attenuation
Mute
122
dB
DAC channel separation
–1dB, 1kHz signal, between left and right HP
out
110
dB
100mVpp, 1kHz signal applied to AVDD
73
dB
100mVpp, 217Hz signal applied to AVDD
78
dB
RL = 16Ω, Output Stage on AVDD = 1.8V
THDN < 1%, Input CM = 0.9V,
Output CM = 0.9V
15
RL = 16Ω Output Stage on LDOIN = 3.3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.65V
64
DAC PSRR
Power Delivered
99
–83
85°C
dB
–70
dB
–68
mW
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT
Device Setup
Load = 16Ω (single-ended), 50pF,
Headphone Output on AVDD Supply,
Input and Output CM = 0.75V; AVDD = 1.5V,
DOSR = 128, MCLK = 256 * fs,
Channel Gain = –2dB, word length = 20-bits;
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB)
0.375
VRMS
SNR
Signal-to-noise ratio, A-weighted (3) (4)
All zeros fed to DAC input
99
dB
DR
Dynamic range, A-weighted (3) (4)
-60dB 1kHz input full-scale signal
98
dB
THD+N
Total Harmonic Distortion plus Noise
–1dB full-scale, 1kHz input signal
–83
dB
1778
mVRMS
AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT
Device Setup
Load = 32Ω (differential), 50pF,
Headphone Output on LDOIN Supply
Input CM = 0.75V, Output CM = 1.5V,
AVDD = 1.8V, LDOIN = 3.0V, DOSR = 128
MCLK = 256 * fs, Channel (headphone
driver) Gain = 5dB for full scale output signal,
word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio, A-weighted (3) (4)
All zeros fed to DAC input
98
dB
DR
Dynamic range, A-weighted (3) (4)
–60dB 1kHz input full-scale signal
96
dB
THD
Total Harmonic Distortion
–3dB full-scale, 1kHz input signal
–82
dB
RL = 32Ω, Output Stage on LDOIN = 3.3V,
THDN < 1%, Input CM = 0.9V,
Output CM = 1.65V
136
mW
RL = 32Ω Output Stage on LDOIN = 3.0V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.5V
114
mW
Power Delivered
(3)
(4)
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in
higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW DROPOUT REGULATOR (AVdd)
Output Voltage
LDOMode = 1, LDOIN > 1.95V
1.67
LDOMode = 0, LDOIN > 2.0V
1.72
LDOMode = 2, LDOIN > 2.05V
1.77
Output Voltage Accuracy
V
±2
%
15
mV
5
mV
60
μA
LDOMode = 1, LDOIN > 1.95V
1.67
V
LDOMode = 0, LDOIN > 2.0V
1.72
LDOMode = 2, LDOIN > 2.05V
1.77
Load Regulation
Load current range 0 to 50mA
Line Regulation
Input Supply Range 1.9V to 3.6V
Decoupling Capacitor
μF
1
Bias Current
LOW DROPOUT REGULATOR (DVdd)
Output Voltage
Output Voltage Accuracy
Load Regulation
Load current range 0 to 50mA
Line Regulation
Input Supply Range 1.9V to 3.6V
Decoupling Capacitor
%
15
mV
5
mV
μF
1
Bias Current
14
±2
60
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μA
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Electrical Characteristics, Misc.
At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10μF on REF pin, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Reference Voltage Settings
Reference Noise
CMMode = 0 (0.9V)
0.9
CMMode = 1 (0.75V)
0.75
CM = 0.9V, A-weighted, 20Hz to 20kHz bandwidth,
Cref = 10μF
Decoupling Capacitor
1
V
1
μVRfcMS
10
μF
miniDSP (1)
Maximum miniDSP clock frequency - ADC
DVDD = 1.65V
55.3
MHz
Maximum miniDSP clock frequency - DAC
DVDD = 1.65V
55.3
MHz
I(DVDD)
0.9
μA
I(AVDD)
<0.9
μA
I(LDOIN)
<0.9
μA
I(IOVDD)
13
nA
Shutdown Current
Device Setup
(1)
Coarse AVDD supply turned off, LDO_select held at
ground, No external digital input is toggled
miniDSP clock speed is specified by design and not tested in production.
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Electrical Characteristics, Logic Levels
At 25°C, AVDD, DVDD, IOVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
LOGIC FAMILY
VIH
Logic Level
VIL
TYP
UNIT
CMOS
IIH = 5 μA, IOVDD > 1.6V
0.7 × IOVDD
V
IIH = 5μA, 1.2V ≤ IOVDD < 1.6V
0.9 × IOVDD
V
IIH = 5μA, IOVDD < 1.2V
IOVDD
V
IIL = 5 μA, IOVDD > 1.6V
–0.3
IIL = 5μA, 1.2V ≤ IOVDD < 1.6V
IIL = 5μA, IOVDD < 1.2V
VOH
IOH = 2 TTL loads
VOL
IOL = 2 TTL loads
0.3 × IOVDD
V
0.1 × IOVDD
V
0
V
0.8 × IOVDD
Capacitive Load
16
MAX
V
0.1 × IOVDD
10
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V
pF
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SLAS894A – MAY 2013 – REVISED AUGUST 2013
Interface Timing
Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
All specifications at 25°C, DVdd = 1.8V
WCLK
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
DOUT
th(DI)
tS(DI)
DIN
Figure 3. I2S LJF and RJF Timing in Master Mode
Table 2. I2S LJF and RJF Timing in Master Mode (see Figure 3)
PARAMETER
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNITS
MAX
td(WS)
WCLK delay
30
20
ns
td(DO-WS)
WCLK to DOUT delay (For LJF Mode only)
20
20
ns
td(DO-BCLK)
BCLK to DOUT delay
22
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
24
12
ns
tf
Fall time
24
12
ns
ns
ns
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WCLK
th(WS)
tL(BCLK)
BCLK
tH(BCLK)
ts(WS)
td(DO-WS)
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 4. I2S LJF and RJF Timing in Slave Mode
Table 3. I2S LJF and RJF Timing in Slave Mode (see Figure 4)
PARAMETER
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNITS
MAX
tH(BCLK)
BCLK high period
35
35
tL(BCLK)
BCLK low period
35
35
ts(WS)
WCLK setup
8
8
th(WS)
WCLK hold
8
td(DO-WS)
WCLK to DOUT delay (For LJF mode only)
td(DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
4
4
tf
Fall time
4
4
18
8
20
20
22
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ns
22
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Typical DSP Timing Characteristics
All specifications at 25°C, DVdd = 1.8V
WCLK
td(WS)
td(WS)
BCLK
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 5. DSP Timing in Master Mode
Table 4. DSP Timing in Master Mode (see Figure 5)
PARAMETER
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNITS
MAX
td(WS)
WCLK delay
30
20
ns
td(DO-BCLK)
BCLK to DOUT delay
22
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
24
12
ns
tf
Fall time
24
12
ns
ns
ns
WCLK
th(ws)
BCLK
ts(ws)
th(ws)
th(ws)
tL(BCLK)
tH(BCLK)
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 6. DSP Timing in Slave Mode
Table 5. DSP Timing in Slave Mode (see Figure 6)
PARAMETER
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNITS
MAX
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
ns
td(DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
ns
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
22
22
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I2C Interface Timing
Figure 7. I2C Interface Timing
Table 6. I2C Interface Timing
PARAMETER
TEST CONDITION
Standard-Mode
MIN
TYP
Fast-Mode
MAX
100
UNITS
MAX
SCL clock frequency
tHD;STA
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated.
4.0
0.8
μs
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4.0
0.6
μs
tSU;STA
Setup time for a repeated START
condition
4.7
0.8
μs
tHD;DAT
Data hold time: For I2C bus
devices
tSU;DAT
Data set-up time
tr
SDA and SCL Rise Time
tf
SDA and SCL Fall Time
tSU;STO
Set-up time for STOP condition
4.0
0.8
μs
tBUF
Bus free time between a STOP
and START condition
4.7
1.3
μs
Cb
Capacitive load for each bus line
0
0
TYP
fSCL
20
0
MIN
400
3.45
0
1000
20+0.1Cb
300
300
20+0.1Cb
300
250
0.9
100
400
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kHz
μs
ns
400
ns
ns
pF
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SPI Interface Timing
SS
S
t
t Lead
t
t Lag
td
sck
SCLK
t sckl
tf
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
BIT 6 . . . 1
LSB OUT
ta
MOSI
t hi
t su
MSB IN
BIT 6 . . . 1
LSB IN
Figure 8. SPI Interface Timing Diagram
Timing Requirements
At 25°C, DVdd = 1.8V
Table 7. SPI Interface Timing (See Figure 8)
PARAMETER
TEST CONDITION
IOVDD=1.8V
MIN
tsck
SCLK Period (1)
tsckh
IOVDD=3.3V
TYP MAX
MIN
TYP
UNITS
MAX
100
50
ns
SCLK Pulse width High
50
25
ns
tsckl
SCLK Pulse width Low
50
25
ns
tlead
Enable Lead Time
30
20
ns
ttrail
Enable Trail Time
30
20
ns
td;seqxfr
Sequential Transfer Delay
40
20
ns
ta
Slave DOUT access time
40
20
ns
tdis
Slave DOUT disable time
40
20
ns
tsu
DIN data setup time
15
th;DIN
DIN data hold time
15
tv;DOUT
DOUT data valid time
tr
tf
(1)
10
ns
10
ns
25
18
ns
SCLK Rise Time
4
4
ns
SCLK Fall Time
4
4
ns
These parameters are based on characterization and are not tested in production.
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Typical Characteristics
Device Power Consumption
Device power consumption largely depends on PowerTune configuration. For information on device power
consumption, see the TLV320AIC3254-Q1 Application Reference Guide, literature number SLAU497.
Typical Performance
ADC SNR
vs
CHANNEL GAIN
TOTAL HARMONIC DISTORTION
vs
HEADPHONE OUTPUT POWER
100
0
THD - Total Harmonic Distortion - dB
SNR - Signal-to-Noise Ratio - dB
CM=0.9 V,
-10 RL = 32 W
RIN = 10 kW, Differential
95
90
RIN = 20 kW, Differential
85
80
75
RIN = 10 kW, Single Ended
70
65
RIN = 20 kW, Single Ended
60
55
-20
CM=1.65 V,
RL = 16 W
-30
-40
-50
-60
-70
-80
-100
20
0
60
40
0
20
Channel Gain - dB
40
60
80
Headphone Output Power - mW
Figure 9.
HEADPHONE SNR AND OUTPUT POWER
vs
OUTPUT COMMON MODE SETTING
0
70
105
Load = 32 W BTL
-10
100
-20
SNR - Signal-to-Noise Ratio - dB
THD - Total Harmonic Distortion - dB
100
Figure 10.
TOTAL HARMONIC DISTORTION
vs
HEADPHONE OUTPUT POWER
-30
CM=1.5 V
-40
CM=1.65 V
-50
-60
-70
-80
60
SNR
95
50
90
40
85
80
30
OUTPUT POWER
75
20
70
10
65
-90
-100
60
0
50
100
150
Headphone output Power - mW
200
0
0.75
Figure 11.
22
CM=1.65 V,
RL = 32 W
-90
50
-20
CM=0.9 V,
RL = 16 W
0.9
1.5
1.25
Output Common Mode Setting - V
1.65
Figure 12.
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LDO DROPOUT VOLTAGE
vs
LOAD CURRENT
LDO LOAD RESPONSE
350
20
DVDD LDO
15
Change In Output Voltage - mV
300
Dropout Voltage - mV
250
200
AVDD LDO
150
100
50
10
AVDD LDO
5
0
DVDD LDO
-5
-10
-15
0
-20
0
10
20
30
Load - mA
40
50
0
10
Figure 13.
20
Load - mA
30
40
50
Figure 14.
MICBIAS MODE 2, CM = 0.9V, LDOIN OP STAGE
vs
MICBIAS LOAD CURRENT
2.6
MicBIAS Voltage - mV
2.55
2.5
2.45
2.4
0
0.5
1
1.5
2
MicBIAS Load - mA
2.5
3
Figure 15.
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FFT
SINGLE ENDED LINE INPUT TO ADC FFT at -1dBr vs
FREQUENCY
DAC PLAYBACK TO HEADPHONE FFT at -1dBFS vs
FREQUENCY
0
0
DAC
ADC
-20
-20
-40
Power - dBr
Power - dBFs
-40
-60
-80
-60
-80
-100
-100
-120
-120
-140
0
5000
20000
15000
10000
f - Frequency - Hz
0
5000
10000
f - Frequency - Hz
Figure 16.
15000
20000
Figure 17.
DAC PLAYBACK TO LINE-OUT FFT at -1dBFS vs
FREQUENCY
LINE INPUT TO HEADPHONE FFT at 446mVrms vs
FREQUENCY
0
0
DAC
-20
-20
-40
Power - dBr
Power - dBr
-40
-60
-60
-80
-80
-100
-100
-120
-140
-120
0
5000
10000
f - Frequency - Hz
15000
0
20000
5000
10000
f - Frequency - Hz
Figure 18.
15000
20000
Figure 19.
LINE INPUT TO LINE-OUT FFT at 446mVrms vs
FREQUENCY
0
-20
Power - dBr
-40
-60
-80
-100
-120
-140
0
5000
10000
15000
20000
f - Frequency - Hz
Figure 20.
24
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TYPICAL CIRCUIT CONFIGURATION
Host Processor
Reset MCLK
SCL
SDA
BCLK
WCLK
DOUT
DIN
SPI_Select
1k
1k
2.7k
MICBIAS
1k
0.1uF
4700pF
0.1uF
LOL
0.1uF
1k
IN1_R
TPA2012
0.1uF Class D Amp
LOR
4700pF
0.1uF
0.1uF
IN1_L
0.1uF
1.9...3.6V
IN2_L
LDOIN
0.1uF 1.0uF 10uF
0.1uF
IN2_R
1.1...3.6V
1k
1k
IOVDD
MFP3/SCLK
0.1uF
IN3_R
HPR
Headset_Mic
Earjack
microphone
and headset
speakers
LDO_SELECT
HPL
AVSS
DVSS
IOVSS
AVDD
DVDD
REF
Headset_Spkr_R 47uF
10 uF
Headset_Spkr_L
Headset_Gnd
10 uF
10 uF
47uF
Figure 21. Typical Circuit Configuration
Application Overview
The TLV320AIC3254-Q1 offers a wide range of configuration options. Figure 1 shows the basic functional blocks
of the device.
Device Connections
Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are Reset, LDO_Select and the SPI_Select pin, which are HW control pins. Depending on
the state of SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI
protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Multifunction Pins.
Multifunction Pins
Table 8 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
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Table 8. Multifunction Pin Assignments
Pin Function
A
1
2
3
4
5
6
7
8
MCLK
BCLK
WCLK
DIN
MFP1
DOUT
MFP2
DMDIN/
MFP3/
SCLK
DMCLK/
MFP4/
MISO
GPIO
MFP5
S (1)
S (2)
PLL Input
B
Codec Clock Input
C
,D
(4)
S
S,D
2
E (5)
I S BCLK output
2
E
I S WCLK input
F
I2S WCLK output
G
I2S ADC word clock input
S (3)
E
(2)
2
I S BCLK input
D
S
(1)
S (3)
E, D
E
E
2
H
I S ADC WCLK out
I
I2S DIN
J
I2S DOUT
K
General Purpose Output I
K
General Purpose Output II
K
General Purpose Output III
L
General Purpose Input I
L
General Purpose Input II
L
General Purpose Input III
M
INT1 output
N
INT2 output
O
Digital Microphone Data Input
P
Digital Microphone Clock Output
E
E
E
E, D
E, D
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Q
2
Secondary I S BCLK input
E
E
R
Secondary I2S WCLK in
E
E
S
Secondary I2S DIN
E
E
2
T
Secondary I S DOUT
U
Secondary I2S BCLK OUT
E
E
E
V
Secondary I2S WCLK OUT
E
E
E
W
Headphone Detect Input
E
E
X
(1)
(2)
(3)
(4)
(5)
E
E
Aux Clock Output
E
S(1):
S(2):
(3)
The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S : The GPIO/MFP5 pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/MFP5 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
Analog Audio IO
The analog IO path of the TLV320AIC3254-Q1 features a large set of options for signal conditioning as well as
signal routing:
• 6 analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• 2 mixer amplifiers for analog bypass
• 2 low power analog bypass channels
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•
•
•
•
•
•
•
SLAS894A – MAY 2013 – REVISED AUGUST 2013
Mute function
Automatic gain control (AGC)
Built in microphone bias
Stereo digital microphone interface
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
Analog Low Power Bypass
The TLV320AIC3254-Q1 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation; this configuration supports low-power operation during analog-bypass
mode.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1_L to the
left headphone amplifier (HPL) and IN1_R to HPR.
ADC Bypass Using Mixer Amplifiers
In addition to the analog low-power bypass mode, another bypass mode uses the programmable gain amplifiers
of the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line or headphone outputs, fully bypassing the ADC and DAC.
To enable this mode, the mixer amplifiers are powered on via software command.
Headphone Outputs
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in singleended AC-coupled headphone configurations, or loads down to 32Ω in differential mode, where a speaker is
connected between HPL and HPR. In single-ended drive configuration these drivers can drive up to 15mW
power into each headphone channel while operating from 1.8V analog supplies. While running from the AVDD
supply, the output common-mode of the headphone driver is set by the common-mode setting of analog inputs in
Page 1, Register 10, Bit D6, to allow maximum utilization of the analog supply range while simultaneously
providing a higher output-voltage swing. In cases when higher output-voltage swing is required, the headphone
amplifiers can run directly from the higher supply voltage on LDOIN input (up to 3.6V). To use the higher supply
voltage for higher output signal swing, the output common-mode can be adjusted to either 1.25V, 1.5V or 1.65V
by configuring Page 1, Register 10, Bits D5-D4. When the common-mode voltage is configured at 1.65V and
LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power into a 16Ω load.
The headphone drivers are capable of driving a mixed combination of DAC signal, left and right ADC PGA signal
and line-bypass from analog input IN1L and IN1R by configuring Page 1, Register 12 and Page 1, Register 13
respectively. The ADC PGA signals can be attenuated up to 30dB before routing to headphone drivers by
configuring Page 1, Register 24 and Page 1, Register 25. The analog line-input signals can be attenuated up to
72dB before routing by configuring Page 1, Register 22 and 23. The level of the DAC signal can be controlled
using the digital volume control of the DAC in Page 0, Reg 65 and 66. To control the output-voltage swing of
headphone drivers, the digital volume control provides a range of –6.0dB to +29.0dB (6) in steps of 1dB. These
can be configured by programming Page 1, Register 16 and 17. These level controls are not meant to be used
as dynamic volume control, but to set output levels during initial device configuration. Refer to for
recommendations for using headphone volume control for achieving 0dB gain through the DAC channel with
various configurations.
Line Outputs
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in
the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the
analog input common-mode setting or to 1.65V. With output common-mode setting of 1.65V and DRVdd_HP
supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a
mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable.
(6)
If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute.
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ADC
The TLV320AIC3254-Q1 includes a stereo audio ADC, which uses a delta-sigma modulator with a
programmable oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates from
8kHz to 192kHz. In order to provide optimal system power management, the stereo recording path can be
powered up one channel at a time, to support the case where only mono record capability is required.
The ADC path of the TLV320AIC3254-Q1 features a large set of options for signal conditioning as well as signal
routing:
• Two ADCs
• Six analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• Two programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• Two mixer amplifiers for analog bypass
• Two low power analog bypass channels
• Fine gain adjustment of digital channels with 0.1dB step size
• Digital volume control with a range of -12 to +20dB
• Mute function
• Automatic gain control (AGC)
In addition to the standard set of ADC features the TLV320AIC3254-Q1 also offers the following special
functions:
• Built in microphone bias
• Stereo digital microphone interface
• Channel-to-channel phase adjustment
• Fast charge of ac-coupling capacitors
• Anti thump
• Adaptive filter mode
ADC Processing
The TLV320AIC3254-Q1 ADC channel includes a built-in digital decimation filter to process the oversampled
data from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range.
The decimation filter can be chosen from three different types, depending on the required frequency response,
group delay and sampling rate.
ADC Processing Blocks
The TLV320AIC3254-Q1 offers a range of processing blocks which implement various signal processing
capabilities along with decimation filtering. These processing blocks give users the choice of how much and what
type of signal processing they may use and which decimation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the device.
Table 9 gives an overview of the available processing blocks and their properties. The Resource Class Column
(RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
• AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column
(RC) gives an approximate indication of power consumption.
28
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Table 9. ADC Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required
AOSR Value
Resource
Class
PRB_R1 (1)
Stereo
A
Yes
0
No
128,64
6
PRB_R2
Stereo
A
Yes
5
No
128,64
8
PRB_R3
Stereo
A
Yes
0
25-Tap
128,64
8
PRB_R4
Right
A
Yes
0
No
128,64
3
PRB_R5
Right
A
Yes
5
No
128,64
4
PRB_R6
Right
A
Yes
0
25-Tap
128,64
4
PRB_R7
Stereo
B
Yes
0
No
64
3
PRB_R8
Stereo
B
Yes
3
No
64
4
PRB_R9
Stereo
B
Yes
0
20-Tap
64
4
PRB_R10
Right
B
Yes
0
No
64
2
PRB_R11
Right
B
Yes
3
No
64
2
PRB_R12
Right
B
Yes
0
20-Tap
64
2
PRB_R13
Stereo
C
Yes
0
No
32
3
PRB_R14
Stereo
C
Yes
5
No
32
4
PRB_R15
Stereo
C
Yes
0
25-Tap
32
4
PRB_R16
Right
C
Yes
0
No
32
2
PRB_R17
Right
C
Yes
5
No
32
2
PRB_R18
Right
C
Yes
0
25-Tap
32
2
(1)
Default
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
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DAC
The TLV320AIC3254-Q1 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel
of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter.
The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal
images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize
power dissipation and performance, the TLV320AIC3254-Q1 allows the system designer to program the
oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling
ratios for lower input data rates and lower oversampling ratios for higher input data rates.
The TLV320AIC3254-Q1 DAC channel includes a built-in digital interpolation filter to generate oversampled data
for the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3254-Q1 features many options for signal conditioning and signal routing:
• 2 headphone amplifiers
– Usable in single-ended or differential mode
– Analog volume setting with a range of -6 to +29dB
– Class-D mode
• 2 line-out amplifiers
– Usable in single-ended or differential mode
– Analog volume setting with a range of -6 to +29dB
• Digital volume control with a range of -63.5 to +24dB
• Mute function
• Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320AIC3254-Q1 also offers the following special features:
• Built in sine wave generation (beep generator)
• Digital auto mute
• Adaptive filter mode
DAC Processing Blocks — Overview
The TLV320AIC3254-Q1 implements signal processing capabilities and interpolation filtering via processing
blocks. These fixed processing blocks give users the choice of how much and what type of signal processing
they may use and which interpolation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy balancing power conservation
and signal processing flexibility. Less signal processing capability will result in less power consumed by the
device. Table 10 gives an overview over all available processing blocks of the DAC channel and their properties.
The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• 3D – Effect
• Beep Generator
The processing blocks are tuned for typical cases and can achieve high image rejection or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients. The Resource Class Column (RC)
gives an approximate indication of power consumption.
30
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Table 10. Overview – DAC Predefined Processing Blocks
(1)
Processing
Block No.
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
Resource
Class
PRB_P1 (1)
A
Stereo
No
3
No
No
No
8
PRB_P2
A
Stereo
Yes
6
Yes
No
No
12
PRB_P3
A
Stereo
Yes
6
No
No
No
10
PRB_P4
A
Left
No
3
No
No
No
4
PRB_P5
A
Left
Yes
6
Yes
No
No
6
PRB_P6
A
Left
Yes
6
No
No
No
6
PRB_P7
B
Stereo
Yes
0
No
No
No
6
PRB_P8
B
Stereo
No
4
Yes
No
No
8
PRB_P9
B
Stereo
No
4
No
No
No
8
PRB_P10
B
Stereo
Yes
6
Yes
No
No
10
PRB_P11
B
Stereo
Yes
6
No
No
No
8
PRB_P12
B
Left
Yes
0
No
No
No
3
PRB_P13
B
Left
No
4
Yes
No
No
4
PRB_P14
B
Left
No
4
No
No
No
4
PRB_P15
B
Left
Yes
6
Yes
No
No
6
PRB_P16
B
Left
Yes
6
No
No
No
4
PRB_P17
C
Stereo
Yes
0
No
No
No
3
PRB_P18
C
Stereo
Yes
4
Yes
No
No
6
PRB_P19
C
Stereo
Yes
4
No
No
No
4
PRB_P20
C
Left
Yes
0
No
No
No
2
PRB_P21
C
Left
Yes
4
Yes
No
No
3
PRB_P22
C
Left
Yes
4
No
No
No
2
PRB_P23
A
Stereo
No
2
No
Yes
No
8
PRB_P24
A
Stereo
Yes
5
Yes
Yes
No
12
PRB_P25
A
Stereo
Yes
5
Yes
Yes
Yes
12
Default
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
Powertune
The TLV320AIC3254-Q1 features PowerTune, a mechanism to balance power-versus-performance trade-offs at
the time of device configuration. The device can be tuned to minimize power dissipation, to maximize
performance, or to an operating point between the two extremes to best fit the application. The TLV320AIC3254Q1 PowerTune modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for
the playback (DAC) path.
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
Digital Audio IO Interface
Audio data flows between the host processor and the TLV320AIC3254-Q1 on the digital audio data serial
interface, or audio bus. This very flexible bus includes left or right-justified data options, support for I2S or PCM
protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master-slave
configurability for each bus clock line, and the ability to communicate with multiple devices within a system
directly.
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The audio bus of the TLV320AIC3254-Q1 can be configured for left or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0,
Register 27, D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or
Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the
beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this
clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word
lengths, and to support the case when multiple TLV320AIC3254-Q1s may share the same audio bus.
The TLV320AIC3254-Q1 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.
The TLV320AIC3254-Q1 also has the feature to invert the polarity of the bit-clock used to transfer the audio data
as compared to the default clock polarity used. This feature can be used independently of the mode of audio
interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.
The TLV320AIC3254-Q1 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line
into a hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability
with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM)
can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio
serial data bus is powered down while configured in master mode, the pins associated with the interface are put
into a hi-Z output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3254-Q1, these clocks are
active only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock
operation reduces power consumption. However, it also supports a feature when both the word clocks and bitclocks can be active even when the codec in the device is powered down. This continuous clock feature is useful
when using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in
the system as general-purpose clocks.
Clock Generation and PLL
The TLV320AIC3254-Q1 supports a wide range of options for generating clocks for the ADC and DAC sections
as well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the
miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference
clocks on MCLK BCLK or GPIO, the TLV320AIC3254-Q1 also provides the option of using the on-chip PLL
which supports a wide range of fractional multiplication values to generate the required clocks. Starting from
CODEC_CLKIN the TLV320AIC3254-Q1 provides several programmable clock dividers to help achieve a variety
of sampling rates for ADC, DAC and clocks for the miniDSP.
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3254-Q1.
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
Control Interfaces
The TLV320AIC3254-Q1 control interface supports SPI or I2C communication protocols, with the protocol
selectable using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should
be tied low. Changing the state of SPI_SELECT during device operation is not recommended.
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I2C Control
The TLV320AIC3254-Q1 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is
a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver
contention.
SPI Control
In the SPI control mode, the TLV320AIC3254-Q1 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3254-Q1) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
Power Supply
To power up the device, a 3.3V system rail (1.9V to 3.6V) can be used. The IOVDD voltage can be in the range of
1.1V - 3.6V. Internal LDOs generate the appropriate digital core voltage of 1.65V and analog core voltage of 1.8V
(minimum 1.5V). For maximum flexibility, the respective voltages can also be supplied externally, bypassing the
built-in LDOs. To support high-output drive capabilities, the output stages of the output amplifiers can be driven
from the analog core voltage or the 1.9…3.6V rail used for the LDO inputs (LDO_in).
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
Device Special Functions
The following special functions are available to support advanced system requirements:
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TLV320AIC3254-Q1Application Reference Guide, SLAU497.
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TLV320AIC3254-Q1
SLAS894A – MAY 2013 – REVISED AUGUST 2013
www.ti.com
The TLV320AIC3254-Q1 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the
second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1152 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data. Typical algorithms for the TLV320AIC3254-Q1 miniDSPs are active
noise cancellation, acoustic echo cancellation or advanced DSP sound enhancement algorithms.
Software
Software development for the TLV320AIC3254-Q1 is supported through TI's comprehensive PurePath Studio
Development Environment; a powerful, easy-to-use tool designed specifically to simplify software development
on the TLV320AIC3254-Q1 miniDSP audio platform. The Graphical Development Environment consists of a
library of common audio functions that can be dragged-and-dropped into an audio signal flow and graphically
connected together. The DSP code can then be assembled from the graphical signal flow with the click of a
mouse.
Please visit the TLV320AIC3254-Q1 product folder on www.ti.com to learn more about PurePath Studio and the
latest status on available, ready-to-use DSP algorithms.
Register Map Summary
Table 11. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2
0x00
0x02
Reserved Register
0
3
0x00
0x03
Reserved Register
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P and R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9-10
0x00
0x09-0x0A
Reserved Register
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15
0x00
0x0F
miniDSP_D Instruction Control Register 1
0
16
0x00
0x10
miniDSP_D Instruction Control Register 2
0
17
0x00
0x11
miniDSP_D Interpolation Factor Setting Register
0
18
0x00
0x12
Clock Setting Register 8, NADC Values
0
19
0x00
0x13
Clock Setting Register 9, MADC Values
0
20
0x00
0x14
ADC Oversampling (AOSR) Register
0
21
0x00
0x15
miniDSP_A Instruction Control Register 1
0
22
0x00
0x16
miniDSP_A Instruction Control Register 2
0
23
0x00
0x17
miniDSP_A Decimation Factor Setting Register
0
24
0x00
0x18
Reserved Register
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
34
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SLAS894A – MAY 2013 – REVISED AUGUST 2013
Table 11. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Digital Interface Misc. Setting Register
0
35
0x00
0x23
Reserved Register
0
36
0x00
0x24
ADC Flag Register
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Register
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Sticky Flag Register 3
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Interrupt Flag Register 3
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Register
0
52
0x00
0x34
GPIO/MFP5 Control Register
0
53
0x00
0x35
DOUT/MFP2 Function Control Register
0
54
0x00
0x36
DIN/MFP1 Function Control Register
0
55
0x00
0x37
MISO/MFP4 Function Control Register
0
56
0x00
0x38
SCLK/MFP3 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
0
60
0x00
0x3C
DAC Signal Processing Block Control Register
0
61
0x00
0x3D
ADC Signal Processing Block Control Register
0
62
0x00
0x3E
miniDSP_A and miniDSP_D Configuration Register
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
Left DAC Channel Digital Volume Control Register
0
66
0x00
0x42
Right DAC Channel Digital Volume Control Register
0
67
0x00
0x43
Headset Detection Configuration Register
0
68
0x00
0x44
DRC Control Register 1
0
69
0x00
0x45
DRC Control Register 2
0
70
0x00
0x46
DRC Control Register 3
0
71
0x00
0x47
Beep Generator Register 1
0
72
0x00
0x48
Beep Generator Register 2
0
73
0x00
0x49
Beep Generator Register 3
0
74
0x00
0x4A
Beep Generator Register 4
0
75
0x00
0x4B
Beep Generator Register 5
0
76
0x00
0x4C
Beep Generator Register 6
0
77
0x00
0x4D
Beep Generator Register 7
0
78
0x00
0x4E
Beep Generator Register 8
0
79
0x00
0x4F
Beep Generator Register 9
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SLAS894A – MAY 2013 – REVISED AUGUST 2013
www.ti.com
Table 11. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
80
0x00
0x50
Reserved Register
0
81
0x00
0x51
ADC Channel Setup Register
0
82
0x00
0x52
ADC Fine Gain Adjust Register
0
83
0x00
0x53
Left ADC Channel Volume Control Register
0
84
0x00
0x54
Right ADC Channel Volume Control Register
0
85
0x00
0x55
ADC Phase Adjust Register
0
86
0x00
0x56
Left Channel AGC Control Register 1
0
87
0x00
0x57
Left Channel AGC Control Register 2
0
88
0x00
0x58
Left Channel AGC Control Register 3
0
89
0x00
0x59
Left Channel AGC Control Register 4
0
90
0x00
0x5A
Left Channel AGC Control Register 5
0
91
0x00
0x5B
Left Channel AGC Control Register 6
0
92
0x00
0x5C
Left Channel AGC Control Register 7
0
93
0x00
0x5D
Left Channel AGC Control Register 8
0
94
0x00
0x5E
Right Channel AGC Control Register 1
0
95
0x00
0x5F
Right Channel AGC Control Register 2
0
96
0x00
0x60
Right Channel AGC Control Register 3
0
97
0x00
0x61
Right Channel AGC Control Register 4
0
98
0x00
0x62
Right Channel AGC Control Register 5
0
99
0x00
0x63
Right Channel AGC Control Register 6
0
100
0x00
0x64
Right Channel AGC Control Register 7
0
101
0x00
0x65
Right Channel AGC Control Register 8
0
102
0x00
0x66
DC Measurement Register 1
0
103
0x00
0x67
DC Measurement Register 2
0
104
0x00
0x68
Left Channel DC Measurement Output Register 1
0
105
0x00
0x69
Left Channel DC Measurement Output Register 2
0
106
0x00
0x6A
Left Channel DC Measurement Output Register 3
0
107
0x00
0x6B
Right Channel DC Measurement Output Register 1
0
108
0x00
0x6C
Right Channel DC Measurement Output Register 2
0
109
0x00
0x6D
Right Channel DC Measurement Output Register 3
0
110-127
0x00
0x6E-0x7F
Reserved Register
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
Power Configuration Register
1
2
0x01
0x02
LDO Control Register
1
3
0x01
0x03
Playback Configuration Register 1
1
4
0x01
0x04
Playback Configuration Register 2
1
5-8
0x01
0x05-0x08
Reserved Register
1
9
0x01
0x09
Output Driver Power Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
Over Current Protection Configuration Register
1
12
0x01
0x0C
HPL Routing Selection Register
1
13
0x01
0x0D
HPR Routing Selection Register
1
14
0x01
0x0E
LOL Routing Selection Register
1
15
0x01
0x0F
LOR Routing Selection Register
1
16
0x01
0x10
HPL Driver Gain Setting Register
1
17
0x01
0x11
HPR Driver Gain Setting Register
36
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SLAS894A – MAY 2013 – REVISED AUGUST 2013
Table 11. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
1
18
0x01
0x12
LOL Driver Gain Setting Register
1
19
0x01
0x13
LOR Driver Gain Setting Register
1
20
0x01
0x14
Headphone Driver Startup Control Register
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
IN1L to HPL Volume Control Register
1
23
0x01
0x17
IN1R to HPR Volume Control Register
1
24
0x01
0x18
Mixer Amplifier Left Volume Control Register
1
25
0x01
0x19
Mixer Amplifier Right Volume Control Register
1
26-50
0x01
0x1A-0x32
Reserved Register
1
51
0x01
0x33
MICBIAS Configuration Register
1
52
0x01
0x34
Left MICPGA Positive Terminal Input Routing Configuration Register
1
53
0x01
0x35
Reserved Register
1
54
0x01
0x36
Left MICPGA Negative Terminal Input Routing Configuration Register
1
55
0x01
0x37
Right MICPGA Positive Terminal Input Routing Configuration Register
1
56
0x01
0x38
Reserved Register
1
57
0x01
0x39
Right MICPGA Negative Terminal Input Routing Configuration Register
1
58
0x01
0x3A
Floating Input Configuration Register
1
59
0x01
0x3B
Left MICPGA Volume Control Register
1
60
0x01
0x3C
Right MICPGA Volume Control Register
1
61
0x01
0x3D
ADC Power Tune Configuration Register
1
62
0x01
0x3E
ADC Analog Volume Control Flag Register
1
63
0x01
0x3F
DAC Analog Gain Control Flag Register
1
64-70
0x01
0x40-0x46
Reserved Register
1
71
0x01
0x47
Analog Input Quick Charging Configuration Register
1
72-122
0x01
0x48-0x7A
Reserved Register
1
123
0x01
0x7B
Reference Power-up Configuration Register
1
124-127
0x01
0x7C-0x7F
Reserved Register
8
0
0x08
0x00
Page Select Register
8
1
0x08
0x01
ADC Adaptive Filter Configuration Register
8
2-7
0x08
0x02-0x07
Reserved
8
8-127
0x08
0x08-0x7F
ADC Coefficients Buffer-A C(0:29)
9-16
0
0x09-0x10
0x00
Page Select Register
9-16
1-7
0x09-0x10
0x01-0x07
Reserved
9-16
8-127
0x09-0x10
0x08-0x7F
ADC Coefficients Buffer-A C(30:255)
26-34
0
0x1A-0x22
0x00
Page Select Register
26-34
1-7
0x1A-0x22
0x01-0x07
Reserved.
26-34
8-127
0x1A-0x22
0x08-0x7F
ADC Coefficients Buffer-B C(0:255)
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02-0x07
Reserved
44
8-127
0x2C
0x08-0x7F
DAC Coefficients Buffer-A C(0:29)
45-52
0
0x2D-0x34
0x00
Page Select Register
45-52
1-7
0x2D-0x34
0x01-0x07
Reserved.
45-52
8-127
0x2D-0x34
0x08-0x7F
DAC Coefficients Buffer-A C(30:255)
62-70
0
0x3E-0x46
0x00
Page Select Register
62-70
1-7
0x3E-0x46
0x01-0x07
Reserved.
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www.ti.com
Table 11. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
62-70
8-127
0x3E-0x46
0x08-0x7F
DAC Coefficients Buffer-B C(0:255)
80-114
0
0x50-0x72
0x00
Page Select Register
80-114
1-7
0x50-0x72
0x01-0x07
Reserved.
80-114
8-127
0x50-0x72
0x08-0x7F
miniDSP_A Instructions
152-186
0
0x98-0xBA
0x00
Page Select Register
152-186
1-7
0x98-0xBA
0x01-0x07
Reserved.
152-186
8-127
0x98-0xBA
0x08-0x7F
miniDSP_D Instructions
38
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SLAS894A – MAY 2013 – REVISED AUGUST 2013
REVISION HISTORY
Changes from Revision Initial (May 2013) to Revision A
Page
•
Corrected secondary function list for MFP1 ......................................................................................................................... 4
•
Corrected typo in test conditions, Electrical Characteristics, ADC ....................................................................................... 8
•
Changed plot label from 10kΩ to 20kΩ .............................................................................................................................. 22
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39
PACKAGE OPTION ADDENDUM
www.ti.com
3-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
6PAIC3254IRHBRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RHB
32
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU NIPDAU
Level-3-260C-168 HR
(4/5)
-40 to 85
AIC3254
IRHBQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV320AIC3254-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Sep-2013
• Catalog: TLV320AIC3254
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
6PAIC3254IRHBRQ1
Package Package Pins
Type Drawing
VQFN
RHB
32
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
6PAIC3254IRHBRQ1
VQFN
RHB
32
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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