Texas Instruments | 3-W Mono Class-D Amplifier With SmartGain AGC/DRC (Rev. A) | Datasheet | Texas Instruments 3-W Mono Class-D Amplifier With SmartGain AGC/DRC (Rev. A) Datasheet

Texas Instruments 3-W Mono Class-D Amplifier With SmartGain AGC/DRC (Rev. A) Datasheet
TPA2029D1
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SLOS661A – DECEMBER 2011 – REVISED APRIL 2012
3-W Mono Class-D Audio Amplifier With SmartGain™ AGC/DRC
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FEATURES
DESCRIPTION
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The TPA2029D1 is a mono, filter-free Class-D audio
power amplifier with dynamic range compression
(DRC) and automatic gain control (AGC). It is
available in a 1.63 mm x 1.63 mm WCSP package.
1
2
Filter-Free Class-D Architecture
3 W Into 4 Ω at 5 V (10% THD+N)
880 mW Into 8 Ω at 3.6 V (10% THD+N)
Power Supply Range: 2.5 V to 5.5 V
3 Selectable AGC functions
Low Supply Current: 1.8 mA
Low Shutdown Current: 0.2 μA
High PSRR: 80 dB
Fast Start-up Time: 5 ms
AGC Enable/Disable Function
Limiter Enable/Disable Function
Short-Circuit and Thermal Protection
Space-Saving Package
– 1.63 mm × 1.63 mm WCSP (YZF)
The DRC/AGC function in the TPA2029D1 can be
enabled and disabled. The DRC/AGC function is
configured to automatically prevent distortion of the
audio signal and enhance quiet passages that are
normally not heard. The DRC/AGC is also configured
to protect the speaker from damage at high power
levels and compress the dynamic range of music to fit
within the dynamic range of the speaker. The
TPA2029D1 is capable of driving 3 W at 5 V into 4Ω
load or 880 mW at 3.6 V into 8Ω load. The device
features an enable pin and also provides thermal and
short circuit protection.
In addition to these features, a fast start-up time and
small package size make the TPA2029D1 an ideal
choice for Notebook PCs, PDAs and other portable
applications.
APPLICATIONS
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Wireless or Cellular Handsets and PDAs
Portable Navigation Devices
Portable DVD Player
Notebook PCs
Portable Radio
Portable Games
Educational Toys
USB Speakers
TPA2029D1 is available with different default
AGC/DRC settings for various system requirements.
See Table 2 for more detail.
SIMPLIFIED APPLICATION DIAGRAM
To Battery
10 mF
Analog
Baseband
or
CODEC
PVdd
TPA2029D1
CIN 1 mF
(Optional)
OUT+
ININ+
OUT-
Digital
BaseBand
GPIO
Master Enable
AGC1
AGC2
EN
PGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartGain is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPA2029D1
SLOS661A – DECEMBER 2011 – REVISED APRIL 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
GPIO
Interface
AGC1
Bias and
References
AGC2
IC Enable
CIN
Differential
Input
EN
Control Interface
PVDD
OUT+
ININ+
Volume
Control
Class-D
Modulator
Power
Stage
OUT-
1 mF
AGC
Reference
AGC
PGND
DEVICE PINOUT
WCSP (YZF) PACKAGE
(TOP VIEW)
2
PGND
AGC1
AGC2
A1
A2
A3
OUT+
EN
IN+
B1
B2
B3
OUT-
PVDD
IN-
C1
C2
C3
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PIN FUNCTIONS
PIN
NAME
I/O/P
DESCRIPTION
WCSP
IN+
B3
I
Positive audio input
IN–
C3
I
Negative audio input
EN
B2
I
Enable terminal (active high)
AGC2
A3
I
AGC select function pin 2
AGC1
A2
I
AGC select function pin 1
OUT+
B1
O
Positive differential output
OUT–
C1
O
Negative differential output
PVDD
C2
P
Power supply
PGND
A1
P
Power ground
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted).
VALUE / UNIT
VDD
Supply voltage
Input voltage
PVDD
–0.3 V to 6 V
EN, INR+, INR–, INL+, INL–
–0.3 V to VDD+0.3 V
AGC1, AGC2
–0.3 V to 6 V
Continuous total power dissipation
See Dissipation Ratings Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
ESD
Electro-Static Discharge
Tolerance, all pins
RLOAD
Minimum load resistance
(1)
Human Body Model (HBM)
2 KV
Charged Device Model (CDM)
500 V
3.6 Ω
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS TABLE (1)
(1)
PACKAGE
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
9-ball WCSP
1.19 W
9.52 mW/°C
0.76 W
0.62 W
Dissipations ratings are for a 2-side, 2-plane PCB.
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AVAILABLE OPTIONS (1)
(1)
(2)
TA
PACKAGED DEVICES (2)
–40°C to 85°C
9-pin, 1.63 mm × 1.63 mm WCSP
PART NUMBER
SYMBOL
TPA2029D1YZFR
QWI
TPA2029D1YZFT
QWI
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com
The YZF packages are only available taped and reeled. The suffix R indicates a reel of 3000; the suffix T indicates a reel of 250.
RECOMMENDED OPERATING CONDITIONS
MIN MAX
VDD
Supply voltage
PVDD
2.5
VIH
High-level input voltage
EN, AGC1, AGC2
1.3
VIL
Low-level input voltage
EN, AGC1, AGC2
TA
Operating free-air temperature
–40
5.5
UNIT
V
V
0.6
V
85
°C
ELECTRICAL CHARACTERISTICS
at TA = 25°C, VDD = 3.6 V, EN = 1.3 V, and RL = 8 Ω + 33 μH (unless otherwise noted).
PARAMETER
VDD
ISDZ
TEST CONDITIONS
MIN
Supply voltage range
Shutdown quiescent current
2.5
3.6
5.5
EN = 0.35 V, VDD = 2.5 V
0.1
1
EN = 0.35 V, VDD = 3.6 V
0.2
1
EN = 0.35 V, VDD = 5.5 V
0.3
1
VDD = 2.5 V
1.6
4.5
VDD = 3.6 V
1.8
4.7
IDD
Supply current
fSW
Class D Switching Frequency
IIH
High-level input current
VDD = 5.5 V, EN = 5.8 V
IIL
Low-level input current
VDD = 5.5 V, EN = –0.3 V
tSTART
Start-up time
2.5 V ≤ VDD ≤ 5.5 V no pop, CIN ≤ 1 μF
VDD = 5.5 V
POR
TYP MAX
275
5.5
kHz
1
µA
µA
2
V
V
dB
RL = 8 Ω, Vicm = 0.5 V and Vicm = VDD – 0.8 V,
differential inputs shorted
–75
Voo
Output offset voltage
VDD = 3.6 V, AV = 6 dB, RL = 8 Ω, inputs ac grounded
1.5
ZO
Output Impedance in shutdown mode
EN = 0.35 V
Gain accuracy
Compression and limiter disabled, Gain = 0 to 30 dB
Power supply rejection ratio
VDD = 2.5 V to 4.7 V
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ms
2.3
0.2
Input common mode rejection
4
mA
325
CMRR
PSRR
µA
2.1
5
Power on reset hysteresis
V
300
–1
Power on reset ON threshold
UNIT
10
2
–0.5
kΩ
0.5
–80
mV
dB
dB
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OPERATING CHARACTERISTICS
at TA = 25°C, VDD = 3.6V, EN = 1.3 V, RL = 8 Ω +33 μH, and AV = 6 dB (unless otherwise noted).
PARAMETER
TEST CONDITIONS
kSVR
VDD = 3.6 Vdc with ac of 200 mVPP at 217 Hz
power-supply ripple rejection ratio
THD+N
Total harmonic distortion + noise
Nr
Output integrated noise
f
Frequency response
PO(max)
MIN
0.1%
faud_in = 1 kHz; PO = 1.25 W; VDD = 5 V
0.1%
faud_in = 1 kHz; PO = 710 mW; VDD = 3.6 V
1%
faud_in = 1 kHz; PO = 1.4 W; VDD = 5 V
1%
Efficiency
UNIT
dB
Av = 6 dB
42
μV
Av = 6 dB floor, A-weighted
30
μV
20
20000
Hz
THD+N = 10%, VDD = 5 V, RL = 8 Ω
1.72
W
THD+N = 10%, VDD = 3.6 V, RL = 8 Ω
880
mW
THD+N = 1%, VDD = 5 V, RL = 8 Ω
1.4
W
THD+N = 1% , VDD = 3.6 V, RL = 8 Ω
710
mW
THD+N = 10% , VDD = 5 V, RL = 4 Ω
η
MAX
–70
faud_in = 1 kHz; PO = 550 mW; VDD = 3.6 V
Av = 6 dB
Maximum output power
TYP
3
THD+N = 1%, VDD = 3.6 V, RL = 8 Ω, PO= 0.71 W
91%
THD+N = 1%, VDD = 5 V, RL = 8 Ω, PO = 1.4 W
93%
W
Figure 1. TEST SET-UP FOR GRAPHS
TPA2029D1
CI
+
Measurement
Output
–
IN+
OUT+
Load
CI
IN–
VDD
+
OUT–
30 kHz
Low-Pass
Filter
+
Measurement
Input
–
GND
1 mF
VDD
–
(1)
All measurements were taken with a 1-μF CI (unless otherwise noted.)
(2)
A 33-μH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3)
The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (1 kΩ
4.7 nF) is used on each output for the data sheet graphs.
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TYPICAL CHARACTERISTICS
with C(DECOUPLE) = 1 μF, CI = 1 µF.
All THD + N graphs are taken with outputs out of phase (unless otherwise noted).
All data is taken on left channel.
Table of Graphs
FIGURE
Quiescent supply current
vs Supply voltage
Figure 2
Total harmonic distortion + noise
vs Frequency
Figure 3
Total harmonic distortion + noise
vs Frequency
Figure 4
Total harmonic distortion + noise
vs Output power
Figure 5
Supply ripple rejection ratio
vs Frequency
Figure 6
Efficiency
vs Output power (per channel)
Figure 7
Total power dissipation
vs Total output power
Figure 8
Total supply current
vs Total output power
Output power
vs Supply voltage
Figure 9
Figure 10 , Figure 11
Shutdown time
Figure 12
Startup time
Figure 13
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
IDD − Quiescent Supply Current − mA
10
9
8
RL = 8 Ω + 33 µH
EN = VDD
7
6
5
4
3
2
1
0
2.5
3.0
3.5
4.0
4.5
VDD − Supply Voltage − V
5.0
5.5
THD+N − Total Harmonic Distortion + Noise − %
QUIESCENT SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
Gain = 6 dB
RL = 8 Ω + 33 µH
VDD = 3.6 V
1
PO = 0.25 W
0.1
0.01
PO = 0.05 W
0.001
20
G001
Figure 2.
6
PO = 0.5 W
100
1k
f − Frequency − Hz
10k
20k
G008
Figure 3.
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10
Gain = 6 dB
RL = 8 Ω + 33 µH
VDD = 5 V
1
0.1
PO = 0.5 W
PO = 0.1 W
0.01
PO = 1 W
0.001
20
100
1k
10k
f − Frequency − Hz
20k
1
3
G012
90
80
VDD = 3.6 V
70
60
50
40
30
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
10
VDD = 5 V
100
1k
10k
0
0.0
20k
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
20
−70
f − Frequency − Hz
0.5
1.0
1.5
2.0
PO − Output Power − W
G014
G015
Figure 6.
Figure 7.
TOTAL POWER DISSIPATION
vs
TOTAL OUTPUT POWER
TOTAL SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
0.14
0.50
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
0.45
IDD − Supply Current − A
PD − Power Dissipation − W
0.1
100
Gain = 6 dB
RL = 8 Ω + 33 µH
−50
VDD = 3.6 V
0.08
VDD = 2.5 V
VDD = 5 V
0.06
0.04
0.02
0.00
0.0
0.01
0.01
SUPPLY RIPPLE REJECTION RATIO
VDD = 2.5 V
0.10
0.1
EFFICIENCY
vs
OUTPUT POWER (PER CHANNEL)
−40
0.12
VDD = 5 V
1
Figure 5.
−30
−80
20
VDD = 3.6 V
G009
−20
−60
10
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
Figure 4.
0
−10
100
PO − Output Power − W
η − Efficiency − %
KSVR − Supply Ripple Rejection Ratio − dB
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
0.40
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
0.35
VDD = 5 V
VDD = 3.6 V
0.30
0.25
VDD = 2.5 V
0.20
0.15
0.10
0.05
0.5
1.0
1.5
PO − Output Power − W
2.0
0.00
0.0
G016
Figure 8.
0.5
1.0
1.5
2.0
PO − Output Power − W
G017
Figure 9.
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OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
2.0
4.0
Gain = 6 dB
RL = 8 Ω + 33 µH
f = 1 kHz
1.5
Gain = 6 dB
RL = 4 Ω + 33 µH
f = 1 kHz
3.5
PO − Output Power − W
PO − Output Power − W
2.5
THD = 10%
1.0
THD = 1%
0.5
3.0
2.5
THD = 10%
2.0
1.5
THD = 1%
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
2.5
5.5
VDD − Supply Voltage − V
3.0
3.5
4.0
4.5
5.0
VDD − Supply Voltage − V
G021
Figure 10.
Figure 11.
VOLTAGE
vs
SHUTDOWN TIME
VOLTAGE
vs
STARTUP TIME
Figure 12.
Figure 13.
5.5
G022
ZI – Input Impedance – kW
Nominal Input Impedance - Per Leg
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Gain – dB
Figure 14.
8
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APPLICATION INFORMATION
AUTOMATIC GAIN CONTROL
The Automatic Gain Control (AGC) feature provides continuous automatic gain adjustment to the amplifier
through an internal PGA. This feature enhances the perceived audio loudness and at the same time prevents
speaker damage from occurring (Limiter function).
The AGC works by detecting the audio input envelope. The gain changes depending on the amplitude, the limiter
level, the compression ratio, and the attack and release time. The gain changes constantly as the audio signal
increases and/or decreases to create the compression effect. The gain step size for the AGC is 0.5 dB. If the
audio signal has near-constant amplitude, the gain does not change. Figure 15 shows how the AGC works.
INPUT SIGNAL
Limiter threshold
Limiter threshold
B
C
D
E
A
GAIN
OUTPUT SIGNAL
Limiter threshold
Release Time
Hold Time
Attack Time
Limiter threshold
A.
Gain decreases with no delay; attack time is reset. Release time and hold time are reset.
B.
Signal amplitude above limiter level, but gain cannot change because attack time is not over.
C.
Attack time ends; gain is allowed to decrease from this point forward by one step. Gain decreases because the
amplitude remains above limiter threshold. All times are reset
D.
Gain increases after release time finishes and signal amplitude remains below desired level. All times are reset after
the gain increase.
E.
Gain increases after release time is finished again because signal amplitude remains below desired level. All times
are reset after the gain increase.
Figure 15. Input and Output Audio Signal vs Time
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Gain - dB
Since the number of gain steps is limited the compression region is limited as well. The following figure shows
how the gain changes vs. the input signal amplitude in the compression region.
VIN - dBV
Figure 16. Input Signal Voltage vs Gain
Thus the AGC performs a mapping of the input signal vs. the output signal amplitude.
Pins AGC1 and AGC 2 are used to enable/disable the limiter, compression, and noise gate function. Table 1
shows each function.
Table 1. FUNCTION DEFINITION FOR AGC1 AND AGC2
AGC1
AGC2
0
0
Function
AGC Function disabled
0
1
AGC Limiter Function enabled
1
0
AGC, Limiter, and Compression Functions enabled
1
1
AGC, Limiter, Compression, and Noise Gate Functions enabled
The default values for the TPA2029D1 AGC function are given in Table 2. The default values can be changed at
the factory during production. Refer to the TI representative for assistance with different default value requests.
Table 2. AGC DEFAULT VALUES
10
AGC Parameters
TPA2029D1
Attack Time
14.084 ms / 6 dB step
Release Time
822 ms/ 6 dB step
Hold Time
off
Fixed Gain
9 dB
NoiseGate Threshold
4 mV
Output Limiter Level
9 dBV
Max Gain
30 dB
Compression Ratio
2:1
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DECOUPLING CAPACITOR (CS)
The TPA2029D1 is a high-performance Class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) 1-μF ceramic capacitor
(typically) placed as close as possible to the device PVDD lead works best. Placing this decoupling capacitor
close to the TPA2029D1 is important for the efficiency of the Class-D amplifier, because any resistance or
inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lowerfrequency noise signals, a 4.7 μF or greater capacitor placed near the audio power amplifier would also help, but
it is not required in most applications because of the high PSRR of this device.
INPUT CAPACITORS (CI)
The input capacitors and input resistors form a high-pass filter with the corner frequency, fC, determined in
Equation 1.
1
fC =
(2p ´ RI ´ CI )
(1)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase
output offset. Equation 2 is used to solve for the input coupling capacitance. If the corner frequency is within the
audio band, the capacitors should have a tolerance of ±10% or better, because any mismatch in capacitance
causes an impedance mismatch at the corner frequency and below.
1
CI =
(2p ´ RI ´ fC )
(2)
COMPONENT LOCATION
Place all the external components very close to the TPA2029D1. Placing the decoupling capacitor, CS, close to
the TPA2029D1 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace
between the device and the capacitor can cause a loss in efficiency.
EFFICIENCY AND THERMAL INFORMATION
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the packages are shown in the dissipation rating table. Converting this to θJA for the WCSP package:
1
1
θJA =
=
= 105o C/W
Derating Factor 0.0095
(3)
Given θJA of 100°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.4 W for 3 W output power into 4-Ω load, 5-V supply, from Figure 7, the maximum ambient
temperature can be calculated with the following equation.
TA Max = TJMax - θJA PDMAX = 150 - 105 (0.4) = 108°C
(4)
Equation 4 shows that the calculated maximum ambient temperature is 108°C at maximum power dissipation
with a 5-V supply and 4-Ω a load. The TPA2029D1 is designed with thermal protection that turns the device off
when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more
resistive than 8-Ω dramatically increases the thermal performance by reducing the output current and increasing
the efficiency of the amplifier.
OPERATION WITH DACS AND CODECS
In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor
from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with the
switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-pass
filter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problem
and allow proper performance. See the functional block diagram.
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FILTER FREE OPERATION AND FERRITE BEAD FILTERS
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the
frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC
and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,
choose one with high impedance at high frequencies, and low impedance at low frequencies. In addition, select a
ferrite bead with adequate current rating to prevent distortion of the output signal.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker. Figure 17 shows typical ferrite bead and LC output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 17. Typical Ferrite Bead Filter (Chip bead example: TDK: MPZ1608S221A)
PACKAGE INFORMATION
Package Dimensions
The package dimensions for this YZF package are shown in the table below. See the package drawing at the
end of this data sheet for more details.
Table 3. YZF Package Dimensions
Packaged Devices
D
E
TPA2029D1YZF
Min = 1594μm
Max = 1654μm
Min = 1594μm
Max = 1654μm
REVISION HISTORY
Changes from Revision December 2011 (*) to Revision A
•
12
Page
Added Figure 14 ................................................................................................................................................................... 8
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPA2029D1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPA2029D1YZFR
ACTIVE
DSBGA
YZF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
QWI
TPA2029D1YZFT
ACTIVE
DSBGA
YZF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
QWI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA2029D1YZFR
DSBGA
YZF
9
3000
180.0
8.4
TPA2029D1YZFT
DSBGA
YZF
9
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.71
1.71
0.81
4.0
8.0
Q1
1.71
1.71
0.81
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2029D1YZFR
DSBGA
YZF
9
3000
210.0
185.0
35.0
TPA2029D1YZFT
DSBGA
YZF
9
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0009
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
BALL TYP
0.35
0.15
0.05 C
1 TYP
SYMM
C
1
TYP
SYMM
B
D: Max = 1.655 mm, Min =1.594 mm
0.5
TYP
E: Max = 1.655 mm, Min =1.594 mm
A
9X
0.015
0.35
0.25
C A B
1
2
3
0.5 TYP
4219558/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
9X ( 0.245)
1
2
3
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.245)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
( 0.245)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219558/A 10/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
9X ( 0.25)
1
2
3
A
(0.5) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 40X
4219558/A 10/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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Copyright © 2018, Texas Instruments Incorporated
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