Texas Instruments | 24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,Eight-Channel Audio Digital.. | Datasheet | Texas Instruments 24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,Eight-Channel Audio Digital.. Datasheet

Texas Instruments 24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,Eight-Channel Audio Digital.. Datasheet
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,
Eight-Channel Audio Digital-to-Analog Converter
Check for Samples: PCM1690-Q1
FEATURES
1
• Qualified for Automotive Applications
• 24-Bit Delta-Sigma DAC
• 8-Channel DAC:
– High Performance: Differential, fS = 48 kHz
– THD+N: –94 dB
– SNR: 113 dB
– Dynamic Range: 113 dB
– Sampling Rate: 8 kHz to 192 kHz
– System Clock: 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 fS
– Differential Voltage Output: 8 VPP
– Analog Low-Pass Filter Included
– 4x/8x Oversampling Digital Filter:
– Passband Ripple: ±0.0018 dB
– Stop Band Attenuation: –75 dB
– Zero Flag
• Flexible Audio Interface:
– I/F Format: I2S™, Left-/Right-Justified, DSP,
TDM
– Data Length: 16, 20, 24, 32 Bits
• Flexible Mode Control:
– 3-Wire SPI™, 2-Wire I2C™-Compatible
Serial Control Interface, or
Hardware Control
• Multi Functions via SPI or I2C I/F:
– Audio I/F Format Select: I2S, Left-Justified,
Right-Justified, DSP, TDM
– Digital Attenuation and Soft Mute
– Digital De-Emphasis: 32 kHz, 44.1 kHz,
48 kHz
– Data Polarity Control
– Power Down
• Multi Functions via H/W Control:
– Audio I/F Format Select: I2S, TDM
– Digital De-Emphasis Filter: 44.1 kHz
• Analog Mute by Clock Halt Detection
2345
•
•
•
•
External RESET Pin
Power Supplies:
– 5 V for Analog and 3.3 V for Digital
Package: HTSSOP-48
Operating Temperature Range:
– –40°C to +85°C
APPLICATIONS
•
•
•
•
•
•
Blu-ray™ DVD Players
HD DVD Players
AV Receivers
Home Theaters
Car Audio External Amplifiers
Car Audio AVN Applications
DESCRIPTION
The PCM1690-Q1 is a high-performance, single-chip,
24-bit, eight-channel, audio digital-to-analog converter
(DAC) with differential outputs. The eight-channel,
24-bit DAC employs an enhanced, multi-level
delta-sigma (ΔΣ) modulator and supports 8-kHz to
192-kHz sampling rates and a 16-/20-/24-/32-bit width
digital audio input word on the audio interface. The
audio interface of the PCM1690-Q1 supports the
time-division-multiplexed (TDM) format in addition to
the standard I2S, left-justified, right-justified, and DSP
formats.
The PCM1690-Q1 can be controlled through a
three-wire, SPI-compatible interface, or two-wire,
I2C-compatible serial interface in software, which
provides access to all functions including digital
attenuation, soft mute, de-emphasis, and so forth.
Also, hardware control mode provides a subset of
user-programmable functions through two control
pins. The PCM1690-Q1 is available in a 12-mm ×
8-mm (12-mm × 6-mm body) HTSSOP-48 package.
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Blu-ray is a trademark of Blu-ray Disk Association.
SPI is a trademark of Motorola.
I2S, I2C are trademarks of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PCM1690-Q1
HTSSOP-48
DCA
–40°C to +85°C
PCM1690Q
PCM1690IDCARQ
1
Tape and Reel, 2000
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
PCM1690-Q1
UNIT
Supply voltage: VCC1, VCC2
PARAMETER
–0.3 to +6.5
V
Supply voltage: VDD
–0.3 to +4.0
V
Ground voltage differences: AGND1, AGND2, DGND
±0.1
V
Supply voltage differences: VCC1, VCC2
±0.1
V
–0.3 to +6.5
V
Digital input voltage:
BCK, LRCK, DIN1/2/3/4, MODE, ZERO1, ZERO2
–0.3 to (VDD + 0.3) < +4.0
V
Analog input voltage: VCOM, VOUT1–8±
–0.3 to (VCC + 0.3) < +6.5
V
Digital input voltage: RST, TEST, MS, MC, MD, SCKI, AMUTEI, AMUTEO
±10
mA
Ambient temperature under bias
–40 to +125
°C
Storage temperature
–55 to +150
°C
Junction temperature
+150
°C
Lead temperature (soldering, 5s)
+260
°C
Package temperature (IR reflow, peak)
+260
°C
Input current (all pins except supplies)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
PCM1690-Q1
MIN
TYP
MAX
UNIT
Analog supply voltage, VCC
PARAMETER
4.5
5.0
5.5
V
Digital supply voltage, VDD
3.0
3.3
3.6
V
Digital Interface
Digital input clock frequency
Analog output voltage
Analog output load resistance
LVTTL compatible
Sampling frequency, LRCK
System clock frequency, SCKI
8
192
kHz
2.048
36.864
MHz
Differential
8
To ac-coupled GND
5
To dc-coupled GND
15
kΩ
kΩ
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature
2
PCM1690-Q1 consumer grade
–40
VPP
+25
50
pF
20
pF
+85
°C
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: Digital Input/Output
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
PCM1690-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DATA FORMAT
I2S, LJ, RJ, DSP, TDM
Audio data interface format
16, 20, 24,
32
Audio data word length
Audio data format
Bits
MSB first, twos complement
Sampling frequency
fS
8
128 fS, 192 fS, 256 fS,
384 fS, 512 fS, 768 fS, 1152 fS
System clock frequency
48
192
kHz
2.048
36.864
MHz
2.0
VDD
VDC
0.8
VDC
5.5
VDC
0.8
VDC
±10
μA
INPUT LOGIC
Input logic level
Input logic level
Input logic current
Input logic current
VIH
(1) (2)
VIL
(1) (2)
VIH
(3) (4)
VIL
(3) (4)
IIH
(2) (3)
IIL
(2) (3)
VIN = 0 V
IIH
(1) (4)
VIN = VDD
IIL
(1) (4)
VIN = 0 V
2.0
VIN = VDD
+65
±10
μA
+100
μA
±10
μA
OUTPUT LOGIC
Output logic level
(5)
IOUT = –4 mA
(5) (6)
IOUT = +4 mA
VOH
VOL
2.4
VDC
0.4
VDC
REFERENCE OUTPUT
VCOM output voltage
VCOM output impedance
0.5 ×
VCC1
V
7.5
kΩ
Allowable VCOM output source/sink current
(1)
(2)
(3)
(4)
(5)
(6)
1
μA
BCK and LRCK (Schmitt trigger input with 50-kΩ typical internal pull-down resistor).
DIN1/2/3/4 (Schmitt trigger input).
SCKI, TEST/ADR1/RSV, MC/SCL/FMT, MD/SDA/DEMP, and AMUTEI (Schmitt trigger input, 5-V tolerant).
RST and MS/ADR0/RSV (Schmitt trigger input with 50-kΩ typical internal pull-down resistor, 5-V tolerant).
ZERO1 and ZERO2.
SDA (I2C mode, open-drain low output) and AMUTEO (open-drain low output).
Copyright © 2011, Texas Instruments Incorporated
3
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: DAC
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
PCM1690-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
16
24
MAX
UNIT
DAC CHARACTERISTICS
Resolution
Bits
DC ACCURACY
Gain mismatch channel-to-channel
±2.0
±6
% of FSR
Gain error
±2.0
±6
% of FSR
Bipolar zero error
±1.0
DYNAMIC PERFORMANCE (1)
% of FSR
(2)
Total harmonic distortion + noise
THD+N
fS = 48 kHz, VOUT = 0 dB
–94
fS = 96 kHz, VOUT = 0 dB
–94
dB
fS = 192 kHz, VOUT = 0 dB
–94
dB
fS = 48 kHz, EIAJ, A-weighted
Dynamic range
Sighnal-to-noise ratio
SNR
dB
113
dB
fS = 96 kHz, EIAJ, A-weighted
113
dB
fS = 192 kHz, EIAJ, A-weighted
113
dB
113
dB
fS = 96 kHz, EIAJ, A-weighted
113
dB
fS = 192 kHz, EIAJ, A-weighted
113
dB
109
dB
fS = 48 kHz, EIAJ, A-weighted
fS = 48 kHz
Channel separation
(between one channel and others)
106
–88
106
103
fS = 96 kHz
109
dB
fS = 192 kHz
108
dB
Differential
1.6 ×
VCC1
VPP
0.5 ×
VCC1
V
ANALOG OUTPUT
Output voltage
Center voltage
Load impedance
To ac-coupled GND (3)
5
To dc-coupled GND (3)
15
LPF frequency response
kΩ
kΩ
f = 20 kHz
–0.04
dB
f = 44 kHz
–0.18
dB
DIGITAL FILTER PERFORMANCE WITH SHARP ROLL-OFF
Passband (single, dual)
Except SCKI = 128 fS and 192 fS
0.454 × fS
Hz
SCKI = 128 fS and 192 fS
0.432 × fS
Hz
0.432 × fS
Hz
Passband (quad)
Stop band (single, dual)
Except SCKI = 128 fS and 192 fS
0.546 × fS
Hz
SCKI = 128 fS and 192 fS
0.569 × fS
Hz
0.569 × fS
Stop band (quad)
Passband ripple
< 0.454 × fS, 0.432 × fS
Stop band attenuation
> 0.546 × fS, 0.569 × fS
(1)
(2)
(3)
4
Hz
±0.0018
–75
dB
dB
In differential mode at VOUTx± pin, fOUT = 1 kHz, using Audio Precision System II, Average mode with 20-kHz LPF and 400-Hz HPF.
fS = 48 kHz: SCKI = 512 fS (single), fS = 96 kHz : SCKI = 256 fS (dual), fS = 192 kHz : SCKI = 128 fS (quad).
Allowable minimum input resistance of differential to single-ended converter with D to S Gain = G is calculated as (1 + 2G)/(1 + G) × 5k
for ac-coupled and (1+ 0.9G)/(1 + G) × 15k for dc-coupled connection; refer to Figure 41 and Figure 42 of the Application Information
section.
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: DAC (continued)
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
PCM1690-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.328 × fS
Hz
DIGITAL FILTER PERFORMANCE WITH SLOW ROLL-OFF
Passband
0.673 × fS
Stop band
Passband ripple
< 0.328 × fS
Stop band attenuation
> 0.673 × fS
Hz
±0.0013
–75
dB
dB
DIGITAL FILTER PERFORMANCE
Group delay time (single, dual)
Except SCKI = 128 fS and 192 fS
28/fS
sec
SCKI = 128 fS and 192 fS
19/fS
sec
Group delay time (quad)
19/fS
sec
De-emphasis error
±0.1
dB
ELECTRICAL CHARACTERISTICS: Power-Supply Requirements
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
PCM1690-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1/2
4.5
5.0
5.5
VDC
VDD
3.0
3.3
3.6
VDC
fS = 48 kHz
74
110
mA
fS = 192 kHz
74
POWER-SUPPLY REQUIREMENTS
Voltage range
ICC
Full power-down
Supply current
(1)
57
fS = 192 kHz
Full power-down
(1)
mA
mA
μA
60
558
fS = 192 kHz
Full power-down
90
76
(1)
fS = 48 kHz
Power dissipation
μA
170
fS = 48 kHz
IDD
mA
847
mW
621
mW
1.05
mW
TEMPERATURE RANGE
Operating temperature
Thermal resistance
(1)
PCM1690-Q1 Consumer grade
θJA
HTSSOP-48
–40
+85
+23
°C
°C/W
SCKI, BCK, and LRCK stopped.
Copyright © 2011, Texas Instruments Incorporated
5
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
PIN CONFIGURATION
DCA PACKAGE
HTSSOP-48 (12 mm x 8 mm)
(TOP VIEW)
RSV2
1
48 RSV2
RSV1
2
47 VCC2
RSV2
3
46 AGND2
RSV1
4
45 RSV2
RSV2
5
44 VOUT1-
LRCK
6
43 VOUT1+
BCK
7
42 VOUT2-
DIN1
8
41 VOUT2+
DIN2
9
40 VOUT3-
DIN3 10
39 VOUT3+
DIN4 11
38 VOUT4-
VDD 12
PCM1690
Thermal Pad
DGND 13
37 VOUT4+
36 VOUT5-
SCKI 14
35 VOUT5+
RST 15
34 VOUT6-
ZERO1 16
33 VOUT6+
ZERO2 17
32 VOUT7-
AMUTEI 18
31 VOUT7+
AMUTEO 19
30 VOUT8-
MD/SDA/DEMP 20
29 VOUT8+
28 RSV2
MC/SCL/FMT 21
27 AGND1
MS/ADR0/RSV 22
26 VCOM
TEST/ADR1/RSV 23
25 VCC1
MODE 24
TERMINAL FUNCTIONS
TERMINAL
NAME
PIN
I/O
PULLDOWN
5-V
TOLERANT
RSV2
1
—
—
—
Reserved, tied to analog ground
RSV1
2
—
—
—
Reserved, left open
RSV2
3
—
—
—
Reserved, tied to analog ground
RSV1
4
—
—
—
Reserved, left open
RSV2
5
—
—
—
Reserved, tied to analog ground
LRCK
6
I
Yes
No
Audio data word clock input
BCK
7
I
Yes
No
Audio data bit clock input
DIN1
8
I
No
No
Audio data input for DAC1 and DAC2
DIN2
9
I
No
No
Audio data input for DAC3 and DAC4
DIN3
10
I
No
No
Audio data input for DAC5 and DAC6
DIN4
11
I
No
No
Audio data input for DAC7 and DAC8
6
DESCRIPTION
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
PIN
I/O
PULLDOWN
5-V
TOLERANT
VDD
12
—
—
—
Digital power supply, +3.3 V
DGND
13
—
—
—
Digital ground
SCKI
14
I
No
Yes
System clock input
RST
15
I
Yes
Yes
Reset and power-down control input with active low
ZERO1
16
O
No
No
Zero detect flag output 1
ZERO2
17
O
No
No
Zero detect flag output 2
AMUTEI
18
I
No
Yes
Analog mute control input with active low
AMUTEO
19
O
No
Yes
Analog mute status output (1) with active low
MD/SDA/DEMP
20
I/O
No
Yes
Input data for SPI, data for I2C (1), de-emphasis control for hardware
control mode
MC/SCL/FMT
21
I
No
Yes
Clock for SPI, clock for I2C, format select for hardware control mode
MS/ADR0/RSV
22
I
Yes
Yes
Chip Select for SPI, address select 0 for I2C, reserve (set low) for
hardware control mode
TEST/ADR1/RSV
23
I/O
No
Yes
Test (factory use, left open) for SPI, address select 1 for I2C,
reserve (set low) for hardware control mode
MODE
24
I
No
No
Control port mode selection. Tied to VDD: SPI, left open: H/W
mode, tied to DGND: I2C
VCC1
25
—
—
—
Analog power supply 1, +5 V
VCOM
26
—
—
—
Voltage common decoupling
AGND1
27
—
—
—
Analog ground 1
RSV2
28
—
—
—
Reserved, tied to analog ground
VOUT8+
29
O
No
No
Positive analog output from DAC8
VOUT8-
30
O
No
No
Negative analog output from DAC8
VOUT7+
31
O
No
No
Positive analog output from DAC7
VOUT7-
32
O
No
No
Negative analog output from DAC7
VOUT6+
33
O
No
No
Positive analog output from DAC6
VOUT6-
34
O
No
No
Negative analog output from DAC6
VOUT5+
35
O
No
No
Positive analog output from DAC5
VOUT5-
36
O
No
No
Negative analog output from DAC5
VOUT4+
37
O
No
No
Positive analog output from DAC4
VOUT4-
38
O
No
No
Negative analog output from DAC4
VOUT3+
39
O
No
No
Positive analog output from DAC3
VOUT3-
40
O
No
No
Negative analog output from DAC3
VOUT2+
41
O
No
No
Positive analog output from DAC2
VOUT2-
42
O
No
No
Negative analog output from DAC2
VOUT1+
43
O
No
No
Positive analog output from DAC1
VOUT1-
44
O
No
No
Negative analog output from DAC1
RSV2
45
—
—
—
Reserved, tied to analog ground
AGND2
46
—
—
—
Analog ground 2
VCC2
47
—
—
—
Analog power supply 2, +5 V
RSV2
48
—
—
—
Reserved, tied to analog ground
(1)
DESCRIPTION
Open-drain configuration in out mode.
Copyright © 2011, Texas Instruments Incorporated
7
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VOUT1+
DIN1
DIN2
DIN3
DIN4
BCK
LRCK
Audio Interface
SCKI
SCK Manager
DAC
VOUT1VOUT2+
DAC
VOUT2VOUT3+
TEST/ADR1/RSV
MS/ADR0/RSV
MC/SCL/FMT
MD/SDA/DEMP
MODE
ZERO1
ZERO2
AMUTEI
AMUTEO
RST
VCC1
AGND1
VCC2
AGND2
VDD
DGND
VCOM
8
DAC
VOUT3VOUT4+
DAC
Control Interface
2
(SPI/I C/HW)
VOUT4-
Digital Filter
and
Volume
VOUT5+
DAC
VOUT5VOUT6+
DAC
VOUT6VOUT7+
DAC
VOUT7-
Power Supply and
Common Voltage
VOUT8+
DAC
VOUT8-
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: Digital Filter
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
FREQUENCY RESPONSE
(Single Rate)
FREQUENCY RESPONSE PASSBAND
(Single Rate)
0
0.010
Sharp
Slow
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
1
2
-0.010
4
3
0
0.1
Normalized Frequency (fS)
0.4
Figure 2.
FREQUENCY RESPONSE
(Dual Rate)
FREQUENCY RESPONSE PASSBAND
(Dual Rate)
0.5
0.010
Sharp
Slow
-20
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
0.3
Figure 1.
0
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
1
2
-0.010
4
3
0
0.1
Normalized Frequency (fS)
0.2
0.3
0.4
0.5
Normalized Frequency (fS)
Figure 3.
Figure 4.
FREQUENCY RESPONSE
(Quad Rate)
FREQUENCY RESPONSE PASSBAND
(Quad Rate)
0.010
0
Sharp
Slow
-20
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
0.2
Normalized Frequency (fS)
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
0.5
1.0
Normalized Frequency (fS)
Figure 5.
Copyright © 2011, Texas Instruments Incorporated
1.5
2.0
-0.010
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (fS)
Figure 6.
9
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: Digital De-Emphasis Filter
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
DE-EMPHASIS CHARACTERISTIC
(fS = 44.1 kHz)
0
0
-1
-1
-2
-2
-3
-3
Amplitude (dB)
Amplitude (dB)
DE-EMPHASIS CHARACTERISTIC
(fS = 48 kHz)
-4
-5
-6
-4
-5
-6
-7
-7
-8
-8
-9
-9
-10
-10
0
4
2
6
8
10
12
14
16
18
20
22
0
2
4
6
Frequency (kHz)
8
10
12
14
16
18
20
Frequency (kHz)
Figure 7.
Figure 8.
DE-EMPHASIS CHARACTERISTIC
(fS = 32 kHz)
ANALOG FILTER CHARACTERISTIC
0
0
-1
-10
-3
Amplitude (dB)
Amplitude (dB)
-2
-4
-5
-6
-20
-30
-7
-8
-40
-9
-10
0
2
4
6
8
Frequency (kHz)
Figure 9.
10
10
12
14
-50
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 10.
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: Dynamic Performance
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
DYNAMIC RANGE AND SNR
vs
TEMPERATURE
THD+N
vs
TEMPERATURE
118
Dynamic Range and SNR (dB)
-90
THD+N (dB)
-92
-94
-96
-98
-100
116
Dynamic Range
114
SNR
112
110
108
106
-102
-40
-15
35
10
60
85
-40
-15
Temperature (°C)
Figure 12.
THD+N
vs
SUPPLY VOLTAGE
DYNAMIC RANGE AND SNR
vs
SUPPLY VOLTAGE
85
Dynamic Range and SNR (dB)
118
-92
THD+N (dB)
60
Figure 11.
-90
-94
-96
-98
-100
-102
4.50
35
10
Temperature (°C)
4.75
5.00
Supply Voltage (V)
Figure 13.
Copyright © 2011, Texas Instruments Incorporated
5.25
5.50
116
Dynamic Range
114
SNR
112
110
108
106
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Figure 14.
11
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: Output Spectrum
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
Mode = Auto, unless otherwise noted.
OUTPUT SPECTRUM
(–60 dB, N = 32768)
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
OUTPUT SPECTRUM
(0 dB, N = 32768)
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
20
15
10
0
5
10
Frequency (kHz)
Frequency (kHz)
Figure 15.
Figure 16.
15
20
OUTPUT SPECTRUM
(BPZ, N = 32768)
0
-20
Amplitude (dB)
-40
-60
-80
-100
-120
-140
-160
0
5
10
15
20
Frequency (kHz)
Figure 17.
12
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PCM1690-Q1
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PRODUCT OVERVIEW
The PCM1690-Q1 is a high-performance, multi-channel DAC targeted for consumer audio applications such as
Blu-ray DVD players and HD DVD players, as well as home multi-channel audio applications (such as home
theaters and A/V receivers). The PCM1690-Q1 consists of an eight-channel DAC. The DAC output type is fixed
with a differential configuration. The PCM1690-Q1 supports 16-/20-/24-/32-bit linear PCM input data in I2S- and
left-justified audio formats, and 24-bit linear PCM input data in right-justified, DSP, and TDM formats for various
sampling frequencies from 8 kHz to 192 kHz. The TDM format is useful for saving bus line interface numbers for
multi-channel audio data communication between the DAC and a digital audio processor. The PCM1690-Q1
offers three modes for device control: two-wire I2C software, three-wire SPI software, and hardware modes.
ANALOG OUTPUTS
The PCM1690-Q1 includes eight DACs, each with individual pairs of differential voltage outputs pins. The
full-scale output voltage is (1.6 × VCC1) VPP at the differential output mode. A dc-coupled load is allowed in
addition to an ac-coupled load if the load resistance conforms to the specification. These balanced outputs are
each capable of driving 0.8 VCC1 (4 VPP) typical into a 5-kΩ, ac-coupled or 15-kΩ, dc-coupled load with VCC1 =
+5 V. The internal output amplifiers for VOUT1 through VOUT8 are biased to the dc common voltage, equal to
(0.5 × VCC1).
The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy
present at the DAC outputs as a result of the noise shaping characteristics of the PCM1690-Q1 delta-sigma (ΔΣ)
DACs. The frequency response of this filter is shown in the Analog Filter Characteristic (Figure 10) of the Typical
Characteristics. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for
most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further
discussion of DAC post-filter circuits is provided in the Application Information section.
Table 1. Pin Assignments in Differential Output Mode
DIGITAL INPUT
DIN1
DIN2
DIN3
DIN4
CHANNEL
DIFFERENTIAL OUTPUT
1 (DAC1)
VOUT1+, VOUT1–
2 (DAC2)
VOUT2+, VOUT2–
3 (DAC3)
VOUT3+, VOUT3–
4 (DAC4)
VOUT4+, VOUT4–
5 (DAC5)
VOUT5+, VOUT5–
6 (DAC6)
VOUT6+, VOUT6–
7 (DAC7)
VOUT7+, VOUT7–
8 (DAC8)
VOUT8+, VOUT8–
VOLTAGE REFERENCE VCOM
The PCM1690-Q1 includes a pin for the common-mode voltage output, VCOM. This pin should be connected to
the analog ground via a decoupling capacitor. This pin can also be used to bias external high-impedance circuits,
if they are required.
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SYSTEM CLOCK INPUT
The PCM1690-Q1 requires an external system clock input applied at the SCKI input for DAC operation. The
system clock operates at an integer multiple of the sampling frequency, or fS. The multiples supported in DAC
operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, and 1152 fS. Details for these system clock
multiples are shown in Table 2. Figure 18 and Table 3 show the SCKI timing requirements.
Table 2. System Clock Frequencies for Common Audio Sampling Rates
DEFAULT
SAMPLING
MODE
SAMPLING
FREQUENCY
SYSTEM CLOCK FREQUENCY (MHz)
fS (kHz)
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
8
N/A
N/A
2.0480
3.0720
4.0960
6.1440
9.2160
16
2.0480
3.0720
4.0960
6.1440
8.1920
12.2880
18.4320
Single rate
Dual rate
Quad rate
1152 fS
32
4.0960
6.1440
8.1920
12.2880
16.3840
24.5760
36.8640
44.1
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
N/A
48
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
N/A
88.2
11.2896
16.9344
22.5792
33.8688
N/A
N/A
N/A
96
12.2880
18.4320
24.5760
36.8640
N/A
N/A
N/A
176.4
22.5792
33.8688
N/A
N/A
N/A
N/A
N/A
192
24.5760
36.8640
N/A
N/A
N/A
N/A
N/A
tSCH
High
2.0 V
Low
0.8 V
System Clock
(SCKI)
tSCL
tSCY
Figure 18. System Clock Timing Requirements
Table 3. Timing Requirements for Figure 18
SYMBOL
14
PARAMETER
MIN
MAX
UNIT
tSCY
System clock cycle time
27
ns
tSCH
System clock width high
10
ns
tSCL
System clock width low
10
ns
—
System clock duty cycle
40
60
%
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
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SAMPLING MODE
The PCM1690-Q1 supports three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In
single rate mode, the DAC operates at an oversampling frequency of x128 (except when SCKI = 128 fS and 192
fS). This mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the DAC operates at
an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad
rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected
according to the ratio of system clock frequency and sampling frequency by default (that is, single rate for 512 fS,
768 fS, and 1152 fS; dual rate for 256 fS and 384 fS; and quad rate for 128 fS and 192 fS), but manual selection is
also possible for specified combinations through the serial mode control register.
Table 4 and Figure 19 show the relation among the oversampling rate (OSR) of the digital filter and ΔΣ
modulator, the noise-free shaped bandwidth, and each sampling mode setting.
Table 4. DAC Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth for Each Sampling Mode
SAMPLING
MODE
REGISTER
SETTING
Auto
Single
NOISE-FREE SHAPED BANDWIDTH (kHz) (1)
SYSTEM CLOCK
FREQUENCY
(xfS)
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
DIGITAL FILTER
OSR
MODULATOR
OSR
512, 768, 1152
40
N/A
N/A
×8
x128
x64
256, 384
20
40
N/A
x8
128, 192 (2)
10
20
40
x4
x32
512, 768, 1152
40
N/A
N/A
x8
x128
256, 384
40
N/A
N/A
x8
x128
128, 192
Dual
Quad
(1)
(2)
(2)
20
N/A
N/A
x4
x64
256, 384
20
40
N/A
x8
x64
128, 192 (2)
20
40
N/A
x4
x64
(2)
10
20
40
x4
x32
128, 192
Bandwidth in which noise is shaped out.
Quad mode filter characteristic is applied.
0
DSM_Single
DSM_Dual
DSM_Quad
-20
Amplitude (dB)
-40
DF_Single
DF_Dual
DF_Quad
-60
-80
-100
-120
-140
-160
-180
-200
0
0.5
1.0
1.5
2.0
Normalized Frequency (fS)
Figure 19. ΔΣ Modulator and Digital Filter Characteristic
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RESET OPERATION
The PCM1690-Q1 has both an internal power-on reset circuit and an external reset circuit. The sequences for
both reset circuits are illustrated in Figure 20 and Figure 21. Figure 20 describes the timing at the internal
power-on reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the
internal reset is released after 3846 SCKI clock cycles from power-on if RST is held high and SCKI is provided.
VOUT from the DACs are forced to the VCOM level initially (that is, 0.5 × VCC1) and settle at a specified level
according to the rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an
output that corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the
internal reset is not released, and both operating modes are maintained at reset and power-down states; after
synchronization forms again, the DAC returns to normal operation with the previous sequences.
Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low,
and provides a device reset and power-down state that achieves the lowest power dissipation state available in
the PCM1690-Q1. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the
internal reset is asserted, all registers and memory are reset, and finally the PCM1690-Q1 enters into all
power-down states. At the same time, VOUT is immediately forced into the AGND1 level. To begin normal
operation again, toggle RST high; the same power-up sequence is performed as the power-on reset shown in
Figure 20.
The PCM1690-Q1 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then
VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however,
simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the
response for VCC on with VDD on.
(VDD = 3.3 V, typ)
VDD
0V
(VDD = 2.2 V, typ)
SCKI,
BCK,
LRCK
RST
Synchronous Clocks
3846 ´ SCKI
Normal Operation
Internal Reset
VOUT1± to
VOUT8±
0.5 ´ VCC
VCOM
(0.5 ´ VCC1)
Figure 20. Power-On-Reset Timing Requirements
(VDD = 3.3 V, typ)
VDD
SCKI,
BCK,
LRCK
0V
Synchronous Clocks
Synchronous Clocks
100 ns (min)
RST
3846 ´ SCKI
Internal Reset
Normal Operation
Power-Down
Normal Operation
VOUT1± to
VOUT8±
0.5 ´ VCC
Figure 21. External Reset Timing Requirements
16
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
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AUDIO SERIAL PORT OPERATION
The PCM1690-Q1 audio serial port consists of six signals: BCK, LRCK, DIN1, DIN2, DIN3, and DIN4. BCK is a
bit clock input. LRCK is a left/right word clock input or frame synchronization clock input. DIN1/2/3/4 are the
audio data inputs for VOUT1–8.
AUDIO DATA INTERFACE FORMATS AND TIMING
The PCM1690-Q1 supports 10 audio data interface formats: 16-/20-/24-/32-bit I2S, 16-/20-/24-/32-bit left-justified,
24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I2S mode DSP, 24-bit left-justified
mode TDM, 24-bit I2S mode TDM, 24-bit left-justified mode high-speed TDM, and 24-bit I2S mode high-speed
TDM. In the case of I2S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per
LRCK period are supported; but 48 BCKs are limited in 192/384/768 fS SCKI, and 32 BCKs are limited in 16-bit
right-justified only. In the case of TDM data format in single rate, BCK, LRCK, and DIN1 are used. In the case of
TDM data format in dual rate, BCK, LRCK, and DIN1/2 are used. In the case of high-speed TDM format in dual
rate, BCK, LRCK, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCK, LRCK, and
DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 fS, 256 fS, 128 fS,
and fBCK ≤ fSCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by control
register settings in software control mode. All data must be in binary twos complement and MSB first.
Table 5 summarizes the applicable formats and describes the relationships among them and the respective
restrictions with mode control. Figure 22 through Figure 28 show 10 audio interface data formats.
Table 5. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions
CONTROL
MODE
FORMAT
DATA BITS
MAX LRCK
FREQUENCY (fS)
SCKI RATE (xfS)
BCK RATE (xfS)
APPLICABLE PINS
I2S/Left-Justified
16/20/24/32 (1)
192 kHz
128 to 1152 (2)
64, 48
DIN1/2/3/4
Right-Justified
24, 16
192 kHz
128 to 1152 (2)
64, 48, 32 (16 bit) (3)
DIN1/2/3/4
I S/Left-Justified DSP
24
192 kHz
128 to 768
64
DIN1/2/3/4
24
48 kHz
256, 512
256
DIN1
24
96 kHz
128, 256
128
DIN1/2
2
Software
control
I2S/ Left-Justified TDM
High-Speed
I2S/Left-Justified TDM
24
96 kHz
256
256
DIN1
24
192 kHz
128
128
DIN1/2
I2S
16/20/24/32 (1)
192 kHz
128 to 1152 (2)
64, 48
DIN1/2/3/4
24
48 kHz
512
256
DIN1
24
96 kHz
256
128
DIN1/2
Hardware
control
(1)
(2)
(3)
I2S TDM
32-bit data length is acceptable only for BCK = 64 fS and when using I2S and Left-Justified format.
1152 fS is acceptable only for fS = 32 kHz, BCK = 64 fS, and when using I2S, Left-Justified, and 24-bit Right-Justified format.
BCK = 32 fS is supported only for 16-bit data length.
Ch 1 (DIN1) or Ch 3 (DIN2)
Ch 5 (DIN3) or Ch 7 (DIN4)
LRCK
Ch 2 (DIN1) or Ch 4 (DIN2)
Ch 6 (DIN3) or Ch 8 (DIN4)
BCK
DIN1/2/3/4
N M L
2
1 0
LSB
MSB
N M L
MSB
2
1 0
LSB
Figure 22. Audio Data Format: 16-/20-/24-/32-Bit I2S
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
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LRCK
Ch 2 (DIN1) or Ch 4 (DIN2)
Ch 6 (DIN3) or Ch 8 (DIN4)
Ch 1 (DIN1) or Ch 3 (DIN2)
Ch 5 (DIN3) or Ch 7 (DIN4)
BCK
DIN1/2/3/4
N M L
2
N M L
1 0
LSB
MSB
1 0
2
N
LSB
MSB
Figure 23. Audio Data Format: 16-/20-/24-/32-Bit Left-Justified
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
Ch 2 (DIN1) or Ch 4 (DIN2)
Ch 6 (DIN3) or Ch 8 (DIN4)
Ch 1 (DIN1) or Ch 3 (DIN2)
Ch 5 (DIN3) or Ch 7 (DIN4)
LRCK
BCK
DIN1/2/3/4
0
23 22 21
2
MSB
1
0
23 22 21
LSB
2
MSB
1
0
LSB
Figure 24. Audio Data Format: 24-Bit Right-Justified
LRCK
Ch 2 (DIN1) or Ch 4 (DIN2)
Ch 6 (DIN3) or Ch 8 (DIN4)
Ch 1 (DIN1) or Ch 3 (DIN2)
Ch 5 (DIN3) or Ch 7 (DIN4)
BCK
DIN1/2/3/4
15 14 13
0
2
MSB
1 0
15 14 13
LSB
2
MSB
1 0
LSB
Figure 25. Audio Data Format: 16-Bit Right-Justified
1/fS (64 BCKs)
Ch 1 (DIN1) or Ch 3 (DIN2)
Ch 5 (DIN3) or Ch 7 (DIN4)
LRCK
Ch 2 (DIN1) or Ch 4 (DIN2)
Ch 6 (DIN3) or Ch 8 (DIN4)
BCK
Left-Justified Mode
DIN1/2/3/4
23 22 21
2
1
0
2
1
23 22 21
2
1
0
2
1
23 22 21
2
I S Mode
DIN1/2/3/4
23 22 21
0
23 22 21
0
23 22
Figure 26. Audio Data Format: 24-Bit DSP Format
18
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SBAS551 – JUNE 2011
www.ti.com
1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)
LRCK
BCK
Left-Justified Mode
DIN1
(Single)
2
I S Mode
DIN1
(Single)
Left-Justified Mode
DIN1/2
(Dual)
23 22
23 22
23 22
0
23 22
Ch 2
32 BCKs
0
23 22
23 22
0
1 0
23 22
0
23 22
Ch 3
32 BCKs
23 22
0
23 22
Ch 4
32 BCKs
0
23 22
Ch 1/Ch 5
32 BCKs
2
I S Mode
DIN1/2
(Dual)
0
Ch 1
32 BCKs
23 22
0
1 0
23 22
23 22
23 22
0
23 22
Ch 6
32 BCKs
0
23 22
Ch 2/Ch 6
32 BCKs
1 0
0
Ch 5
32 BCKs
23 22
0
23 22
Ch 7
32 BCKs
0
1 0
23 22
0
23 22
23 22
23 22
23 22
0
1 0
Ch 3/Ch 7
32 BCKs
1 0
0
Ch 8
32 BCKs
23 22
23 22
Ch 4/Ch 8
32 BCKs
1 0
23 22
1 0
23 22
Figure 27. Audio Data Format: 24-Bit TDM Format (SCKI = 128 fS, 256 fS, and 512 fS Only)
1/fS (256 BCKs at Dual Rate, 128 BCKs at Quad Rate)
LRCK
BCK
Left-Justified Mode
DIN1
(Dual)
2
I S Mode
DIN1
(Dual)
Left-Justified Mode
DIN1/2
(Quad)
23 22
23 22
23 22
23 22
0
23 22
Ch 2
32 BCKs
0
23 22
1 0
23 22
1 0
0
23 22
Ch 3
32 BCKs
0
23 22
23 22
Ch 1/Ch 5
32 BCKs
2
I S Mode
DIN1/2
(Quad)
0
Ch 1
32 BCKs
0
23 22
Ch 4
32 BCKs
0
23 22
1 0
0
23 22
23 22
Ch 2/Ch 6
32 BCKs
23 22
1 0
0
23 22
Ch 5
32 BCKs
0
23 22
Ch 6
32 BCKs
0
23 22
1 0
0
23 22
1 0
23 22
0
23 22
Ch 8
32 BCKs
0
23 22
Ch 3/Ch 7
32 BCKs
23 22
0
Ch 7
32 BCKs
23 22
1 0
0
23 22
23 22
Ch 4/Ch 8
32 BCKs
23 22
1 0
23 22
Figure 28. Audio Data Format: 24-Bit High-Speed TDM Format
(SCKI = 128 fS and 256 fS Only)
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AUDIO INTERFACE TIMING
Figure 29 and Figure 30 describe the detailed interface timing specifications.
tBCH
tBCL
BCK
(Input)
1.4 V
tBCY
tLRH
tLRS
LRCK
(Input)
1.4 V
tDIS
tDIH
DIN1/2/3/4
1.4 V
Figure 29. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats
Table 6. Timing Requirements for Figure 29
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tBCY
BCK cycle time
75
ns
tBCH
BCK pulse width high
35
ns
tBCL
BCK pulse width low
35
ns
tLRS
LRCK setup time to BCK rising edge
10
ns
tLRH
LRCK hold time to BCK rising edge
10
ns
tDIS
DIN1/2/3/4 setup time to BCK rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCK rising edge
10
ns
tBCL
tBCH
BCK
(Input)
1.4 V
tBCY
tLRH
tLRS
LRCK
(Input)
1.4 V
tDIS
tLRW
tDIH
DIN1/2/3/4
1.4 V
Figure 30. Audio Interface Timing Requirements for DSP and TDM Data Formats
Table 7. Timing Requirements for Figure 30
SYMBOL
MIN
TYP
MAX
UNIT
BCK cycle time
40
ns
tBCH
BCK pulse width high
15
ns
tBCL
BCK pulse width low
15
ns
LRCK pulse width high (DSP format)
tBCY
tBCY
LRCK pulse width high (TDM format)
tBCY
1/fS – tBCY
tLRS
LRCK setup time to BCK rising edge
10
ns
tLRH
LRCK hold time to BCK rising edge
10
ns
tDIS
DIN1/2/3/4 setup time to BCK rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCK rising edge
10
ns
tLRW
20
DESCRIPTION
tBCY
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PCM1690-Q1
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SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
The PCM1690-Q1 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore,
SCKI and LRCK must have a specific relationship. The PCM1690-Q1 does not need a specific phase
relationship between the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a
specific frequency relationship (ratiometric) between LRCK, BCK, and SCKI.
If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling
frequency change, etc., the DAC internal operation stops within 1/fS, and the analog output is forced into VCOM
(0.5 VCC1) until re-synchronization between SCKI, LRCK, and BCK completes and then 38/fS (single, dual rate)
or 29/fS (quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not occur,
and this analog output control and discontinuity does not occur.
Figure 31 shows the DAC analog output during loss of synchronization. During undefined data periods, some
noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or
zero) data to normal data creates a discontinuity of data on the analog outputs, which then may generate some
noise in the audio signal.
DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and
re-synchronization processes will occur after the system clock resumes.
State of
Synchronization
Synchronous
Asynchronous
Within 1/fS
Undefined Data
DAC
VOUTX±
VCOM
(0.5 VCC1)
Synchronous
38/fS (single, dual rate)
29/fS (quad rate)
Normal
Normal
Figure 31. DAC Outputs During Loss of Synchronization
ZERO FLAG
The PCM1690-Q1 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations
shown in Table 8. Zero flag combinations are selected through control register settings. If the input data of the
left and right channel of all assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the
ZERO1/2 bits are set to a high level, logic '1' state. Furthermore, if the input data of any channels of assigned
channels read '1', the ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is
supported for 16-/20-/24-bit data width, but is not supported for 32-bit data width.
The active polarity of the zero flag output can be inverted through control register settings. The reset default is
active high for zero detection. In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination
A shown in Table 8.
Table 8. Zero Flag Outputs Combination
ZERO FLAG COMBINATION
ZERO1
ZERO2
A
DATA1, left channel
DATA1, right channel
B
DATA1–4
DATA1–4
C
DATA4
DATA1–3
D
DATA1
DATA2–4
AMUTE CONTROL
The PCM1690-Q1 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control
pin of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital
input and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute
circuit. AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such
as an SCKI halt, asynchronous detect, zero detect, or issue with the DAC disable command) that forces the DAC
outputs to a center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output,
pull-ups by the appropriate resistors are required for proper operation.
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Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA
when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down
control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even
if the power-down control is asserted.
MODE CONTROL
The PCM1690-Q1 includes three mode control interfaces with two oversampling configurations, depending on
the input state of the MODE pin, as shown in Table 9. The pull-up and pull-down resistors must each be less
than 10 kΩ.
Table 9. Mode Control Selection
MODE
Tied to DGND, low
Left open
Tied to VDD, high
MODE CONTROL INTERFACE
2
Two-wire (I C) serial control, selectable oversampling configuration
Two-wire parallel control, auto mode oversampling configuration
Three-wire (SPI) serial control, selectable oversampling configuration
The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the
RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or
reset. From the mode control selection described in Table 9, the functions of four pins are changed, as shown in
Table 10.
Table 10. Pin Functions for Interface Mode
PIN ASSIGNMENTS
PIN
SPI
I2C
H/W
20
MD (input)
SDA (input/output)
DEMP (input)
21
MC (input)
SCL (input)
FMT (input)
22
MS (input)
ADR0 (input)
RSV (input, low)
23
Test (output, open)
ADR1 (input)
RSV (input, low)
In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or
I2C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through
the high/low control of two specific pins, as described in the following section.
PARALLEL HARDWARE CONTROL
The functions shown in Table 11 and Table 12 are controlled by two pins, DEMP and FMT, in parallel hardware
control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of all eight channels. The FMT
pin controls the audio interface format for all eight channels.
Table 11. DEMP Functionality
DEMP
DESCRIPTION
Low
De-emphasis off
High
44.1 kHz de-emphasis on
Table 12. FMT Functionality
FMT
DESCRIPTION
Low
16-/20-/24-/32-bit I2S format
High
24-bit I2S mode TDM format
THREE-WIRE (SPI) SERIAL CONTROL
The PCM1690-Q1 includes an SPI-compatible serial port that operates asynchronously with the audio serial
interface. The control interface consists of MD/SDA/DEMP, MC/SCL/FMT, and MS/ADR0/RSV. MD is the serial
data input to program the mode control registers. MC is the serial bit clock that shifts the data into the control
port. MS is the select input to enable the mode control port.
22
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CONTROL DATA WORD FORMAT
All single write operations via the serial control port use 16-bit data words. Figure 32 shows the control data word
format. The first bit (fixed at '0') is for write controls; after the first bit are seven other bits, labeled ADR[6:0] that
set the register address for the write operation. The eight least significant bits (LSBs), D[7:0] on MD, contain the
data to be written to the register specified by ADR[6:0].
MSB
0
LSB
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
D6
D7
D5
Register Address
D3
D4
D2
D1
D0
Register Data
Figure 32. Control Data Word Format for MD
REGISTER WRITE OPERATION
Figure 33 shows the functional timing diagram for single write operations on the serial control port. MS is held at
a high state until a register is to be written. To start the register write cycle, MS is set to a low state. 16 clocks
are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the 16th clock cycle
has been completed, MS is set high to latch the data into the indexed mode control register.
Also, the PCM1690-Q1 supports multiple write operations in addition to single write operations, which can be
performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and
register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation can be
accomplished by setting MS to a high state.
MS
MC
MD
X
(1)
'0'
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
ADR6
(1) X = don't care.
Figure 33. Register Write Operation
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TIMING REQUIREMENTS
Figure 34 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are
critical for proper control port operation.
tMHH
MS
1.4 V
tMCH
tMSS
tMCL
tMSH
MC
1.4 V
tMCY
tMDS
ADR0
MSB (R/W)
MD
tMDH
LSB (D0)
D7
1.4 V
Figure 34. Three-Wire Serial Control Interface Timing
Table 13. Timing Requirements for Figure 34
SYMBOL
PARAMETER
MIN
MAX
UNIT
tMCY
MC pulse cycle time
100
ns
tMCL
MC low-level time
40
ns
tMCH
MC high-level time
40
ns
tMHH
MS high-level time
tMCY
ns
tMSS
MS falling edge to MC rising edge
30
ns
tMSH
MS rising edge from MC rising edge for LSB
15
ns
tMDH
MD hold time
15
ns
tMDS
MD setup time
15
ns
TWO-WIRE (I2C) SERIAL CONTROL
The PCM1690-Q1 supports an I2C-compatible serial bus and data transmission protocol for fast mode configured
as a slave device. This protocol is explained in the I2C specification 2.0.
The PCM1690-Q1 has a 7-bit slave address, as shown in Figure 35. The first five bits are the most significant
bits (MSB) of the slave address and are factory-preset to '10011'. The next two bits of the address byte are
selectable bits that can be set by MS/ADR0/RSV and TEST/ADR1/RSV. A maximum of four PCM1690-Q1s can
be connected on the same bus at any one time. Each PCM1690-Q1 responds when it receives its own slave
address.
MSB
1
LSB
0
0
1
1
ADR1
ADR0
R/W
Figure 35. Slave Address
24
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PACKET PROTOCOL
A master device must control the packet protocol, which consists of a start condition, slave address with the
read/write bit, data if a write operation is required, acknowledgment if a read operation is required, and stop
condition. The PCM1690-Q1 supports both slave receiver and transmitter functions. Details about DATA for both
write and read operations are described in Figure 36.
SDA
SCL
1 to 7
St
Slave Address
8
9
(1)
R/W
ACK
1 to 8
(2)
(3)
DATA
9
1 to 8
9
9
ACK
DATA
ACK
ACK
Sp
Start
Condition
Stop
Condition
(1) R/W: Read operation if '1'; write operation otherwise.
(2) ACK: Acknowledgment of a byte if '0', not Acknowledgment of a byte if '1'.
(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.
Figure 36. I2C Packet Control Protocol
WRITE OPERATION
The PCM1690-Q1 supports a receiver function. A master device can write to any PCM1690-Q1 register using
single or multiple accesses. The master sends a PCM1690-Q1 slave address with a write bit, a register address,
and the data. If multiple access is required, the address is that of the starting register, followed by the data to be
transferred. When valid data are received, the index register automatically increments by one. When the register
address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1690-Q1 does
not send an acknowledgment. Figure 37 illustrates a diagram of the write operation. The register address and
write data are in 8-bit, MSB-first format.
Transmitter
M
M
M
S
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
W
ACK
Reg Address
ACK
Write Data 1
ACK
Write Data 2
ACK
ACK
Sp
NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.
Figure 37. Framework for Write Operation
READ OPERATION
A master device can read the registers of the PCM1690-Q1. The value of the register address is stored in an
indirect index register in advance. The master sends the PCM1690-Q1 slave address with a read bit after storing
the register address. Then the PCM1690-Q1 transfers the data that the index register points to. Figure 38 shows
a diagram of the read operation.
Transmitter
M
M
Data Type
St
Slave Address
M
S
M
S
M
M
M
S
S
M
M
W
ACK
Reg Address
ACK
Sr
Slave Address
R
ACK
Read Data
NACK
Sp
NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,
NACK = Not acknowledge, and Sp = Stop condition.
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 38. Framework for Read Operation
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TIMING REQUIREMENTS: SCL AND SDA
A detailed timing diagram for SCL and SDA is shown in Figure 39.
Repeated
START
START
tBUF
STOP
tD-HD
tD-SU
tSDA-R
tP-SU
SDA
tSCL-R
tSDA-F
tS-HD
tLOW
SCL
tSCL-F
tS-HD
tHI
tS-SU
Figure 39. SCL and SDA Control Interface Timing
Table 14. Timing Requirements for Figure 39
STANDARD MODE
SYMBOL
PARAMETER
MIN
MAX
FAST MODE
MIN
UNIT
400
kHz
SCL clock frequency
tBUF
Bus free time between STOP and START condition
4.7
1.3
μs
tLOW
Low period of the SCL clock
4.7
1.3
μs
tHI
High period of the SCL clock
4.0
0.6
μs
tS-SU
Setup time for START/Repeated START condition
4.7
0.6
μs
tS-HD
Hold time for START/Repeated START condition
4.0
0.6
μs
tD-SU
Data setup time
250
100
ns
tD-HD
Data hold time
0
3450
0
900
ns
tSCL-R
Rise time of SCL signal
1000
20 + 0.1 CB
300
ns
tSCL-F
Fall time of SCL signal
1000
20 + 0.1 CB
300
ns
tSDA-R
Rise time of SDA signal
1000
20 + 0.1 CB
300
ns
tSDA-F
Fall time of SDA signal
1000
20 + 0.1 CB
300
tP-SU
Setup time for STOP condition
tGW
Allowable glitch width
N/A
50
CB
Capacitive load for SDA and SCL line
400
100
VNH
Noise margin at high level for each connected device
(including hysteresis)
0.2 × VDD
0.2 × VDD
V
VNL
Noise margin at low level for each connected device
(including hysteresis)
0.1 × VDD
0.1 × VDD
V
VHYS
Hysteresis of Schmitt trigger input
N/A
0.05 × VDD
V
26
100
MAX
fSCL
4.0
ns
μs
0.6
pF
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PCM1690-Q1
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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)
The PCM1690-Q1 has many user-programmable functions that are accessed via control registers, and are
programmed through the SPI or I2C serial control port. Table 15 shows the available mode control functions
along with reset default conditions and associated register address. Table 16 lists the register map.
Table 15. User-Programmable Mode Control Functions
RESET DEFAULT
REGISTER
LABEL
Mode control register reset
FUNCTION
Normal operation
64
MRST
System reset
Normal operation
64
SRST
Mute disabled
64
AMUTE[3:0]
Analog mute function control
Sampling mode selection
Auto
64
SRDA[1:0]
Power save
65
PSMDA
2
I S
65
FMTDA[3:0]
Normal operation
66
OPEDA[3:0]
Sharp roll-off
66
FLT[3:0]
Power-save mode selection
Audio interface format selection
Operation control
Digital filter roll-off control
Output phase selection
Normal
67
REVDA[8:1]
Soft mute control
Mute disabled
68
MUTDA[8:1]
Zero flag
Not detected
69
ZERO[8:1]
0 dB to –63 dB, 0.5 dB step
70
DAMS
Disabled
70
DEMP[1:0]
70
AZRO[1:0]
Digital attenuation mode
Digital de-emphasis function control
ZERO1: DIN1, left-channel
Zero flag function selection
ZERO2: DIN1, right-channel
Zero flag polarity selection
Digital attenuation level setting
High for detection
70
ZREV
0 dB, no attenuation
71–79
ATDAx[7:0]
Table 16. Register Map
ADR[6:0]
(1)
DATA[7:0]
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
64
40
MRST
SRST
AMUTE3
AMUTE2
AMUTE1
AMUTE0
SRDA1
SRDA0
65
41
PSMDA
RSV (1)
RSV (1)
RSV (1)
FMTDA3
FMTDA2
FMTDA1
FMTDA0
66
42
OPEDA3
OPEDA2
OPEDA1
OPEDA0
FLT3
FLT2
FLT1
FLT0
67
43
REVDA8
REVDA7
REVDA6
REVDA5
REVDA4
REVDA3
REVDA2
REVDA1
68
44
MUTDA8
MUTDA7
MUTDA6
MUTDA5
MUTDA4
MUTDA3
MUTDA2
MUTDA1
69
45
ZERO8
ZERO7
ZERO6
ZERO5
ZERO4
ZERO3
ZERO2
ZERO1
(1)
(1)
70
46
DAMS
RSV
DEMP1
DEMP0
RSV
AZRO1
AZRO0
ZREV
71
47
RSV (1)
RSV (1)
RSV (1)
RSV (1)
RSV (1)
RSV (1)
RSV (1)
RSV (1)
72
48
ATDA17
ATDA16
ATDA15
ATDA14
ATDA13
ATDA12
ATDA11
ATDA10
73
49
ATDA27
ATDA26
ATDA25
ATDA24
ATDA23
ATDA22
ATDA21
ATDA20
74
4A
ATDA37
ATDA36
ATDA35
ATDA34
ATDA33
ATDA32
ATDA31
ATDA30
75
4B
ATDA47
ATDA46
ATDA45
ATDA44
ATDA43
ATDA42
ATDA41
ATDA40
76
4C
ATDA57
ATDA56
ATDA55
ATDA54
ATDA53
ATDA52
ATDA51
ATDA50
77
4D
ATDA67
ATDA66
ATDA65
ATDA64
ATDA63
ATDA62
ATDA61
ATDA60
78
4E
ATDA77
ATDA76
ATDA75
ATDA74
ATDA73
ATDA72
ATDA71
ATDA70
79
4F
ATDA87
ATDA86
ATDA85
ATDA84
ATDA83
ATDA82
ATDA81
ATDA80
RSV must be set to '0'.
REGISTER DEFINITIONS
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
64
40
MRST
SRST
AMUTE3
AMUTE2
AMUTE1
AMUTE0
SRDA1
SRDA0
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MRST
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Mode control register reset
This bit sets the mode control register reset to the default value. Pop noise may be generated.
Returning the MRST bit to '1' is unnecessary, because it is automatically set to '1' after the mode
control register is reset.
Default value = 1.
MRST
SRST
Mode control register reset
0
Set default value
1
Normal operation (default)
System reset
This bit controls system reset, the resynchronization between the system clock and sampling
clock, and DAC operation restart. The mode control register is not reset and the PCM1690-Q1
does not go into a power-down state. Returning the SRST bit to '1' is unnecessary; it is
automatically set to '1' after triggering a system reset.
Default value = 1.
SRST
System reset
0
Resynchronization
1
Normal operation (default)
AMUTE[3:0] Analog mute function control
These bits control the enabling/disabling of each source event that triggers the analog mute
control circuit.
Default value = 0000.
AMUTE
28
Analog mute function control
xxx0
Disable analog mute control by SCKI lost
xxx1
Enable analog mute control by SCKI lost
xx0x
Disable analog mute control by asynchronous detect
xx1x
Enable analog mute control by asynchronous detect
x0xx
Disable analog mute control by ZERO1 and ZERO2 detect
x1xx
Enable analog mute control by ZERO1 and ZERO2 detect
0xxx
Disable analog mute control by DAC disable command
1xxx
Enable analog mute control by DAC disable command
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SRDA[1:0]
Sampling mode selection
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is
automatically set according to multiples between the system clock and sampling clock, single rate
for 512 fS, 768 fS, and 1152 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA
Sampling mode selection
00
Auto (default)
01
Single rate
10
Dual rate
11
Quad rate
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
65
41
PSMDA
RSV
RSV
RSV
FMTDA3
FMTDA2
FMTDA1
FMTDA0
PSMDA
Power-save mode selection
This bit selects the power-save mode for the OPEDA[3:0] function. When PSMDA = 0,
OPEDA[3:0] controls the power-save mode and normal operation. When PSMDA = 1, OPEDA
functions controls the DAC disable (not power-save mode) and normal operation.
Default value: 0.
PSMDA
RSV
Power-save mode selection
0
Power-save enable mode (default)
1
Power-save disable mode
Reserved
Reserved; do not use.
FMTDA[3:0] Audio interface format selection
These bits control the audio interface format for DAC operation. Details of the format, and any
related restrictions with the system clock are described in the Audio Data Interface Formats and
Timing section.
Default value: 0000 (16-/20-/24-/32-bit I2S format).
FMTDA
Audio interface format selection
0000
16-/20-/24-/32-bit I2S format (default)
0001
16-/20-/24-/32-bit left-justified format
0010
24-bit right-justified format
0011
16-bit right-justified format
0100
24-bit I2S mode DSP format
0101
24-bit left-justified mode DSP format
0110
24-bit I2S mode TDM format
0111
24-bit left-justified mode TDM format
1000
24-bit high-speed I2S mode TDM format
1001
24-bit high-speed left-justified mode TDM format
101x
Reserved
11xx
Reserved
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DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
66
42
OPEDA3
OPEDA2
OPEDA1
OPEDA0
FLT3
FLT2
FLT1
FLT0
OPEDA[3:0] Operation control
These bits control the DAC operation mode. In operation disable mode, the DAC output is cut off
from DIN and the internal DAC data are reset. If PSMDA = 1, the DAC output is forced into
VCOM. IF PSMDA = 0, the DAC output is forced into AGND and the DAC goes into a
power-down state. For normal operating mode, these bits must be '0'. The serial mode control is
effective during operation disable mode.
Default value: 0000.
OPEDA
FLT[3:0]
Operation control
xxx0
DAC1/2 normal operation
xxx1
DAC1/2 operation disable with or without power save
xx0x
DAC3/4 normal operation
xx1x
DAC3/4 operation disable with or without power save
x0xx
DAC5/6 normal operation
x1xx
DAC5/6 operation disable with or without power save
0xxx
DAC7/8 normal operation
1xxx
DAC7/8 operation disable with or without power save
Digital filter roll-off control
These bits allow users to select the digital filter roll-off that is best suited to their applications.
Sharp and slow filter roll-off selections are available. The filter responses for these selections are
shown in the Typical Characteristics section of this data sheet.
Default value: 0000.
30
FLT
Digital filter roll-off control
xxx0
DAC1/2 sharp roll-off
xxx1
DAC1/2 slow roll-off
xx0x
DAC3/4 sharp roll-off
xx1x
DAC3/4 slow roll-off
x0xx
DAC5/6 sharp roll-off
x1xx
DAC5/6 slow roll-off
0xxx
DAC7/8 sharp roll-off
1xxx
DAC7/8 slow roll-off
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DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
67
43
REVDA8
REVDA7
REVDA6
REVDA5
REVDA4
REVDA3
REVDA2
REVDA1
REVDA[8:1] Output phase selection
These bits are used to control the phase of DAC analog signal outputs.
Default value: 0000 0000.
REVDA
Output phase selection
xxxx xxx0
DAC1 normal output
xxxx xxx1
DAC1 inverted output
xxxx xx0x
DAC2 normal output
xxxx xx1x
DAC2 inverted output
xxxx x0xx
DAC3 normal output
xxxx x1xx
DAC3 inverted output
xxxx 0xxx
DAC4 normal output
xxxx 1xxx
DAC4 inverted output
xxx0 xxxx
DAC5 normal output
xxx1 xxxx
DAC5 inverted output
xx0x xxxx
DAC6 normal output
xx1x xxxx
DAC6 inverted output
x0xx xxxx
DAC7 normal output
x1xx xxxx
DAC7 inverted output
0xxx xxxx
DAC8 normal output
1xxx xxxx
DAC8 inverted output
Copyright © 2011, Texas Instruments Incorporated
31
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
68
44
MUTDA8
MUTDA7
MUTDA6
MUTDA5
MUTDA4
MUTDA3
MUTDA2
MUTDA1
MUTDA[8:1] Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding DAC
outputs, VOUT. The Soft Mute function is incorporated into the digital attenuators. When mute is
disabled (MUTDA[8:1] = 0), the attenuator and DAC operate normally. When mute is enabled by
setting MUTDA[8:1] = 1, the digital attenuator for the corresponding output is decreased from the
current setting to infinite attenuation. By setting MUTDA[8:1] = 0, the attenuator is increased to
the last attenuation level in the same manner as it is for decreasing levels. This configuration
reduces pop and zipper noise during muting of the DAC output. This Soft Mute control uses the
same resource of digital attenuation level setting. Mute control has priority over the digital
attenuation level setting.
Default value: 0000 0000.
MUTDA
32
Soft Mute control
xxxx xxx0
DAC1 Mute disabled
xxxx xxx1
DAC1 Mute enabled
xxxx xx0x
DAC2 Mute disabled
xxxx xx1x
DAC2 Mute enabled
xxxx x0xx
DAC3 Mute disabled
xxxx x1xx
DAC3 Mute enabled
xxxx 0xxx
DAC4 Mute disabled
xxxx 1xxx
DAC4 Mute enabled
xxx0 xxxx
DAC5 Mute disabled
xxx1 xxxx
DAC5 Mute enabled
xx0x xxxx
DAC6 Mute disabled
xx1x xxxx
DAC6 Mute enabled
x0xx xxxx
DAC7 Mute disabled
x1xx xxxx
DAC7 Mute enabled
0xxx xxxx
DAC8 Mute disabled
1xxx xxxx
DAC8 Mute enabled
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
69
45
ZERO8
ZERO7
ZERO6
ZERO5
ZERO4
ZERO3
ZERO2
ZERO1
ZERO[8:1]
Zero flag (read-only)
These bits indicate the present status of the zero detect circuit for each DAC channel; these bits
are read-only.
ZERO
Zero flag
xxxx xxx0
DAC1 zero input not detected
xxxx xxx1
DAC1 zero input detected
xxxx xx0x
DAC2 zero input not detected
xxxx xx1x
DAC2 zero input detected
xxxx x0xx
DAC3 zero input not detected
xxxx x1xx
DAC3 zero input detected
xxxx 0xxx
DAC4 zero input not detected
xxxx 1xxx
DAC4 zero input detected
xxx0 xxxx
DAC5 zero input not detected
xxx1 xxxx
DAC5 zero input detected
xx0x xxxx
DAC6 zero input not detected
xx1x xxxx
DAC6 zero input detected
x0xx xxxx
DAC7 zero input not detected
x1xx xxxx
DAC7 zero input detected
0xxx xxxx
DAC8 zero input not detected
1xxx xxxx
DAC8 zero input detected
Copyright © 2011, Texas Instruments Incorporated
33
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
70
46
DAMS
RSV
DEMP1
DEMP0
RSV
AZRO1
AZRO0
ZREV
DAMS
Digital attenuation mode
This bit selects the attenuation mode.
Default value: 0.
DAMS
RSV
Digital attenuation mode
0
Fine step: 0.5-dB step for 0 dB to –63 dB range (default)
1
Wide range: 1-dB step for 0 dB to –100 dB range
Reserved
Reserved; do not use.
DEMP[1:0]
Digital de-emphasis function/sampling rate control
These bits are used to disable or enable the various sampling frequencies of the digital
de-emphasis function.
Default value: 00.
DEMP
AZRO[1:0]
Digital de-emphasis function/sampling rate control
00
Disable (default)
01
48 kHz enable
10
44.1 kHz enable
11
32 kHz enable
Zero flag channel combination selection
The AZRO[1:0] bits are used to select the zero flag channel combination for ZERO1 and ZERO2.
If the analog mute function control by ZERO flags is used, AZRO[1:0] should not be set '00';
otherwise, analog mute works even if the data of DATA2–4 are not zero.
Default value: 00B.
AZRO
ZREV
Zero flag combination selection
00
Combination A: ZERO1 = DATA1 left channel, ZERO2 = DATA1 right channel
(default)
01
Combination B: ZERO1 = DATA1–4, ZERO2 = DATA1–4
10
Combination C: ZERO1 = DATA4, ZERO2 = DATA1–3
11
Combination D: ZERO1 = DATA1, ZERO2 = DATA2–4
Zero flag polarity selection
This bit controls the polarity of the zero flag pin.
Default value: 0.
34
ZREV
Zero flag polarity selection
0
High for zero detect (default)
1
Low for zero detect
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
71
72
73
74
75
76
77
78
79
47
48
49
4A
4B
4C
4D
4E
4F
RSV
ATDA17
ATDA27
ATDA37
ATDA47
ATDA57
ATDA67
ATDA77
ATDA87
RSV
ATDA16
ATDA26
ATDA36
ATDA46
ATDA56
ATDA66
ATDA76
ATDA86
RSV
ATDA15
ATDA25
ATDA35
ATDA45
ATDA55
ATDA65
ATDA75
ATDA85
RSV
ATDA14
ATDA24
ATDA34
ATDA44
ATDA54
ATDA64
ATDA74
ATDA84
RSV
ATDA13
ATDA23
ATDA33
ATDA43
ATDA53
ATDA63
ATDA73
ATDA83
RSV
ATDA12
ATDA22
ATDA32
ATDA42
ATDA52
ATDA62
ATDA72
ATDA82
RSV
ATDA11
ATDA21
ATDA31
ATDA41
ATDA51
ATDA61
ATDA71
ATDA81
RSV
ATDA10
ATDA20
ATDA30
ATDA40
ATDA50
ATDA60
ATDA70
ATDA80
RSV
Reserved
Reserved; do not use.
ATDAx[7:0]
Digital attenuation level setting
Where x = 1 to 8, corresponding to the DAC output (VOUTx).
Each DAC output (VOUT1 through VOUT8) has a digital attenuation function. The attenuation level
can be set from 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by
incrementing or decrementing one step (S dB) for every 8/fS time interval until the programmed
attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation
(or mute). R (Range) and S (Step) is –63 and 0.5 for DAMS = 0 and –100 and 1.0 for DAMS = 1,
respectively. The DAMS bit is defined in Register 70 (46h). Table 17 shows attenuation levels for
various settings.
The attenuation level for each channel can be set individually using the following formula:
Attenuation level (dB) = S × (ATDAx[7:0]DEC – 255)
where ATDAx[7:0]DEC = 0 through 255.
For ATDAx[7:0]DEC = 0 through 128 with DAMS = 0 or 0 through 154 with DAMS = 1, attenuation
is set to infinite attenuation (mute).
Default value: 1111 1111.
Table 17. Attenuation Levels for Various Settings
ATDAx[7:0]
ATTENUATION LEVEL SETTING
BINARY
DECIMAL
DAMS = 0
DAMS = 1
1111 1111
255
0 dB, no attenuation (default)
0 dB, no attenuation (default)
1111 1110
254
–0.5 dB
–1 dB
1111 1101
253
–1.0 dB
–2 dB
...
...
...
...
1001 1100
156
–45.9 dB
–99 dB
1001 1011
155
–50.0 dB
–100 dB
1001 1010
154
–50.5 dB
Mute
...
...
...
...
1000 0010
130
–62.5 dB
Mute
1000 0001
129
–63.0 dB
Mute
0000 0000
128
Mute
Mute
...
...
...
...
0000 0000
0
Mute
Mute
Copyright © 2011, Texas Instruments Incorporated
35
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
APPLICATION INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 40, with the necessary power-supply bypassing and decoupling
components. Texas Instruments’ PLL170X is used to generate the system clock input at SCKI, as well as to
generate the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) are recommended
for SCKI, LRCK, BCK, DIN1, DIN2, DIN3, and DIN4 for electromagnetic interference (EMI) reduction.
POWER SUPPLY AND GROUNDING
The PCM1690-Q1 requires +5 V for the analog supply and +3.3 V for the digital supply. The +5-V supply is used
to power the DAC analog and output filter circuitry, and the +3.3-V supply is used to power the digital filter and
serial interface circuitry. For best performance, it is recommended to use a linear regulator with the +5-V and
+3.3-V supplies.
Five capacitors are required for supply bypassing (see Figure 40). These capacitors should be located as close
as possible to the PCM1690-Q1 package. The 10-μF capacitors are aluminum electrolytic, while the three 1-μF
capacitors are ceramic.
36
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
PCM1690
R1
R2
R3
Audio DSP or
Decoder
R4
R5
R6
1
RSV2
RSV2 48
2
RSV1
VCC2 47
3
RSV2
AGND2 46
4
RSV1
RSV2 45
5
RSV2
VOUT1- 44
6
LRCK
VOUT1+ 43
7
BCK
VOUT2- 42
8
DIN1
VOUT2+ 41
9
DIN2
VOUT3- 40
10 DIN3
VOUT3+ 39
11 DIN4
VOUT4- 38
12 VDD
VOUT4+ 37
13 DGND
VOUT5- 36
14 SCKI
VOUT5+ 35
15 RST
VOUT6- 34
16 ZERO1
VOUT6+ 33
17 ZERO2
VOUT7- 32
18 AMUTEI
VOUT7+ 31
19 AMUTEO
VOUT8- 30
20 MD/SDA/DEMP
VOUT8+ 29
C3
C1
R7
PLL170x
R8
mC or mP
LPF and Buffer
R9
21 MC/SCL/FMT
22 MS/ADR0/RSV
23 TEST/ADR1/RSV
24 MODE
Termination
Circuit
RSV2 28
AGND1 27
VCOM 26
+
C4
C2
VCC1 25
+5 V
+
+
C6
+3.3 V
C5
0V
24
3.3 V
R10
24
R10
24
0V
(High)
(Open)
(Low)
NOTE: C1 through C3 are 1-μF ceramic capacitors. C4 through C6 are 10-μF electrolytic capacitors. R1 through R7 are 22-Ω to 100-Ω
resistors. R8 and R9 are resistors appropriate for pull-up. R10 is less than 10 kΩ.
Figure 40. Basic Connection Diagram
Copyright © 2011, Texas Instruments Incorporated
37
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
LOW-PASS FILTER AND DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER FOR DAC OUTPUTS
ΔΣ DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the
expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise
must be low-pass filtered in order to provide optimal converter performance. This filtering is accomplished by a
combination of on-chip and external low-pass filters.
Figure 41 and Figure 42 show the recommended external differential-to-single-ended converter with low-pass
active filter circuits for ac-coupled and dc-coupled applications. These circuits are second-order Butterworth
filters using a multiple feedback (MFB) circuit arrangement that reduces sensitivity to passive component
variations over frequency and temperature. For more information regarding MFB active filter designs, please
refer to Applications Bulletin SBAA055, Dynamic Performance Testing of Digital Audio D/A Converters, available
from the TI web site (www.ti.com) or the local Texas Instruments' sales office.
Because the overall system performance is defined by the quality of the DACs and the associated analog output
circuitry, high-quality audio op amps are recommended for the active filters. Texas Instruments’ OPA2134,
OPA2353, and NE5532A dual op amps are shown in Figure 41 and Figure 42, and are recommended for use
with the PCM1690-Q1.
R2
C2
R1
R3
47W
C1
+
VOUT(4 VPP)
10 mF
+
VOUT+
(4 VPP)
10 mF
Analog Output
(2 VRMS)
R3
R1
R2
C2
NOTE: Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 7.5-kΩ; R2 = 5.6-kΩ; R3 = 360-Ω; C1 = 3300-pF; C2 = 680-pF; Gain = 0.747; f–3
dB = 53 kHz.
Figure 41. AC-Coupled, Post-LPF and Differential to Single-Ended Buffer
R2
C2
VOUT+
(4 VPP)
VOUT(4 VPP)
R1
R3
47W
C1
R1
Analog Output
(2 VRMS)
R3
R2
C2
NOTE: Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 15-kΩ; R2 = 11-kΩ; R3 = 820-Ω; C1 = 1500-pF; C2 = 330-pF; Gain = 0.733; f–3
dB = 54 kHz.
Figure 42. DC-Coupled, Post-LPF and Differential to Single-Ended Buffer
38
Copyright © 2011, Texas Instruments Incorporated
PCM1690-Q1
SBAS551 – JUNE 2011
www.ti.com
PCB LAYOUT GUIDELINES
A typical printed circuit board (PCB) layout for the PCM1690-Q1 is shown in Figure 43. A ground plane is
recommended, with the analog and digital sections being isolated from one another using a split or cut in the
circuit board. The PCM1690-Q1 should be oriented with the digital I/O pins facing the ground plane split/cut to
allow for short, direct connections to the digital audio interface and control signals originating from the digital
section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This configuration
prevents the switching noise present on the digital supply from contaminating the analog power supply and
degrading the dynamic performance of the PCM1690-Q1.
Analog Power
Digital Power
+3.3 VD
DGND
AGND
+5 VA +VS -VS
VDD VCC
Digital Logic
and
Audio
Processor
DGND
PCM1690
Output
Circuits
Digital
Ground
AGND
Digital Section
Analog Section
Analog
Ground
Return Path for 3.3 VD and Digital Signals
Figure 43. Recommended PCB Layout
Copyright © 2011, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
PCM1690IDCARQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
DCA
48
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
PCM1690Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2014
OTHER QUALIFIED VERSIONS OF PCM1690-Q1 :
• Catalog: PCM1690
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM1690IDCARQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DCA
48
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM1690IDCARQ1
HTSSOP
DCA
48
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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