Texas Instruments | 24-Bit, 192-kHz Sampling, Enhanced Multilevel Delta-Sigma, Stereo, Audio DAC | Datasheet | Texas Instruments 24-Bit, 192-kHz Sampling, Enhanced Multilevel Delta-Sigma, Stereo, Audio DAC Datasheet

Texas Instruments 24-Bit, 192-kHz Sampling, Enhanced Multilevel Delta-Sigma, Stereo, Audio DAC Datasheet
PCM1789-Q1
Burr-Brown Audio
SBAS546 – MARCH 2011
www.ti.com
24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,
Stereo, Audio Digital-to-Analog Converter
Check for Samples: PCM1789-Q1
FEATURES
1
• Qualified for Automotive Applications
• Enhanced Multi-Level Delta-Sigma DAC:
– High Performance: Differential, fS = 48 kHz
– THD+N: –94 dB
– SNR: 113 dB
– Dynamic Range: 113 dB
– Sampling Rate: 8 kHz to 192 kHz
– System Clock: 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 fS
– Differential Voltage Output: 8 VPP
– Analog Low-Pass Filter Included
– 4x/8x Oversampling Digital Filter:
– Passband Ripple: ±0.0018 dB
– Stop Band Attenuation: –75 dB
– Zero Flags (16-/20-/24-Bits)
• Flexible Audio Interface:
– I/F Format: I2S™, Left-/Right-Justified, DSP
– Data Length: 16, 20, 24, 32 Bits
• Flexible Mode Control:
– 3-Wire SPI™, 2-Wire I2C™-Compatible
Serial Control Interface, or
Hardware Control
– Connect Up To 4 Devices on One SPI Bus
• Multi Functions via SPI or I2C I/F:
– Audio I/F Format Select: I2S, Left-Justified,
Right-Justified, DSP
– Digital Attenuation and Soft Mute
– Digital De-Emphasis: 32 kHz, 44.1 kHz,
48 kHz
– Data Polarity Control
– Power-Save Mode
• Multi Functions via Hardware Control:
234
•
•
•
•
•
– Audio I/F Format Select: I2S, Left-Justified
– Digital De-Emphasis Filter: 44.1 kHz
Analog Mute by Clock Halt Detection
External Reset Pin
Power Supplies:
– 5 V for Analog and 3.3 V for Digital
Package: TSSOP-24
Operating Temperature Range:
– –40°C to +105°C
APPLICATIONS
•
•
•
AV Receivers
Car Audio External Amplifiers
Car Audio AVN Applications
DESCRIPTION
The PCM1789-Q1 is a high-performance, single-chip,
24-bit, stereo, audio digital-to-analog converter (DAC)
with differential outputs. The two-channel, 24-bit DAC
employs an enhanced multi-level, delta-sigma (ΔΣ)
modulator, and supports 8 kHz to 192 kHz sampling
rates and a 16-/20-/24-/32-bit width digital audio input
word on the audio interface. The audio interface of
PCM1789-Q1 supports a 24-bit, DSP format in
addition to I2S, left-justified, and right-justified
formats.
The PCM1789-Q1 can be controlled through a
three-wire,
SPI-compatible
or
two-wire,
I2C-compatible serial interface in software, which
provides access to all functions including digital
attenuation, soft mute, de-emphasis, and so forth.
Also, hardware control mode provides two
user-programmable functions through two control
pins. The PCM1789-Q1 is available in a 24-pin
TSSOP package.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
2
2
I S, I C are trademarks of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
PCM1789-Q1
SBAS546 – MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
–40°C to 105°C
(1)
PACKAGE
TSSOP-24 – PW
Reel of 2000
ORDERABLE PART
TOP-SIDE MARKING
PCM1789TPWRQ1
PCM1789T
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
PCM1789-Q1
UNIT
VCC1, VCC2
–0.3 to +6.5
V
VDD
–0.3 to +4.0
V
Ground voltage differences: AGND1, AGND2, DGND
±0.1
V
Supply voltage differences: VCC1, VCC2
±0.1
V
RST, ADR5, MS, MC, MD, SCKI, AMUTEI
–0.3 to +6.5
V
BCK, LRCK, DIN, MODE, ZERO1, ZERO2
–0.3 to (VDD + 0.3) < +4.0
V
–0.3 to (VCC + 0.3) < +6.5
V
Supply voltage
Digital input voltage
Analog input voltage: VCOM, VOUTL±, VOUTR±
±10
mA
Ambient temperature under bias
–40 to +125
°C
Storage temperature
–55 to +150
°C
Junction temperature
+150
°C
Lead temperature (soldering, 5s)
+260
°C
Package temperature (IR reflow, peak)
+260
°C
Input current (all pins except supplies)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
PCM1789-Q1
MIN
TYP
MAX
UNIT
Analog supply voltage, VCC
PARAMETER
4.5
5.0
5.5
V
Digital supply voltage, VDD
3.0
3.3
3.6
V
Digital Interface
Digital input clock frequency
Analog output voltage
Analog output load resistance
LVTTL-compatible
Sampling frequency, LRCK
System clock frequency, SCKI
8
192
kHz
2.048
36.864
MHz
Differential
8
To ac-coupled GND
5
To dc-coupled GND
15
kΩ
kΩ
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature
2
PCM1789-Q1 consumer grade
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–40
VPP
25
50
pF
20
pF
105
°C
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Product Folder Link(s): PCM1789-Q1
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ELECTRICAL CHARACTERISTICS: Digital Input/Output
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
PCM1789-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DATA FORMAT
I2S, LJ, RJ, DSP
Audio data interface format
Audio data word length
16, 20, 24, 32
Audio data format
Bits
MSB first, twos complement
Sampling frequency
fS
8
128 fS, 192 fS, 256 fS,
384 fS, 512 fS, 768 fS, 1152 fS
System clock frequency
48
192
kHz
2.048
36.864
MHz
2.0
VDD
VDC
0.8
VDC
5.5
VDC
0.8
VDC
INPUT LOGIC
Input logic level
Input logic level
Input logic current
Input logic current
VIH
(1) (2)
VIL
(1) (2)
VIH
(3) (4)
VIL
(3) (4)
IIH
(2) (3)
VIN = VDD
±10
μA
IIL
(2) (3)
VIN = 0 V
±10
μA
IIH
(1) (4)
VIN = VDD
+100
μA
IIL
(1) (4)
VIN = 0 V
±10
μA
2.0
+65
OUTPUT LOGIC
Output logic level
(5)
IOUT = –4 mA
(5) (6)
IOUT = +4 mA
VOH
VOL
2.4
VDC
0.4
VDC
REFERENCE OUTPUT
0.5 ×
VCC1
VCOM output voltage
VCOM output impedance
7.5
Allowable VCOM output source/sink current
(1)
(2)
(3)
(4)
(5)
(6)
V
kΩ
1
μA
BCK and LRCK (Schmitt trigger input with 50-kΩ typical internal pull-down resistor).
DIN (Schmitt trigger input).
SCKI, ADR5/ADR1/RSV, MC/SCL/FMT, MD/SDA/DEMP, and AMUTEI (Schmitt trigger input, 5-V tolerant).
RST and MS/ADR0/RSV (Schmitt trigger input with 50-kΩ typical internal pull-down resistor, 5-V tolerant).
ZERO1 and ZERO2.
AMUTEO and SDA (I2C mode, open-drain low output).
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ELECTRICAL CHARACTERISTICS: DAC
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
PCM1789-Q1
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP
16
24
MAX
UNIT
Bits
DC ACCURACY
Gain mismatch channel-to-channel
±2.0
±6.0
% of FSR
Gain error
±2.0
±6.0
% of FSR
±1.0
Bipolar zero error
DYNAMIC PERFORMANCE (1)
Total harmonic distortion + noise
THD+N
fS = 48 kHz
–94
fS = 96 kHz
–94
dB
fS = 192 kHz
–94
dB
113
dB
fS = 96 kHz, EIAJ, A-weighted
113
dB
fS = 192 kHz, EIAJ, A-weighted
113
dB
113
dB
113
dB
113
dB
109
dB
fS = 96 kHz
109
dB
fS = 192 kHz
108
dB
Differential
1.6 × VCC1
VPP
VOUT = 0 dB
fS = 48 kHz, EIAJ, A-weighted
Dynamic range
106
fS = 48 kHz, EIAJ, A-weighted
Signal-to-noise ratio
% of FSR
(2)
SNR
106
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted
fS = 48 kHz
Channel separation
103
–88
dB
ANALOG OUTPUT
Output voltage
0.5 × VCC1
Center voltage
Load impedance
LPF frequency response
To ac-coupled GND (3)
5
To dc-coupled GND (3)
15
V
kΩ
kΩ
f = 20 kHz
–0.04
dB
f = 44 kHz
–0.18
dB
DIGITAL FILTER PERFORMANCE WITH SHARP ROLL-OFF
Passband (single, dual)
Except SCKI = 128 fS and 192 fS
0.454 × fS
Hz
SCKI = 128 fS and 192 fS
0.432 × fS
Hz
0.432 × fS
Hz
Passband (quad)
Stop band (single, dual)
Except SCKI = 128 fS and 192 fS
0.546 × fS
Hz
SCKI = 128 fS and 192 fS
0.569 × fS
Hz
0.569 × fS
Stop band (quad)
Passband ripple
< 0.454 × fS, 0.432 × fS
Stop band attenuation
> 0.546 × fS, 0.569 × fS
(1)
(2)
(3)
4
Hz
±0.0018
–75
dB
dB
In differential mode at VOUTx± pin, fOUT = 1 kHz, using Audio Precision System II, Average mode with 20-kHz LPF and 400-Hz HPF.
fS = 48 kHz: SCKI = 512 fS (single), fS = 96 kHz : SCKI = 256 fS (dual), fS = 192 kHz : SCKI = 128 fS (quad).
Allowable minimum input resistance of differential-to-single-ended converter with D-to-S gain = G is calculated as (1 + 2G)/(1 + G) × 5k
for ac-coupled, and (1+ 0.9G)/(1 + G) × 15k for dc-coupled connection; refer to Figure 38 and Figure 39.
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PCM1789-Q1
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ELECTRICAL CHARACTERISTICS: DAC (continued)
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
PCM1789-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.328 × fS
Hz
DIGITAL FILTER PERFORMANCE WITH SLOW ROLL-OFF
Passband
0.673 × fS
Stop band
Passband ripple
< 0.328 × fS
Stop band attenuation
> 0.673 × fS
Hz
±0.0013
dB
–75
dB
DIGITAL FILTER PERFORMANCE
Group delay time (single, dual)
Except SCKI = 128 fS and 192 fS
28/fS
sec
SCKI = 128 fS and 192 fS
19/fS
sec
Group delay time (quad)
19/fS
sec
De-emphasis error
±0.1
dB
ELECTRICAL CHARACTERISTICS: Power-Supply Requirements
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
PCM1789-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1/2
4.5
5.0
5.5
VDC
VDD
3.0
3.3
3.6
VDC
fS = 48 kHz
19
28
mA
fS = 192 kHz
19
POWER-SUPPLY REQUIREMENTS
Voltage range
ICC
Full power-down
Supply current
(1)
18
fS = 192 kHz
Full power-down
mA
mA
μA
60
154
fS = 192 kHz
Full power-down
30
22
(1)
fS = 48 kHz
Power dissipation
μA
170
fS = 48 kHz
IDD
mA
(1)
239
mW
168
mW
1.05
mW
TEMPERATURE RANGE
Operating temperature
Thermal resistance
(1)
PCM1789-Q1 consumer grade
θJA
TSSOP-24
–40
°C
+85
115
°C/W
SCKI, BCK, and LRCK stopped.
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PIN CONFIGURATION
PW PACKAGE
TSSOP-24
(TOP VIEW)
LRCK
1
24 ADR5/ADR1/RSV
BCK
2
23 MS/ADR0/RSV
DIN
3
22 MC/SCL/FMT
RST
4
21 MD/SDA/DEMP
SCKI
5
20 MODE
VDD
6
19 ZERO1
PCM1789
DGND
7
18 ZERO2/AMUTEO
VCC1
8
17 AMUTEI
VCOM
9
16 VCC2
15 AGND2
AGND1 10
VOUTL- 11
14 VOUTR-
VOUTL+ 12
13 VOUTR+
TERMINAL FUNCTIONS
TERMINAL
NAME
PIN
I/O
PULLDOWN
5-V
TOLERANT
LRCK
1
I
Yes
No
Audio data word clock input
BCK
2
I
Yes
No
Audio data bit clock input
DIN
3
I
No
No
Audio data input
RST
4
I
Yes
Yes
Reset and power-down control input with active low
SCKI
5
I
No
Yes
System clock input
VDD
6
—
—
—
Digital power supply, +3.3 V
DGND
7
—
—
—
Digital ground
VCC1
8
—
—
—
Analog power supply 1, +5 V
VCOM
9
—
—
—
Voltage common decoupling
AGND1
10
—
—
—
Analog ground 1
VOUTL–
11
O
No
No
Negative analog output from DAC left channel
VOUTL+
12
O
No
No
Positive analog output from DAC left channel
VOUTR+
13
O
No
No
Positive analog output from DAC right channel
VOUTR–
14
O
No
No
Negative analog output from DAC right channel
AGND2
15
—
—
—
Analog ground 2
VCC2
16
—
—
—
Analog power supply 2, +5 V
AMUTEI
17
I
No
Yes
Analog mute control input with active low
ZERO2/AMUTEO
18
O
No
No
Zero detect flag output 2/Analog mute control output (1) with active low
ZERO1
19
O
No
No
Zero detect flag output 1
MODE
20
I
No
No
Control port mode selection. Tied to VDD: SPI, ADR6 = 1, pull-up: SPI,
ADR6 = 0, pull-down: H/W auto mode, tied to DGND: I2C
MD/SDA/DEMP
21
I/O
No
Yes
Input data for SPI, data for I2C (1), de-emphasis control for hardware
control mode
MC/SCL/FMT
22
I
No
Yes
Clock for SPI, clock for I2C, format select for hardware control mode
MS/ADR0/RSV
23
I
Yes
Yes
Chip Select for SPI, address select 0 for I2C, reserve (set low) for
hardware control mode
ADR5/ADR1/RSV
24
I
No
Yes
Address select 5 for SPI, address select 1 for I2C, reserve (set low) for
hardware control mode
(1)
6
DESCRIPTION
Open-drain configuration in out mode.
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FUNCTIONAL BLOCK DIAGRAM
BCK
LRCK
DIN
SCKI
Audio Interface
Clock Manager
DAC
(Left Ch)
Interpolation
Filter
Digital Attenuation
Digital Mute
De-Emphasis
DAC
(Right Ch)
VOUTL+
VOUTLVOUTR+
VOUTR-
VCOM
VCOM
MODE
VCC1
ADR5/ADR1/RSV
MS/ADR0/RSV
MC/SCL/FMT
MD/SDA/DEMP
RST
AGND1
Control Interface
2
(SPI/I C/Hardware)
AMUTEI
Power Supply
and
Common Voltage
VCC2
AGND2
VDD
ZERO1
DGND
ZERO2/AMUTEO
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TYPICAL CHARACTERISTICS: Digital Filter
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
FREQUENCY RESPONSE
(Single Rate)
FREQUENCY RESPONSE PASSBAND
(Single Rate)
0
0.010
Sharp
Slow
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
1
2
-0.010
4
3
0
0.1
Normalized Frequency (fS)
FREQUENCY RESPONSE
(Dual Rate)
FREQUENCY RESPONSE PASSBAND
(Dual Rate)
0.5
0.010
Sharp
Slow
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
0.4
Figure 2.
-20
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
1
2
-0.010
4
3
0
0.1
Normalized Frequency (fS)
0.2
0.3
0.4
0.5
Normalized Frequency (fS)
Figure 3.
Figure 4.
FREQUENCY RESPONSE
(Quad Rate)
FREQUENCY RESPONSE PASSBAND
(Quad Rate)
0
0.010
Sharp
Slow
-20
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
0.3
Figure 1.
0
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
0.5
1.0
1.5
2.0
-0.010
0
Normalized Frequency (fS)
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (fS)
Figure 5.
8
0.2
Normalized Frequency (fS)
Figure 6.
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TYPICAL CHARACTERISTICS: Digital De-Emphasis Filter
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
DE-EMPHASIS CHARACTERISTIC
(fS = 44.1 kHz)
0
0
-1
-1
-2
-2
-3
-3
Amplitude (dB)
Amplitude (dB)
DE-EMPHASIS CHARACTERISTIC
(fS = 48 kHz)
-4
-5
-6
-4
-5
-6
-7
-7
-8
-8
-9
-9
-10
-10
0
4
2
6
8
10
12
14
16
18
20
22
0
2
4
6
Frequency (kHz)
8
10
12
14
16
18
20
Frequency (kHz)
Figure 7.
Figure 8.
DE-EMPHASIS CHARACTERISTIC
(fS = 32 kHz)
ANALOG FILTER CHARACTERISTIC
0
0
-1
-10
-3
Amplitude (dB)
Amplitude (dB)
-2
-4
-5
-6
-20
-30
-7
-8
-40
-9
-10
0
2
4
6
8
10
12
14
-50
1k
Frequency (kHz)
10k
100k
1M
10M
Frequency (Hz)
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS: Dynamic Performance
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs
TEMPERATURE
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs
TEMPERATURE
118
Dynamic Range and SNR (dB)
-92
THD+N (dB)
-94
-96
-98
-100
-102
Dynamic Range
114
SNR
112
110
108
106
-104
-40
-15
10
35
Temperature (°C)
60
85
-40
85
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE
118
Dynamic Range and SNR (dB)
-96
-98
-100
-102
4.75
5.00
Supply Voltage (V)
5.25
5.50
116
Dynamic Range
114
SNR
112
110
108
106
4.50
Figure 13.
10
60
Figure 12.
-94
-104
4.50
10
35
Temperature (°C)
-15
Figure 11.
-92
THD+N (dB)
116
4.75
5.00
Supply Voltage (V)
5.25
5.50
Figure 14.
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TYPICAL CHARACTERISTICS: Output Spectrum
All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling
mode = Auto, unless otherwise noted.
OUTPUT SPECTRUM
(–60 dB, N = 32768)
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
OUTPUT SPECTRUM
(0 dB, N = 32768)
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
10
Frequency (kHz)
15
0
20
5
10
Frequency (kHz)
Figure 15.
15
20
Figure 16.
OUTPUT SPECTRUM
(BPZ, N = 32768)
0
-20
Amplitude (dB)
-40
-60
-80
-100
-120
-140
-160
0
5
10
Frequency (kHz)
15
20
Figure 17.
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PRODUCT OVERVIEW
The PCM1789-Q1 is a high-performance stereo DAC targeted for consumer audio applications such as Blu-ray
Disc players and DVD players, as well as home multi-channel audio applications (such as home theater and A/V
receivers). The PCM1789-Q1 consists of a two-channel DAC. The DAC output type is fixed with a differential
configuration. The PCM1789-Q1 supports 16-/20-/24-/32-bit linear PCM input data in I2S and left-justified audio
formats, and 24-bit linear PCM input data in right-justified and DSP formats with various sampling frequencies
from 8 kHz to 192 kHz. The PCM1789-Q1 offers three modes for device control: two-wire I2C software,
three-wire SPI software, and hardware.
ANALOG OUTPUTS
The PCM1789-Q1 includes a two-channel DAC, with a pair of differential voltage outputs pins. The full-scale
output voltage is (1.6 × VCC1) VPP in differential output mode. A dc-coupled load is allowed in addition to an
ac-coupled load, if the load resistance conforms to the specification. These balanced outputs are each capable of
driving 0.8 VCC1 (4 VPP) typical into a 5-kΩ ac-coupled or 15-kΩ dc-coupled load with VCC1 = +5 V. The internal
output amplifiers for VOUTL and VOUTR are biased to the dc common voltage, equal to 0.5 VCC1.
The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy
present at the DAC outputs as a result of the noise shaping characteristics of the PCM1789-Q1 delta-sigma (ΔΣ)
DACs. The frequency response of this filter is shown in the Analog Filter Characteristic (Figure 10) of the Typical
Characteristics. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for
most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further
discussion of DAC post-filter circuits is provided in the Application Information section.
VOLTAGE REFERENCE VCOM
The PCM1789-Q1 includes a pin for the common-mode voltage output, VCOM. This pin should be connected to
the analog ground via a decoupling capacitor. This pin can also be used to bias external high-impedance circuits,
if they are required.
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SYSTEM CLOCK INPUT
The PCM1789-Q1 requires an external system clock input applied at the SCKI input for DAC operation. The
system clock operates at an integer multiple of the sampling frequency, or fS. The multiples supported in DAC
operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, and 1152 fS. Details for these system clock
multiples are shown in Table 1. Figure 18 and Table 2 show the SCKI timing requirements.
Table 1. System Clock Frequencies for Common Audio Sampling Rates
DEFAULT
SAMPLING
MODE
SAMPLING
FREQUENCY, fS
(kHz)
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
8
N/A
N/A
2.0480
3.0720
4.0960
6.1440
9.2160
16
2.0480
3.0720
4.0960
6.1440
8.1920
12.2880
18.4320
Single rate
Dual rate
Quad rate
SYSTEM CLOCK FREQUENCY (MHz)
1152 fS
32
4.0960
6.1440
8.1920
12.2880
16.3840
24.5760
36.8640
44.1
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
N/A
48
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
N/A
88.2
11.2896
16.9344
22.5792
33.8688
N/A
N/A
N/A
96
12.2880
18.4320
24.5760
36.8640
N/A
N/A
N/A
176.4
22.5792
33.8688
N/A
N/A
N/A
N/A
N/A
192
24.5760
36.8640
N/A
N/A
N/A
N/A
N/A
tSCH
High
2.0 V
System Clock
(SCKI)
0.8 V
Low
tSCL
tSCY
Figure 18. System Clock Timing Diagram
Table 2. Timing Requirements for Figure 18
SYMBOL
PARAMETER
MIN
tSCY
System clock cycle time
27
MAX
UNIT
ns
tSCH
System clock width high
10
ns
tSCL
System clock width low
10
—
System clock duty cycle
40
ns
60
%
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SAMPLING MODE
The PCM1789-Q1 supports three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In
single rate mode, the DAC operates at an oversampling frequency of x128 (except when SCKI = 128 fS and 192
fS); this mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the DAC operates at an
oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate
mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected
according to the ratio of system clock frequency and sampling frequency by default (that is, single rate for 512 fS,
768 fS, and 1152 fS; dual rate for 256 fS and 384 fS; and quad rate for 128 fS and 192 fS), but manual selection is
also possible for specified combinations through the serial mode control register.
Table 3 and Figure 19 show the relationship among the oversampling rate (OSR) of the digital filter and ΔΣ
modulator, the noise-free shaped bandwidth, and each sampling mode setting.
Table 3. Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth for Each Sampling Mode
SAMPLING
MODE
REGISTER
SETTING
Auto
Single
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
DIGITAL FILTER
OSR
MODULATOR
OSR
512, 768, 1152
40
N/A
N/A
×8
x128
x64
256, 384
20
40
N/A
x8
128, 192 (2)
10
20
40
x4
x32
512, 768, 1152
40
N/A
N/A
x8
x128
256, 384
40
N/A
N/A
x8
x128
128, 192
Dual
Quad
(1)
(2)
NOISE-FREE SHAPED BANDWIDTH (1)
(kHz)
SYSTEM CLOCK
FREQUENCY
(xfS)
(2)
20
N/A
N/A
x4
x64
256, 384
20
40
N/A
x8
x64
128, 192 (2)
20
40
N/A
x4
x64
(2)
10
20
40
x4
x32
128, 192
Bandwidth in which noise is shaped out.
Quad mode filter characteristic is applied.
0
DSM_Single
DSM_Dual
DSM_Quad
-20
Amplitude (dB)
-40
DF_Single
DF_Dual
DF_Quad
-60
-80
-100
-120
-140
-160
-180
-200
0
0.5
1.0
1.5
2.0
Normalized Frequency (fS)
Figure 19. ΔΣ Modulator and Digital Filter Characteristic
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RESET OPERATION
The PCM1789-Q1 has both an internal power-on reset circuit and an external reset circuit. The sequences for
both reset circuits are shown in Figure 20 and Figure 21. Figure 20 illustrates the timing at the internal power-on
reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset
is released after 3846 SCKI clock cycles from power-on, if RST is held high and SCKI is provided. VOUTx from
the DAC is forced to the VCOM level initially (that is, 0.5 × VCC1) and settles at a specified level according to the
rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an output that
corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset is
not released, and both operating modes are maintained at reset and power-down states. After synchronization
forms again, the DAC returns to normal operation with the previous sequences.
Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low,
and provides a device reset and power-down state that achieves the lowest power dissipation state available in
the PCM1789-Q1. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the
internal reset is asserted, all registers and memory are reset, and finally, the PCM1789-Q1 enters into all
power-down states. At the same time, VOUT is immediately forced into the AGND1 level. To begin normal
operation again, toggle RST high; the same power-up sequence is performed as the power-on reset shown in
Figure 20.
The PCM1789-Q1 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then
VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however,
simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the
response for VCC on with VDD on.
(VDD = 3.3 V, typ)
VDD
0V
(VDD = 2.2 V, typ)
SCKI,
BCK,
LRCK
RST
Synchronous Clocks
3846 ´ SCKI
Normal Operation
Internal Reset
VOUTx±
0.5 ´ VCC
VCOM
(0.5 ´ VCC1)
Figure 20. Power-On-Reset Timing Requirements
(VDD = 3.3 V, typ)
VDD
SCKI,
BCK,
LRCK
0V
Synchronous Clocks
Synchronous Clocks
100 ns (min)
RST
3846 ´ SCKI
Internal Reset
Normal Operation
Power-Down
Normal Operation
0.5 ´ VCC
VOUTx±
Figure 21. External Reset Timing Requirements
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AUDIO SERIAL PORT OPERATION
The PCM1789-Q1 audio serial port consists of three signals: BCK, LRCK, and DIN. BCK is a bit clock input.
LRCK is a left/right word clock or frame synchronization clock input. DIN is the audio data input for VOUTL/R.
AUDIO DATA INTERFACE FORMATS AND TIMING
The PCM1789-Q1 supports six audio data interface formats: 16-/20-/24-/32-bit I2S, 16-/20-/24-/32-bit left-justified,
24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, and 24-bit I2S mode DSP. In the case of
I2S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are
supported; however, 48 BCKs are limited to 192/384/768 fS SCKI, and 32 BCKs are limited to 16-bit right-justified
only. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by the FMTDA[2:0]
bits in control register 17 (11h) in software control mode. All data must be in binary twos complement and MSB
first.
Table 4 summarizes the applicable formats and describes the relationships among them and the respective
restrictions with mode control. Figure 22 through Figure 26 show six audio interface data formats.
Table 4. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions
FORMAT
DATA BITS
MAX LRCK FREQUENCY
(fS)
SCKI RATE (xfS)
BCK RATE (xfS)
I S/Left-Justified
16/20/24/32 (1)
192 kHz
128 to 1152 (2)
64, 48
24, 16
192 kHz
(2)
I S/Left-Justified DSP
24
192 kHz
128 to 768
64
I2S/Left-Justified
16/20/24/32 (1)
192 kHz
128 to 1152 (2)
64, 48
CONTROL MODE
2
Software control
Right-Justified
2
Hardware control
(1)
(2)
(3)
128 to 1152
64, 48, 32 (16 bit) (3)
32-bit data length is acceptable only for BCK = 64 fS and when using I2S or Left-Justified format.
1152 fS is acceptable only for fS = 32 kHz, BCK = 64 fS, and when using I2S, Left-Justified, or 24-bit Right-Justified format.
BCK = 32 fS is supported only for 16-bit data length.
LRCK
Right Channel
Left Channel
BCK
DIN
N M L
2
1 0
LSB
MSB
N M L
1 0
2
MSB
LSB
Figure 22. Audio Data Format: 16-/20-/24-/32-Bit I2S
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
LRCK
Right Channel
Left Channel
BCK
DIN
N M L
2
1 0
LSB
MSB
N M L
MSB
2
1 0
N
LSB
Figure 23. Audio Data Format: 16-/20-/24-/32-Bit Left-Justified
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
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Right Channel
Left Channel
LRCK
BCK
DIN
0
23 22 21
2
1
MSB
0
23 22 21
LSB
2
1
MSB
0
LSB
Figure 24. Audio Data Format: 24-Bit Right-Justified
LRCK
Right Channel
Left Channel
BCK
DIN
0
15 14 13
2
1 0
MSB
15 14 13
LSB
1 0
2
MSB
LSB
Figure 25. Audio Data Format: 16-Bit Right-Justified
1/fS (64 BCKs)
Left Channel
LRCK
Right Channel
BCK
Left-Justified Mode
DIN
23 22 21
2
1
0
2
1
23 22 21
2
1
0
2
1
23 22 21
2
I S Mode
DIN
23 22 21
0
23 22 21
0
23 22
Figure 26. Audio Data Format: 24-Bit DSP Format
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AUDIO INTERFACE TIMING
Figure 27 and Table 5 describe the detailed audio interface timing specifications.
tBCL
tBCH
BCK
(Input)
1.4 V
tBCY
tLRH
tLRS
LRCK
(Input)
1.4 V
tDIS
tLRW
tDIH
DIN
(Input)
1.4 V
Figure 27. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I2S, and DSP Data Formats
Table 5. Timing Requirements for Figure 27
SYMBOL
MIN
TYP
MAX
UNIT
tBCY
BCK cycle time
75
ns
tBCH
BCK pulse width high
35
ns
tBCL
BCK pulse width low
35
tLRW
18
DESCRIPTION
LRCK pulse width high (LJ, RJ and I2S formats)
ns
1/(2 × fS)
1/(2 × fS)
sec
tBCY
sec
LRCK pulse width high (DSP format)
tBCY
tLRS
LRCK setup time to BCK rising edge
10
ns
tLRH
LRCK hold time to BCK rising edge
10
ns
tDIS
DIN setup time to BCK rising edge
10
ns
tDIH
DIN hold time to BCK rising edge
10
ns
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SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
The PCM1789-Q1 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore,
SCKI and LRCK must have a specific relationship. The PCM1789-Q1 does not need a specific phase
relationship between the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a
specific frequency relationship (ratiometric) between LRCK, BCK, and SCKI.
If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling
frequency change, etc., the DAC internal operation stops within 1/fS, and the analog output is forced into VCOM
(0.5 VCC1) until re-synchronization among SCKI, LRCK, and BCK completes, and then either 38/fS (single, dual
rate) or 29/fS (quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not
occur, and this analog output control and discontinuity does not occur.
Figure 28 shows the DAC analog output during loss of synchronization. During undefined data periods, some
noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or
zero) data to normal data creates a discontinuity of data on the analog outputs, which may then generate some
noise in the audio signal.
The DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and
re-synchronization processes will occur after the system clock resumes.
State of
Synchronization
Asynchronous
Synchronous
Synchronous
Within 1/fS
Undefined Data
DAC
VOUTx±
VCOM
(0.5 VCC1)
38/fS (single, dual rate)
29/fS (quad rate)
Normal
Normal
Figure 28. DAC Outputs During Loss of Synchronization
ZERO FLAG
The PCM1789-Q1 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations
shown in Table 6. Zero flag combinations are selected through the AZRO bit in control register 22 (16h). If the
input data of all the assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the
ZERO1/2 bits are set to a high level, logic '1' state. Furthermore, if the input data of any of the assigned channels
read '1', the ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for
16-/20-/24-bit data width, but is not supported for 32-bit data width.
The active polarity of the zero flag output can be inverted through the ZREV bit in control register 22 (16h). The
reset default is active high for zero detection.
In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A, shown in Table 6.
Table 6. Zero Flag Outputs Combination
ZERO FLAG COMBINATION
ZERO1
ZERO2
A
Left channel
Right channel
B
Left channel or right channel
Left channel and right channel
Note that the ZERO2 pin is multiplexed with AMUTEO pin. Selection of ZERO2 or AMUTEO can be changed
through the MZSEL bit in control register 22 (16h). The default setting after reset is the selection of ZERO2.
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AMUTE CONTROL
The PCM1789-Q1 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control
pin of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital
input and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute
circuit. AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such
as an SCKI halt, asynchronous detect, zero detect, or by the DAC disable command) that forces the DAC
outputs to a center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output,
pull-ups by the appropriate resistors are required for proper operation.
Note that the AMUTEO pin is multiplexed with the ZERO2 pin. The desired pin is selected through the MZSEL bit
in control register 22 (16h). The default setting is the selection of the ZERO2 pin.
Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA
when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down
control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even
if power-down control is asserted.
MODE CONTROL
The PCM1789-Q1 includes three mode control interfaces with three oversampling configurations, depending on
the input state of the MODE pin, as shown in Table 7. The pull-up and pull-down resistors must be 220 kΩ ±5%.
Table 7. Interface Mode Control Selection
MODE
Tied to DGND
Pull-down resistor to DGND
MODE CONTROL INTERFACE
Two-wire (I2C) serial control, selectable oversampling configuration
Two-wire parallel control, auto mode oversampling configuration
Pull-up resistor to VDD
Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '0'
Tied to VDD
Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '1'
The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the
RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or
reset. From the mode control selection described in Table 7, the functions of four pins are changed, as shown in
Table 8.
Table 8. Pin Functions for Interface Mode
PIN ASSIGNMENTS
PIN
SPI
I2C
H/W
21
MD (input)
SDA (input/output)
DEMP (input)
22
MC (input)
SCL (input)
FMT (input)
23
MS (input)
ADR0 (input)
RSV (input, low)
24
ADR5 (input)
ADR1 (input)
RSV (input, low)
In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or
I2C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through
the high/low control of two specific pins, as described in the following section.
PARALLEL HARDWARE CONTROL
The functions shown in Table 9 and Table 10 are controlled by two pins, DEMP and FMT, in parallel hardware
control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of both channels. The FMT pin
controls the audio interface format for both channels.
Table 9. DEMP Functionality
20
DEMP
DESCRIPTION
Low
De-emphasis off
High
44.1 kHz de-emphasis on
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Table 10. FMT Functionality
FMT
DESCRIPTION
Low
16-/20-/24-/32-bit I2S format
High
16-/20-/24-/32-bit left-justified format
THREE-WIRE (SPI) SERIAL CONTROL
The PCM1789-Q1 includes an SPI-compatible serial port that operates asynchronously with the audio serial
interface. The control interface consists of MD/SDA/DEMP, MC/SCL/FMT, and MS/ADR0/RSV. MD is the serial
data input used to program the mode control registers. MC is the serial bit clock that shifts the data into the
control port. MS is the select input used to enable the mode control port.
CONTROL DATA WORD FORMAT
All single write operations via the serial control port use 16-bit data words. Figure 29 shows the control data word
format. The first bit (fixed at '0') is for write operation. After the first bit are seven other bits, labeled ADR[6:0],
that set the register address for the write operation. ADR6 is determined by the status of the MODE pin. ADR5 is
determined by the state of the ADR5/ADR1/RSV pin. A maximum of four PCM1789-Q1s can be connected on
the same bus at any one time. Each PCM1789-Q1 responds when receiving its own register address. The eight
least significant bits (LSBs), D[7:0] on MD, contain the data to be written to the register address specified by
ADR[6:0].
MSB
0
LSB
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
D6
D7
D5
Register Address
D3
D4
D2
D1
D0
Register Data
Figure 29. Control Data Word Format for MD
REGISTER WRITE OPERATION
Figure 30 shows the functional timing diagram for single write operations on the serial control port. MS is held at
a high state until a register is to be written to. To start the register write cycle, MS is set to a low state. 16 clocks
are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the 16th clock cycle
has been completed, MS is set high to latch the data into the indexed mode control register.
In addition to single write operations, the PCM1789-Q1 also supports multiple write operations, which can be
performed by sending the N-bytes (where N ≤ 9) of the 8-bit register data that follow after the first 16-bit register
address and register data, while keeping the MC clocks and MS at a low state. Ending a multiple write operation
can be accomplished by setting MS to a high state.
MS
MC
MD
X
(1)
'0'
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
ADR6
(1) X = don't care.
Figure 30. Register Write Operation
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TIMING REQUIREMENTS
Figure 31 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are
critical for proper control port operation.
tMHH
MS
1.4 V
tMCH
tMSS
tMCL
tMSH
MC
1.4 V
tMCY
tMDS
ADR0
MSB (R/W)
MD
tMDH
LSB (D0)
D7
1.4 V
Figure 31. Three-Wire Serial Control Interface Timing
Table 11. Timing Requirements for Figure 31
SYMBOL
PARAMETER
MIN
MAX
UNIT
tMCY
MC pulse cycle time
100
ns
tMCL
MC low-level time
40
ns
tMCH
MC high-level time
40
ns
tMHH
MS high-level time
tMCY
ns
tMSS
MS falling edge to MC rising edge
30
ns
tMSH
MS rising edge from MC rising edge for LSB
15
ns
tMDH
MD hold time
15
ns
tMDS
MD setup time
15
ns
TWO-WIRE (I2C) SERIAL CONTROL
The PCM1789-Q1 supports an I2C-compatible serial bus and data transmission protocol for fast mode configured
as a slave device. This protocol is explained in the I2C specification 2.0.
The PCM1789-Q1 has a 7-bit slave address, as shown in Figure 32. The first five bits are the most significant
bits (MSBs) of the slave address and are factory-preset to '10011'. The next two bits of the address byte are
selectable bits that can be set by MS/ADR0/RSV and ADR5/ADR1/RSV. A maximum of four PCM1789-Q1s can
be connected on the same bus at any one time. Each PCM1789-Q1 responds when it receives its own slave
address.
MSB
1
LSB
0
0
1
1
ADR1
ADR0
R/W
Figure 32. Slave Address
22
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PACKET PROTOCOL
A master device must control the packet protocol, which consists of a start condition, a slave address with the
read/write bit, data if a write operation is required, an acknowledgment if a read operation is required, and a stop
condition. The PCM1789-Q1 supports both slave receiver and transmitter functions. Details about DATA for both
write and read operations are described in Figure 33.
SDA
SCL
1 to 7
St
Slave Address
8
9
(1)
R/W
1 to 8
ACK
(2)
(3)
DATA
9
1 to 8
9
9
ACK
DATA
ACK
ACK
Sp
Start
Condition
Stop
Condition
(1) R/W: Read operation if '1'; write operation otherwise.
(2) ACK: Acknowledgment of a byte if '0', not Acknowledgment of a byte if '1'.
(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.
Figure 33. I2C Packet Control Protocol
WRITE OPERATION
The PCM1789-Q1 supports a receiver function. A master device can write to any PCM1789-Q1 register using
single or multiple accesses. The master sends a PCM1789-Q1 slave address with a write bit, a register address,
and the data. If multiple access is required, the address is that of the starting register, followed by the data to be
transferred. When valid data are received, the index register automatically increments by one. When the register
address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1789-Q1 does
not send an acknowledgment. Figure 34 illustrates a diagram of the write operation. The register address and
write data are in 8-bit, MSB-first format.
Transmitter
M
M
M
S
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
W
ACK
Reg Address
ACK
Write Data 1
ACK
Write Data 2
ACK
ACK
Sp
NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.
Figure 34. Framework for Write Operation
READ OPERATION
A master device can read the registers of the PCM1789-Q1. The value of the register address is stored in an
indirect index register in advance. The master sends the PCM1789-Q1 slave address with a read bit after storing
the register address. Then the PCM1789-Q1 transfers the data that the index register points to. Figure 35 shows
a diagram of the read operation.
Transmitter
Data Type
M
St
M
Slave Address
M
W
S
ACK
M
Reg Address
S
ACK
M
Sr
M
Slave Address
(1)
M
S
S
M
M
R
ACK
Read Data
NACK
Sp
(1) The slave address after the repeated start condition must be the same as the previous slave address.
NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,
NACK = Not acknowledge, and Sp = Stop condition.
Figure 35. Framework for Read Operation
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TIMING REQUIREMENTS: SCL AND SDA
A detailed timing diagram for SCL and SDA is shown in Figure 36.
Repeated
START
START
tBUF
STOP
tD-HD
tD-SU
tSDA-R
tP-SU
SDA
tSCL-R
tSDA-F
tS-HD
tLOW
SCL
tSCL-F
tS-HD
tHI
tS-SU
Figure 36. SCL and SDA Control Interface Timing
Table 12. Timing Requirements for Figure 36
STANDARD MODE
SYMBOL
PARAMETER
MIN
MAX
FAST MODE
MIN
100
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
tBUF
Bus free time between STOP and START condition
4.7
1.3
μs
tLOW
Low period of the SCL clock
4.7
1.3
μs
tHI
High period of the SCL clock
4.0
0.6
μs
tS-SU
Setup time for START/Repeated START condition
4.7
0.6
μs
tS-HD
Hold time for START/Repeated START condition
4.0
0.6
μs
tD-SU
Data setup time
250
100
tD-HD
Data hold time
0
tSCL-R
ns
3450
0
900
ns
Rise time of SCL signal
1000
20 + 0.1 CB
300
ns
tSCL-F
Fall time of SCL signal
1000
20 + 0.1 CB
300
ns
tSDA-R
Rise time of SDA signal
1000
20 + 0.1 CB
300
ns
tSDA-F
Fall time of SDA signal
1000
20 + 0.1 CB
300
tP-SU
Setup time for STOP condition
tGW
Allowable glitch width
N/A
50
ns
CB
Capacitive load for SDA and SCL line
400
100
pF
VNH
Noise margin at high level for each connected device
(including hysteresis)
0.2 × VDD
0.2 × VDD
V
VNL
Noise margin at low level for each connected device
(including hysteresis)
0.1 × VDD
0.1 × VDD
V
VHYS
Hysteresis of Schmitt trigger input
N/A
0.05 × VDD
V
24
4.0
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μs
0.6
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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)
The PCM1789-Q1 has many user-programmable functions that are accessed via control registers, and are
programmed through the SPI or I2C serial control port. Table 13 shows the available mode control functions
along with reset default conditions and associated register addresses. Table 14 lists the register map.
Table 13. User-Programmable Mode Control Functions
RESET DEFAULT
REGISTER (1)
LABEL
Mode control register reset
Normal operation
16
MRST
System reset
Normal operation
16
SRST
Mute disabled
16
AMUTE[3:0]
FUNCTION
Analog mute function control
Sampling mode selection
Auto
16
SRDA[1:0]
Power save
17
PSMDA
2
I S
17
FMTDA[2:0]
Normal operation
18
OPEDA
Sharp roll-off
18
FLT
Power-save mode selection
Audio interface format selection
Operation control
Digital filter roll-off control
Output phase selection
Normal
19
REVDA[2:1]
Soft mute control
Mute disabled
20
MUTDA[2:1]
Zero flag
Not detected
21
ZERO[2:1]
0 dB to –63 dB, 0.5-dB step
22
DAMS
Disabled
22
DEMP[1:0]
ZERO2
22
MZSEL
22
AZRO
Digital attenuation mode
Digital de-emphasis function control
AMUTEO/ZERO flag selection
ZERO1: left-channel
Zero flag function selection
ZERO2: right-channel
Zero flag polarity selection
Digital attenuation level setting
(1)
High for detection
22
ZREV
0 dB, no attenuation
24, 25
ATDAx[7:0]
If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state
of ADR6, 5 (01, 10 and 11).
Table 14. Register Map
ADR[6:0]
(1)
(2)
(1)
DATA[7:0]
DEC
HEX
B7
B6
B5
B4
B3
B2
16
10
17
11
18
12
19
13
RSV
20
14
RSV (2)
MRST
SRST
AMUTE3
AMUTE2
AMUTE1
AMUTE0
SRDA1
SRDA0
PSMDA
RSV (2)
RSV (2)
RSV (2)
RSV (2)
FMTDA2
FMTDA1
FMTDA0
RSV (2)
RSV (2)
RSV (2)
OPEDA
RSV (2)
RSV (2)
RSV (2)
FLT
(2)
(2)
(2)
(2)
(2)
(2)
RSV (2)
RSV (2)
RSV (2)
REVDA2
REVDA1
RSV (2)
RSV (2)
MUTDA2
MUTDA1
21
15
RSV (2)
RSV (2)
RSV (2)
RSV (2)
RSV (2)
RSV (2)
(2)
ZERO2
ZERO1
(2)
RSV
RSV
RSV
RSV
RSV
B1
B0
22
16
DAMS
RSV
DEMP1
DEMP0
MZSEL
RSV
AZRO
ZREV
23
17
RSV (2)
RSV (2)
RSV (2)
RSV (2)
RSV (2)
RSV (2)
RSV (2)
RSV (2)
24
18
ATDA17
ATDA16
ATDA15
ATDA14
ATDA13
ATDA12
ATDA11
ATDA10
25
19
ATDA27
ATDA26
ATDA25
ATDA24
ATDA23
ATDA22
ATDA21
ATDA20
If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state
of ADR6, 5 (01, 10 and 11).
RSV must be set to '0'.
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REGISTER DEFINITIONS
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
16
10
MRST
SRST
AMUTE3
AMUTE2
AMUTE1
AMUTE0
SRDA1
SRDA0
MRST
Mode control register reset
This bit sets the mode control register reset to the default value. Pop noise may be generated.
Returning the MRST bit to '1' is unnecessary because it is automatically set to '1' after the mode
control register is reset.
Default value = 1.
MRST
SRST
Mode control register reset
0
Set default value
1
Normal operation (default)
System reset
This bit controls the system reset, which includes the resynchronization between the system
clock and sampling clock, and DAC operation restart. The mode control register is not reset and
the PCM1789-Q1 does not go into a power-down state. Returning the SRST bit to '1' is
unnecessary; it is automatically set to '1' after triggering a system reset.
Default value = 1.
SRST
System reset
0
Resynchronization
1
Normal operation (default)
AMUTE[3:0] Analog mute function control
These bits control the enabling/disabling of each source event that triggers the analog mute
control circuit.
Default value = 0000.
AMUTE
26
Analog mute function control
xxx0
Disable analog mute control by SCKI halt
xxx1
Enable analog mute control by SCKI halt
xx0x
Disable analog mute control by asynchronous detect
xx1x
Enable analog mute control by asynchronous detect
x0xx
Disable analog mute control by ZERO1 and ZERO2 detect
x1xx
Enable analog mute control by ZERO1 and ZERO2 detect
0xxx
Disable analog mute control by DAC disable command
1xxx
Enable analog mute control by DAC disable command
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SRDA[1:0]
Sampling mode selection
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is
automatically set according to multiples between the system clock and sampling clock: single rate
for 512 fS, 768 fS, and 1152 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA
Sampling mode selection
00
Auto (default)
01
Single rate
10
Dual rate
11
Quad rate
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
17
11
PSMDA
RSV
RSV
RSV
RSV
FMTDA2
FMTDA1
FMTDA0
PSMDA
Power-save mode selection
This bit selects the power-save mode for the OPEDA function. When PSMDA = 0, OPEDA
controls the power-save mode and normal operation. When PSMDA = 1, OPEDA functions
controls the DAC disable (not power-save mode) and normal operation.
Default value: 0.
PSMDA
RSV
Power-save mode selection
0
Power-save enable mode (default)
1
Power-save disable mode
Reserved
Reserved; do not use.
FMTDA[2:0] Audio interface format selection
These bits control the audio interface format for DAC operation. Details of the format and any
related restrictions with the system clock are described in the Audio Data Interface Formats and
Timing section.
Default value: 0000 (16-/20-/24-/32-bit I2S format).
FMTDA
Audio interface format selection
000
16-/20-/24-/32-bit I2S format (default)
001
16-/20-/24-/32-bit left-justified format
010
24-bit right-justified format
011
16-bit right-justified format
100
24-bit I2S mode DSP format
101
24-bit left-justified mode DSP format
110
Reserved
111
Reserved
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DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
18
12
RSV
RSV
RSV
OPEDA
RSV
RSV
RSV
FLT
RSV
Reserved
Reserved; do not use.
OPEDA
Operation control
This bit controls the DAC operation mode. In operation disable mode, the DAC output is cut off
from DIN and the internal DAC data are reset. If PSMDA = 1, the DAC output is forced into
VCOM. If PSMDA = 0, the DAC output is forced into AGND and the DAC goes into a
power-down state. For normal operating mode, this bit must be '0'. The serial mode control is
effective during operation disable mode.
Default value: 0.
OPEDA
FLT
Operation control
0
Normal operation
1
Operation disable with or without power save
Digital filter roll-off control
This bit allows users to select the digital filter roll-off that is best suited to their applications. Sharp
and slow filter roll-off selections are available. The filter responses for these selections are shown
in the Typical Characteristics sections of this data sheet.
Default value: 0.
FLT
Digital filter roll-off control
0
Sharp roll-off
1
Slow roll-off
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
19
13
RSV
RSV
RSV
RSV
RSV
RSV
REVDA2
REVDA1
RSV
Reserved
Reserved; do not use.
REVDA[2:1] Output phase selection
These bits are used to control the phase of the DAC analog signal outputs.
Default value: 00.
REVDA
28
Output phase selection
x0
Left channel normal output
x1
Left channel inverted output
0x
Right channel normal output
1x
Right channel inverted output
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DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
20
14
RSV
RSV
RSV
RSV
RSV
RSV
MUTDA2
MUTDA1
RSV
Reserved
Reserved; do not use.
MUTDA[2:1] Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding DAC
outputs, VOUTx. The Soft Mute function is incorporated into the digital attenuators. When mute is
disabled (MUTDA[2:1] = 0), the attenuator and DAC operate normally. When mute is enabled by
setting MUTDA[2:1] = 1, the digital attenuator for the corresponding output is decreased from the
current setting to infinite attenuation. By setting MUTDA[2:1] = 0, the attenuator is increased to
the last attenuation level in the same manner as it is for decreasing levels. This configuration
reduces pop and zipper noise during muting of the DAC output. This Soft Mute control uses the
same resource of digital attenuation level setting. Mute control has priority over the digital
attenuation level setting.
Default value: 00.
MUTDA
Soft Mute control
x0
Left channel mute disabled
x1
Left channel mute enabled
0x
Right channel mute disabled
1x
Right channel mute enabled
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
21
15
RSV
RSV
RSV
RSV
RSV
RSV
ZERO2
ZERO1
RSV
Reserved
Reserved; do not use.
ZERO[2:1]
Zero flag (read-only)
These bits indicate the present status of the zero detect circuit for each DAC channel; these bits
are read-only.
ZERO
Zero flag
x0
Left channel zero input not detected
x1
Left channel zero input detected
0x
Right channel zero input not detected
1x
Right channel zero input detected
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DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
22
16
DAMS
RSV
DEMP1
DEMP0
MZSEL
RSV
AZRO
ZREV
DAMS
Digital attenuation mode
This bit selects the attenuation mode.
Default value: 0.
DAMS
RSV
Digital attenuation mode
0
Fine step: 0.5-dB step for 0 dB to –63 dB range (default)
1
Wide range: 1-dB step for 0 dB to –100 dB range
Reserved
Reserved; do not use.
DEMP[1:0]
Digital de-emphasis function/sampling rate control
These bits are used to disable and enable the various sampling frequencies of the digital
de-emphasis function.
Default value: 00.
DEMP
MZSEL
Digital de-emphasis function/sampling rate control
00
Disable (default)
01
48 kHz enable
10
44.1 kHz enable
11
32 kHz enable
AMUTEO/ZERO flag selection
This bit is used to select the function of the ZERO2 pin.
Default value: 0.
MZSEL
AZRO
AMUTEO/ZERO flag selection
0
The ZERO2 pin functions as ZERO2 (default).
1
The ZERO2 pin functions as AMUTEO.
Zero flag channel combination selection
This bit is used to select the zero flag channel combination for ZERO1 and ZERO2.
Default value: 0.
AZRO
ZREV
Zero flag combination selection
0
Combination A: ZERO1 = left channel, ZERO2 = right channel (default)
1
Combination B: ZERO1 = left channel or right channel, ZERO2 = left channel and
right channel
Zero flag polarity selection
This bit controls the polarity of the zero flag pin.
Default value: 0.
30
ZREV
Zero flag polarity selection
0
High for zero detect (default)
1
Low for zero detect
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DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
23
24
25
17
18
19
RSV
ATDA17
ATDA27
RSV
ATDA16
ATDA26
RSV
ATDA15
ATDA25
RSV
ATDA14
ATDA24
RSV
ATDA13
ATDA23
RSV
ATDA12
ATDA22
RSV
ATDA11
ATDA21
RSV
ATDA10
ATDA20
RSV
Reserved
Reserved; do not use.
ATDAx[7:0] Digital attenuation level setting
Where x = 1 to 2, corresponding to the DAC output (VOUTx).
Both DAC outputs (VOUTL and VOUTR) have a digital attenuation function. The attenuation level
can be set from 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by
incrementing or decrementing one step (S dB) for every 8/fS time interval until the programmed
attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation
(or mute). R (range) and S (step) is –63 and 0.5 for DAMS = 0, and –100 and 1.0 for DAMS = 1,
respectively. The DAMS bit is defined in register 22 (16h). Table 15 shows attenuation levels for
various settings.
The attenuation level for each channel can be set individually using the following formula:
Attenuation level (dB) = S × (ATDAx[7:0]DEC – 255)
where ATDAx[7:0]DEC = 0 through 255.
For ATDAx[7:0]DEC = 0 through 128 with DAMS = 0, or 0 through 154 with DAMS = 1, attenuation
is set to infinite attenuation (mute).
Default value: 1111 1111.
Table 15. Attenuation Levels for Various Settings
ATDAx[7:0]
ATTENUATION LEVEL SETTING
BINARY
DECIMAL
DAMS = 0
DAMS = 1
1111 1111
255
0 dB, no attenuation (default)
0 dB, no attenuation (default)
1111 1110
254
–0.5 dB
–1 dB
1111 1101
253
–1.0 dB
–2 dB
...
...
...
...
1001 1100
156
–45.9 dB
–99 dB
1001 1011
155
–50.0 dB
–100 dB
1001 1010
154
–50.5 dB
Mute
...
...
...
...
1000 0010
130
–62.5 dB
Mute
1000 0001
129
–63.0 dB
Mute
0000 0000
128
Mute
Mute
...
...
...
...
0000 0000
0
Mute
Mute
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APPLICATION INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 37, with the necessary power-supply bypassing and decoupling
components. Texas Instruments’ PLL170X is used to generate the system clock input at SCKI, as well as to
generate the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) are recommended
for SCKI, LRCK, BCK, and DIN for electromagnetic interference (EMI) reduction.
R1
R2
Audio DSP
or
Decoder
R3
R4
PLL170x
ADR5/ADR1/RSV 24
1
LRCK
2
BCK
3
DIN
MC/SCL/FMT 22
4
RST
MD/SDA/DEMP 21
5
SCKI
6
VDD
7
DGND
ZERO2/AMUTEO 18
8
VCC1
AMUTEI 17
9
VCOM
MS/ADR0/RSV 23
MODE 20
PCM1789
Microcontroller
or
Microprocessor
See Termination
Circuit Options Below
ZERO1 19
C1
C2
+
C4
VCC2 16
+5 V
+
C3
AGND2 15
10 AGND1
+3.3 V
R5
11 VOUTL-
VOUTR- 14
12 VOUTL+
VOUTR+ 13
C6
+
C5
0V
LPF and Buffer
LPF and Buffer
Termination Circuit Options (select one)
3.3 V
20
3.3 V
20
R6
20
R6
20
0V
0V
NOTE: C1 through C3 are 1-μF ceramic capacitors. C4 through C6 are 10-μF electrolytic capacitors. R1 through R4 are 22-Ω to 100-Ω
resistors. R5 is a resistor appropriate for pull-up. R6 is a 220-kΩ resistor, ±5%. An appropriate resistor is required for pull-up, if
ZERO2/AMUTEO pin is used as AMUTEO.
Figure 37. Basic Connection Diagram
POWER SUPPLY AND GROUNDING
The PCM1789-Q1 requires +5 V for the analog supply and +3.3 V for the digital supply. The +5-V supply is used
to power the DAC analog and output filter circuitry, and the +3.3-V supply is used to power the digital filter and
serial interface circuitry. For best performance, it is recommended to use a linear regulator (such as the
REG101-5/33, REG102-5/33, or REG103-5/33) with the +5-V and +3.3-V supplies.
Five capacitors are required for supply bypassing, as shown in Figure 37. These capacitors should be located as
close as possible to the PCM1789-Q1 package. The 10-μF capacitors are aluminum electrolytic, while the three
1-μF capacitors are ceramic.
32
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): PCM1789-Q1
PCM1789-Q1
SBAS546 – MARCH 2011
www.ti.com
LOW-PASS FILTER AND DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER FOR DAC OUTPUTS
ΔΣ DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the
expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise
must be low-pass filtered in order to provide optimal converter performance. This filtering is accomplished by a
combination of on-chip and external low-pass filters.
Figure 38 and Figure 39 show the recommended external differential-to-single-ended converter with low-pass
active filter circuits for ac-coupled and dc-coupled applications. These circuits are second-order Butterworth
filters using a multiple feedback (MFB) circuit arrangement that reduces sensitivity to passive component
variations over frequency and temperature. For more information regarding MFB active filter designs, please
refer to Applications Bulletin SBAA055, Dynamic Performance Testing of Digital Audio D/A Converters, available
from the TI web site (www.ti.com) or your local Texas Instruments' sales office.
Because the overall system performance is defined by the quality of the DACs and the associated analog output
circuitry, high-quality audio op amps are recommended for the active filters. Texas Instruments’ OPA2134,
OPA2353, and NE5532A dual op amps are shown in Figure 38 and Figure 39, and are recommended for use
with the PCM1789-Q1.
R2
C2
R3
47W
C1
+
VOUTx(4 VPP)
R1
10 mF
+
VOUTx+
(4 VPP)
R1
10 mF
Analog Output
(2 VRMS)
R3
R2
C2
NOTE: Amplifier is an NE5532A x 1/2 or OPA2134 x1/2; R1 = 7.5 kΩ; R2 = 5.6 kΩ; R3 = 360 Ω; C1 = 3300 pF; C2 = 680 pF; Gain = 0.747;
f–3 dB = 53 kHz.
Figure 38. AC-Coupled, Post-LPF and Differential to Single-Ended Buffer
R2
C2
VOUTx+
(4 VPP)
VOUTx(4 VPP)
R1
R3
47W
C1
R1
Analog Output
(2 VRMS)
R3
R2
C2
NOTE: Amplifier is an NE5532A x 1/2 or OPA2134 x1/2; R1 = 15 kΩ; R2 = 11 kΩ; R3 = 820 Ω; C1 = 1500 pF; C2 = 330 pF; Gain = 0.733;
f–3 dB = 54 kHz.
Figure 39. DC-Coupled, Post-LPF and Differential to Single-Ended Buffer
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Product Folder Link(s): PCM1789-Q1
33
PCM1789-Q1
SBAS546 – MARCH 2011
www.ti.com
PCB LAYOUT GUIDELINES
A typical printed circuit board (PCB) layout for the PCM1789-Q1 is shown in Figure 40. A ground plane is
recommended, with the analog and digital sections being isolated from one another using a split or cut in the
circuit board. The PCM1789-Q1 should be oriented with the digital I/O pins facing the ground plane split/cut to
allow for short, direct connections to the digital audio interface and control signals originating from the digital
section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This configuration
prevents the switching noise present on the digital supply from contaminating the analog power supply and
degrading the dynamic performance of the PCM1789-Q1.
Analog Power
Digital Power
+3.3 VD
DGND
AGND
+5 VA +VS -VS
VDD
Digital Logic
and
Audio
Processor
VCC
DGND
PCM1789
Output
Circuits
Digital
Ground
AGND
Digital Section
Analog Section
Analog
Ground
Return Path for 3.3 VD and Digital Signals
Figure 40. Recommended PCB Layout
34
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Product Folder Link(s): PCM1789-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
PCM1789TPWRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
24
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
PCM1789T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
OTHER QUALIFIED VERSIONS OF PCM1789-Q1 :
• Catalog: PCM1789
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM1789TPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM1789TPWRQ1
TSSOP
PW
24
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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