Texas Instruments | 20W Mono Class-D Audio Power Amplifier (Rev. E) | Datasheet | Texas Instruments 20W Mono Class-D Audio Power Amplifier (Rev. E) Datasheet

Texas Instruments 20W Mono Class-D Audio Power Amplifier (Rev. E) Datasheet
TPA3001D1
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SLOS398E – DECEMBER 2002 – REVISED AUGUST 2010
20-W MONO CLASS-D AUDIO POWER AMPLIFIER
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FEATURES
DESCRIPTION
•
The TPA3001D1 (sometimes referred to as
TPA3001) is a 20-W monaural bridge-tied load (BTL)
class-D audio power amplifier (class-D amp) with high
efficiency, eliminating the need for heat sinks. The
TPA3001D1 can drive 4-Ω or 8-Ω speakers with only
a ferrite bead filter required to reduce EMI.
1
23
•
•
•
•
•
20 W Into 8-Ω Load From 18-V Supply (10%
THD+N)
Short-Circuit Protection (Short to VCC, Short to
GND, Short Between Outputs)
Third-Generation Modulation Technique:
– Replaces Large LC Filter With Small,
Low-Cost Ferrite Bead Filter in Most
Applications
– Improved Efficiency
– Improved SNR
Low Supply Current: 8 mA Typ at 12 V
Shutdown Control: < 1 mA Typ
Space-Saving, Thermally-Enhanced
PowerPAD™ Packaging
The amplifier also includes depop circuitry to reduce
the amount of pop at power-up and when cycling
SHUTDOWN.
The TPA3001D1 (TPA3001) is available in the 24-pin
thermally enhanced TSSOP package (PWP), which
eliminates the need for an external heat sink.
APPLICATIONS
•
•
•
The gain of the amplifier is controlled by two input
terminals, GAIN1 and GAIN0. This allows the
amplifier to be configured for a gain of 12, 18, 23.6,
or 36 dB. The differential input stage provides high
common-mode rejection and improved power-supply
rejection.
LCD Monitors/TVs
Hands-Free Car Kits
Powered Speakers
EFFICIENCY
vs
OUTPUT POWER
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
90
21
8Ω
80
PO − Maximum Output Power − W
4Ω
70
Efficiency − %
60
50
40
30
20
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
10
VCC = 18 V
0
0
4
VCC = 18 V
19
8
12
PO − Output Power − W
16
20
TA = 25°C,
10% THD Maximum
5
3.6 4
5
6
7
8
ZL − Load Impedance − Ω
9
10
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
TPA3001D1
SLOS398E – DECEMBER 2002 – REVISED AUGUST 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS (1)
PACKAGED DEVICES
TA
TSSOP (PWP) (2)
–40°C to 85°C
(1)
(2)
TPA3001D1PWP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g.,
TPA3001D1PWPR).
PWP PACKAGE
(TOP VIEW)
INN
INP
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
BSN
PVCC
OUTN
OUTN
PGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PVCC
OUTP
OUTP
PGND
Pin Functions
PIN
NAME
NO.
AGND
18, 19
I/O
DESCRIPTION
Analog ground terminal
BSN
8
I
Bootstrap terminal for high-side gate drive of negative BTL output (connect a 0.22-mF capacitor with a 51-Ω
resistor in series from OUTN to BSN)
BSP
17
I
Bootstrap terminal for high-side gate drive of positive BTL output (connect a 0.22-mF capacitor with a 51-Ω
resistor in series from OUTP to BSP)
BYPASS
22
I
Connect 1-mF capacitor to ground for BYPASS voltage filtering
COSC
21
I
Connect a 220-pF capacitor to ground to set oscillation frequency
GAIN0
3
I
Bit 0 of gain control (see Table 1 for gain settings)
GAIN1
4
I
Bit 1 of gain control (see Table 1 for gain settings)
INN
1
I
Negative differential input
INP
2
I
Positive differential input
OUTN
10, 11
O
Negative BTL output, connect Schottky diode from PGND to OUTN for short-circuit protection
OUTP
14, 15
O
Positive BTL output, connect Schottky diode from PGND to OUTP for short-circuit protection
PGND
6, 12, 13
PVCC
9, 16
I
High-voltage power supply (for output stages)
ROSC
20
I
Connect a 120-kΩ resistor to ground to set oscillation frequency
SHUTDOWN
5
I
Shutdown terminal (negative logic), TTL compatible, 21-V compliant
VCC
24
I
Analog high-voltage power supply
VCLAMP
7
O
Connect 1-mF capacitor to ground to provide reference voltage for H-bridge gates
VREF
23
O
5-V internal regulator for control circuitry (connect a 0.1-mF to 1-mF capacitor to ground)
Thermal pad
–
–
Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to AGND.
Thermal vias on the PCB should connect this pad to a large copper area on an internal or bottom layer for the
best thermal performance. The PAD must be soldered to the PCB for mechanical reliability.
2
Power ground
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FUNCTIONAL BLOCK DIAGRAM
VREF
AGND
VREF
VCC
VCLAMP
VCC
Clamp
Reference
BSN
PVCC
+
_
Gain
Adjust
INN
Deglitch
Logic
Gate
Drive
OUTN
_
PGND
+
_
BSP
+
_
PVCC
+
Gain
Adjust
INP
+
_
_
+
Deglitch
Logic
Gate
Drive
OUTP
PGND
SD
SHUTDOWN
GAIN1
2
GAIN0
Gain
Biases
and
References
Ramp
Generator
COSC
ROSC
BYPASS
Short-Circuit
Detect
Start-Up
Protection
Logic
Thermal
VCC OK
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage: VCC, PVCC
–0.3 V to 21 V
≥ 3.6 Ω
Load impedance, ZL
SHUTDOWN
Input voltage
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1
–0.3 V to 5.5 V
INN, INP
–0.3 V to 7 V
Continuous total power dissipation
See the Thermal Information Table
Operating free-air temperature range, TA
–40°C to 85°C
Operating junction temperature range, TJ
–40°C to 150°C
Storage temperature range, Tstg
–65°C to 150°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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THERMAL INFORMATION
TPA3001D1
THERMAL METRIC (1) (2)
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
qJB
Junction-to-board thermal resistance
15.2
yJT
Junction-to-top characterization parameter
0.9
yJB
Junction-to-board characterization parameter
8.4
qJCbot
Junction-to-case (bottom) thermal resistance
1.2
(1)
(2)
UNITS
PWP (24 Pins)
36.2
32
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
ZL ≥ 3.6 Ω
Supply voltage, VCC, PVCC
(1)
Load impedance, ZL
MAX
8
18
UNIT
V
Ω
3.6
High-level input voltage, VIH
GAIN0, GAIN1, SHUTDOWN
Low-level input voltage, VIL
GAIN0, GAIN1, SHUTDOWN
Operating free-air temperature, TA
(1)
MIN
2
V
–40
0.8
V
85
°C
The TPA3001D1 must not be used with any speaker or load (including speaker with output filter) that could vary below 3.6 Ω over the
audio frequency band.
ELECTRICAL CHARACTERISTICS
TA = 25°C, PVCC = VCC = 12 V (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP MAX UNIT
|VOS|
Output offset voltage (measured
differentially)
VI = 0 V, AV = 12, 18, 23.6 dB
50
PSRR
Power supply rejection ratio
PVCC = 11.5 V to 12.5 V
|IIH|
High-level input current
PVCC = 12 V, VI = PVCC
1
|IIL|
Low-level input current
PVCC = 12 V, VI = 0 V
1
mA
15
mA
VI = 0 V, AV = 36 dB
100
–73
SHUTDOWN = 2 V, no load
Supply current
SHUTDOWN = VCC, VCC = 18 V, PO = 20 W,
RL = 8 Ω
ICC(SD)
Supply current, shutdown mode
SHUTDOWN = 0.8 V
fs
Switching frequency
ROSC = 120 kΩ, COSC = 220 pF
rds(on)
Output transistor on resistance (total)
IO = 1 A, TJ = 25°C
G
Gain
dB
8
ICC
mV
1.3
mA
A
1
2
250
mA
kHz
0.2
0.3
0.7
Ω
GAIN1 = 0.8 V, GAIN0 = 0.8 V
10.9
12
12.8
dB
GAIN1 = 0.8 V, GAIN0 = 2 V
17.1
18
18.7
dB
GAIN1 = 2 V, GAIN0 = 0.8 V
22.7
23.6
24.3
dB
GAIN1 = 2 V, GAIN0 = 2 V
34.9
36
36.7
dB
OPERATING CHARACTERISTICS
PVCC = VCC = 12 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Continuous output power at 10%
THD+N
f = 1 kHz, RL = 4 Ω
f = 1 kHz, RL = 8 Ω
9
Continuous output power at 1%
THD+N
f = 1 kHz, RL = 4 Ω
10.3
f = 1 kHz, RL = 8 Ω
7.2
THD+N
Total harmonic distortion plus noise
PO = 10 W, RL = 4 Ω, f = 20 Hz to 20 kHz
BOM
Maximum output-power bandwidth
THD = 1%
PO
4
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MAX
UNIT
12.8
W
0.2%
20
kHz
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OPERATING CHARACTERISTICS (continued)
PVCC = VCC = 12 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kSVR
Supply ripple rejection ratio
f = 1 kHz, C(BYPASS) = 1 mF
SNR
Signal-to-noise ratio
PO = 10 W, RL = 4 Ω
95
dB
C(BYPASS) = 1 mF, f = 20 Hz to 22 kHz, no weighting
filter used, gain = 12 dB
86
mV(rms)
Vn
–70
Noise output voltage
C(BYPASS) = 1 mF, f = 20 Hz to 22 kHz, A-weighted
filter, gain = 12 dB
ZI
Input impedance
See Table 1.
dB
–81
dBV
66
mV(rms)
–84
dBV
> 23
kΩ
OPERATING CHARACTERISTICS
PVCC = VCC = 18 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
f = 1 kHz, RL = 4 Ω
Output power at 10% THD+N
PO
Output power at 1% THD+N
20
f = 1 kHz, RL = 4 Ω
10.3
f = 1 kHz, RL = 8 Ω
BOM
Maximum output-power bandwidth
THD = 1%
kSVR
Supply ripple rejection ratio
SNR
Signal-to-noise ratio
PO = 2 W, RL = 8Ω, f = 20 Hz to 20 kHz
0.3%
20
kHz
f = 1 kHz, CBYPASS = 1 mF
–70
dB
PO = 15 W, RL = 8 Ω
102
dB
86
mV(rms)
Noise output voltage
C(BYPASS) = 1 mF, f = 20 Hz to 22 kHz, A-weighted
filter, gain = 12 dB
Input impedance
W
1%
C(BYPASS) = 1 mF, f = 20 Hz to 20 kHz, no weighting
filter used, gain = 12 dB
ZI
UNIT
16
PO = 15 W, RL = 8Ω, f = 20 Hz to 20 kHz
Total harmonic distortion plus noise
MAX
12.8
f = 1 kHz, RL = 8 Ω
THD+N
Vn
TYP
See Table 1.
–81
dBV
66
mV(rms)
84
dBV
>23
kΩ
SPACER
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency
vs Output power
PO
Maximum output power
vs Load impedance
ICC
Supply current
ICC(SD)
Shutdown current
THD+N
Total harmonic distortion + noise
kSVR
Supply voltage rejection ratio
vs Supply voltage
vs Output power
vs Frequency
Gain and phase
CMRR
Common-mode rejection ratio
VIO
Input offset voltage
1
2, 3, 4
5
6
7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17, 18
19, 20, 21, 22, 23, 24, 25
26
vs Frequency
27
28
vs Common-mode input voltage
29
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EFFICIENCY
vs
OUTPUT POWER
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
21
90
8Ω
80
PO − Maximum Output Power − W
70
Efficiency − %
60
50
40
30
20
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
10
VCC = 12 V
0
0
2
4
6
8
VCC = 18 V
19
4Ω
10
12
TA = 25°C,
10% THD Maximum
5
3.6 4
14
5
PO − Output Power − W
Figure 1.
Figure 2.
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
21
10
TA = 60°C
19
19
VCC = 18 V
PO − Maximum Output Power − W
PO − Maximum Output Power − W
9
21
TA = 45°C
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
5
3.6 4
VCC = 18 V
17
15
13
VCC = 15 V
11
9
VCC = 12 V
7
5
6
7
8
ZL − Load Impedance − Ω
9
10
5
3.6 4
Figure 3.
6
6
7
8
ZL − Load Impedance − Ω
5
6
7
8
ZL − Load Impedance − Ω
9
10
Figure 4.
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SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs
SUPPLY VOLTAGE
5
11
ICC(SD) − Shutdown Current − µA
SHUTDOWN = 0.8 V
ICC − Supply Current − mA
10
9
8
7
4
3
2
1
0
6
8
10
12
14
16
8
18
10
14
16
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
18
10
THD+N − Total Harmonic Distortion + Noise − %
10
THD+N − Total Harmonic Distortion + Noise − %
12
VCC − Supply Voltage − V
VCC − Supply Voltage − V
VCC = 18 V
RL = 8 Ω
Gain = 12 dB
1
1 kHz
0.1
20 kHz
0. 01
20 Hz
VCC = 18 V
RL = 8 Ω
Gain = 36 dB
1
1 kHz
20 kHz
0.1
20 Hz
0.01
0.001
0
5
10
15
20
0
PO − Output Power − W
5
10
15
20
PO − Output Power − W
Figure 7.
Figure 8.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 15 V
RL = 8 Ω
Gain = 12 dB
1
1 kHz
20 kHz
20 Hz
0.1
0. 01
0.001
VCC = 15 V
RL = 8 Ω
Gain = 36 dB
1
20 kHz
1 kHz
0.01
0
5
10
15
20
0
5
PO − Output Power − W
15
Figure 9.
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
10
VCC = 15 V
RL = 4 Ω
Gain = 12 dB
1
1 kHz
0.1
20 Hz
20 kHz
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PO − Output Power − W
10
VCC = 15 V
RL = 4 Ω
Gain = 36 dB
1
1 kHz
0.1
20 Hz
20 kHz
0.01
0.01
0
5
10
0
5
10
PO − Output Power − W
PO − Output Power − W
Figure 11.
8
20 Hz
0.1
Figure 12.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V
RL = 8 Ω
Gain = 12 dB
1
1 kHz
20 kHz
20 Hz
0.1
0. 01
VCC = 12 V
RL = 8 Ω
Gain = 36 dB
1
1 kHz
20 kHz
20 Hz
0.1
0.01
0.001
0
5
10
0
15
5
15
Figure 13.
Figure 14.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
10
VCC = 12 V
RL = 4 Ω
Gain = 12 dB
1
1 kHz
0.1
20 Hz
20 kHz
0. 01
0.001
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PO − Output Power − W
PO − Output Power − W
VCC = 12 V
RL = 4 Ω
Gain = 36 dB
1
1 kHz
0.1
20 kHz
20 Hz
0.01
0
5
10
0
PO − Output Power − W
5
10
PO − Output Power − W
Figure 15.
Figure 16.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 8 V
RL = 4 Ω
Gain = 12 dB
1
1 kHz
0.1
20 Hz
20 kHz
0.01
VCC = 8 V
RL = 4 Ω
Gain = 36 dB
1
1 kHz
0.1
20 kHz
20 Hz
0.01
0
2
4
6
0
2
PO − Output Power − W
Figure 18.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
VCC = 18 V
RL = 8 Ω
PO = 10 W
PO = 500 mW
0.1
PO = 2 W
0.01
100
1k
10k 20k
VCC = 15 V
RL = 8 Ω
PO = 10 W
0.1
PO = 500 mW
0.01
PO = 2 W
0.001
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 19.
10
6
Figure 17.
1
0.001
20
4
PO − Output Power − W
Figure 20.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
VCC = 15 V
RL = 4 Ω
PO = 10 W
0.1
PO = 500 mW
0.01
0.001
20
PO = 2 W
100
1k
VCC = 12 V
RL = 8 Ω
PO = 5 W
PO = 250 mW
0.1
0.01
PO = 1 W
0.001
20
10k 20k
100
f − Frequency − Hz
Figure 22.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V
RL = 4 Ω
PO = 2 W
PO = 500 mW
0.01
PO = 7.5 W
0.001
20
10k 20k
Figure 21.
1
0.1
1k
f − Frequency − Hz
100
1k
10k 20k
VCC = 8 V
RL = 8 Ω
PO = 3 W
1
PO = 250 mW
0.1
PO = 1 W
0.01
0.001
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 23.
Figure 24.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
10
−50
kSVR − Supply Voltage Rejection Ratio − dB
VCC = 8 V
RL = 4 Ω
PO = 5 W
1
PO = 1 W
0.1
PO = 250 mW
0.01
0.001
20
100
−60
VCC = 8 V
−70
VDD = 15 V
−80
−90
20
10k 20k
1k
C(Bypass) = 1 µF
RL = 8 Ω
100
Figure 26.
GAIN AND PHASE
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
30
20
12
10
0
10
−20
Phase
6
−30
−40
4
−50
−60
VCC = 8 V
RL = 8 Ω
−70
0
100
1k
10k
−80
100k
Phase − °
Gain − dB
−10
8
VCC = 8 V to 18 V
RL = 8 Ω
−41
−42
−43
−44
−45
−46
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 27.
12
30k
−40
CMRR − Common-Mode Rejection Ratio − dB
Gain
20
10k
Figure 25.
14
2
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 28.
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INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6
VIO − Input Offset Voltage − mV
5
VCC = 8 V to 18 V
4
3
2
1
0
−1
−2
−3
−4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIC − Common-Mode Input Voltage − V
Figure 29.
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APPLICATION INFORMATION
APPLICATION CIRCUIT
U1
TPA3001D1
C1
IN–
0.47 µF
1
2
IN+
C2
0.47 µF
3
GAIN SELECT
4
GAIN SELECT
5
SHUTDOWN
CONTROL
6
7
C10
1 µF
VCC
R2
C8
0.22 µF
51 Ω
8
9
10
C7
10 µF
C5
1 µF
11
12
VCC
INN
VCC
INP
VREF
GAIN0
BYPASS
GAIN1
COSC
23
C3
1 µF
22
21
ROSC
PGND
AGND
C4
1 µF
C11
1 µF
C12
220 pF R1
20
SHUTDOWN
120 kΩ
19
18
VCLAMP
AGND
BSN
BSP
PVCC
PVCC
OUTN
OUTP
OUTN
OUTP
PGND
PGND
D2
24
17
R3
16
51 Ω
C9
0.22 µF
15
VCC
C6
1 µF
14
13
D1
PowerPAD
L2
(Ferrite
Bead)
L1
(Ferrite
Bead)
C15
1 nF
C14
1 nF
L1, L2: Fair-Rite, Part Number 2512067007Y3
D1, D2: Diodes, Inc., Part Number B130
Figure 30. Typical Application Circuit
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3001D1.
TRADITIONAL CLASS-D MODULATION SCHEME
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss, thus causing a high supply current.
14
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OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
–12 V
Current
Figure 31. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3001D1 MODULATION SCHEME
The TPA3001D1 uses a modulation scheme that still has each output switching from ground to VCC. However,
OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%
and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is
greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the
switching period, greatly reducing the switching current, which reduces any I2R losses in the load. (See
Figure 32.)
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
–12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
–12 V
Current
Figure 32. The TPA3001D1 Output Voltage and Current Waveforms Into an Inductive Load
MAXIMUM ALLOWABLE OUTPUT POWER (SAFE OPERATING AREA)
The TPA3001D1 can drive load impedances as low as 3.6 Ω from power supply voltages ranging from 8 V to
18 V. To prevent device failure, however, the output power of the TPA3001D1 must be limited. Figure 33 shows
the maximum allowable output power versus load impedance for three power-supply voltages at an ambient
temperature of 25°C. (For ambient temperatures of 45°C and 60°C, see Figure 3 and Figure 4.)
16
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21
VCC = 18 V
PO − Maximum Output Power − W
19
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
TA = 25°C,
10% THD Maximum
5
3.6 4
5
6
7
8
ZL − Load Impedance − Ω
9
10
Figure 33. Output Power
DRIVING A LOW-IMPEDANCE LOAD FROM A HIGH POWER-SUPPLY VOLTAGE
When driving low-impedance loads (e.g., a 4-Ω speaker), the output power can be limited by reducing the
maximum audio input signal level or by reducing the gain of the TPA3001D1. The maximum input voltage may
be calculated with Equation 1.
Vin(pp),max =
8PO(avg),max ´ ZL
AV
(1)
where
PO(avg),max = maximum continuous output power (W)
ZL = load impedance (Ω)
æ G(dB) ö
A V = voltage gain (V/V) = ç
÷
è 20 ø
For example, consider an application in which the TPA3001D1 drives a 4-Ω speaker from an 18-V power supply.
The gain is selected to be 18 dB. The maximum allowable output power for a 4-Ω load impedance is 12.8 W.
From Equation 1, the input voltage must not exceed 2.54 Vpp.
In this same example, however, if the maximum output voltage of audio signal source is 5 Vpp, then the gain of
the TPA3001D1 should be reduced to 12 dB to eliminate the need for limiting the input signal.
The input voltage may be limited using a variety of methods, depending on what is known about the audio signal
source. If the maximum output voltage of the source is known, a resistive voltage divider in conjunction with
proper TPA3001D1 gain selection may be used to prevent distortion. If the maximum audio source voltage is
unknown, diodes may be used to clamp the input voltage, at the cost of distortion when the input signal level
exceeds the required clamping voltage.
DRIVING THE OUTPUT INTO CLIPPING
The output of the TPA3001D1 may be driven into clipping to attain a higher output power than is possible with no
distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power into
the load may be calculated with Equation 2.
P O(10% THD) + P O(1% THD)
1.25
(2)
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For example, consider an application in which the TPA3001D1 drives an 8-Ω speaker from an 18-V power
supply. The maximum output power with no distortion (less than 1% THD) is 16 W, which corresponds to a
maximum peak output voltage of 16 V. For the same output voltage level driven into clipping (10% THD), the
output power is increased to 20 W.
OUTPUT FILTER CONSIDERATIONS
A ferrite bead filter (shown in Figure 34) should be used in order to pass FCC and/or CE radiated emissions
specifications and if a frequency-sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces
EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting
a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long
wires (greater than 11 inches) from the amplifier to the speaker, as shown in Figure 35 and Figure 36.
Ferrite
Chip Bead
OUTP
1 nF
4 Ω or Greater
Ferrite
Chip Bead
OUTN
1 nF
Figure 34. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3)
15 µH
Ferrite
Chip Bead
OUTP
0.22 mF
15 µH
1 nF
1 µF
Ferrite
Chip Bead
4Ω
OUTN
0.22 mF
1 nF
Figure 35. Typical LC Output Filter for 4-Ω Speaker, Cutoff Frequency of 27 kHz
33 µH
Ferrite
Chip Bead
OUTP
0.1 mF
33 µH
1 nF
0.47 µF
Ferrite
Chip Bead
8Ω
OUTN
0.1 mF
1 nF
Figure 36. Typical LC Output Filter for 8-Ω Speaker, Cutoff Frequency of 27 kHz
18
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SHORT-CIRCUIT PROTECTION
The TPA3001D1 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the
outputs, the part immediately disables the output drive and enters into shutdown mode. This is a latched fault
and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high state
for normal operation. This clears the short-circuit flag and allows for normal operation if the short was removed. If
the short was not removed, the protection circuitry again activates.
Two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to the
TPA3001D1 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and OUTN
as shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5 V at a
minimum of 1-A output current and a dc blocking voltage rating of at least 30 V. The diodes must also be rated to
operate at a junction temperature of 150°C.
If short-circuit protection is not required, the Schottky diodes may be omitted.
THERMAL PROTECTION
Thermal protection on the TPA3001D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
THERMAL CONSIDERATION: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE
To calculate the maximum ambient temperature, Equation 3 may be used:
TAmax = TJmax – qJAPDissipated
(3)
where: TJmax = 150°C
qJA = 1 / derating factor = 1 / 0.03333 = 30°C/W
(The derating factor for the 24-pin PWP package is given in the dissipation rating table.)
To estimate the power dissipation, Equation 4 may be used:
P Dissipated + PO(average)
((1ńEfficiency) * 1)
(4)
Efficiency = ~85% for an 8-Ω load or = ~75% for a 4-Ω load
Example: What is the maximum ambient temperature for an application that requires the TPA3001D1 to drive
10 W into an 8-Ω speaker?
PDissipated = 10 W × ((1 / 0.85) – 1) = 1.76 W
TAmax = 150°C – (30°C/W × 1.76 W) = 97.2°C
This calculation shows that the TPA3001D1 can drive 10 W into an 8-Ω speaker up to the absolute maximum
ambient temperature rating of 85°C, which must never be exceeded. Also, refer to Figure 2, Figure 3, and
Figure 4 to determine the minimum load impedance for the desired output power.
GAIN SETTING VIA GAIN0 AND GAIN1 INPUTS
The gain of the TPA3001D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part to part is small. However, the input impedance may shift by
30% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 23 kΩ, which is the absolute minimum input impedance of the TPA3001D1. At the lower gain
settings, the input impedance could increase as high as 313 kΩ.
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Table 1. Gain Settings
GAIN1
GAIN0
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE
(kΩ)
TYP
TYP
0
0
12
241
0
1
18
168
1
0
23.6
104
1
1
36
33
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3-dB
or cutoff frequency also changes by over six times.
Zf
Ci
Input
Signal
IN
Zi
The –3-dB frequency can be calculated using Equation 5. Use Table 1 for ZI values.
1
f+
2p Z iCi
(5)
INPUT CAPACITOR, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 6.
−3 dB
fc +
1
2 p Zi C i
fc
(6)
The value of CI is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where ZI is 241 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6 is
reconfigured as Equation 7.
1
Ci +
2p Z i f c
(7)
20
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In this example, CI is 33 nF, so one would likely choose a value of 0.1 mF, as this value is commonly used. If the
gain is known and will be constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor
is the leakage path from the input source through the input network (CI) and the feedback network to the load.
This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,
especially in high-gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in
most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it
is important to confirm the capacitor polarity in the application.
POWER SUPPLY DECOUPLING
The TPA3001D1 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 mF, placed as close as possible to the device VCC lead works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 mF or greater placed near the audio
power amplifier is recommended.
BSN AND BSP CAPACITORS
The full H-bridge output stage uses only NMOS transistors. It therefore requires bootstrap capacitors for the high
side of each output to turn on correctly. A 0.22-mF ceramic capacitor, rated for at least 25 V, must be connected
from each output to its corresponding bootstrap input. Specifically, one 0.22-mF capacitor must be connected
from OUTP to BSP, and one 0.22-mF capacitor must be connected from OUTN to BSN. (See Figure 30.)
BSN AND BSP RESISTORS
To limit the current when charging the bootstrap capacitors, a resistor with a value of approximately 50 Ω (±10%
maximum) must be placed in series with each bootstrap capacitor. The current is limited to less than 500 mA.
VCLAMP CAPACITOR
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, an internal
regulator clamps the gate voltage. A 1-mF capacitor must be connected from VCLAMP (pin 7) to ground and
must be rated for at least 25 V. The voltage at VCLAMP (pin 7) varies with VCC and may not be used for
powering any other circuitry.
MIDRAIL BYPASS CAPACITOR
The midrail bypass capacitor (C11 of Figure 30) is the most critical capacitor and serves several important
functions. During start-up or recovery from shutdown mode, CBYPASS determines the rate at which the amplifier
starts up. The second function is to reduce noise produced by the power supply caused by coupling into the
output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as
degraded PSRR and THD+N.
For the bypass capacitor (C11), a ceramic or tantalum low-ESR capacitor of 0.47 mF to 1 mF is recommended for
the best THD noise, and depop performance. The bypass capacitor must have a value greater than the input
capacitors for optimum depop performance.
VREF DECOUPLING CAPACITOR
The VREF terminal (pin 23) is the output of an internally-generated 5-V supply, used for the oscillator and
gain-setting logic. It requires a 0.1-mF to 1-mF capacitor to ground to keep the regulator stable. The regulator may
not be used to power any additional circuitry.
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DIFFERENTIAL INPUT
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3001D1 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3001D1 with a single-ended
source, ac ground the INN input through a capacitor and apply the audio signal to the INP input. In a
single-ended input application, the INN input should be ac-grounded at the audio source instead of at the device
input for best noise performance.
SWITCHING FREQUENCY
The switching frequency is determined using the values of the components connected to ROSC (pin 20) and
COSC (pin 21) and may be calculated with Equation 8:
6.6
fs +
ROSC COSC
(8)
The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC.
SHUTDOWN OPERATION
The TPA3001D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, ICC(SD) = 1 mA. SHUTDOWN should never be left
unconnected, because amplifier operation would be unpredictable.
Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once
any digital circuitry has settled. However, if SHUTDOWN is to be left unused, the terminal may be connected
directly to VCC.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance
the more the real capacitor behaves like an ideal capacitor.
START-UP TIME
The start-up time can be calculated with Equation 9:
t startup + 8.2 ms ) 2 100 kW C11
(9)
where C11 is the value of the bypass capacitor as shown in Figure 30.
22
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PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3001D1 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors—As shown in the Typical Application Circuit , the high-frequency 0.1-mF decoupling
capacitors should be placed as close to the PVCC (pin 9 and pin 16) and VCC (pin 24) terminals as possible.
The BYPASS (pin 22) capacitor, VREF (pin 23) capacitor, and VCLAMP (pin 7) capacitor should also be
placed as close to the device as possible. The large (10 mF or greater) bulk power-supply decoupling
capacitor should be placed near the TPA3001D1.
• Grounding—The VCC (pin 24) decoupling capacitor, VREF (pin 23) capacitor, BYPASS (pin 22) capacitor,
COSC (pin 21) capacitor, and ROSC (pin 20) resistor should each be grounded to analog ground (AGND, pin
18 and pin 19). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground
(PGND, pin 12 and pin 13). Analog ground and power ground may be connected at the thermal pad, which
should be used as a central ground connection or star ground for the TPA3001D1.
• Output filter—The ferrite filter (Figure 34) should be placed as close to the output terminals (pins 10, 11, 14,
and 15) as possible for the best EMI performance. The LC filter (Figure 35 and Figure 36) should be placed
close to the ferrite filter. The capacitors used in both the ferrite and LC filters should be grounded to power
ground.
• Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad thermal land should be 1,6 mm by 6 mm (63 mils by
236.2 mils). Two rows of solid vias (four vias per row, 0,3302 mm or 13 mils diameter) should be equally
spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal
layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal-relief or webbed vias. For
additional information, see the PowerPAD Thermally Enhanced Package application report (SLMA002).
For an example layout, see the TPA3001D1EVM 20-W Mono Class-D Audio Power Amplifier user's guide
(SLOU156).
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPA3001D1PWP
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA3001D1
TPA3001D1PWPG4
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA3001D1
TPA3001D1PWPR
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA3001D1
TPA3001D1PWPRG4
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA3001D1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA3001D1PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA3001D1PWPR
HTSSOP
PWP
24
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 24
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
4.4 x 7.6, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 2.200
PLASTIC SMALL OUTLINE
6.6
TYP
6.2
PIN 1 ID
AREA
A
SEATING PLANE
0.1 C
22X 0.65
24
1
C
2X
7.15
7.9
7.7
NOTE 3
12
B
13
24X
4.5
4.3
0.30
0.19
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
(1)
2.40
1.65
DETAIL A
TYPICAL
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
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EXAMPLE BOARD LAYOUT
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
( 0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
BASED ON
0.125 THICK
STENCIL
SYMM
22X (0.65)
13
12
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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