Texas Instruments | TPA3005D2: 6-W Stereo Class-D Audio Power Amplifier (Rev. A) | Datasheet | Texas Instruments TPA3005D2: 6-W Stereo Class-D Audio Power Amplifier (Rev. A) Datasheet

Texas Instruments TPA3005D2: 6-W Stereo Class-D Audio Power Amplifier (Rev. A) Datasheet
TPA3005D2
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SLOS427A – MAY 2004 – REVISED AUGUST 2010
6-W STEREO CLASS-D AUDIO POWER AMPLIFIER
Check for Samples: TPA3005D2
FEATURES
1
•
•
2
•
•
•
•
•
•
DESCRIPTION
6-W/Ch Into an 8-Ω Load From a 12-V Supply
Up to 92% Efficient, Class-D Operation
Eliminates Need For Heatsinks
8.5-V to 18-V Single-Supply Operation
Four Selectable, Fixed Gain Settings
Differential Inputs Minimizes Common-Mode
Noise
Space-Saving, Thermally Enhanced
PowerPAD™ Packaging
Thermal Protection and Short Circuit
Pinout Similar to TPA3002D2, TPA3003D2,
and TPA3004D2
The TPA3005D2 is a 6-W (per channel) efficient,
Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3005D2 can drive stereo speakers
as low as 8 Ω. The high efficiency of the TPA3005D2
eliminates the need for external heatsinks when
playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 15.3, 21.2, 27.2,
and 31.8 dB.
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts. Thermal
protection
ensures
the
maximum
junction
temperature is not exceeded.
APPLICATIONS
LCD Monitors and TVs
All-In-One PCs
PVCC 10 µF
10 µF PVCC
220 nF
220 nF
BSRP
PVCCR
PVCCR
ROUTP
ROUTP
PGNDR
ROUTN
PGNDR
ROUTN
NC
NC
LINN
NC
TPA3005D2
AVDDREF
AVDD
GAIN0
COSC
GAIN1
ROSC
220 nF
PVCC
0.1 µF
10 µF
10 µF
BSLP
PVCCL
LOUTP
LOUTP
VCLAMPL
PGNDL
AGND
NC
PGNDL
NC
0.1 µF
0.1 µF
10 µF
AGND
NC
BSLN
Gain
Control
LINP
LOUTN
0.47 µF
AVCC
AVCC
V2P5
LOUTN
0.47 µF
NC
RINP
PVCCL
0.47 µF
1 µF
VCLAMPR
RINN
0.47 µF
0.47 µF
Left Differential
Inputs
0.1 µF
SHUTDOWN
PVCCL
Right Differential
Inputs
PVCCR
Shutdown/Mute
Control
PVCCR
BSRN
0.1 µF
PVCCL
•
•
1 µF
220 pF
120 kΩ
1 µF
220 nF
PVCC
† †Optimal output filter for EMI suppression
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
TPA3005D2
SLOS427A – MAY 2004 – REVISED AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
(2)
TA
PACKAGED DEVICE
48-PIN HTQFP (PHP) (1) (2)
-40°C to 85°C
TPA3005D2PHP
The PHP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g.,
TPA3005D2PHPR).
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
TPA3005D2
Supply voltage range
AVCC, PVCC
-0.3 V to 20 V
SHUTDOWN
-0.3 V to VCC + 0.3 V
≥6Ω
Load Impedance, RL
Input voltage range, VI
GAIN0, GAIN1, RINN, RINP, LINN, LINP
Continuous total power dissipation
-0.3 V to 6 V
See Thermal Information Table
Operating free–air temperature range, TA
- 40°C to 85°C
Operating junction temperature range, TJ
- 40°C to 150°C
Storage temperature range, Tstg
- 65°C to 150°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
(2)
TPA3005D2
qJA
Junction-to-ambient thermal resistance
27.7
qJCtop
Junction-to-case (top) thermal resistance
14.8
qJB
Junction-to-board thermal resistance
9.4
yJT
Junction-to-top characterization parameter
0.6
yJB
Junction-to-board characterization parameter
5.6
qJCbot
Junction-to-case (bottom) thermal resistance
0.3
(1)
(2)
UNITS
PHP (48 PINS)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
8.5
18
UNIT
Supply voltage, VCC
PVCC, AVCC
High-level input voltage, VIH
SHUTDOWN, GAIN0, GAIN1
Low-level input voltage, VIL
SHUTDOWN, GAIN0, GAIN1
0.8
V
SHUTDOWN, VI = VCC = 18 V
10
µA
GAIN0, GAIN1, VI = 5.5 V, VCC = 18 V
1
µA
SHUTDOWN, VI = 0 V, VCC = 18 V
1
µA
GAIN0, GAIN1, VI = 5.5 V, VCC = 18 V
1
µA
High-level input current, IIH
Low-level input current, IIL
Oscillator frequency, fOSC
Frequency is set by selection of ROSC and COSC (see the
Application Information Section).
Operating free–air temperature, TA
2
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2
V
V
200
300
-40
85
kHz
°C
Copyright © 2004–2010, Texas Instruments Incorporated
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SLOS427A – MAY 2004 – REVISED AUGUST 2010
DC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOO|
Class-D output offset voltage
(measured differentially)
INN and INP connected together,
Gain = 36 dB
V2P5
2.5-V Bias voltage
No load
AVDD
+5-V internal supply voltage
IL = 10 mA, SHUTDOWN = 2 V,
VCC = 8.5 V to 18 V
PSRR
Power supply rejection ratio
VCC = 11.5 V to 12.5 V
ICC
Quiescent supply current
SHUTDOWN = 2 V, no load
ICC(SD)
Quiescent supply current in
shutdown mode
SHUTDOWN = 0 V
rDS(on)
Drain-source on-state resistance
VCC = 12 V,
IO = 1 A,
TJ = 25°C
MIN
TYP
MAX
5
55
2.5
GAIN1 = 0.8 V
4.5
5
mV
V
5.5
V
11
22
mA
1.6
25
µA
-80
High side
UNIT
dB
600
Low side
500
Total
mΩ
1100
1300
GAIN0 = 0.8 V
14.6
15.3
16.2
GAIN0 = 2 V
20.5
21.2
21.8
GAIN0 = 0.8 V
26.4
27.2
27.8
GAIN0 = 2 V
31.1
31.8
32.5
G
Gain
ton
Turn-on time
C(V2P5) = 1 µF, SHUTDOWN = 2 V
16
ms
toff
Turn-off time
C(V2P5) = 1 µF, SHUTDOWN = 0.8 V
60
µs
GAIN1 = 2 V
dB
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω, (unless otherwise noted)
PARAMETER
kSVR
PO
TEST CONDITIONS
Supply voltage rejection ratio
Continuous output power
200 mVPP ripple from 20 Hz to 1 kHz,
Gain = 15.6 dB, Inputs ac-coupled to GND
TYP
3
THD+N = 0.23%, f = 1 kHz, RL = 8 Ω
6
Total harmonic distortion plus
noise
PO = 1 W, f = 1 kHz, RL = 8 Ω
Vn
Output integrated noise floor
20 Hz to 22 kHz, A-weighted filter,
Gain = 15.6 dB
MAX
-70
THD+N = 0.13%, f = 1 kHz, RL = 8 Ω
THD+N
UNIT
dB
W
0.1%
-80
dB
-93
dB
97
dB
Thermal trip point
150
°C
Thermal hystersis
20
°C
Crosstalk
SNR
MIN
Signal-to-noise ratio
PO = 1 W, RL = 8 Ω, Gain = 15.6 dB,
f = 1 kHz
Maximum output at THD+N < 0.5%,
f = 1 kHz, Gain = 15.6 dB
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SLOS427A – MAY 2004 – REVISED AUGUST 2010
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FUNCTIONAL BLOCK DIAGRAM
V2P5
PVCC
V2P5
VClamp
Gen
VCLAMPR
BSRN
PVCCR(2)
Gate
Drive
RINN
RINP
ROUTN(2)
Deglitch
and
PWM
Mode
Logic
Gain
Adj.
V2P5
PGNDR
BSRP
PVCCR(2)
Gate
Drive
GAIN0
GAIN1
Gain
Control
To Gain Adj.
Blocks &
Startup Logic
4
PGNDR
V2P5
ROSC
Ramp
Generator
COSC
AVDDREF
ROUTP(2)
SC
Detect
Biases
and
References
Startup and
Protection
Logic
Thermal
VDDok
AVDD
VCCok
5V LDO
AVDD
PVCC
TTL Input
Buffer
(VCC Compl)
SHUTDOWN
VDD
AVCC
AVCC
AGND(2)
VClamp
Gen
VCLAMPL
BSLN
PVCCL(2)
Gate
Drive
V2P5
LINN
LINP
Gain
Adj.
Deglitch
and
PWM
Mode
Logic
LOUTN(2)
PGNDL
BSLP
PVCCL(2)
Gate
Drive
LOUTP(2)
PGNDL
4
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SLOS427A – MAY 2004 – REVISED AUGUST 2010
48 47
46 45 44
43 42
41 40 39 38
BSRP
PVCCR
PVCCR
ROUTP
ROUTP
PGNDR
PGNDR
ROUTN
ROUTN
PVCCR
PVCCR
BSRN
PHP PACKAGE
(TOP VIEW)
37
SHUTDOWN
1
36
VCLAMPR
RINN
2
35
NC
RINP
3
34
NC
V2P5
4
33
AVCC
LINP
5
32
NC
LINN
6
31
NC
AVDDREF
7
30
AGND
NC
8
29
AVDD
GAIN0
9
28
COSC
GAIN1
10
27
ROSC
NC
11
26
AGND
NC
12
25
VCLAMPL
LOUTP
BSLP
PVCCL
PGNDL
PVCCL
24
LOUTP
20 21 22 23
PGNDL
18 19
LOUTN
15 16 17
LOUTN
PVCCL
BSLN
13 14
PVCCL
TPA3005D2
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SLOS427A – MAY 2004 – REVISED AUGUST 2010
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TERMINAL FUNCTIONS
PIN NAME
PIN NUMBER
I/O
AGND
26, 30
-
Analog ground for digital/analog cells in core
AVCC
33
-
High-voltage analog power supply, not connected internally to PVCCR or PVCCL
AVDD
29
O
5-V Regulated output for use by internal cells and GAIN0, GAIN1 pins only. Not
specified for driving other external circuitry.
AVDDREF
7
O
5-V Reference output—connect to gain setting resistor or directly to GAIN0, GAIN1.
BSLN
13
-
Bootstrap I/O for left channel, negative high-side FET
BSLP
24
-
Bootstrap I/O for left channel, positive high-side FET
BSRN
48
-
Bootstrap I/O for right channel, negative high-side FET
BSRP
37
-
Bootstrap I/O for right channel, positive high-side FET
COSC
28
I/O
GAIN0
9
I
Gain select least significant bit. TTL logic levels with compliance to AVDD.
GAIN1
10
I
Gain select most significant bit. TTL logic levels with compliance to AVDD.
LINN
6
I
Negative audio input for left channel
LINP
5
I
Positive audio input for left channel
LOUTN
16, 17
O
Class-D 1/2-H-bridge negative output for left channel
LOUTP
20, 21
O
Class-D 1/2-H-bridge positive output for left channel
8, 11, 12, 31,
32, 34, 35
-
No internal connection
PGNDL
18, 19
-
Power ground for left channel H-bridge
PGNDR
42, 43
-
Power ground for right channel H-bridge
PVCCL
14, 15
-
Power supply for left channel H-bridge (internally connected to pins 22 and 23), not
connected to PVCCR or AVCC.
PVCCL
22, 23
-
Power supply for left channel H-bridge (internally connected to pins 14 and 15), not
connected to PVCCR or AVCC.
PVCCR
38, 39
-
Power supply for right channel H-bridge (internally connected to pins 46 and 47),
not connected to PVCCL or AVCC.
PVCCR
46, 47
-
Power supply for right channel H-bridge (internally connected to pins 38 and 39),
not connected to PVCCL or AVCC.
RINP
3
I
Positive audio input for right channel
RINN
2
I
Negative audio input for right channel
ROSC
27
I/O
I/O current setting resistor for ramp generator.
ROUTN
44, 45
O
Class-D 1/2-H-bridge negative output for right channel
ROUTP
40, 41
O
Class-D 1/2-H-bridge positive output for right channel
SHUTDOWN
1
I
Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with
compliance to VCC.
VCLAMPL
25
-
Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR
36
-
Internally generated voltage supply for right channel bootstrap capacitors.
V2P5
4
O
2.5-V Reference for analog cells.
Thermal Pad
-
-
Connect to AGND and PGND—should be the center point for both grounds. Internal
resistive connection to AGND.
NC
DESCRIPTION
I/O for charge/discharging currents onto capacitor for ramp generator.
TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS
FIGURE
THD+N
Total harmonic distortion + noise
vs Output power
vs Frequency
Closed loop response
ICC
6
1, 2
3, 4, 5, 6
7
Supply current
vs Output power
8
Efficiency
vs Output power
9
Output power
vs Supply voltage
10, 11
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TYPICAL CHARACTERISTICS (continued)
Table 1. TABLE OF GRAPHS (continued)
Crosstalk
vs Frequency
12
kSVR
Supply ripple rejection ratio
vs Frequency
13
CMRR
Commom-mode rejection ratio
vs Frequency
14
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 12 V,
RL = 8 W,
Gain = 21.6 dB
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
1
1 kHz
0.1
20 Hz
0.01
20 m
20 kHz
100 m
1
VCC = 12 V,
RL = 16 W,
Gain = 21.6 dB
1
1 kHz
0.1
20 Hz
0.02
0.01
20 kHz
0.005
20 m
7
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 12 V,
RL = 16 W,
Gain = 21.6 dB
1
0.1
PO = 2.5 W
PO = 1 W
PO = 0.5 W
0.005
20
10
Figure 2.
10
0.01
100 m
1
PO − Output Power − W
Figure 1.
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
PO − Output Power − W
100
1k
f − Frequency − Hz
10
VCC = 18 V,
RL = 16 W,
Gain = 21.6 dB
1
PO = 0.5 W
0.1
PO = 1 W
PO = 2.5 W
0.01
10 k 20 k
20
Figure 3.
100
1k
f − Frequency − Hz
10 k 20 k
Figure 4.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
VCC = 12 V,
RL = 8 W
Gain = 21.6 dB
1
PO = 0.5 W
PO = 1 W
0.1
PO = 2.5 W
VCC = 18 V,
RL = 8 W,
Gain = 21.6 dB
1
PO = 2.5 W
0.1
PO = 1 W
0.01
PO = 5 W
0.005
0.01
20
100
1k
f − Frequency − Hz
20
10 k 20 k
100
Figure 6.
CLOSED LOOP RESPONSE
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
10 k 20 k
1.4
150
32
100
Gain
50
24
Phase
20
0
16
Phase − 5
28
−50
12
VCC = 12 V,
RL = 8 Ω,
Gain = 32 dB
33 kHz, RC LPF
8
4
1
0.8
8W
0.6
16 W
0.4
−100
0.2
−150
0
0
10
100
VCC = 12 V,
LC Filter,
Resistive Load,
Stereo Operation
1.2
ICC − Supply Current − A
36
1k
10k
80k
0
f − Frequency − Hz
Figure 7.
8
1k
f − Frequency − Hz
Figure 5.
40
Gain − dB
10
2
4
6
8
PO − Total Output Power − W
10
12
Figure 8.
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EFFICIENCY
vs
TOTAL OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
100
12
16 W
11
90
10
80
PO − Output Power − W
8W
Efficiency − %
70
60
50
40
30
10
0
1
2
3
4
5
6
7
8
9
10 11
9
THD+N = 10%
8
7
6
5
THD+N = 1%
4
3
VCC = 12 V,
LC Filter,
Resistive Load,
Stereo Operation
20
0
RL = 16 W
2
1
0
12
8
9
PO − Total Output Power − W
11 12 13 14 15 16
VCC − Supply Voltage − V
Figure 9.
Figure 10.
OUTPUT POWER
vs
SUPPLY VOLTAGE
CROSSTALK
vs
FREQUENCY
7
0
RL = 8 W
−10
THD+N = 10%
6
−20
17
18
VCC = 12 V,
PO = 2.5 W,
Gain = 21.6 dB
RL = 8 W
−30
Crosstalk − dB
PO − Output Power − W
10
5
4
THD+N = 1%
−40
−50
−60
−70
3
−80
−90
−100
2
8
9
10
11
12
VCC − Supply Voltage − V
13
14
20
100
1k
10 k 20 k
f − Frequency − Hz
Figure 11.
Figure 12.
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SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
0
−10
−20
CMRR − Common-Mode Rejection Ratio − dB
k SVR − Supply Ripple Rejection Ratio − dB
0
VCC = 12 V,
V(RIPPLE) = 200 mVPP,
RL = 8 W,
Gain = 15.6 dB
−30
−40
−50
−60
−70
−80
−90
−100
20
VCC = 12 V,
Gain = 15.6 dB,
RL = 8 W,
Output Referred
−10
−20
−30
−40
−50
−60
−70
100
1k
10 k 20 k
20
f − Frequency − Hz
Figure 13.
10
100
1k
f − Frequency − Hz
10 k 20 k
Figure 14.
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APPLICATION INFORMATION
*
*
PVCC 1 nF
1 nF
PVCC
220 nF
220 nF
10 mF
10 mF
0.47 mF
0.47 mF
0.47 mF
0.47 mF
BSRP
PVCCR
PVCCR
ROUTP
PGNDR
PGNDR
ROUTN
ROUTN
RINN
NC
RINP
NC
V2P5
AVCC
LINP
NC
LINN
10 mF
10 mF
1 mF
220 pF
120 kW
1 mF
0.1 mF
10 mF
220 nF
220 nF
PVCC 1 nF
Chip ferrite bead (example: Fair-Rite 251206700743)
BSLP
VCLAMPL
PVCCL
NC
PVCCL
AGND
LOUTP
NC
LOUTP
ROSC
PGNDL
GAIN1
PGNDL
COSC
LOUTN
AVDD
GAIN0
0.1 mF
0.1 mF
AGND
NC
BSLN
Gain
Control
AVCC
NC
TPA3005D2
AVDDREF
LOUTN
0.47 mF
*
1 mF
VCLAMPR
PVCCL
Left Differential
Inputs
PVCCR
BSRN
SHUTDOWN
PVCCL
Right Differential
Inputs
PVCCR
Shutdown/Mute
Control
ROUTP
0.1 mF
0.1 mF
1 nF
*
PVCC
*
Figure 15. Stereo Class-D With Differential Inputs
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CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3005D2.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 16. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
−12 V
Current
Figure 16. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3005D2 Modulation Scheme
The TPA3005D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
12
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
−12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
−12 V
Current
Figure 17. The TPA3005D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3005D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.
Effects of Applying a Square Wave Into a Speaker
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for
frequencies beyond the audio band.
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Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency
switching current. The amount of power dissipated in the speaker may be estimated by first considering the
overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the
dominant loss in the system, then the maximum theoretical efficiency for the TPA3005D2 with an 8-Ω load is as
follows:
R
8
L
Efficiency (theoretical, %) +
100% +
100% + 86%
(8 ) 1.3)
R )r
L
ds(on)
(1)
ǒ
Ǔ
The maximum measured output power is approximately 6 W with an 12-V power supply. The total theoretical
power supplied (P(total)) for this worst-case condition would therefore be as follows:
P
O
P
+
+ 6 W + 6.98 W
(total)
0.86
Efficiency
(2)
The efficiency measured in the lab using an 8-W speaker was 81%. The power not accounted for as dissipated
across the rDS(on) may be calculated by simply subtracting the theoretical power from the measured power:
Other losses + P
(total)
(measured) * P
(total)
(theoretical) + 7.41 * 6.98 + 0.43 W
(3)
The quiescent supply current at 12 V is measured to be 22 mA. It can be assumed that the quiescent current
encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any
remaining power is dissipated in the speaker and is calculated as follows:
P
(dis)
+ 0.43 W * (12 V
22 mA) + 0.17 W
(4)
Note that these calculations are for the worst-case condition of 6 W delivered to the speaker. Because the 0.17
W is only 3% of the power delivered to the speaker, it may be concluded that the amount of power actually
dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the
specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the
power generated from a clipping waveform.
When to use an Output Filter
Design the TPA3005D2 without the filter if the traces from amplifier to speaker are short (< 50 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use a LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from
the amplifier to the speaker.
When both a LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the
IC followed by the ferrite bead filter.
33 µH
OUTP
L1
33 µH
OUTN
L2
C1
C2
0.1 µF
0.47 µF
C3
0.1 µF
Figure 18. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
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Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 19. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
Gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3005D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance may shift by
20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 26 kΩ, which is the absolute minimum input impedance of the TPA3005D2. At the lower gain
settings, the input impedance could increase as high as 165 kΩ
Table 2. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE
(kΩ)
TYP
TYP
15.3
137
1
21.2
88
1
0
27.2
52
1
1
31.8
33
GAIN1
GAIN0
0
0
0
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier that can range from its smallest
value, 33 kΩ, to the largest value, 137 kΩ. As a result, if a single capacitor is used in the input high-pass filter,
the -3 dB or cutoff frequency changes when changing gain steps.
Zf
Ci
Input
Signal
IN
Zi
The -3-dB frequency can be calculated using Equation 5. Use Table 2 for Zi values.
1
f+
2p Z iCi
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INPUT CAPACITOR, CI
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined in Equation 6.
−3 dB
fc +
1
2 p Zi C i
fc
(6)
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where Zi is 137 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6 is
reconfigured as Equation 7.
1
Ci +
2p Z i f c
(7)
In this example, Ci is 58 nF, so one would likely choose a value of 0.1 µF as this value is commonly used. If the
gain is known and is constant, use Zi from Table 2 to calculate Ci. A further consideration for this capacitor is the
leakage path from the input source through the input network (Ci) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application.
For the best pop performance, CI should be less than or equal to 1µF.
Power Supply Decoupling,CS
The TPA3005D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF placed as close as possible to the device VCC lead works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended. The 10-µF capacitor also serves as local storage capacitor for supplying
current during large signal transients on the amplifier outputs.
BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from xOUTP to xBSP, and one 220-nF capacitor must be connected from xOUTN to xBSN. (See the
application circuit diagram in Figure 15).
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
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VCLAMP Capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two
internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25) and
VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals vary
with VCC and may not be used for powering any other circuitry.
Internal Regulated 5-V Supply (AVDD)
The AVDD terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator,
preamplifier, and volume control circuitry. It requires a 1-µF capacitor, placed close to the pin, to keep the
regulator stable.
This regulated voltage can be used to control GAIN0 and GAIN1 terminals, but should not be used to drive
external circuitry.
Differential Input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3005D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3005D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac-grounded at
the audio source instead of at the device input for best noise performance.
SHUTDOWN OPERATION
The TPA3005D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
SHORT-CIRCUIT PROTECTION
The TPA3005D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the
outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the
voltage on the SHUTDOWN pin to a logic low and back to the logic high state for normal operation. This clears
the short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the
protection circuitry again activates.
THERMAL PROTECTION
Thermal protection on the TPA3005D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are
disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by
20°C. The device begins normal operation at this point with no external system interaction.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3005D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
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Decoupling capacitors—The high-frequency 0.1-µF decoupling capacitors should be placed as close to the
PVCC (pins 14, 15, 22, 23, 38, 39, 46, and 47) and AVCC (pin 33) terminals as possible. The V2P5 (pin 4)
capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should also be placed as close to the
device as possible. Large (10 µF or greater) bulk power supply decoupling capacitors should be placed near
the TPA3005D2 on the PVCCL, PVCCR, and AVCC terminals.
Grounding—The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor, COSC
(pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pin 26 and
pin 30). The PVCC decoupling capacitors should each be grounded to power ground (PGND, pins 18, 19, 42,
and 43). Analog ground and power ground may be connected at the PowerPAD, which should be used as a
central ground connection or star ground for the TPA3005D2. Basically, an island should be created with a
single connection to PGND at the PowerPAD.
Output filter—The ferrite EMI filter (Figure 19) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 18) should be placed close to the outputs. The capacitors
used in both the ferrite and LC filters should be grounded to power ground. If both filters are used, the LC
filter should be placed first, following the outputs.
PowerPAD—The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils).
The PowerPAD size measures 4,55 x 4,55 mm. Four rows of solid vias (four vias per row, 0,3302 mm or 13
mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid
copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not
thermal relief or webbed vias. For additional information, see the PowerPAD Thermally Enhanced Package
application note, (SLMA002).
For an example layout, see the TPA3005D2 Evaluation Module (TPA3005D2EVM) User Manual, (SLOU165).
Both the EVM user manual and the PowerPAD application note are available on the TI Web site at
http://www.ti.com.
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BASIC MEASUREMENT SYSTEM
This application note focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted-pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 20 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The
analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to
reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement
system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer-input impedance should be high. The output impedance, ROUT, of the APA is normally in the hundreds
of milliohms and can be ignored for all but the power-related calculations.
Figure 20(a) shows a class-AB amplifier system. They take an analog signal input and produce an analog signal
output. These amplifier circuits can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 20(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
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Power Supply
Signal
Generator
APA
RL
Analyzer
20 Hz − 20 kHz
(a) Basic Class−AB
Power Supply
Low-Pass RC
Filter
Signal
Generator
Class-D APA
(A)
RL
Low-Pass RC
Filter
Analyzer
20 Hz − 20 kHz
(b) Filter-Free and Traditional Class-D
(A)
For efficiency measurements with filter-free class-D, RL should be an inductive load like a speaker.
Figure 20. Audio Measurement Systems
The TPA3005D2 uses a modulation scheme that does not require an output filter for operation, but they do
sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs
cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level
of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer
can measure the output sine wave.
DIFFERENTIAL INPUT AND BTL OUTPUT
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the
output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 21. The differential input is a balanced input,
meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output
equates to a balanced output.
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Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
Low−Pass
RC Filter
CIN
RGEN
VGEN
RIN
ROUT
RIN
ROUT
CIN
RGEN
Twisted-Pair Wire
RL
Low−Pass
RC Filter
RANA
CANA
RANA
CANA
Twisted-Pair Wire
Figure 21. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 3).
Table 3 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
Table 3. Recommended Minimum Wire Size for Power Cables
DC POWER LOSS
(MW)
AWG Size
AC POWER LOSS
(MW)
POUT (W)
RL(Ω)
10
4
18
22
16
40
18
42
2
4
18
22
3.2
8
3.7
8.5
1
8
22
28
2
8
2.1
8.1
< 0.75
8
22
28
1.5
6.1
1.6
6.2
CLASS-D RC LOW-PASS FILTER
An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width
modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff
frequency is set above the audio band. The high frequency of the square wave has negligible impact on
measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot
respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the
class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).
The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 22. RL
is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be
available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the
system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin
to minimize ground loops.
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RC Low-Pass Filters
RFILT
CFILT
VL= VIN
RL
AP Analyzer Input
CANA
RANA
CANA
RANA
VOUT
RFILT
CFILT
To APA
GND
Figure 22. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs
The transfer function for this circuit is shown in Equation 8 where wO = REQCEQ, REQ = RFILT || RANA and
CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement
bandwidth, to avoid attenuating the audio signal. Equation 9 provides this cutoff frequency, fC. The value of RFILT
must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the
attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A rule of thumb is
that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement error to less than
1% for RANA ≥ 10 kΩ.
ǒ Ǔ
R
V
OUT
V
IN
f
C
+ Ǹ2
ǒ
+
R
ANA
)R
ANA
FILT
Ǔ
ǒ Ǔ
1 ) j ww
O
f
(8)
MAX
(9)
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to
reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same
cutoff frequency. See Table 4 for the recommended filter component values.
Once fC is determined and RFILT is selected, the filter capacitance is calculated using Equation 9. When the
calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum
desired value calculated in Equation 10.
1
C
+
FILT
2p
f
R
C
FILT
(10)
Table 4 shows recommended values of RFILT and CFILT based on common component values. The value of fC
was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57,000 pF, but
the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and
fC is 34 kHz, which is above the desired value of 28 kHz.
Table 4. Typical RC Measurement Filter Values
22
MEASUREMENT
RFILT
CFILT
Efficiency
1000 Ω
5,600 pF
All other measurements
100 Ω
56,000 pF
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REVISION HISTORY
Changes from Original (May 2004) to Revision A
•
Page
Replaced the DISSIPATION RATING TABLE with the Thermal Inforamtion Table ............................................................. 2
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA3005D2PHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3005D2
TPA3005D2PHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3005D2
TPA3005D2PHPRG4
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3005D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA3005D2PHPR
Package Package Pins
Type Drawing
HTQFP
PHP
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA3005D2PHPR
HTQFP
PHP
48
1000
350.0
350.0
43.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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