Texas Instruments | 20-W Stereo Digital Audio Power Amplifier with Feedback (Rev. A) | Datasheet | Texas Instruments 20-W Stereo Digital Audio Power Amplifier with Feedback (Rev. A) Datasheet

Texas Instruments 20-W Stereo Digital Audio Power Amplifier with Feedback (Rev. A) Datasheet
TAS5704
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SLOS563A – MARCH 2008 – REVISED AUGUST 2010
20-W Stereo Digital Audio Power Amplifier With Feedback
Check for Samples: TAS5704
FEATURES
1
•
2
•
•
•
•
•
•
Audio Input/Output
– 20-W into an 8-Ω Load From an 18-V Supply
– Two Serial Audio Inputs (Four Audio
Channels)
– Supports Multiple Output Configurations:
– 2-Ch Bridged Outputs (20 W × 2)
– 4-Ch Single-Ended Outputs (10 W × 4)
– 2-Ch Single-Ended + 1-Ch Bridged (2.1)
(10 W × 2 + 20 W)
Closed Loop Power Stage Architecture
– Improved PSRR Reduces Power Supply
Performance Requirements
– Higher Damping Factor Provides for
Tighter, More Accurate Sound With
Improved Bass Response
– Lower EMC Emissions
– Output Power is Independent of Supply
Voltage Variation
Wide PVCC Range From (10 V to 26 V)
Supports 32-kHz–192-kHz (DVD-Audio) Sample
Rates (LJ/RJ/I2S)
Line-Level Subwoofer PWM Outputs
Audio/PWM Processing (Hardware Controlled)
– 4-Step Gain Control (-3dB, 3dB, 9dB, 12dB)
– Soft Mute Control (50% Output Duty Cycle)
Factory-Trimmed Internal Oscillator Enables
Automatic Detection of Incoming Sample
Rates
•
Thermal and Short-Circuit Protection
spacer
DESCRIPTION
The TAS5704 is a 20-W, efficient, digital audio power
amplifier for driving stereo bridge-tied speakers. Two
serial data inputs allow processing of up to four
discrete audio channels and seamless integration to
most digital audio processors accepting a wide range
of input data and clock rates. A hardware
configurable data path allows these channels to be
routed to the internal speaker drivers or output via the
subwoofer PWM outputs.
The TAS5704 is a slave-only device receiving all
clocks from external sources. The TAS5704 operates
at a 384-kHz switching rate for 32-, 48-, 96-, and
192-kHz data, and at a 352.8 kHz switching rate for
44.1-, 88.2-, and 176.4-kHz data. The 8×
oversampling combined with the fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
The closed-loop architecture of the TAS5704
provides several benefits. The high power supply
rejection enables superior audio performance from a
noisy, low cost supply. The high damping factor
allows tighter control over speaker movement
resulting in an improved bass response. Finally,
switching edge rate control lowers EMC emissions
without sacrificing audio performance.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
TAS5704
SLOS563A – MARCH 2008 – REVISED AUGUST 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAMS
Bridge-Tied Load (BTL) Mode
3.3 V
10 V–26 V
DVDD/AVDD
AVCC/PVCC
OUT_A
LRCLK
SCLK
Digital
Audio
Source
(TAS3x08)
BST_A
MCLK
SDIN1
LCBTL*
Left
LCBTL*
Right
BST_B
SDIN2
OUT_B
OUT_C
BST_C
GAIN_x (2 pins)
BST_D
MUTE
FORMATx (3 pins)
Control
Inputs
OUT_D
RESET
10 V–26 V
TAS5601
PDN
CONFIG_x (2 pins)
SUB_PWM+
PWM_AP
OUT_A
PWM_AN
PLL_FLTP
SUB_PWM–
PWM_BP
BST_A
LCBTL*
Subwoofer
BST_B
Loop
Filter
PWM_BN
PLL_FLTM
BKND_ERR
FAULT
VALID
RESET
OUT_B
* Refer to TI Application Note (SLOA119) on LC filter design for BTL (AD/BD mode) configuration.
B0264-02
2
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Single-Ended (SE) 2.1 Mode
3.3 V
10 V–26 V
DVDD/AVDD
AVCC/PVCC
OUT_A
LCSE*
LRCLK
SCLK
Digital
Audio
Source
(TAS3x08)
BST_A
MCLK
SDIN1
SDIN2
BST_B
OUT_B
LCSE*
GAIN_x (2 pins)
MUTE
OUT_C
FORMATx (3 pins)
Control
Inputs
RESET
PDN
BST_C
LCBTL*
BST_D
CONFIG_x (2 pins)
OUT_D
PLL_FLTP
Loop
Filter
SUB_PWM+
PLL_FLTM
SUB_PWM–
BKND_ERR
VALID
* Refer to TI Application Note (SLOA119) on LC filter design for SE or BTL configuration.
B0264-05
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Single-Ended (SE) 4.0 Mode
3.3 V
10 V–26 V
DVDD/AVDD
AVCC/PVCC
OUT_A
LCSE*
LRCLK
SCLK
Digital
Audio
Source
(TAS3x08)
BST_A
MCLK
SDIN1
SDIN2
BST_B
OUT_B
LCSE*
OUT_C
LCSE*
GAIN_x (2 pins)
MUTE
FORMATx (3 pins)
Control
Inputs
RESET
BST_C
PDN
CONFIG_x (2 pins)
BST_D
OUT_D
LCSE*
PLL_FLTP
Loop
Filter
SUB_PWM+
PLL_FLTM
SUB_PWM–
BKND_ERR
VALID
* Refer to TI Application Note (SLOA119) on LC filter design for SE configuration.
B0264-04
4
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SLOS563A – MARCH 2008 – REVISED AUGUST 2010
64-PIN, HTQFP PACKAGE
PVCC_B
PVCC_B
BST_B
VCLAMP_AB
BST_A
AVCC
AGND
BYPASS
BST_D
VCLAMP_CD
BST_C
PVCC_C
PVCC_C
OUT_C
OUT_C
OUT_B
PAP Package
(Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
OUT_B
PGND_B
PGND_B
OUT_A
OUT_A
PGND_A
PGND_A
PVCC_A
PVCC_A
AVDD
AVSS
PLL_FLTM
PLL_FLTP
VR_ANA
DVDD
RESET
1
2
3
4
5
6
48
47
46
45
44
43
PGND_C
PGND_C
OUT_D
OUT_D
PGND_D
7
8
9
10
11
12
13
14
15
16
42
41
40
39
38
37
36
35
34
33
PVCC_D
PVCC_D
SUB_PWM+
SUB_PWM–
PGND_D
VALID
BKND_ERR
MCLK
DVDD
CONFIG_1
CONFIG_2
GAIN_1
GAIN_0
FORMAT2
FORMAT1
FORMAT0
MUTE
LRCLK
SCLK
SDIN2
SDIN1
DVSS
VR_DIG
DVSSO
PDN
VREG_EN
OSC_RES
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0071-02
PIN FUNCTIONS
PIN
TYPE
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
NO.
(1)
AGND
57
P
Analog ground for power stage
AVCC
58
P
Analog power supply for power stage. Connect externally to same
potential as PVCC.
AVDD
10
P
3.3-V analog power supply
AVSS
11
P
BKND_ERR
37
DI
BST_A
59
P
NAME
(1)
(2)
3.3-V analog supply ground
Pullup
Active low. A back-end error sequence is initiated by applying a logic
low to this pin. Connect to an external power stage. If no external
power stage is used, connect directly to DVDD.
High-side bootstrap supply for half-bridge A
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are 20-mA weak pullups and all pulldowns are 20-mA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 50 mA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 50 mA while maintaining a logic-1 drive level.
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PIN FUNCTIONS (continued)
PIN
TYPE
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
NO.
(1)
BST_B
61
P
High-side bootstrap supply for half-bridge B
BST_C
53
P
High-side bootstrap supply for half-bridge C
BST_D
55
P
High-side bootstrap supply for half-bridge D
BYPASS
56
O
CONFIG_1
34
P
Pulldown
Input/output configuration.
CONFIG_2
33
P
Pulldown
Input/output configuration.
DVDD
15,
35
P
3.3-V digital power supply
DVSS
26
P
Digital ground
DVSSO
20
P
Oscillator ground
FORMAT0
32
DI
Pulldown
Digital data format select.
FORMAT1
31
DI
Pulldown
Digital data format select.
FORMAT2
30
DI
Digital data format select.
GAIN_0
29
DI
LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
GAIN_1
28
DI
MSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
LRCLK
22
DI
5-V
Input serial audio data left/right clock (sampling rate clock)
MCLK
36
DI
5-V
Master clock input. The input frequency of this clock can range from
4.9 MHz to 49.2 MHz.
MUTE
21
DI
5-V
OSC_RES
19
AO
OUT_A
4, 5
O
Output, half-bridge A
OUT_B
1, 64
O
Output, half-bridge B
OUT_C
49,
50
O
Output, half-bridge C
OUT_D
45,
46
O
Output, half-bridge D
PDN
17
DI
PGND_A
6, 7
P
Power ground for half-bridge A
PGND_B
2, 3
P
Power ground for half-bridge B
PGND_C
47,
48
P
Power ground for half-bridge C
PGND_D
43,
44
P
Power ground for half-bridge D
PLL_FLTM
12
AO
PLL negative loop filter terminal
PLL_FLTP
13
AO
PLL positive loop filter terminal
PVCC_A
8, 9
P
Power supply input for half-bridge output A
PVCC_B
62,
63
P
Power supply input for half-bridge output B
PVCC_C
51,
52
P
Power supply input for half-bridge output C
PVCC_D
41,
42
P
Power supply input for half-bridge output D
NAME
6
Nominally equal to VCC/8. Internal reference voltage for analog cells
Pullup
Performs a soft mute of outputs, active-low. A logic low on this
terminal sets the outputs equal to 50% duty cycle. A logic high on this
terminal allows normal operation. The mute control provides a
noiseless volume ramp to silence. Releasing mute provides a
noiseless ramp to previous volume.
Oscillator trim resistor. Connect an 18.2-kΩ resistor to DVSSO.
5-V
Pullup
Power down, active-low. PDN stops all clocks and outputs stop
switching. When PDN is released, the device powers up all logic,
starts all clocks, and performs a soft start that returns to the previous
configuration. Changes to CONFIG_x, FORMATx, and GAIN_x pins
are ignored on PDN cycling.
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PIN FUNCTIONS (continued)
PIN
TYPE
(1)
5-V
TOLERANT
TERMINATION
NO.
(2)
DESCRIPTION
RESET
16
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that sets
the VALID outputs low, and places the PWM in the hard-mute state
(stops switching). Gain is immediately set to full attenuation. Upon the
release of RESET, if PDN is high, the system performs a 4- to 5-ms
device initialization and sets the gain, output configuration, and format
to the settings determined by the hardware pins.
SCLK
23
DI
5-V
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDIN1
25
DI
5-V
Serial audio data-1 input is one of the serial data input ports. SDIN1
supports three discrete (stereo) data formats.
SDIN2
24
DI
5-V
Serial audio data-2 input is one of the serial data input ports. SDIN2
supports three discrete (stereo) data formats.
SUB_PWM–
39
DO
Subwoofer negative PWM output
SUB_PWM+
40
DO
Subwoofer positive PWM output
VALID
38
DO
Output indicating validity of all PWM channels, active high. Connect
this pin to an external power stage or leave floating.
VCLAMP_AB
60
P
Internally generated voltage supply for channels A and B gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VCLAMP_CD
54
P
Internally generated voltage supply for channels C and D gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VR_ANA
14
P
Internally regulated 1.8-V analog supply voltage. This terminal must
not be used to power external devices.
VR_DIG
27
P
Internally regulated 1.8-V digital supply voltage. This terminal must not
be used to power external devices.
VREG_EN
18
DI
NAME
Pulldown
Voltage regulator enable. Connect directly to GND.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage
(1)
VALUE
UNIT
DVDD, AVDD
–0.3 to 3.6
V
PVCC_X
-0.3 to 30
V
–0.5 to DVDD + 0.5
V
3.3-V digital input
5-V tolerant
(2)
digital input
Input clamp current, IIK (VI < 0 or VI > 1.8 V
Output clamp current, IOK (VO < 0 or VO > 1.8 V
Operating free-air temperature
Operating junction temperature range
Storage temperature range, Tstg
(1)
(2)
–0.5 to 6
V
±20
mA
±20
mA
0 to 85
°C
0 to 150
°C
–40 to 125
°C
Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, and SDIN2.
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THERMAL INFORMATION
TAS5704
THERMAL METRIC (1) (2)
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
15.6
qJB
Junction-to-board thermal resistance
12.6
yJT
Junction-to-top characterization parameter
0.2
yJB
Junction-to-board characterization parameter
7.8
qJCbot
Junction-to-case (bottom) thermal resistance
0.8
(1)
(2)
UNITS
PAP (64 PINS)
27
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
26
V
Digital/analog supply voltage
DVDD
Half-bridge supply voltage
PVCC_xx
VIH
High-level input voltage
3.3-V TTL, 5-V tolerant
VIL
Low-level input voltage
3.3-V TTL, 5-V tolerant
0.8
V
TA
Operating ambient temperature range
0
85
°C
TJ
Operating junction temperature range
0
150
°C
10
2
RL (BTL)
RL (SE)
Load impedance
Output filter: L = 22 mH, C = 680 nF.
RL (PBTL)
V
6.0
8
3.2
4
3.2
4
LO (BTL)
Ω
10
LO (SE)
Minimum output inductance under
short-circuit condition
Output-filter inductance
10
LO (PBTL)
mH
10
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate 2×–1×
oversampled
TEST CONDITIONS
MODE
32–kHz data rate ±2%
12× sample rate
VALUE
UNITS
384
kHz
44.1-, 88.2-, 176.4-kHz data rate ±2%
48-, 96-, 192-kHz data rate ±2%
8×, 4×, and 2× sample rates
352.8
kHz
8×, 4×, and 2× sample rates
384
kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
fMCLKI
TEST CONDITIONS
MIN
Frequency, MCLK (1 / tcyc2)
TYP
4.9
MCLK duty cycle
40%
50%
UNIT
49.2
MHz
60%
MCLK minimum high time
≥2-V MCLK = 49.152 MHz, within the
min and max duty cycle constraints
8
ns
MCLK minimum low time
≤0.8-V MCLK = 49.152 MHz, within the
min and max duty cycle constraints
8
ns
LRCLK allowable drift before LRCLK reset
8
MAX
4
MCLKs
External PLL filter capacitor C1
SMD 0603 Y5V
47
nF
External PLL filter capacitor C2
SMD 0603 Y5V
4.7
nF
External PLL filter resistor R
SMD 0603, metal film
470
Ω
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ELECTRICAL CHARACTERISTICS
DC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, DVDD = AVDD = 3.3 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
3.3-V TTL and 5-V tolerant
(1)
IOH = –4 mA
3.3-V TTL and 5-V tolerant
(1)
IOL = 4 mA
VOL
Low-level output voltage
| VOS |
Class-D output offset voltage
VBYPASS
PVCC/8 reference for analog section
IIL
Low-level input current
IIH
High-level input current
MIN
TYP MAX
V
0.5
±26
No load
2.2
2.26
V
mV
2.3
LRCLK, SCLK, SDINx, MCLK,
GAIN_x
VREG_EN, FORMATx,
CONFIG_x
VI = 0 V, DVDD = 3.6 V
BKND_ERR, RESET, PDN,
MUTE
VI = 0 V, DVDD = 3.6 V
RESET, PDN, MUTE, GAIN_x,
BKND_ERR
VI = 3.6 V, DVDD = 3.6 V
±2
VREG_EN, FORMAT_x,
CONFIGx, LRCLK, SCLK,
SDINx, MCLK
VI = 3.6 V, DVDD = 3.6 V
±50
RESET, PDN, MUTE, LRCLK,
SCLK, SDINx, MCLK, GAIN_x
VI = 5.5 V, DVDD = 3.6 V
±50
V
±2
mA
±50
Normal mode
Supply voltage (DVDD, AVDD)
UNIT
2.4
Power down
(PDNZ = LOW)
mA
65
80
8
16
23
33
33
57
mA
IDD
Digital supply current
ICC
Quiescent supply current
No load
ICC( RESET )
Quiescent supply current in reset mode
No load
58
176
mA
ICC( PDNZ )
Quiescent supply current in power down mode
No load
58
176
mA
PSRR
DC power-supply rejection ratio
PVCC = 17.5 V to 18.5 V
60
Reset (RESET = LOW)
14
Drain-source on-state resistance, high-side
RDS(on)
Total
tON
tOFF
(1)
(2)
240
480
Turnon time (SE mode) (CONFIG_2 = 0)
Turnon time (BTL mode) (CONFIG_2 = 1)
Turnoff time (SE mode) (CONFIG_2 = 0) (2)
Turnoff time (BTL mode) (CONFIG_2 = 0) (2)
dB
240
VCC = 18 V , IO = 500 mA,
TJ = 25°C
Low-side
mA
C(BYPASS) = 1 mF,
Time required for the
BYPASS pin to reach its
final value
mΩ
850
500
30
500
30
ms
ms
5-V tolerant pins are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, and SDIN2.
For pop-free power-off (PVDD = 0 V), it is recommended that PDN be cycled low for at least this period of time before PVDD drops
below 10 V and DVDD drops below 3 V.
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AC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless
otherwise noted) (1)
PARAMETER
KSVR
Supply ripple rejection
Continuous output
power
PO
THD+N
Vn
TEST CONDITIONS
MIN
TYP
MAX
100-mVPP ripple at 20 Hz–20 kHz, BTL, 50%
duty cycle PWM
–60
dB
BTL (RL = 8 Ω, THD+N = 10%, f = 1 kHz,
PVCC = 18 V)
20.6
W
BTL (RL = 8 Ω, THD+N = 7%, f = 1 kHz,
PVCC = 18 V)
19.3
W
SE (RL = 4 Ω, THD+N = 10%, f = 1 kHz,
PVCC = 24 V)
18.1
W
SE (RL = 4 Ω, THD+N = 7%, f = 1 kHz, PVCC
= 24 V)
17.3
W
Total harmonic distortion VCC = 24 V, RL = 4 Ω, f = 1 kHz, PO = 10 W
+ noise (SE)
(half-power)
0.08%
Total harmonic distortion VCC = 18 V, RL = 8 Ω, f = 1 kHz, PO = 10 W
+ noise (BTL)
(half-power)
0.05%
Output integrated noise
UNIT
20 Hz to 22 kHz (BD mode)
89
mV
A-weighted filter; MUTE = LOW
–81
dBV
Crosstalk
PO = 1 W, f = 1 kHz
–69
dB
SNR
Maximum output at THD+N < 1%, f = 1 kHz,
A-weighted
100
dB
Thermal trip point
(output shutdown,
unlatched fault)
150
°C
Thermal hysteresis
15
°C
(1)
Signal-to-noise ratio
All measurement in AD mode (unless otherwise noted).
AC Characteristics, TA = 25°C, PVCC_X, AVCC = 12 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless
otherwise noted) (1)
PARAMETER
KSVR
Supply ripple rejection
PO
Continuous output power
THD+N
Total harmonic distortion
+ noise (BTL)
Vn
Output integrated noise
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100-mVpp ripple at 20 Hz–20 kHz, BTL,
50% duty cycle PWM
–60
dB
BTL (RL = 8 Ω, THD+N = 10%, f = 1 kHz)
9.2
W
BTL (RL = 8 Ω, THD+N = 7%, f = 1 kHz)
8.7
W
SE (RL = 4 Ω, THD+N = 10%, f = 1 kHz)
4.5
W
SE (RL = 4 Ω, THD+N = 7%, f = 1 kHz)
4.2
W
VCC = 12 V, RL = 8 Ω, f = 1 kHz,
PO = 5 W (half-power)
20 Hz to 22 kHz (BD mode)
0.07%
89
mV
A-weighted filter
–81
dBV
Crosstalk
PO = 1 W, f = 1 kHz
–75
dB
SNR
Maximum output at THD+N < 1%,
f = 1 kHz, A-weighted
96
dB
150
°C
15
°C
Signal-to-noise ratio
Thermal trip point (output
shutdown, unlatched fault)
Thermal hysteresis
(1)
10
All measurement in AD mode (unless otherwise noted).
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
CL = 30 pF
MIN
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
32
48
192
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
32
64
SCLK
edges
–1/4
1/4
SCLK
period
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
ns
kHz
Figure 1. Slave Mode Serial Data Interface Timing
HARDWARE SELECT PINS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tsu
MIN
Setup time, FORMATx, CONFIG_x, GAIN_x to RESET rising edge
TYP
MAX
100
UNIT
ms
tsu
FORMATx,
CONFIG_x,
GAIN_x,
RESET
Figure 2. Mode Pins Setup Time
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RESET TIMING (RESET) AND POWER-ON RESET
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
td(VALID_LOW)
Time to assert VALID (reset to power stage) low
tw(RESET)
Pulse duration, RESET active
td(START)
Time to start-up
RESET
TYP
MAX
UNIT
300
ns
1
ms
13.5
ms
Earliest time
that hard mute
could be exited
tw(RESET)
VALID
td(START)
Start system
td(VALID_LOW) £ 300 ns
T0029-05
Figure 3. Reset Timing
When power is applied to DVDD, must be held low for at least 100 ms after DVDD reaches 3.0 V.
3.6 V
3.0 V
DVDD
0V
RESET
100 ms
Figure 4. Power-On Reset Timing
POWER-DOWN (PDN) TIMING
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
td(VALID_LOW)
Time to assert VALID (reset to power stage) low
725
ms
td(STARTUP)
Device startup time
120
ms
tw
Minimum pulse duration required
800
ns
12
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PDN
tw
VALID
td(VALID_LOW)
td(STARTUP)
T0030-04
Figure 5. Power-Down Timing
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BACK-END ERROR (BKND_ERR)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
tw(ER)
Pulse duration, BKND_ERR active (active-low)
tp(valid_high)
Time to stay in the OUT_x low state. After tp(valid_high), the TAS5704 attempts to bring
the system out of the OUT_x low state if BKND_ERR is high.
300
tp(valid_low)
Time TAS5704 takes to bring OUT_x low after BKND_ERR assertion.
350
MAX
UNIT
350
ns
ms
ns
tw(ER)
BKND_ERR
VALID
Normal
Operation
Normal
Operation
tp(valid_high)
tp(valid_low)
T0031-04
Figure 6. Error Recovery Timing
MUTE TIMING (MUTE)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
td(VOL)
(1)
MIN
Volume ramp time. Ramp Time = Number of Steps × Stepsize
(1)
TYP
MAX
1024
UNIT
steps
Stepsize = 4 LRCLKs (for 32–48 kHz sample rate); 8 LRCLKs (for 88.2–96 kHz sample rate); 16 LRCLKs (for 176.4–192 kHz sample
rate)
MUTE
VOLUME
Normal
Operation
Normal
Operation
td(VOL)
td(VOL)
50-50
Duty Cycle
T0032-03
Figure 7. Mute Timing
14
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V
RL = 8 Ω
P=5W
1
P = 2.5 W
0.1
0.01
P = 0.5 W
0.001
20
100
1k
VCC = 18 V
RL = 8 Ω
P = 10 W
1
P=5W
0.1
0.01
P=1W
0.001
20
10k 20k
100
10k 20k
1k
f − Frequency − Hz
f − Frequency − Hz
G002
G001
Figure 8.
Figure 9.
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 24 V
RL = 8 Ω
P = 10 W
1
P=5W
0.1
0.01
P=1W
0.001
20
100
1k
10k 20k
VCC = 12 V
RL = 8 Ω
1
f = 10 kHz
f = 1 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
f − Frequency − Hz
G003
Figure 10.
0.1
1
10
PO − Output Power − W
40
G004
Figure 11.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 18 V
RL = 8 Ω
1
f = 10 kHz
f = 1 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
0.1
1
10
PO − Output Power − W
VCC = 24 V
RL = 8 Ω
1
f = 10 kHz
f = 1 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
40
0.1
1
G005
Figure 13.
EFFICIENCY
vs
OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
3.0
RL = 8 Ω
90
VCC = 18 V
2.5
70
VCC = 24 V
VCC = 18 V
60
ICC − Supply Current − A
80
Efficiency − %
40
G006
Figure 12.
100
VCC = 12 V
50
40
30
2.0
VCC = 12 V
1.5
1.0
VCC = 24 V
20
0.5
10
RL = 8 Ω
0.0
0
0
5
10
15
20
25
PO − Output Power (Per Channel) − W
30
0
5
10
15
20
25
30
PO − Total Output Power − W
G007
Figure 14.
16
10
PO − Output Power − W
35
40
G008
Figure 15.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
CROSSTALK
vs
FREQUENCY
40
−40
RL = 8 Ω
35
−50
−60
Right to Left
−70
THD+N = 10%
25
Crosstalk − dB
PO − Output Power − W
30
20
15
THD+N = 1%
−80
Left to Right
−90
−100
−110
10
−120
5
−130
0
10
12
14
16
18
20
22
VCC − Supply Voltage − V
24
−140
20
26
G009
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
−50
−60
Right to Left
Right to Left
−70
Crosstalk − dB
−70
Crosstalk − dB
10k 20k
G012
Figure 17.
−50
−80
Left to Right
−90
−100
−90
−100
−110
−120
−120
RL = 8 Ω
VCC = 18 V
100
−130
1k
10k 20k
Left to Right
−80
−110
−140
20
1k
Figure 16.
−40
−130
100
f − Frequency − Hz
−40
−60
RL = 8 Ω
VCC = 12 V
RL = 8 Ω
VCC = 24 V
−140
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
G013
Figure 18.
G014
Figure 19.
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TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
OUTPUT POWER
10
PO = 1 W
RL = 4 Ω
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
1
VCC = 12 V
0.1
VCC = 24 V
0.01
VCC = 18 V
0.001
20
100
1k
f = 1 kHz
RL = 4 Ω
1
VCC = 12 V
0.1
VCC = 24 V
0.01
VCC = 18 V
0.001
0.01
10k 20k
0.1
f − Frequency − Hz
1
10
40
PO − Output Power − W
G015
G016
Figure 20.
Figure 21.
EFFICIENCY
vs
OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
2.0
100
RL = 4 Ω
90
VCC = 18 V
80
1.5
VCC = 24 V
VCC = 18 V
ICC − Supply Current − A
Efficiency − %
70
60
VCC = 12 V
50
40
30
VCC = 12 V
1.0
VCC = 24 V
0.5
20
10
RL = 4 Ω
0.0
0
0
5
10
15
20
PO − Output Power (Per Channel) − W
25
0
10
15
20
25
30
PO − Total Output Power − W
G017
Figure 22.
18
5
35
40
G018
Figure 23.
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TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
20
0
RL = 4 Ω
18
−10
−20
16
VCC = 12 V
RL = 8 Ω
V(RIPPLE) = 200 mVpp
−40
12
THD+N = 10%
PSRR − dB
PO − Output Power − W
−30
14
10
8
THD+N = 1%
−50
−60
−70
−80
6
−90
4
−100
2
−110
0
10
12
14
16
18
20
22
VCC − Supply Voltage − V
24
26
−120
20
G019
Figure 24.
100
1k
10k 20k
f − Frequency − Hz
G020
Figure 25.
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DETAILED DESCRIPTION
POWER SUPPLY
The digital portion of the chip requires 3.3 V, and the power section operates from a variable range from 10 V to
26 V.
Clock, Auto Detection, and PLL
The TAS5704 DAP is a clock slave device. It accepts MCLK, SCLK, and LRCLK.
The TAS5704 checks to verify that SCLK is a specific value of 32-fs, 48- fs, or 64-fs. The DAP only supports a 1 ×
fs LRCLK. The timing relationship of these clocks to SDIN1 and SDIN2 is shown in subsequent sections. The
clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the
internal clock.
The DAP can auto-detect and set the internal clock control logic to the appropriate settings for the frequencies of
32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or 192
kHz).
PWM SECTION
The DAP (digital audio processor) has four channels of high-performance digital PWM modulators that are
designed to drive bridge-tied output H-bridge configurations with AD or BD modulation and single-ended output
configurations with AD modulation.
The DAP uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and
high-performance digital audio reproduction.
The PWM section accepts 24-bit PCM data from the DAP and outputs up to 4 PWM audio output channels.
The PWM section has individual channel dc blocking filters that are ALWAYS enabled. The filter cutoff frequency
is less than 1 Hz.
SERIAL DATA INTERFACE
Serial data is input on SDIN1 and SDIN2. The PWM outputs are derived from SDIN1 and SDIN2. The TAS5704
DAP accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in
left-justified, right-justified, and I2S serial data formats. See Table 1 for format control settings.
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A system clock (SCLK) running at
32, 48, or 64 × fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal
changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge
of the bit clock. The DAP masks unused trailing data bit positions.
1/fS
LRCK
L-Channel
R-Channel
SCLK
(= 32 fS, 48 fS or 64 fS)
DATA
N−1 N−2 N−3
MSB
2
1
LSB
0
N–1
N–2 N–3
MSB
2
1
0
N−1
N−2
LSB
Figure 26. I2S Format
20
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Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fs is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
1/fS
LRCK
L-Channel
R-Channel
SLCK
(= 32 fS, 48 fS, or 64 fS)
DATA
2
N−1 N−2 N−3
MSB
1
0
N−1 N−2
LSB
2
N−3
MSB
1
0
N–1
N–2
LSB
Figure 27. Left-Justified Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fs is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks
unused leading data bit positions.
1/fS
LRCK
L-Channel
R-Channel
SCLK
(= 32 fS, 48 fS, or 64 fS)
16-Bit Right-Justified, SCLK = 48 fS or 64 fS
DATA
2
1
0
15 14 13
2
MSB
1
0
15 14 13
2
MSB
LSB
1
0
LSB
16-Bit Right-Justified, SCLK = 32 fS
DATA
2
1
0
15 14 13
2
1
0
2
MSB
LSB
MSB
15 14 13
1
0
LSB
18-Bit Right-Justified, SCLK = 48 fS or 64 fS
DATA
2
1
0
17 16 15
2
MSB
1
0
17 16 15
LSB
2
MSB
1
0
LSB
20-Bit Right-Justified, SCLK = 48 fS or 64 fS
DATA
2
1
0
19 18 17
2
MSB
1
0
19 18 17
LSB
2
MSB
1
0
LSB
24-Bit Right-Justified, SCLK = 48 fS
DATA
2
1
0
23 22 21
2
1
0
LSB
MSB
23 22 21
2
MSB
1
0
LSB
24-Bit Right-Justified, SCLK = 64 fS
DATA
2
1
0
23 22 21
MSB
2
1
0
LSB
23 22 21
MSB
2
1
0
LSB
Figure 28. Right-Justified Format
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Format Control
The digital data input format is selected via three external terminals (FORMAT0, FORMAT1, and FORMAT2).
Table 1 lists the corresponding data format for SDIN1 and SDIN2. LRCLK and SCLK are shared clocks for
SDIN1 and SDIN2. Changes to the FORMATx terminals are latched in immediately on a rising edge of RESET.
Changes to the FORMATx terminals while RESET is high are not allowed.
Table 1. Format Control
SERIAL DIGITAL DATA
FORMAT
FORMAT2
FORMAT1
FORMAT0
0
0
0
16-Bit right-justifed
0
0
1
18-Bit right-justified
0
1
0
20-Bit right-justified
0
1
1
24-Bit right-justified
1
0
0
16-, 24-Bit I2S
1
0
1
16-, 24-Bit left-justified
1
1
0
Reserved. Setting is not allowed.
1
1
1
Reserved. Setting is not allowed.
Gain Control
The gain of the DAP is selected via two external gain pins (GAIN_0 and GAIN_1). Table 2 lists the corresponding
channel gain (for ALL channels) for GAIN_0 and GAIN_1 settings. Individual channel gain is not possible.
Changes to the GAIN_x terminals are latched in immediately on a rising edge of RESET. Changes to the
GAIN_x terminals while RESET is high are not allowed.
Table 2. Gain Control
(1)
OUTPUT VOLTAGE
WITH FULL SCALE
INPUT (Vrms) —
BTL
GAIN_1
GAIN_0
CHANNEL
GAIN (dB)
0
0
-3
17.56
0
1
3
35.04 (1)
1
0
9
70.08 (1)
1
1
12
99.00 (1)
Output clipped. See the calculation example in the Application
section.
Output Configuration Control
The PWM outputs can be remapped to allow 2-ch, 2.1-ch, and 4-ch operation. Two terminals are used for this
mapping, CONFIG_1 and CONFIG_2. Table 3 lists the output configurations that are supported. Changes to the
CONFIG_x terminals are latched in immediately on a rising edge of RESET. Changes to the CONFIG_x
terminals while RESET is high are not allowed.
Table 3. Output Configurations
CONFIG_2
22
CONFIG_1
OUTPUT CONFIGURATION
0
0
2-Ch Mode, BTL, AD modulation. SUB+/- is derived from the SDIN2
input (left channel). SUB+/- is AD modulation with SUB- equal to the
compliment of SUB+.
0
1
2-Ch Mode, BTL, BD modulation. SUB+/- is derived from the SDIN2
input (left channel), and SUB+/- is BD PWM.
1
0
2.1-Ch Mode (2xSE outputs, 1xBTL output). AD modulation. No SUB+/PWM output.
1
1
4-Ch Mode (4xSE outputs). AD modulation. No SUB+/- PWM output.
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APPLICATION INFORMATION
CLOSED-LOOP POWER STAGE CHARACTERISTICS
The TAS5704 is PWM input power stage with a closed loop architecture. A feedback loop varies the PWM output
duty cycle with changes in the supply voltage. This ensures that the output voltage (and output power) remain
the same over transitions in the power supply.
Open-loop power stages have an output duty cycle that is equal to the input duty cycle. Since the duty cycle
does NOT change to compensate for changes in the supply voltage, the output voltage (and power) change with
supply voltage changes. This is undesirable effect that closed-loop architecture of the TAS5704 solves.
The single-ended (SE) gain of the TAS5704 is fixed, and specified below:
TAS5704 Gain = 0.13 / Modulation Level (Vrms/%)
Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.
TAS5704 (SE) Voltage Level (in Vrms) = 0.13 x Modulation Level
The bridge-tied (BTL) gain of the TAS5704 is equal to 2x the SE gain:
TAS5704 (BTL) Voltage Level (in Vrms) = 0.26 x Modulation Level
For a digital modulator like the TAS5704, the default maximum modulation limit is 97.7%. For a full scale input,
the PWM output switches between 2.3% and 97.7%. This equates to a modulation level of 95.4% for a full scale
input (0 dBFS).
For example, calculate the output voltage in RMS volts given a –20 dBFS signal to a digital modulator with a
maximum modulation limit of 97.7% in a BTL output configuration:
TAS5704 Output Voltage = 0.1 (–20dB) x 0.26 (Gain) x 95.4 (Modulation Level)
= 2.48 Vrms
For shutdown and power-down, the PDN terminal should be cycled low for the “turn-off” time specified in the DC
Electrical Characteristics table before PVCC falls below 10 V and DVDD/AVDD falls below 3 V. For SE mode,
this is approximately 500ms. For BTL mode, the time is much faster, at 30ms. This ensures the best “pop”
performance in the system.
POWER SUPPLIES
To allow simplified system design, the TAS5704 requires only a single supply (PVCC) for the the power blocks
and a 3.3 V (DVDD/AVDD) supply for PWM input blocks. In addition, the high-side gate drive is provided by
built-in bootstrap circuits requiring only an external capacitor for each half-bridge.
DVDD/AVDD must be applied at the same time or before PVCC is applied on power-up. For power-down, PVCC
and DVDD/AVDD should remain active while the PDN terminal is cycled low and held low for at least the time
specified for tOFF in the Electrical Characteristics table.
In order for the bootstrap circuit to function properly, it is necessary to connect a small ceramic capacitor from
each bootstrap pin (BS_) to the corresponding output pin (OUT_). When the power-stage output is low, the
bootstrap capacitor is charged through an internal diode. When the power-stage output is high, the bootstrap
capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the
high-side gate drive.
DEVICE PROTECTION SYSTEM
The TAS5704 contains a complete set of protection circuits carefully designed to make system design efficient as
well as to protect the device against any kind of permanent failures due to short circuits, overtemperature,
overvoltage, and undervoltage.
24
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PROTECTION MECHANISMS IN THE TAS5704
•
•
•
•
SCP (short-circuit protection) protects against shorts across the load, to GND, and to PVCC.
OTP turns off the device if Tjunction (typical) > 150°C.
UVP turns off the device if PVCC (typical) < 8.4 V
OVP turns off the device if PVCC (typical) > 27.5 V
A short-circuit condition can be detected also by an external controller. The VALID pin goes low in the event of a
short circuit. The VALID pin can be monitored by an external mC. The TAS5704 initiates a back-end error
sequence by itself to recover from the error, which involves settling VALID low for 300 ms and then retrying to
check whether the short-circuit condition still exists.
RECOVERY FROM ERROR
•
•
•
•
OTP turns on the device back when Tdie(typical) < 135°C.
UVP turns on the device if PVCC (typical) is > 8.5 V.
OVP turns on the device if PVCC (typical) is < 27.2 V.
SCP (short-circuit protection) turns on the device if the short-circuit is removed. See the Back-End Error
section for the sequence.
SINGLE-ENDED OUTPUT CAPACITOR, CO
In single-ended (SE) applications, the dc blocking capacitor forms a high-pass filter with the speaker impedance.
The frequency response rolls of with decreasing frequency at a rate of 20 dB/decade. The cutoff frequency is
determined by
fc = 1/2pCOZL
(1)
Table 4 shows some common component values and the associated cutoff frequencies:
Table 4. Common Filter Responses
SPEAKER IMPEDANCE (Ω)
CSE – DC BLOCKING CAPACITOR (mF)
fc = 60 Hz (–3 dB)
fc = 40 Hz (–3 dB)
fc = 20 Hz (–3 dB)
4
680
1000
2200
8
330
470
1000
OUTPUT FILTER AND FREQUENCY RESPONSE
For the best frequency response, a flat-passband output filter (second-order Butterworth) may be used. The
output filter components consist of the series inductor and capacitor to ground at the output pins. There are
several possible configurations, depending on the speaker impedance and whether the output configuration is
single-ended (SE) or bridge-tied load (BTL). Table 5 lists the recommended values for the filter components. It is
important to use a high-quality capacitor in this application. A rating of at least X7R is required.
Table 5. Recommended Filter Output Components
OUTPUT CONFIGURATION
SPEAKER IMPEDANCE (Ω)
FILTER INDUCTOR (mH)
FILTER CAPACITOR (nF)
4
22
680
8
47
390
4
10
1500
8
22
680
Single Ended (SE)
Bridge Tied Load (BTL)
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Lfilter
Lfilter
OUTA
OUTA
Cfilter
Cfilter
OUTB
Lfilter
Cfilter
Figure 29. BTL Filter Configuration
Figure 30. SE Filter Configuration
POWER-SUPPLY DECOUPLING, CS
The TAS5704 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling to
ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power-supply leads.
For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 mF to 1 mF, placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 mF or greater placed near
the audio power amplifier is recommended. The 220-mF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220-mF or larger capacitor should be placed on each PVCC terminal. A 10-mF
capacitor on the AVCC terminal is adequate. These capacitors must be properly derated for voltage and
ripple-current rating to ensure reliability.
BOOTSTRAP CAPACITORS
The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input.
The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating
power supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
VCLAMP CAPACITOR
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one
internal regulator clamps the gate voltage. One 1-mF capacitor must be connected from each VCLAMP (terminal)
to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with VCC and may
not be used for powering any other circuitry.
VBYP CAPACITOR SELECTION
The scaled supply reference (BYPASS) nominally provides an AVCC/8 internal bias for the preamplifier stages.
The external capacitor for this reference (CBYP) is a critical component and serves several important functions.
During start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts. The start
up time is proportional to 0.5 s per microfarad in single-ended mode (SE/BTL = DVDD). Thus, the recommended
1-mF capacitor results in a start-up time of approximately 500 ms (SE/BTL = DVDD). The second function is to
reduce noise produced by the power supply caused by coupling with the output drive signal. This noise could
result in degraded power-supply rejection and THD+N.
26
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The circuit is designed for a CBYP value of 1 mF for best pop performance. The input capacitors should have the
same value. A ceramic or tantalum low-ESR capacitor is recommended.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TAS5704 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors—The high-frequency 0.1-mF decoupling capacitors should be placed as close to the
PVCC, VR_DIG, and AVCC terminals as possible. The BYPASS capacitor and VCLAMP_XX capacitors
should also be placed as close to the device as possible. Large (220-mF or greater) bulk power-supply
decoupling capacitors should be placed near the TAS5704 on the PVCCx terminals. For single-ended
operation, a 220 mF capacitor should be placed on each PVCC pin. For Bridge-tied operation, a single 220
mF, capacitor can be shared between A and B or C and D.
• Grounding—The AVCC decoupling capacitor and BYPASS capacitor should each be grounded to analog
ground (AGND). The PVCCx decoupling capacitors and VCLAMP_xx capacitors should each be grounded to
power ground (PGND). Analog ground and power ground should be connected at the thermal pad, which
should be used as a central ground connection or star ground for the TAS5704.
• Output filter—The reconstruction LC filter should be placed as close to the output terminals as possible for the
best EMI performance. The capacitors should be grounded to power ground.
• Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance, audio
performance, and optimal reliability. The dimensions of the thermal pad and thermal land are described in the
mechanical section at the back of the data sheet. See TI Technical Briefs SLMA002 and SLOA120 for more
information about using the thermal pad. For recommended PCB footprints, see figures at the end of this data
sheet.
For an example layout, see the TAS5704 Evaluation Module (TAS5704EVM) User Manual, (SLOU189). Both the
EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com.
BASIC MEASUREMENT SYSTEM
This section focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted-pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 31 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the audio power amplifier (APA) output to measure the
voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power
supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two™
audio measurement system (AP-II) by Audio Precision™ includes the signal generator and analyzer in one
package.
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The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 31(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 31(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
Power Supply
Signal
Generator
APA
RL
Analyzer
20 Hz - 20 kHz
(a) Basic Class-AB
Power Supply
Lfilt
Signal
Generator
Class-D APA
Cfilt
RL
Analyzer
20 Hz - 20 kHz
(b) Traditional Class-D
Figure 31. Audio Measurement Systems
28
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SE INPUT AND SE OUTPUT (TAS5704 Stereo Configuration)
The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE
measurement circuit is shown in Figure 32. SE inputs normally have one input pin per channel. In some cases,
two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through
an output ac-coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are
considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.
The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for
best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that
affects the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-mode
noise in the measurement.
Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
CIN
VGEN
RGEN
RIN
Lfilt
CL
Cfilt
Twisted-Pair Wire
RL
RANA
CANA
RANA
CANA
Twisted-Pair Wire
Figure 32. SE Input—SE Output Measurement Circuit
The following general rules should be followed when connecting to APAs with SE inputs and outputs:
• Use an unbalanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 6).
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DIFFERENTIAL INPUT AND BTL OUTPUT (TAS5704 Mono Configuration)
Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180°
out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output
power to the load and eliminating a dc-blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 33. The differential input is a balanced input,
meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the SE output
equates to a balanced output.
Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
CIN
RGEN
VGEN
Lfilt
RIN
Cfilt
CIN
RGEN
RL
Lfilt
RIN
Cfilt
Twisted-Pair Wire
RANA
CANA
RANA
CANA
Twisted-Pair Wire
Figure 33. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 6).
Table 6 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch (30.5-cm)-long wire with a 20-kHz sine-wave signal at 25°C.
Table 6. Recommended Minimum Wire Size for Power Cables
30
DC POWER LOSS
(mW)
AWG Size
AC POWER LOSS
(mW)
POUT (W)
RL(Ω)
10
4
18
22
16
40
18
42
2
4
18
22
3.2
8
3.7
8.5
1
8
22
28
2
8
2.1
8.1
< 0.75
8
22
28
1.5
6.1
1.6
6.2
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REVISION HISTORY
Changes from Original (March 2008) to Revision A
•
Page
Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 8
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PACKAGE OPTION ADDENDUM
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10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TAS5704PAP
ACTIVE
HTQFP
PAP
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 85
TAS5704
TAS5704PAPR
ACTIVE
HTQFP
PAP
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 85
TAS5704
TAS5704PAPRG4
ACTIVE
HTQFP
PAP
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 85
TAS5704
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5704PAPR
Package Package Pins
Type Drawing
HTQFP
PAP
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5704PAPR
HTQFP
PAP
64
1000
350.0
350.0
43.0
Pack Materials-Page 2
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