Texas Instruments | 125W Stereo/250W Mono PurePath HD Digital-Input Power Stage (Rev. B) | Datasheet | Texas Instruments 125W Stereo/250W Mono PurePath HD Digital-Input Power Stage (Rev. B) Datasheet

Texas Instruments 125W Stereo/250W Mono PurePath HD Digital-Input Power Stage (Rev. B) Datasheet
TAS5612
www.ti.com
SLAS682B – NOVEMBER 2009 – REVISED APRIL 2010
125W STEREO / 250W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE
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FEATURES
APPLICATIONS
•
•
•
•
•
•
23
•
•
•
•
•
•
•
•
PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80kHz for High
Frequency Content From HD Sources
– Ultralow 0.03% THD at 1W into 4Ω
– Ultralow 0.01% THD at 1W into 8Ω
– Flat THD at all Frequencies for Natural
Sound
– 80dB PSRR (BTL, No Input Signal)
– >100dB (A weighted) SNR
– Click and Pop Free Startup
Pin compatible with TAS5631, TAS5616 and
TAS5614
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge Tied Load (PBTL)
– Stereo Bridge Tied Load (BTL)
– 2.1 Single Ended Stereo Pair and Bridge
Tied Load Subwoofer
Total Output Power at 10%THD+N
– 250W in Mono PBTL Configuration
– 125W per Channel in Stereo BTL
Configuration
Total Output Power in BTL configuration at
1%THD+N
– 130W Stereo into 3Ω
– 105W Stereo into 4Ω
– 70W Stereo into 6Ω
– 55W Stereo into 8Ω
>90% Efficient Power Stage With 60-mΩ
Output MOSFETs
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
EMI Compliant When Used With
Recommended System Design
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Home Theater Systems
AV Receivers
DVD/Blu-ray™ Disc Receivers
Mini Combo Systems
Active Speakers and Subwoofers
DESCRIPTION
The TAS5612 is a high performance analog input
Class D amplifier with integrated closed loop
feedback technology (known as PurePath™ HD) with
the ability to drive up to 125W (1) Stereo into 4 to 8 Ω
Speakers from a single 32.5V supply.
PurePath™ HD technology enables traditional
AB-Amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class D
amplifiers.
Unlike traditional Class D amplifiers, the distortion
curve only increases once the output levels move into
clipping. PurePath™ HD Power PAD™
PurePath™ HD technology enables lower idle losses
making the device even more efficient.
TOTAL HARMONIC DISTORTION+NOISE
VS
OUTPUT POWER
10
4Ohm (6kHz)
THD+N - Total
tal Harmonic Distortion - %
1
4Ohm (1kHz)
1
0,1
0,01
TC = 75 C
CONFIG = BTL
0,001
0,01
1
100
PO - Output Power - W
(1)
Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
heatslug and the heat sink should be used to achieve high
output power levels.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath, Power PAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TAS5612
SLAS682B – NOVEMBER 2009 – REVISED APRIL 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
Both package types contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DKD PACKAGE
(TOP VIEW)
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
_
GND_D
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 pins PACKAGE
(TOP VIEW)
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD PACKAGE
(TOP VIEW)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
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SLAS682B – NOVEMBER 2009 – REVISED APRIL 2010
MODE SELECTION PINS
MODE PINS
PWM INPUT (1)
OUTPUT
CONFIGURATION
0
2N
2 × BTL
AD mode
1
—
—
Reserved
1
0
2N
2 × BTL
BD mode
0
1
1
1N
1 × BTL +2 ×SE
AD mode
1
0
0
1N
4 × SE
AD mode
2N
1N
M3
M2
M1
0
0
0
0
0
(1)
(2)
1
0
1
1
1
0
1
1
1
1 × PBTL
DESCRIPTION
INPUT_C (2)
INPUT_D (2)
0
0
AD mode
1
0
BD mode
Reserved
The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode
PACKAGE HEAT DISSIPATION RATINGS (1)
PARAMETER
TAS5612PHD
TAS5612DKD
RqJC (°C/W) – 2 BTL or 4 SE channels
3.2
2.1
RqJC (°C/W) – 1 BTL or 2 SE channel(s)
5.4
3.5
RqJC (°C/W) – 1 SE channel
Pad Area
(1)
(2)
(2)
7.9
5.1
64mm2
80mm2
JC is junction-to-case, CH is case-to-heat sink
RqCH is an important consideration. Assume a 2-mil thickness of thermal grease with a thermal conductivity of 2.5 W/mK between the
pad area and the heat sink and both channels active. The RqCH with this condition is 1.1°C/W for the PHD package and 0.44°C/W for
the DKD package.
Table 1. ORDERING INFORMATION (1)
(1)
TA
PACKAGE
DESCRIPTION
0°C–70°C
TAS5612PHD
64 pin HTQFP
0°C–70°C
TAS5612DKD
44 pin PSOP3
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5612
UNIT
VDD to GND
–0.3 to 13.2
V
GVDD to GND
–0.3 to 13.2
V
–0.3 to 53
V
PVDD_X to GND_X (2)
OUT_X to GND_X
(2)
–0.3 to 53
V
–0.3 to 66.2
V
BST_X to GVDD_X (2)
–0.3 to 53
V
VREG to GND
–0.3 to 4.2
V
GND_X to GND
–0.3 to 0.3
V
GND to AGND
–0.3 to 0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO-, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF
to GND
–0.3 to 4.2
V
INPUT_X
–0.3 to 7
V
RESET, SD, OTW1, OTW2, CLIP, READY to GND
–0.3 to 7
V
BST_X to GND_X (2)
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY)
9
mA
0 to 150
°C
–40 to 150
°C
±2
kV
±500
V
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
Electrostatic discharge
(1)
(2)
(3)
Human body model
(3)
(all pins)
Charged device model (3) (all pins)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
16
32.5
34.1
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
3.5
4
1.8
2
1.6
2
2.8
3
7
10
7
15
7
10
352
384
RL(BTL)
RL(SE)
Load impedance
Output filter according to schematics in
the application information section.
RL(PBTL)
RL(BTL)
Load Impedance
Output filter according to schematics in
the application information section.
(ROC = 22kΩ, add Schottky diodes from
OUT_X to GND_X)
Output filter inductance
Minimum output inductance at IOC
LOUTPUT(BTL)
LOUTPUT(SE)
LOUTPUT(PBTL)
FPWM
PWM frame rate
CPVDD
PVDD close decoupling capacitors
ROC
Over-current programming resistor
Resistor tolerance = 5%
ROC_LACTHED
Over-current programming resistor
Resistor tolerance = 5%
TJ
Junction temperature
4
Ω
mH
500
kHz
2.0
mF
22
30
kΩ
47
64
kΩ
0
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Ω
150
°C
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SLAS682B – NOVEMBER 2009 – REVISED APRIL 2010
PIN FUNCTIONS
PIN
Function (1)
DESCRIPTION
10
P
Analog ground
54
43
P
HS bootstrap supply (BST), external 0.033mF capacitor to OUT_A required.
41
34
P
HS bootstrap supply (BST), external 0.033mF capacitor to OUT_B required.
BST_C
40
33
P
HS bootstrap supply (BST), external 0.033mF capacitor to OUT_C required.
BST_D
27
24
P
HS bootstrap supply (BST), external 0.033mF capacitor to OUT_D required.
CLIP
18
—
O
Clipping warning; open drain; active low
C_STARTUP
3
5
O
Startup ramp requires a charging capacitor of 4.7nF to GND
TEST
12
14
I
Connect to VREG node
GND
7, 23, 24, 57, 58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate drive voltage supply requires 0.1mF capacitor to GND
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1mF capacitor to GND
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1mF capacitor to GND
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1mF capacitor to GND
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22mF capacitor to GND
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22mF capacitor to GND
INPUT_A
4
6
I
Input signal for half bridge A
INPUT_B
5
7
I
Input signal for half bridge B
INPUT_C
10
12
I
Input signal for half bridge C
INPUT_D
11
13
I
Input signal for half bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59–62
–
—
No connect, pins may be grounded.
NC
13, 14
15, 16
—
No connect, pins may be grounded.
OC_ADJ
1
3
O
Analog overcurrent programming pin requires resistor to ground.
OTW
—
18
O
Overtemperature warning signal, open drain, active low.
OTW1
16
—
O
Overtemperature warning signal, open drain, active low.
OTW2
17
—
O
Overtemperature warning signal, open drain, active low.
OUT_A
52, 53
39, 40
O
Output, half bridge A
OUT_B
44, 45
36
O
Output, half bridge B
OUT_C
36, 37
31
O
Output, half bridge C
OUT_D
28, 29
27, 28
O
Output, half bridge D
63
1
P
PSU Reference requires close decoupling of 4.7mF to GND
PVDD_A
50, 51
41, 42
P
Power supply input for half bridge A requires close decoupling of 2uF capacitor GND_A
PVDD_B
42, 43
35
P
Power supply input for half bridge B requires close decoupling of 2uF capacitor GND_B
PVDD_C
38, 39
32
P
Power supply input for half bridge C requires close decoupling of 2uF capacitor GND_C
PVDD_D
30, 31
25, 26
P
Power supply input for half bridge D requires close decoupling of 2uF capacitor GND_D
READY
19
19
O
Normal operation; open drain; active high
RESET
2
4
I
Device reset Input; active low
SD
15
17
O
Shutdown signal, open drain, active low
VDD
64
2
P
Power supply for digital voltage regulator requires a 47mF capacitor in parallel with a
0.1mF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 4.7mF to GND
VREG
9
11
P
Digital regulator supply filter pin requires 0.1mF capacitor to GND
NAME
PHD NO.
DKD NO.
AGND
8
BST_A
BST_B
PSU_REF
(1)
I = Input, O = Output, P = Power
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TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
Filtering
and
Startup/Stop
System
microcontroller
(2)
AMP RESET
LeftChannel
Output
PWM_A
C_STARTUP
VI_CM
PSU_REF
RESET
VALID
/CLIP
*NOTE1
READY
/SD
TAS5518/
TAS5508/
TAS5086
/OTW1, /OTW2, /OTW
I2C
BST_A
BST_B
OUT_A
INPUT_A
PWM_B
Input
H-Bridge 1
INPUT_B
Output
H-Bridge 1
2
OUT_B
2
Bootstrap
Caps
2nd Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
PWM_C
INPUT_C
PWM_D
INPUT_D
OUT_C
Input
H-Bridge 2
Output
H-Bridge 2
2
OUT_D
8
32.5V
PVDD
12V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
8
OC_ADJ
TEST
VREG
AGND
M3
2nd Order
L-C Output
Filter for
each
H-Bridge
BST_C
VDD
M2
GND
M1
GND_A, B, C, D
Hardwire
Mode
Control
GVDD_A, B, C, D
2
PVDD_A, B, C, D
RightChannel
Output
BST_D
Bootstrap
Caps
4
GVDD, VDD,
and VREG
Power Supply
Decoupling
Hardwire
OverCurrent
Limit
GND
GVDD (12V)/VDD (12V)
VAC
(1)
6
Logic AND is inside or outside the micro controller.
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FUNCTIONAL BLOCK DIAGRAM
CLIP
READY
OTW1
OTW2
SD
PROTECTION & I/O LOGIC
M1
M2
M3
RESET
STARTUP
CONTROL
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
GVDD_A
GVDD_C
GVDD_B
OVER-LOAD
PROTECTION
PPSC
CURRENT
SENSE
CB3C
4
4
4
GND
GVDD_D
OC_ADJ
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_A
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
PSU_REF
GVDD_B
VI_CM
INPUT_D
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
-
+
ANALOG COMPARATOR MUX
PVDD_X
GND
PVDD_B
PWM
RECEIVER
+
ANALOG INPUT MUX
4
AGC
BST_B
+
ANALOG
LOOP FILTER
INPUT_B
INPUT_C
-
ANALOG
LOOP FILTER
INPUT_A
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
+
OUT_C
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
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AUDIO CHARACTERISTICS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)
and a TAS5612 power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4Ω, fS = 384 kHz, ROC = 30kΩ, TC = 75°C,
Output Filter: LDEM = 7mH, CDEM = 680nF, MODE = 000, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP MAX UNIT
RL = 3Ω, 10% THD+N (ROC=22kΩ, add Schottky
diodes from OUT_X to GND_X)
165
RL = 4Ω, 10% THD+N
125
RL = 3Ω, 1% THD+N (ROC=22kΩ, add Schottky
diodes from OUT_X to GND_X)
130
RL = 4Ω, 1% THD+N
105
1 W, RL = 4Ω
0.03%
1 W, RL = 8Ω
0.01%
W
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise
A-weighted, TAS5518 Modulator
|VOS|
Output offset voltage
No signal
SNR
Signal-to-noise ratio (1)
A-weighted, TAS5518 Modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5518
modulator
103
dB
Pidle
Power dissipation due to Idle losses
(IPVDD_X)
PO = 0, 4 channels switching (2)
2
W
(1)
(2)
8
114
20
mV
30
mV
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses also are affected by core losses of output inductors.
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AUDIO CHARACTERISTICS (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)
and a TAS5612 power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 2Ω, fS = 384kHz, ROC = 30kΩ, TC = 75°C,
Output Filter: LDEM = 7mH, CDEM = 1mF, MODE = 101-00, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP MAX
RL = 2Ω, 10%, THD+N
250
RL = 3Ω, 10% THD+N
165
RL = 4Ω, 10% THD+N
125
RL = 2Ω, 1% THD+N
210
RL = 3Ω, 1% THD+N
135
RL = 4Ω, 1% THD+N
UNIT
W
105
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 Modulator
120
mV
SNR
Signal to noise ratio (1)
A-weighted, TAS5518 Modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using
TAS5518 modulator
103
dB
Pidle
Power dissipation due to idle losses (IPVDD_X)
PO = 0, 4 channels switching (2)
1.7
W
(1)
(2)
0.03%
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 32.5V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 384kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VI_CM
Analog comparator reference node, VI_CM
IVDD
VDD supply current
IGVDD_x
Gate-supply current per half-bridge
IPVDD_x
Half-bridge idle current
VDD = 12V
3
3.3
3.6
V
1.5
1.75
1.9
V
Operating, 50% duty cycle
20
Idle, reset mode
20
50% duty cycle
10
Reset mode
1.5
50% duty cycle without output filter or
load
15
mA
540
mA
Reset mode, No switching
mA
mA
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, excludes metallization
resistance,
GVDD = 12V
60
100
mΩ
60
100
mΩ
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 32.5V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 384kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
I/O PROTECTION
Vuvp,G
Undervoltage protection limit, GVDD_x
Vuvp,hyst
10
(1)
V
0.6
V
OTW1 (1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTWhyst
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event.
(1)
25
Overtemperature error
OTE (1)
OTEHYST
OLPC
(1)
145
155
°C
165
°C
OTE-OTW differential
30
°C
A reset needs to occur for SD to be released
following an OTE event
25
°C
2.6
ms
Overload protection counter
fPWM = 384kHz
Overcurrent limit protection
IOC
Overcurrent limit protection, latched
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 30kΩ
12.6
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 22kΩ
(With Schottky diodes from OUT_X to
GND_X)
16.3
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 64kΩ
12.6
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 47kΩ
(With Schottky diodes from OUT_X to
GND_X)
16.3
A
A
IOCT
Overcurrent response time
Time from application of short condition to
Hi-Z of affected half bridge
150
ns
IPD
Internal pulldown resistor at output of each
half bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode.
3
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
INPUT_X, M1, M2, M3, RESET
1.9
V
0.8
V
100
mA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW1 to VREG,
OTW2 to VREG, SD to VREG
VOH
High level output voltage
VOL
Low level output voltage
IO = 4mA
FANOUT
Device fanout OTW1, OTW2, SD, CLIP,
READY
No external pullup
(1)
10
Internal pullup resistor
External pullup of 4.7kΩ to 5V
20
26
33
3
3.3
3.6
4.5
5
200
30
500
V
mV
devices
Specified by design.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC+NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
200
TC = 75°C
TC = 75°C
THD+N = 10%
3W
4W
1
3W
150
6W
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
8W
0.1
4W
6W
8W
100
50
0.01
0.001
0.01
0.1
1
100
10
PO - Output Power - W
0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVDD - Supply Voltage - V
1000
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
SYSTEM EFFICIENCY
vs
OUTPUT POWER
150
100
TC = 75°C
90
3W
80
8W
70
100
6W
Efficiency - %
PO - Output Power - W
4W
8W
50
6W
4W
60
50
40
30
20
TC = 25°C
THD+N = 10%
10
0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVDD - Supply Voltage - V
0
0
Figure 3.
50
100
150
200
250
2 Channel Output Power - W
300
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEMS POWER LOSS
vs
OUTPUT POWER
OUTPUT POWER
vs
CASE TEMPERATURE
40
200
3W
TC = 25°C
THD+N = 10%
4W
4W
150
PO - Output Power - W
Power Loss - W
30
6W
20
8W
6W
100
50
10
8W
THD+N = 10%
0
20
0
0
50
100
150
200
250
300
30
2 Channel Output Power - W
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion - %
TC = 75°C,
VREF = 22.98 V,
Sample Rate = 48 kHz,
FFT Size = 16384
-40
Noise Amplitude - dB
90
100
10
0
-20
40
50
60
70
80
TC - Case Temperature - °C
-60
-80
-100
-120
4W
-140
RL = 4 W,
TC = 75°C,
Toroidal Output Inductors
1
0.1
1W
0.01
17.3 W (1/8 Power)
-160
0
5
10
15
f - Frequency - kHz
20
0.001
10
Figure 7.
12
100
1k
10k
f - Frequency - Hz
100k
Figure 8.
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC+NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
300
TC = 75°C
TC = 75°C
THD+N = 10%
2W
3W
2W
250
3W
4W
1
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
6W
8W
0.1
4W
200
6W
150
8W
100
0.01
50
0.001
0.01
0.1
1
100
10
PO - Output Power - W
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVDD - Supply Voltage - V
1000
Figure 9.
Figure 10.
OUTPUT POWER
vs
CASE TEMPERATURE
300
2W
250
PO - Output Power - W
3W
200
4W
150
6W
100
8W
50
0
20
30
40
80
90
50
70
60
TC - Case Temperature - °C
Figure 11.
100
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APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 2oz. (70mm) is recommended for use with the TAS5612. The use of this material
can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB
trace inductance.
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000mF, 50V support more applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
DECOUPLING CAPACITOR RECOMMENDATION
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1mF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50V is required for use with a 32.5v power
supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices in the use of the TAS5612.
14
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2 mF
30 kW
2 mF
2 mF
2 mF
2 mF
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Figure 12. Typical Differential (2N) BTL Application With BD Modulation Filters
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TAS5612
30 kW
2 mF
2 mF
2 mF
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2 mF
SLAS682B – NOVEMBER 2009 – REVISED APRIL 2010
Figure 13. Typical (2N) PBTL Application With BD Modulation Filters
16
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2 mF
2 mF
30 kW
2 mF
SLAS682B – NOVEMBER 2009 – REVISED APRIL 2010
2 mF
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Figure 14. Typical Differential Input BTL Application with BD Modulation Filters DKD Package
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5612 needs only a 12V supply in addition to the (typical) 32.5V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and
output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12 V source,
it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit
board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended
high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their
associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors
must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 4000kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5612 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 32.5V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5612 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5612 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5612 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1
OTW2,
OTW
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
DESCRIPTION
Note that asserting RESET low forces the SD signal high, independent of faults being present. TI recommends
monitoring the OTW signal using the system micro controller and responding to an overtemperature warning
signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown
(OTE).
To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW
outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5612 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5612 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table.
BTL Mode
PBTL Mode
SE Mode
Local Error In
Turns Off
Local Error In
Turns Off
Local Error In
Turns Off
A
A+B
A
A+B+C+D
A
A+B
B
C
C+D
D
B
B
C
C
D
D
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an over current after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup will not
activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges
are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts
switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no
shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The total
duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is
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<15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will not react to changes
applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released. A device
reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the
detection is not performed in SE mode. To make sure not to trip the PPSC detection system it is recommended
not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options has individual over temperature protection schemes.
PHD Package
The TAS5612 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5612 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5612 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after
an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the
falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal
goes low, hence, filtering is needed if the signal is intended for audio muting in non micro controller systems.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
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PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 12.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 15. Printed Circuit Board - Top Layer
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Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 16. Printed Circuit Board - Bottom Layer
SPACER
REVISION HISTORY
Changes from Original (November 2009) to Revision A
Page
•
Added Features bullet - Ultralow 0.01% THD at 1W into 8Ω ............................................................................................... 1
•
Changed Test Conditions of THD+N in the AUDIO CHARACTERISTICS (BTL) - 1 W, RL = 8Ω ........................................ 8
Changes from Revision A (January 2010) to Revision B
Page
•
Deleted the Product Preview banner from the DKD PACKAGE .......................................................................................... 2
•
Changed Pin 41 from BST_C To BST_B in the PHD PACKAGE ........................................................................................ 2
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TAS5612PHD
NRND
HTQFP
PHD
64
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TAS5612
TAS5612PHDR
NRND
HTQFP
PHD
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TAS5612
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5612PHDR
Package Package Pins
Type Drawing
HTQFP
PHD
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
17.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
17.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5612PHDR
HTQFP
PHD
64
1000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PHD 64
HTQFP - 1.20 mm max height
QUAD FLATPACK
14 x 14, 0.8 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224851/A
www.ti.com
PACKAGE OUTLINE
HTQFP - 1.2 mm max height
PHD0064B
PLASTIC QUAD FLATPACK
14.05
13.95
NOTE 3
PIN 1 ID
64
8.00
6.68
B
49
48
1
THERMAL PAD
4
14.05
13.95
NOTE 3
16.15
15.85
TYP
8.00
6.68
16
32
17
A
33
64 X 0.40
0.30
60 X 0.8
4 X 12
0.2
SEE DETAIL A
C A B
C
1.2 MAX
SEATING PLANE
(0.127) TYP
17
32
16
33
0.25
GAGE PLANE
1.05
0.95
0°-7°
0.75
0.45
1
48
64
49
0.1 C
0.15
0.05
DETAIL A
TYPICAL
4224850/A 05/2019
NOTES:
1.
2.
3.
4.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
See technical brief. PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
(www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004) for information regarding recommended board layout.
www.ti.com
EXAMPLE BOARD LAYOUT
HTQFP - 1.2 mm max height
PHD0064B
PLASTIC QUAD FLATPACK
SYMM
49
64
64 X (1.5)
1
48
64 X (0.55)
60 X (0.8)
SYMM
(15.4)
33
(R0.05) TYP
16
32
17
(15.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
EXPOSED
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224850/A 05/2019
NOTES: (continued)
5.
6.
7.
Publication IPC-7351 may have alternate designs.
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
HTQFP - 1.2 mm max height
PHD0064B
PLASTIC QUAD FLATPACK
SYMM
49
64
64 X (1.5)
1
48
64 X (0.55)
60 X (0.8)
SYMM
(15.4)
33
(R0.05) TYP
16
32
17
(15.4)
SOLDER PASTE EXAMPLE
SCALE: 6X
4224850/A 05/2019
NOTES: (continued)
7.
8.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2019, Texas Instruments Incorporated
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