Texas Instruments | 1.25-W Mono Fully Differential Audio Power Amplifier (Rev. F) | Datasheet | Texas Instruments 1.25-W Mono Fully Differential Audio Power Amplifier (Rev. F) Datasheet

Texas Instruments 1.25-W Mono Fully Differential Audio Power Amplifier (Rev. F) Datasheet
DRB
GQV, ZQV
TPA6203A1
DGN
www.ti.com.......................................................................................................................................................... SLOS364F – MARCH 2002 – REVISED JUNE 2008
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
• 1.25 W Into 8 Ω From a 5-V Supply at
THD = 1% (Typical)
• Low Supply Current: 1.7 mA Typical
• Shutdown Control < 10 µA
• Only Five External Components
– Improved PSRR (90 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– Improved CMRR Eliminates Two Input
Coupling Capacitors
– C(BYPASS) Is Optional Due to Fully
Differential Design and High PSRR
• Avaliable in a 2 mm x 2 mm MicroStar
Junior ™ BGA Package (GQV, ZQV)
• Available in 3 mm x 3 mm QFN Package (DRB)
• Available in an 8-Pin PowerPAD™ MSOP
(DGN)
•
1
2
Designed for Wireless or Cellular Handsets
and PDAs
DESCRIPTION
The TPA6203A1 is a 1.25-W mono fully differential
amplifier designed to drive a speaker with at least
8-Ω impedance while consuming less than 37 mm2
(ZQV package option) total printed-circuit board
(PCB) area in most applications. This device operates
from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent
supply current. The TPA6203A1 is available in the
space-saving 2 mm x 2 mm MicroStar Junior™ BGA
package, and the space saving 3 mm x 3 mm QFN
(DRB) package.
Features like 85-dB PSRR from 90 Hz to 5 kHz,
improved RF-rectification immunity, and small PCB
area makes the TPA6203A1 ideal for wireless
handsets. A fast start-up time of 4 µs with minimal
pop makes the TPA6203A1 ideal for PDA
applications.
APPLICATION CIRCUIT
In From
DAC
RI
+ RI
ININ+
To Battery
RF
Cs
_
VO+
(1)C
CS
B
VO+
RF
SHUTDOWN
Actual Solution Size
VDD
RF
GND
Bias
Circuitry
C(BYPASS)
(Optional)
5,25 mm
RI
RI
RF
6,9 mm
Applies to the GQV/ZQV Packages Only
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Junior, PowerPAD, MicroStar Junior are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2008, Texas Instruments Incorporated
TPA6203A1
SLOS364F – MARCH 2002 – REVISED JUNE 2008.......................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES (1) (2) (3)
(1)
(2)
(3)
MicroStar Junior™
(GQV)
MicroStar Junior™
(ZQV)
QFN
(DRB)
MSOP
(DGN)
Device
TPA6203A1GQVR
TPA6203A1ZQVR
TPA6203A1DRB
TPA6203A1DGN
Symbolization
AADI
AAEI
AAJI
AAII
The GQV is the standard MicroStar Junior package. The ZQV is a lead-free option and is qualified for 260° lead-free assembly.
The GQV and ZQV packages are only available taped and reeled. The suffix R designates taped and reeled parts.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Supply voltage, VDD
-0.3 V to 6 V
Input voltage, VI
INx and SHUTDOWN pins
-0.3 V to VDD + 0.3 V
Continuous total power dissipation
See Dissipation Rating Table
Operating free-air temperature, TA
-40°C to 85°C
Junction temperature, TJ
-40°C to 125°C
Storage temperature, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
(1)
ZQV, DRB, DGN
260°C
GQV
235°C
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD
TYP
2.5
High-level input voltage, VIH
SHUTDOWN
Low-level input voltage, VIL
SHUTDOWN
Common-mode input voltage, VIC
VDD = 2.5 V, 5.5 V, CMRR ≤ -60 dB
MAX
5.5
2
-40
Load impedance, ZL
6.4
V
V
0.5
Operating free-air temperature, TA
UNIT
0.8
V
VDD-0.8
V
85
°C
Ω
8
DISSIPATION RATINGS
2
PACKAGE
TA ≤ 25°C
POWER RATING
GQV, ZQV
DRB
DERATING FACTOR
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
885 mW
8.8 mW/°C
486 mW
354 mW
2.7 W
21.8 mW/°C
1.7 W
1.4 W
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ELECTRICAL CHARACTERISTICS
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
|VOO|
Output offset voltage (measured
differentially)
VI = 0 V, VDD = 2.5 V to 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD-0.8
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
CMRR
Common-mode rejection ratio
VOL
Low-level output voltage
RL = 8 Ω, VIN+ = VDD,
VIN- = 0 V or VIN+ = 0 V, VIN- = VDD
MIN
VOH
High-level output voltage
UNIT
9
mV
-90
-70
dB
-70
-65
-62
-55
VDD = 5.5 V
0.30
0.46
VDD = 3.6 V
0.22
VDD = 2.5 V
0.19
VDD = 5.5 V
RL = 8 Ω, VIN+ = VDD,
VIN- = 0 V or VIN+ = 0 V, VIN- = VDD
TYP MAX
4.8
VDD = 3.6 V
VDD = 2.5 V
|IIH|
High-level input current
VDD = 5.5 V, VI = 5.8 V
|IIL|
Low-level input current
VDD = 5.5 V, VI = -0.3 V
IDD
Supply current
VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = 2 V
IDD(SD)
Supply current in shutdown mode SHUTDOWN = 0.8 V, VDD = 2.5 V to 5.5 V, No load
V
0.26
5.12
3.28
2.1
dB
V
2.24
1.2
µA
1.2
µA
1.7
2
mA
0.01
0.9
µA
TYP
MAX
UNIT
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 1 V/V, RL = 8 Ω
PARAMETER
PO
THD+N
kSVR
SNR
Output power
Total harmonic distortion
plus noise
Supply ripple rejection ratio
Signal-to-noise ratio
TEST CONDITIONS
THD + N = 1%, f = 1 kHz
MIN
VDD = 5 V
1.25
VDD = 3.6 V
0.63
VDD = 2.5 V
0.3
VDD = 5 V, PO = 1 W, f = 1 kHz
0.06%
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz
0.07%
VDD = 2.5 V, PO = 200 mW, f = 1 kHz
0.08%
C(BYPASS) = 0.47 °F,
VDD = 3.6 V to 5.5 V,
Inputs ac-grounded with CI = 2 µF
f = 217 Hz to 2 kHz,
VRIPPLE = 200 mVPP
-87
C(BYPASS) = 0.47 µF,
VDD = 2.5 V to 3.6 V,
Inputs ac-grounded with CI = 2 µF
f = 217 Hz to 2 kHz,
VRIPPLE = 200 mVPP
-82
C(BYPASS) = 0.47 µF,
VDD = 2.5 V to 5.5 V,
Inputs ac-grounded with CI = 2 µF
f = 40 Hz to 20 kHz,
VRIPPLE = 200 mVPP
≤-74
VDD = 5 V, PO= 1 W
Vn
Output voltage noise
f = 20 Hz to 20 kHz
CMRR
Common-mode rejection
ratio
VDD = 2.5 V to 5.5 V,
resistor tolerance = 0.1%,
gain = 4V/V, VICM = 200 mVPP
ZI
Input impedance
ZO
Output impedance
Shutdown mode
Shutdown attenuation
f = 20 Hz to 20 kHz, RF = RI = 20 kΩ
104
No weighting
17
A weighting
13
f = 20 Hz to 1 kHz
≤-85
f = 20 Hz to 20 kHz
≤-74
Product Folder Link(s): TPA6203A1
dB
dB
µVRMS
dB
2
MΩ
-80
dB
>10k
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MicroStar Junior™ (GQV or ZQV) PACKAGE
(TOP VIEW)
VOSHUTDOWN
BYPASS
GND
1 2 3
A
B
C
VDD
VO+
ININ+
(SIDE VIEW)
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
SHUTDOWN
1
8 V
O-
BYPASS
2
7 GND
IN+
3
6 VDD
IN-
4
5 VO+
8-PIN MSOP (DGN) PACKAGE
(TOP VIEW)
SHUTDOWN
1
8
VO-
BYPASS
2
7
GND
IN+
3
6
VDD
IN-
4
5
VO+
Terminal Functions
TERMINAL
GQV
DRB,
DGN
I/O
BYPASS
C1
2
I
Mid-supply voltage. Adding a bypass capacitor improves PSRR.
GND
B2
7
I
High-current ground
IN-
C3
4
I
Negative differential input
IN+
C2
3
I
Positive differential input
SHUTDOWN
B1
1
I
Shutdown terminal (active low logic)
VDD
A3
6
I
Supply voltage terminal
VO+
B3
5
O
Positive BTL output
VO-
A1
8
O
Negative BTL output
NAME
Thermal Pad
4
DESCRIPTION
Connect to ground. Thermal pad must be soldered down in all applications to properly secure device
on the PCB.
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www.ti.com.......................................................................................................................................................... SLOS364F – MARCH 2002 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Supply voltage
1
vs Load resistance
2, 3
Power dissipation
vs Output power
4, 5
Maximum ambient temperature
vs Power dissipation
PO
Output power
PD
vs Output power
Total harmonic distortion + noise
vs Frequency
6
7, 8
9, 10, 11, 12
vs Common-mode input voltage
CMRR
IDD
13
Supply voltage rejection ratio
vs Frequency
Supply voltage rejection ratio
vs Common-mode input voltage
18
GSM Power supply rejection
vs Time
19
GSM Power supply rejection
vs Frequency
20
vs Frequency
21
vs Common-mode input voltage
22
Closed loop gain/phase
vs Frequency
23
Open loop gain/phase
vs Frequency
24
vs Supply voltage
25
vs Shutdown voltage
26
vs Bypass capacitor
27
Common-mode rejection ratio
Supply current
Start-up time
14, 15, 16, 17
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TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
1.8
THD+N = 10%
1
0.8
0.6
THD+N = 1%
0.4
0.4
0
0
3.5
4
4.5
5
VDD = 2.5 V
0.6
0.2
3
VDD = 3.6 V
0.8
0.2
2.5
0.8
VDD = 2.5 V
0.6
0.4
13
18
23
28
8
32
13
18
23
RL - Load Resistance - Ω
RL - Load Resistance - Ω
28
Figure 1.
Figure 2.
Figure 3.
POWER DISSIPATION
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
MAXIMUM AMBIENT
TEMPERATURE
vs
POWER DISSIPATION
0.6
PD - Power Dissipation - W
8Ω
0.3
0.25
0.2
0.15
16 Ω
0.1
0.05
Maximum Ambient Temperature - oC
VDD = 5 V
0.35
8Ω
0.5
0.4
0.3
16 Ω
0.2
0.1
0
0
0.2
0.4
0.6
32
90
0.7
VDD = 3.6 V
80
70
60
50
40
30
ZQV Package Only
20
10
0
0.8
0
0.2
PO - Output Power - W
0.4
0.6
0.8
1
1.2
0
1.4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
PD - Power Dissipation - W
PO - Output Power - W
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
10
5
2.5 V
2
3.6 V
1
0.5
5V
0.2
0.1
0.05
0.02
RL = 8 Ω, f = 1 kHz
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
0.01
10 m
100 m
1
2 3
THD+N - Total Harmonic Distortion + Noise - %
Figure 4.
10
5
2
RL = 16 Ω
f = 1 kHz
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
1
0.5
0.2
2.5 V
5V
3.6 V
0.1
0.05
0.02
0.01
10 m
100 m
PO - Output Power - W
PO - Output Power - W
Figure 7.
Figure 8.
1
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2
THD+N - Total Harmonic Distortion + Noise - %
PD - Power Dissipation - W
VDD = 3.6 V
1
0
8
0.4
0
VDD = 5 V
1.2
0.2
VDD - Supply Voltage - V
THD+N - Total Harmonic Distortion + Noise - %
1.4
VDD = 5 V
1
f = 1 kHz
THD+N = 10%
Gain = 1 V/V
1.6
PO - Output Power - W
1.2
f = 1 kHz
THD+N = 1%
Gain = 1 V/V
1.2
PO - Output Power - W
1.4
PO - Output Power - W
1.8
1.4
RL = 8 Ω
f = 1 kHz
Gain = 1 V/V
1.6
6
OUTPUT POWER
vs
LOAD RESISTANCE
10
5
0.5
VDD = 5 V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
0.2
250 mW
2
1
50 mW
0.1
0.05
0.02
1W
0.01
0.005
0.002
0.001
20
100 200
1k 2k
f - Frequency - Hz
10 k 20 k
Figure 9.
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Product Folder Link(s): TPA6203A1
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TYPICAL CHARACTERISTICS (continued)
1
0.5
25 mW
0.2
0.1
125 mW
0.05
0.02
500 mW
0.01
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
10
5
VDD = 2.5 V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
2
1
0.5
15 mW
0.2
0.1
75 mW
0.05
0.02
200 mW
0.01
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion + Noise - %
2
10
5
VDD = 3.6 V
CI = 2 µF
RL = 16 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
2
1
0.5
0.2
25 mW
125 mW
0.1
0.05
0.02
0.01
250 mW
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
Figure 12.
TOTAL HARMONIC DISTORTION +
NOISE
vs
COMMON MODE INPUT VOLTAGE
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
f = 1 kHz
PO = 200 mW
1
VDD = 2.5 V
0.10
k
VDD = 3.6 V
0.01
0
0
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0.47 µF
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 1 V/V
-10
-20
-30
-40
-50
-60
VDD =2. 5 V
-70
VDD = 5 V
-80
-90
VDD = 3.6 V
-100
20
0.5
1
1.5
2
2.5
3
3.5
VIC - Common Mode Input Voltage - V
k
10
- Supply Voltage Rejection Ratio - dB
SVR
Figure 11.
- Supply Voltage Rejection Ratio - dB
SVR
Figure 10.
50 100 200
500 1 k 2 k
0
Gain = 5 V/V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0.47 µF
Vp-p = 200 mV
Inputs ac-Grounded
-10
-20
-30
-40
-50
VDD =2. 5 V
-60
VDD = 5 V
-70
-80
VDD = 3.6 V
-90
-100
5 k 10 k 20 k
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
f - Frequency - Hz
Figure 13.
Figure 14.
Figure 15.
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION
RATIO
vs
COMMON MODE INPUT VOLTAGE
-20
-30
-40
-50
VDD =2. 5 V
-60
VDD = 5 V
-70
VDD = 3.6 V
-80
-90
-100
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
0
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Inputs ac-Grounded
Gain = 1 V/V
-10
-20
-30
-40
C(Bypass) = 0.47 µF
-50
-60
C(Bypass) = 0
C(Bypass) = 1 µF
-70
C(Bypass) = 0.1 µF
-80
SVR
CI = 2 µF
RL = 8 Ω
Inputs Floating
Gain = 1 V/V
-90
-100
k
- Supply Voltage Rejection Ratio - dB
SVR
0
-10
- Supply Voltage Rejection Ratio - dB
f - Frequency - Hz
k
- Supply Voltage Rejection Ratio - dB
SVR
k
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion + Noise - %
10
5
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
20
50 100 200
500 1 k 2 k
f - Frequency - Hz
f - Frequency - Hz
Figure 16.
Figure 17.
5 k 10 k 20 k
-10
f = 217 Hz
C(Bypass) = 0.47 µF
RL = 8 Ω
Gain = 1 V/V
-20
-30
VDD = 2.5 V
-40
VDD = 3.6 V
-50
-60
-70
-80
VDD = 5 V
-90
0
1
2
3
4
VIC - Common Mode Input Voltage - V
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
GSM POWER SUPPLY
REJECTION
vs
FREQUENCY
0
C1
Frequency
217.41 Hz
-50
C1 - Duty
20 %
-100
C1 Pk-Pk
504 mV
VO
2 ms/div
-150
VDD Shown in Figure 19
CI = 2 µF,
C(Bypass) = 0.47 µF,
Inputs ac-Grounded
Gain = 1V/V
-50
-100
-150
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1 k 2 k
5 k 10 k 20 k
f - Frequency - Hz
Figure 20.
Figure 21.
COMMON MODE REJECTION RATIO
vs
COMMON MODE INPUT VOLTAGE
CLOSED LOOP GAIN/PHASE
vs
FREQUENCY
OPEN LOOP GAIN/PHASE
vs
FREQUENCY
40
-20
220
Phase
30
20
VDD = 2.5 V
-50
VDD = 5 V
20
-10
-20
-30
-60
-70
-40
-100
-80
-50
-90
0
0.5 1
1.5 2
2.5 3
3.5 4
10
100
1k
50
50
0
0
-50
-50
Phase
-100
-180
-150
-150
-220
10 M
-200
-140
-70
4.5 5
100
Gain
-100
VDD = 3.6 V
RL = 8 Ω
Gain = 1 V/V
-60
VDD = 3.6 V
-100
150
100
60
-20
-60
150
100
Gain
0
-40
200
VDD = 3.6 V
RL = 8 Ω
140
10
-30
200
180
Gain - dB
RL = 8 Ω
Gain = 1 V/V
Phase - Degrees
0
-10
10 k
100 k 1 M
100
f - Frequency - Hz
1k
10 k
100 k
1M
Figure 23.
Figure 24.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
START-UP TIME(1)
vs
BYPASS CAPACITOR
1.8
1.8
1.6
1.6
1.4
1.4
-200
10 M
f - Frequency - Hz
Figure 22.
6
5
1.2
1
0.8
0.6
0.4
VDD = 2.5 V
1.2
1.0
VDD = 3.6 V
0.8
VDD = 5 V
Start-Up Time - ms
I DD - Supply Current - mA
I DD - Supply Current - mA
-30
Figure 19.
VIC - Common Mode Input Voltage - V
0.6
0.4
0
0 0.5 1
1.5 2 2.5 3 3.5
4 4.5 5
5.5
4
3
2
1
0.2
0.2
8
VDD = 2.5 V to 5 V
VIC = 200 mVp-p
RL = 8 Ω
Gain = 1 V/V
-20
f - Frequency - Hz
Gain - dB
CMRR - Common Mode Rejection Ratio - dB
Ch1 100 mV/div
Ch4 10 mV/div
t - Time - ms
0
0
-10
Phase - Degrees
C1 High
3.598 V
VO - Output Voltage - dBV
Voltage - V
VDD
CMRR - Common Mode Rejection Ratio - dB
COMMON MODE REJECTION RATIO
vs
FREQUENCY
V DD - Supply Voltage - dBV
GSM POWER SUPPLY
REJECTION
vs
TIME
0
0
0
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
VDD - Supply Voltage - V
Voltage on SHUTDOWN Terminal - V
Figure 25.
Figure 26.
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(1)
0.5
1
1.5
C(Bypass) - Bypass Capacitor - µF
2
Start-Up time is the time it takes (from a
low-to-high transition on SHUTDOWN) for the
gain of the amplifier to reach -3 dB of the final
gain.
Figure 27.
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Product Folder Link(s): TPA6203A1
TPA6203A1
www.ti.com.......................................................................................................................................................... SLOS364F – MARCH 2002 – REVISED JUNE 2008
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
The TPA6203A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a
common- mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential
voltage that is equal to the differential input times the
gain. The common-mode feedback ensures that the
common-mode voltage at the output is biased around
VDD/2 regardless of the common- mode voltage at the
input.
•
APPLICATION SCHEMATICS
Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6203A1, allows the inputs to be biased at
voltage other than mid-supply. For example, if a
DAC has mid-supply lower than the mid-supply of
the TPA6203A1, the common-mode feedback
circuit adjusts for that, and the TPA6203A1
outputs are still biased at mid-supply of the
TPA6203A1. The inputs of the TPA6203A1 can
be biased from 0.5 V to VDD - 0.8 V. If the inputs
are biased outside of that range, input coupling
capacitors are required.
• Mid-supply bypass capacitor, C(BYPASS), not
required: The fully differential amplifier does not
require a bypass capacitor. This is because any
shift in the mid-supply affects both positive and
Figure 28 through Figure 30 show application
schematics for differential and single-ended inputs.
Typical values are shown in Table 1.
Table 1. Typical Component Values
COMPONENT
VALUE
RI
10 kΩ
RF
10 kΩ
C(BYPASS)(1)
0.22 µF
CS
1 µF
CI
0.22 µF
(1) C(BYPASS) is optional
VDD
RF
In From
DAC
- RI
IN-
+ RI
IN+
To Battery
Cs
_
VO+
VO-
+
RF
SHUTDOWN
negative channels equally and cancels at the
differential output. However, removing the bypass
capacitor slightly worsens power supply rejection
ratio (kSVR), but a slight decrease of kSVR may be
acceptable when an additional component can be
eliminated (see Figure 17).
Better RF-immunity: GSM handsets save power
by turning on and shutting off the RF transmitter at
a rate of 217 Hz. The transmitted signal is
picked-up on input and output traces. The fully
differential amplifier cancels the signal much
better than the typical audio amplifier.
GND
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 28. Typical Differential Input Application Schematic
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VDD
RF
CI
IN
+
RI
IN-
RI
IN+
CI
To Battery
Cs
_
VO+
VO-
+
RF
GND
SHUTDOWN
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
VDD
RF
CI
RI
IN
RI
CI
To Battery
Cs
IN-
_
VO+
VO-
IN+
+
RF
GND
SHUTDOWN
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 30. Single-Ended Input Application Schematic
Bypass Capacitor (CBYPASS) and Start-Up Time
Selecting Components
Resistors (RF and RI)
The input (RI) and feedback resistors (RF) set the
gain of the amplifier according to Equation 1.
Gain = RF/RI
(1)
RF and RI should range from 1 kΩ to 100 kΩ. Most
graphs were taken with RF = RI = 20 kΩ.
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to keep the performance
optimized.
10
The internal voltage divider at the BYPASS pin of this
device sets a mid-supply voltage for internal
references and sets the output common mode
voltage to VDD/2. Adding a capacitor to this pin filters
any noise into this pin and increases the kSVR.
C(BYPASS)also determines the rise time of VO+ and VOwhen the device is taken out of shutdown. The larger
the capacitor, the slower the rise time. Although the
output rise time depends on the bypass capacitor
value, the device passes audio 4 µs after taken out of
shutdown and the gain is slowly ramped up based on
C(BYPASS).
To minimize pops and clicks, design the circuit so the
impedance (resistance and capacitance) detected by
both inputs, IN+ and IN-, is equal.
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Input Capacitor (CI)
Decoupling Capacitor (CS)
The TPA6203A1 does not require input coupling
capacitors if using a differential input source that is
biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance
or better gain-setting resistors if not using input
coupling capacitors.
The TPA6203A1 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead
lengths between the amplifier and the speaker. For
higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series- resistance
(ESR) ceramic capacitor, typically 0.1 µF to 1 µF,
placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise
signals, a 10-µF or greater capacitor placed near the
audio power amplifier also helps, but is not required
in most applications because of the high PSRR of this
device.
In the single-ended input application an input
capacitor, CI, is required to allow the amplifier to bias
the input signal to the proper dc level. In this case, CI
and RI form a high-pass filter with the corner
frequency determined in Equation 2.
1
fc +
2pR C
I I
(2)
–3 dB
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent
value of this resistance the more the real capacitor
behaves like an ideal capacitor.
fc
The value of CI is important to consider as it directly
affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10 kΩ and
the specification calls for a flat bass response down
to 100 Hz. Equation 2 is reconfigured as Equation 3.
1
C +
I
2pR f c
I
(3)
In this example, CI is 0.16 µF, so one would likely
choose a value in the range of 0.22 µF to 0.47 µF. A
further consideration for this capacitor is the leakage
path from the input source through the input network
(RI, CI) and the feedback resistor (RF) to the load.
This leakage current creates a dc offset voltage at the
input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason, a
ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications,
as the dc level there is held at VDD/2, which is likely
higher than the source dc level. It is important to
confirm the capacitor polarity in the application.
DIFFERENTIAL OUTPUT VERSUS
SINGLE-ENDED OUTPUT
Figure 31 shows a Class-AB audio power amplifier
(APA) in a fully differential configuration. The
TPA6203A1 amplifier has differential outputs driving
both ends of the load. There are several potential
benefits to this differential drive configuration, but
initially consider power to the load. The differential
drive to the speaker means that as one side is
slewing up, the other side is slewing down, and vice
versa. This in effect doubles the voltage swing on the
load as compared to a ground referenced load.
Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from
the same supply rail and load impedance (see
Equation 4).
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V
V (rms) +
V
Power +
O(PP)
2 Ǹ2
2
(rms)
R
L
(4)
VDD
VO(PP)
RL
low-frequency performance of the system. This
frequency-limiting effect is due to the high pass filter
network created with the speaker impedance and the
coupling capacitance and is calculated with
Equation 5.
1
fc +
2pR C
L C
(5)
For example, a 68-µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which
eliminates the need for the blocking capacitors.
Low-frequency performance is then limited only by
the input network and speaker response. Cost and
PCB space are also minimized by eliminating the
bulky coupling capacitor.
VDD
2x VO(PP)
VDD
VO(PP)
CC
RL
–VO(PP)
Figure 31. Differential Output Configuration
In a typical wireless handset operating at 3.6 V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 200
mW to 800 mW. In sound power that is a 6-dB
improvement—which is loudness that can be heard.
In addition to increased power there are frequency
response concerns. Consider the single-supply SE
configuration shown in Figure 32. A coupling
capacitor is required to block the dc offset voltage
from reaching the load. This capacitor can be quite
large (approximately 33 µF to 1000 µF) so it tends to
be expensive, heavy, occupy valuable PCB area, and
have
the
additional
drawback
of
limiting
12
VO(PP)
–3 dB
fc
Figure 32. Single-Ended Output and Frequency
Response
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the
BTL configuration produces 4× the output power of
the SE configuration.
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FULLY DIFFERENTIAL AMPLIFIER
EFFICIENCY AND THERMAL INFORMATION
VO
Class-AB amplifiers are inefficient. The primary cause
of these inefficiencies is voltage drop across the
output stage transistors. There are two components
of the internal voltage drop. One is the headroom or
dc voltage drop that varies inversely to output power.
The second component is due to the sinewave nature
of the output. The total voltage drop can be
calculated by subtracting the RMS value of the output
voltage from VDD. The internal voltage drop multiplied
by the average value of the supply current, IDD(avg),
determines the internal power dissipation of the
amplifier.
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the
power supply to the power delivered to the load. To
accurately calculate the RMS and average values of
power in the load and in the amplifier, the current and
voltage waveform shapes must first be understood
(see Figure 33).
P
Efficiency of a BTL amplifier +
P
V(LRMS)
IDD
IDD(avg)
Figure 33. Voltage and Current Waveforms for
BTL Amplifiers
Although the voltages and currents for SE and BTL
are sinusoidal in the load, currents from the supply
are very different between SE and BTL
configurations. In an SE application the current
waveform is a half-wave rectified shape, whereas in
BTL it is a full-wave rectified waveform. This means
RMS conversion factors are different. Keep in mind
that for most of the waveform both the push and pull
transistors are not on at the same time, which
supports the fact that each amplifier in the BTL
device only draws current from the supply for half the
waveform. The following equations are the basis for
calculating amplifier efficiency.
L
SUP
where:
2
V rms 2
V
V
P + L
, and V
+ P , therefore, P + P
L
LRMS
L
Ǹ
R
2R
2
L
L
1
and P SUP + VDD I DDavg and I DDavg + p
ŕ
p V
P sin(t) dt + 1
p
R
0
L
2V
P
P [cos(t)] p +
0
pR
R
L
L
V
Therefore,
2V
V
DD P
pR
L
substituting PL and PSUP into equation 6,
P
SUP
+
2
Efficiency of a BTL amplifier +
where:
V
P
+
VP
2 RL
2 V DD V P
p RL
Ǹ2 PL RL
+
p VP
4 VDD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the
power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(6)
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Therefore,
Θ
p
h BTL +
Ǹ2 PL RL
4V
DD
(7)
Table 2. Efficiency and Maximum Ambient
Temperature vs Output Power in 5-V 8-Ω BTL
Systems
Output
Power
(W)
Efficiency
(%)
Internal
Dissipation
(W)
Power
From
Supply
(W)
Max
Ambient
Temperature
(°C)
0.25
31.4
0.55
0.75
62
0.50
44.4
0.62
1.12
54
1.00
62.8
0.59
1.59
58
1.25
70.2
0.53
1.78
65
+
1
1
+
+ 113°CńW
0.0088
Derating Factor
(9)
Given θJA, the maximum allowable junction
temperature, and the maximum internal dissipation,
the maximum ambient temperature can be calculated
with the following equation. The maximum
recommended
junction
temperature
for
the
TPA6203A1 is 125°C.
T A Max + T J Max * ΘJA P Dmax
+ 125 * 113(0.634) + 53.3°C
(10)
Equation 10 shows that the maximum ambient
temperature is 53.3°C at maximum power dissipation
with a 5-V supply.
Table 2 employs Equation 7 to calculate efficiencies
for four different output power levels. Note that the
efficiency of the amplifier is quite low for lower power
levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less
than in the half power range. Calculating the
efficiency for a specific system is the key to proper
power supply design. For a 1.25-W audio system with
8-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 1.8 W.
A final point to remember about Class-AB amplifiers
is how to manipulate the terms in the efficiency
equation to the utmost advantage when possible.
Note that in Equation 7, VDD is in the denominator.
This indicates that as VDD goes down, efficiency goes
up.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential
output application:
2 V2
DD
P D max +
p 2 RL
(8)
PDmax for a 5-V, 8-Ω system is 634 mW.
The maximum ambient temperature depends on the
heat sinking ability of the PCB system. The derating
factor for the 2 mm x 2 mm Microstar Junior™
package is shown in the dissipation rating table.
Converting this to θJA:
14
JA
Table 2 shows that for most applications no airflow is
required to keep junction temperatures in the
specified range. The TPA6203A1 is designed with
thermal protection that turns the device off when the
junction temperature surpasses 150°C to prevent
damage to the IC. Also, using more resistive than 8-Ω
speakers dramatically increases the thermal
performance by reducing the output current.
PCB LAYOUT
In making the pad size for the BGA balls, it is
recommended that the layout use soldermask-defined (SMD) land. With this method, the
copper pad is made larger than the desired land area,
and the opening size is defined by the opening in the
solder mask material. The advantages normally
associated with this technique include more closely
controlled size and better copper adhesion to the
laminate. Increased copper also increases the
thermal performance of the IC. Better size control is
the result of photo imaging the stencils for masks.
Small plated vias should be placed near the center
ball connecting ball B2 to the ground plane. Added
plated vias and ground plane act as a heatsink and
increase the thermal performance of the device.
Figure 34 shows the appropriate diameters for a 2
mm X 2 mm MicroStar Junior™ BGA layout.
It is very important to keep the TPA6203A1 external
components very close to the TPA6203A1 to limit
noise pickup. The TPA6203A1 evaluation module
(EVM) layout is shown in the next section as a layout
example.
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0.38 mm
0.25 mm
0.28 mm
C1
B1
C2
B2
C3
B3
A1
VIAS to Ground Plane
A3
Solder Mask
Paste Mask (Stencil)
Copper Trace
Figure 34. MicroStar Junior™ BGA Recommended Layout
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8-Pin QFN (DRB) Layout
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste
should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the
package.
0.7 mm
0.33 mm plugged vias (5 places)
1.4 mm
0.38 mm
0.65 mm
1.95 mm
Solder Mask: 1.4 mm x 1.85 mm centered in package
Make solder paste a hatch pattern to fill 50%
3.3 mm
Figure 35. TPA6203A1 8-Pin QFN (DRB) Board Layout (Top View)
16
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA00194DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AAII
TPA6203A1DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AAII
TPA6203A1DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AAII
TPA6203A1DRB
ACTIVE
SON
DRB
8
121
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AAJI
TPA6203A1DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AAJI
TPA6203A1ZQVR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQV
8
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
-40 to 85
AAEI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPA6203A1DGNR
HVSSOP
DGN
8
2500
330.0
12.4
TPA6203A1DGNR
HVSSOP
DGN
8
2500
330.0
TPA6203A1DRBR
SON
DRB
8
3000
330.0
W
Pin1
(mm) Quadrant
5.3
3.4
1.4
8.0
12.0
Q1
12.4
5.3
3.4
1.4
8.0
12.0
Q1
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPA6203A1ZQVR
BGA MI
CROSTA
R JUNI
OR
ZQV
8
2500
330.0
8.4
2.3
2.3
1.4
4.0
8.0
Q1
TPA6203A1ZQVR
BGA MI
CROSTA
R JUNI
OR
ZQV
8
2500
330.0
8.4
2.3
2.3
1.4
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA6203A1DGNR
HVSSOP
DGN
8
2500
364.0
364.0
27.0
TPA6203A1DGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
TPA6203A1DRBR
SON
DRB
8
3000
367.0
367.0
35.0
TPA6203A1ZQVR
BGA MICROSTAR
JUNIOR
ZQV
8
2500
338.1
338.1
20.6
TPA6203A1ZQVR
BGA MICROSTAR
JUNIOR
ZQV
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.5 0.1
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
(0.65)
8X
0.37
0.25
0.1
0.05
C A B
C
0.5
0.3
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31) 1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.23)
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
8X (0.31)
4X
(0.725)
8
1
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2019, Texas Instruments Incorporated
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