Texas Instruments | 2.5-W Mono Filter-Free Class-D Audio Power Amplifier | Datasheet | Texas Instruments 2.5-W Mono Filter-Free Class-D Audio Power Amplifier Datasheet

Texas Instruments 2.5-W Mono Filter-Free Class-D Audio Power Amplifier Datasheet
TPA2031D1
www.ti.com........................................................................................................................................................................................................ SLOS546 – MAY 2008
2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
• Pin-to-Pin Compatibility with TPA2010D1
• 32 ms Start-up Time Eliminates CODEC
Click/Pop noise
• Maximum Battery Life and Minimum Heat
– Efficiency With an 8-Ω Speaker:
– 88% at 400 mW
– 2.8-mA Quiescent Current
– 0.5-µA Shutdown Current
• Only Three External Components
– Optimized PWM Output Stage Eliminates
LC Output Filter
– Improved PSRR (–75 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) Eliminates Need for
a Voltage Regulator
– Fully Differential Design Reduces RF
Rectification and Eliminates Bypass
Capacitor
– Improved CMRR Eliminates Two Input
Coupling Capacitors
• Wafer Chip Scale Packaging (WCSP)
– NanoFree™ (YZF)
•
1
2
Ideal for Wireless or Cellular Handsets and
PDAs
DESCRIPTION
The TPA2031D1 is a 2.5-W high efficiency filter-free
class-D audio power amplifier in a 1,45 mm × 1,45
mm wafer chip scale package (WCSP) that requires
only three external components.
Features like 88% efficiency, –75-dB PSRR,
improved RF-rectification immunity, and 8 mm2 total
PCB area make the TPA2031D1 class-D amp ideal
for cellular handsets. 32 ms start-up time allows the
TPA2031D1
to
share
the
same
GPIO
enable/shutdown control as the CODEC without
passing through the CODEC turn-on pop.
In cellular handsets, the earpiece, speaker phone,
and melody ringer can each be driven by the
TPA2031D1. The TPA2031D1 allows independent
gain while summing signals from separate sources,
and has a low 36 µV noise floor, A-weighted.
APPLICATION CIRCUIT
To Battery
Internal
Oscillator
+
RI
Differential
Input
-
RI
VDD
CS
IN_
PWM
9-BALL
WAFER CHIP SCALE
YZF PACKAGE
TPA2031D1 DIMENSIONS
(TOP VIEW OF PCB)
VO+
HBridge
VO-
+
1,55 mm
1,40 mm
IN+
IN+
GND
VO-
A1
A2
A3
VDD
PVDD
GND
B1
B2
B3
GND
SHUTDOWN
Bias
Circuitry
INTPA2031D1
C1
SHUTDOWN VO+
C2
C3
1,55 mm
1,40 mm
Note: Pin A1 is marked with a “0” for
Pb-free (YZF).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPA2031D1
SLOS546 – MAY 2008........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
TA
PACKAGE
–40°C to 85°C
Wafer chip scale packaging – Lead free (YZF)
PART NUMBER
TPA2031D1YZF
SYMBOL
(1)
CEI
The YZF package is only available taped and reeled. Add the suffix R to the end of the part number for a reel of 3000 (e.g.,
TPA2031D1YZFR); or, add the suffix T for a reel of 250 (e.g., TPA2031D1YZFT).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPA2031D1
VDD
Supply voltage
VI
Input voltage
In active mode
–0.3 V to 6 V
In SHUTDOWN mode
–0.3 V to 7 V
–0.3 V to VDD + 0.3 V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature
–40°C to 85°C
TJ
Operating junction temperature
–40°C to 150°C
Tstg
Storage temperature
–65°C to 150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these are any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VDD
Supply voltage
2.5
5.5
VIH
High-level input voltage
SHUTDOWN
V
1.3
VDD
V
VIL
Low-level input voltage
SHUTDOWN
RI
Input resistor
Gain ≤ 20 V/V (26 dB)
0
0.35
VIC
Common mode input voltage range VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB
0.5
VDD–0.8
V
TA
Operating free-air temperature
–40
85
°C
15
V
kΩ
PACKAGE DISSIPATION RATINGS
(1)
2
PACKAGE
DERATING FACTOR (1)
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
YZF
7.8 mW/°C
975 mW
624 mW
507 mW
Derating factor measured with High-K board.
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ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
1
25
mV
VDD = 2.5 V to 5.5 V
–75
–55
dB
Common mode rejection ratio
VDD = 2.5 V to 5.5 V, VIC = VDD/2 to 0.5 V,
VIC = VDD/2 to VDD –0.8 V
–68
–49
dB
|IIH|
High-level input current
VDD = 5.5 V, VI = 5.8 V
100
µA
|IIL|
Low-level input current
VDD = 5.5 V, VI = –0.3 V
5
µA
|VOS|
Output offset voltage
(measured differentially)
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
PSRR
Power supply rejection ratio
CMRR
I(Q)
Quiescent current
I(SD)
Shutdown current
rDS(on)
f(sw)
Static drain-source on-state
resistance
MIN
VDD = 5.5 V, no load
3.4
VDD = 3.6 V, no load
2.8
VDD = 2.5 V, no load
2.2
3.2
V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V
0.5
2
VDD = 2.5 V
700
VDD = 3.6 V
500
VDD = 5.5 V
400
4.9
mA
µA
mΩ
Output impedance in SHUTDOWN
V(SHUTDOWN) = 0.4 V
>1
Switching frequency
VDD = 2.5 V to 5.5 V
200
250
300
Gain
VDD = 2.5 V to 5.5 V
285 kW
RI
300 kW
RI
315 kW
RI
Resistance from shutdown to GND
UNIT
kΩ
300
kHz
V
V
kΩ
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDD = 5 V
THD + N = 10%, f = 1 kHz, RL = 4 Ω
THD + N = 1%, f = 1 kHz, RL = 4 Ω
PO
Output power
THD + N = 10%, f = 1 kHz, RL = 8 Ω
THD + N = 1%, f = 1 kHz, RL = 8 Ω
Total harmonic distortion plus
noise
VDD = 3.6 V
1.3
VDD = 2.5 V
0.52
VDD = 5 V
2.08
VDD = 3.6 V
1.06
VDD = 2.5 V
0.42
VDD = 5 V
1.45
VDD = 3.6 V
0.73
VDD = 2.5 V
0.33
VDD = 5 V
1.19
VDD = 3.6 V
0.59
0.18%
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz
0.19%
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz
0.20%
f = 217 Hz,
V(RIPPLE) = 200 mVpp
kSVR
Supply ripple rejection ratio
SNR
Signal-to-noise ratio
VDD = 5 V, PO = 1 W, RL = 8 Ω
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with CI = 2 µF
No weighting
48
A weighting
36
CMRR
Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
f = 217 Hz
–63
ZI
Input impedance
142
VDD = 3.6 V
W
W
W
W
0.26
VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz
VDD = 3.6 V, Inputs ac-grounded
with CI = 2 µF
Start-up time from shutdown
–67
dB
97
dB
150
µVRMS
dB
158
32
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UNIT
2.5
VDD = 2.5 V
THD+N
TYP MAX
kΩ
ms
3
TPA2031D1
SLOS546 – MAY 2008........................................................................................................................................................................................................ www.ti.com
Terminal Functions
TERMINAL
NAME
I/O
YZF
DESCRIPTION
IN–
C1
I
Negative differential input
IN+
A1
I
Positive differential input
VDD
B1
I
Power supply
VO+
C3
O
Positive BTL output
GND
A2, B3
I
High-current ground
VO-
A3
O
Negative BTL output
SHUTDOWN
C2
I
Shutdown terminal (active low logic)
PVDD
B2
I
Power supply
FUNCTIONAL BLOCK DIAGRAM
*Gain =
150 kΩ
RI
*Gain = 2 V/V
B1, B2
VDD
150 kΩ
IN- C1
_
+
VDD
+
_
Deglitch
Logic
Gate
Drive
+
_
Deglitch
Logic
Gate
Drive
A3
VO-
_
+
_
+
+
_
IN+ A1
150 kΩ
C2
SHUTDOWN
TTL
SD Input
Buffer
300 kΩ
Notes:
* Total gain =
4
2x
Biases
and
References
Ramp
Generator
Startup
Protection
Logic
C3
VO+
OC
Detect
A2, B3
GND
150 kΩ
RI
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Efficiency
vs Output power
1, 2
Power dissipation
vs Output power
3, 4
Supply current
vs Output power
5, 6
I(Q)
Quiescent current
vs Supply voltage
7
I(SD)
Shutdown current
vs Shutdown voltage
8
PD
PO
Output power
THD+N
Total harmonic distortion plus noise
vs Supply voltage
9
vs Load resistance
10, 11
vs Output power
12, 13
vs Frequency
14, 15, 16, 17
vs Common-mode input voltage
KSVR
Supply voltage rejection ratio
vs Frequency
GSM power supply rejection
KSVR
Supply voltage rejection ratio
CMRR
Common-mode rejection ratio
18
Voltage
19, 20, 21
vs Time
22
vs Frequency
23
vs Common-mode input voltage
24
vs Frequency
25
vs Common-mode input voltage
26
vs Start-up time
27
TEST SET-UP FOR GRAPHS
CI
TPA2031D1
RI
+
Measurement
Output
-
IN+
CI
OUT+
Load
RI
INVDD
+
OUT-
30 kHz
Low Pass
Filter
+
Measurement
Input
-
GND
1 µF
VDD
-
Notes:
(1) C I was Shorted for any Common-Mode input voltage measurement
(2) A 33- µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
. An RC low pass filter (100 Ω, 47 nF) is
used on each output for the data sheet graphs.
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5
TPA2031D1
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EFFICIENCY
vs
OUTPUT POWER
90
90
80
VDD = 5 V,
RL = 8 Ω, 33 µH
70
60
50
40
Class AB.
VDD = 5 V,
RL = 8 Ω
30
20
1.4
70
Efficiency − %
VDD = 2.5 V,
RL = 8 Ω, 33 µH
VDD = 3.6 V,
RL = 4 Ω, 33 µH
VDD = 2.5 V,
RL = 4 Ω, 33 µH
50
40
Class AB.
VDD = 5 V,
RL = 4 Ω
20
10
0
0.2
0.4
0.6
1
0.8
0
1.2
0.2
VDD = 5 V, RL = 8 Ω
0
1.2 1.4 1.6 1.8 2
0
0.5
1
1.5
2
Figure 2.
Figure 3.
POWER DISSIPATION
vs
OUTPUT POWER
SUPPLY CURRENT
vs
OUTPUT POWER
SUPPLY CURRENT
vs
OUTPUT POWER
Class-AB 3.6 V, 8 Ω
0.4
0.3
VDD = 3.6 V, RL = 4 Ω
0.2
0.1
VDD = 3.6 V,
RL = 8 Ω, 33 µH
0.2
0.4
0.6
0.8
1
400
VDD = 2.5 V
300
200
100
VDD = 5 V,
VDD = 3.6 V
200
150
100
VDD = 2.5 V
50
VDD = 5 V
0
0.5
1
1.5
2
0
2.5
0.2
0.4
0.6
0.8
1.2
1
PO − Output Power − W
PO − Output Power − W
PO − Output Power − W
Figure 4.
Figure 5.
Figure 6.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
I (SD) − Shutdown Current − µ A
4.5
RL = 8 Ω, (resistive)
RL = 8 Ω,
33 µH
3.5
3
2.5
1.5
VDD = 5 V
1
VDD = 3.6 V
VDD = 2.5 V
0.5
4.5
5
5.5
VDD − Supply Voltage − V
Figure 7.
VDD = 5 V
2
VDD = 3.6 V
1.5
VDD = 2.5 V
1
0.5
0
0
4
PO at 10% THD
Gain = 2 V/V
f = 1 kHz
2.5
No Load
3.5
1.4
3
2
5
3
RL = 8 Ω, 33 µH
0
0
1.2
2.5
250
VDD = 3.6 V
I DD − Supply Current − mA
0.5
300
RL = 4 Ω, 33 µH
500
Class-AB 3.6 V, 4 Ω
I DD − Supply Current − mA
P D − Power Dissipation − W
VDD = 5 V, RL = 4 Ω,
0.4
Figure 1.
0
I DD − Supply Current − mA
0.6
PO − Output Power − W
0.6
2
2.5
Class-AB 5 V, 8 Ω
0.8
PO − Output Power − W
600
4
1
PO − Output Power − W
0.7
0
0.2 0.4 0.6 0.8 1
PO − Output Power − W
0 0
Class-AB 5 V, 4 Ω
1.2
VDD = 5 V,
RL = 4 Ω,
33 µH
60
30
10
6
POWER DISSIPATION
vs
OUTPUT POWER
P D − Power Dissipation − W
100
80
Efficiency − %
EFFICIENCY
vs
OUTPUT POWER
0
0.1
0.2
0.3
0.4
Shutdown Voltage − V
Figure 8.
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0.5
4
8
12
16
20
24
28
32
RL − Load Resistance − Ω
Figure 9.
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3
2.5
VDD = 5 V
PO at 1% THD
Gain = 2 V/V
f = 1 kHz
1.5
VDD = 3.6 V
1
Gain = 2 V/V
f = 1 kHz
2.5
PO − Output Power − W
VDD = 2.5 V
0.5
RL = 4 Ω, 10% THD
2
RL = 4 Ω, 1% THD
1.5
1
RL = 8 Ω,10% THD
0.5
0
2.5
0
4
8
12
16
20
24
RL − Load Resistance − Ω
28
32
RL = 8 Ω,1% THD
3
3.5
4
4.5
VCC − Supply Voltage − V
5
20
RL = 4 Ω,
f = 1 kHz,
Gain = 2 V/V
10
5
2.5 V
3V
2
3.6 V
1
5V
0.5
0.2
0.1
20m
50m 100m 200m 500m 1
PO − Output Power − W
2
3
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
20
RL = 8 Ω,
f = 1 kHz,
Gain = 2 V/V
10
5
2.5 V
3V
3.6 V
2
5V
1
0.5
0.2
0.1
5m 10m 20m 50m 100m 200m 500m 1
2
THD+N − Total Harmonic Distortion + Noise − %
Figure 10.
10
VDD = 5 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
5
2
PO = 50 mW
PO = 250 mW
1
0.5
PO = 1W
0.2
0.1
0.05
0.02
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
5
2
PO = 25 mW
PO = 125 mW
1
0.5
PO = 500 mW
0.2
0.1
0.05
0.02
0.01
0.005
0.01
20
PO − Output Power − W
10
THD+N − Total Harmonic Distortion + Noise − %
PO − Output Power − W
2
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
THD+N − Total Harmonic Distortion + Noise − %
OUTPUT POWER
vs
LOAD RESISTANCE
50 100 200
500 1k
2k
5k 10k 20k
20
50 100 200 500 1k 2k
f − Frequency − Hz
5k 10k 20k
Figure 15.
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION +
NOISE
vs
COMMON MODE INPUT VOLTAGE
10
VDD = 2.5 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
5
2
PO = 15 mW
PO = 75 mW
1
0.5
PO = 200 mW
0.2
0.1
0.05
0.02
0.01
20
50 100 200 500 1k 2k
5k 10k 20k
f − Frequency − Hz
Figure 16.
10
PO = 250 mW
CI = 2 µF
RL = 4 Ω
Gain = 2 V/V
5
2
1
VDD = 3.6 V
VDD = 3 V
0.5
0.2
VDD = 2.5 V
0.1
0.05
0.02
0.01
VDD = 4 V
20
50 100 200
VDD = 5 V
500 1k 2k
5k 10k 20k
f − Frequency − Hz
Figure 17.
THD+N − Total Harmonic Distortion + Noise − %
Figure 14.
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
f − Frequency − Hz
Figure 13.
10
f = 1 kHz
PO = 200 mW
VDD = 2.5 V
1
VDD = 5 V
VDD = 3.6 V
0.1
0
0.5
1
1.5 2
2.5
3
3.5
4 4.5
Figure 18.
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VIC − Common Mode Input Voltage − V
7
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SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
−30
Inputs ac-grounded
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
−50
VDD = 2. 5 V
VDD = 3.6 V
−60
−70
−80
−30
Inputs ac-grounded
CI = 2 µF
RL = 4 Ω
Gain = 2 V/V
−40
VDD = 2.5 V
−50
−60
VDD = 3.6 V
−70
−80
100
1k
VDD = 5 V
−60
−70
VDD = 3.6 V
−80
VDD = 2.5 V
−90
20
−50
VDD = 5 V
VDD = 5 V
−90
Inputs floating
RL = 8 Ω
−40
−90
20
10 k 20 k
100
1k
20
10 k 20 k
100
Figure 19.
1k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 20.
GSM POWER SUPPLY REJECTION
vs
TIME
GSM POWER SUPPLY REJECTION
vs
FREQUENCY
0
C1 − High
3.6 V
−50
C1 − Amp
512 mV
−100
VO − Output Voltage − dBV
VDD
200 mV/div
C1 − Duty
12%
VOUT
20 mV/div
0
VDD Shown in Figure 22
CI = 2 µF,
Inputs ac-grounded
Gain = 2V/V
−50
−100
−150
0
400
t − Time − 2 ms/div
800
−40
VDD = 3.6 V
VDD = 2. 5 V
−50
VDD = 5 V
−60
−70
−80
0
0.5
1
1.5
2
2.5
3
3.5 4
4.5 5
DC Common Mode Voltage − V
Figure 24.
8
2000
−50
VIC = 200 mVPP
RL = 8 Ω
Gain = 2 V/V
−55
−60
VDD = 3.6 V
−65
−70
−75
20
100
1k
f − Frequency − Hz
10 k 20 k
Figure 25.
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COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
CMRR − Common Mode Rejection Ratio − dB
−30
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common Mode Rejection Ratio − dB
Sopply Ripple Rejection Ratio − dB
−20
1600
Figure 23.
SUPPLY RIPPLE REJECTION RATIO
vs
DC COMMON MODE VOLTAGE
0
1200
f − Frequency − Hz
Figure 22.
−10
−150
V DD − Supply Voltage − dBV
−40
Sopply Ripple Rejection Ratio − dB
Sopply Ripple Rejection Ratio − dB
−30
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
Sopply Ripple Rejection Ratio − dB
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
−10
−20
−30
−40
VDD = 3.6 V
VDD = 2.5 V
−50
−60
−70
−80
VDD = 5 V,
Gain = 2
−90
−100
0
1
2
3
4
5
VIC − Common Mode Input Voltage − V
Figure 26.
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VOLTAGE
vs
START-UP TIME
4
SHUTDOWN
3
V − Voltage − V
2
1
0
Output
−1
−2
−3
−4
0.00
VDD = 3.6 V
RL = 8 Ω + 33 µH
PO = 500 mW
f = 200 Hz
0.02
0.04
0.06
0.08
0.10
t − Time − s
Figure 27.
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
The TPA2031D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless
of the common-mode voltage at the input. The fully differential TPA2031D1 can still be used with a single-ended
input; however, the TPA2031D1 should be used with differential inputs when in a noisy environment, like a
wireless handset, to ensure maximum noise rejection.
Advantages of Fully Differential Amplifiers
• Input-coupling capacitors not required:
– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply voltage. For
example, if a codec has a mid-supply voltage lower than the mid-supply voltage of the TPA2031D1, the
common-mode feedback circuit adjusts, and the TPA2031D1 outputs are still biased at mid-supply voltage
of the TPA2031D1. The inputs of the TPA2031D1 can be biased from 0.5 V to VDD –0.8 V. If the inputs
are biased outside of that range, input-coupling capacitors are required.
• Mid-supply bypass capacitor, C(BYPASS), not required:
– The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
• Better RF-immunity:
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal
much better than the typical audio amplifier.
COMPONENT SELECTION
Figure 28 shows the TPA2031D1 typical schematic with differential inputs and Figure 29 shows the TPA2031D1
with differential inputs and input capacitors, and Figure 30 shows the TPA2031D1 with single-ended inputs.
Differential inputs should be used whenever possible because the single-ended inputs are much more
susceptible to noise.
Table 1. Typical Component Values
(1)
REF DES
VALUE
EIA SIZE
MANUFACTURER
RI
150 kΩ (±0.5%)
0402
Panasonic
PART NUMBER
ERJ2RHD154V
CS
1 µF (+22%, –80%)
0402
Murata
GRP155F50J105Z
CI (1)
3.3 nF (±10%)
0201
Murata
GRP033B10J332K
CI is only needed for single-ended input, or if VICM is not between 0.5 V and VDD–0.8 V. CI = 3.3 nF
(with RI= 150 kΩ) gives a high-pass corner frequency of 321 Hz.
Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to Equation 1.
Gain =
2 × 150 kW æ V ö
ç ÷
RI
èVø
(1)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with
1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2031D1 to limit noise injection on the high-impedance nodes.
10
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For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2031D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
Decoupling Capacitor (CS)
The TPA2031D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1
µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the
TPA2031D1 is very important for the efficiency of the class-D amplifier, because any resistance or inductance in
the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise
signals, a 10 µF or greater capacitor placed near the audio power amplifier would also help, but it is not required
in most applications because of the high PSRR of this device.
Input Capacitors (CI)
The TPA2031D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD –0.8 V (shown in Figure 28). If the input signal is not biased within the recommended
common-mode input range, if needing to use the input as a high pass filter (shown in Figure 29), or if using a
single-ended source (shown in Figure 30), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 2.
fC =
1
(2p ´ RI ´ CI )
(2)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
Equation 3 is reconfigured to solve for the input coupling capacitance.
CI =
1
(2p ´ RI ´ fC )
(3)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
To Battery
Internal
Oscillator
+
RI
IN_
Differential
Input
-
SHUTDOWN
RI
VDD
PWM
HBridge
CS
VO+
VO-
+
IN+
GND
Bias
Circuitry
TPA2031D1
Filter-Free Class D
Figure 28. Typical TPA2031D1 Application Schematic With Differential Input for a Wireless Phone
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CI
Differential
Input
To Battery
Internal
Oscillator
RI
IN_
CI
VDD
PWM
VO+
HBridge
VO-
+
RI
CS
IN+
GND
Bias
Circuitry
SHUTDOWN
TPA2031D1
Filter-Free Class D
Figure 29. TPA2031D1 Application Schematic With Differential Input and Input Capacitors
TPA2031D1
Figure 30. TPA2031D1 Application Schematic With Single-Ended Input
SUMMING INPUT SIGNALS WITH THE TPA2031D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2031D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input
source can be set independently (see Equation 4 and Equation 5, and Figure 31).
V
V
Gain 1 + O + 2 x 150 kW
V
R
V
I1
I1
(4)
V
V
Gain 2 + O + 2 x 150 kW
V
R
V
I2
I2
(5)
ǒǓ
ǒǓ
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
12
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If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain 1
= 0.1 V/V. The resistor values would be. . .
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
Differential
Input 1
+
RI1
-
RI1
+
RI2
To Battery
Internal
Oscillator
Differential
Input 2
RI2
CS
IN_
-
VDD
PWM
HBridge
VO+
VO-
+
IN+
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 31. Application Schematic With TPA2031D1 Summing Two Differential Inputs
Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 32 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in Equation 8. To assure that each input is balanced, the single-ended input must be
driven by a low-impedance source even if the input is not in use
V
V
Gain 1 + O + 2 x 150 kW
V
R
V
I1
I1
(6)
V
V
Gain 2 + O + 2 x 150 kW
V
R
V
I2
I2
(7)
ǒǓ
ǒǓ
CI2 =
1
(2p RI2 fc2 )
(8)
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set
to gain 2 = 2 V/V, the resistor values would be…
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz...
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C
I2
C
I2
u
1
ǒ2p 150kW 20HzǓ
(9)
u 53 nF
(10)
RI1
Differential
Input 1
Single-Ended
Input 2
RI1
CI2 R
I2
To Battery
Internal
Oscillator
CS
IN_
RI2
VDD
PWM
HBridge
VO+
VO-
+
IN+
CI2
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 32. Application Schematic With TPA2031D1 Summing Differential Input and Single-Ended Input
Signals
Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 11 through Equation 14,
and Figure 33). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN– terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
V
Gain 1 + O + 2 x 150 kW
V
R
V
I1
I1
(11)
V
V
Gain 2 + O + 2 x 150 kW
V
R
V
I2
I2
(12)
1
C +
I1
ǒ2p RI1 f c1Ǔ
(13)
1
C +
I2
ǒ2p RI2 f c2Ǔ
(14)
C +C ) C
P
I1
I2
(15)
R
R
I2
R + I1
P
R ) R
I1
I2
(16)
ǒǓ
ǒǓ
ǒ
14
Ǔ
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Single-Ended
Input 1
Single-Ended
Input 2
CI1 R
I1
To Battery
CI2 R
I2
Internal
Oscillator
CS
IN_
RP
VDD
PWM
VO+
HBridge
VO-
+
IN+
CP
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 33. Application Schematic With TPA2031D1 Summing Two Single-Ended Inputs
BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use non-solder-mask-defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 34 and Table 2 show the appropriate diameters for a
WCSP layout. The TPA2031D1 evaluation module (EVM) layout is shown in the next section as a layout
example.
Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Solder Mask
Thickness
Figure 34. Land Pattern Dimensions
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Table 2. Land Pattern Dimensions
SOLDER PAD
DEFINITIONS
COPPER PAD
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
OPENING
STENCIL
THICKNESS
Non-solder-mask
defined (NSMD)
275 µm
(+0.0, –25 µm)
375 µm
(+0.0, –25 µm)
1 oz max (32 µm)
275 µm x 275 µm Sq.
(rounded corners)
125 µm thick
NOTES:
1. Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
2. Recommend solder paste is Type 3 or Type 4.
3. Best reliability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction in
thermal fatigue performance.
5. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils results in inferior solder paste volume control.
7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
Component Location
Place all the external components very close to the TPA2031D1. The input resistors need to be very close to the
TPA2031D1 input pins so noise does not couple on the high impedance nodes between the input resistors and
the input amplifier of the TPA2031D1. Placing the decoupling capacitor, CS, close to the TPA2031D1 is
important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device
and the capacitor can cause a loss in efficiency.
Trace Width
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB
traces. Figure 35 shows the layout of the TPA2031D1 evaluation module (EVM).
For high current pins (VDD, GND VO+, and VO–) of the TPA2031D1, use 100-µm trace widths at the solder balls
and at least 500-µm PCB traces to ensure proper performance and output power for the device.
For input pins (IN–, IN+, and SHUTDOWN) of the TPA2031D1, use 75-µm to 100-µm trace widths at the solder
balls. IN– and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input
resistors, RIN, as close to the TPA2031D1 as possible is recommended.
16
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75 mm
100 mm
100 mm
100 mm
375 mm
(+0, -25 mm)
275 mm
(+0, -25 mm)
100 mm
Circular Solder Mask Opening
Paste Mask (Stencil)
= Copper Pad Size
75 mm
100 mm
75 mm
Figure 35. Close Up of TPA2031D1 Land Pattern From TPA2031D1 EVM
EFFICIENCY AND THERMAL INFORMATION
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the YZF package is shown in the dissipation rating table. Converting this to θJA:
1
1
q
+
+
+ 128.2°CńW
JA
0.0078
Derating Factor
(17)
Given θJA of 128.2°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.4 W (2.25 W, 4-Ω load, 5-V supply, from Figure 3), the maximum ambient temperature can be
calculated with the following equation.
T Max + T Max * q P
+ 150 * 128.2 (0.4) + 98.72°C
A
J
JA Dmax
(18)
Equation 18 shows that the calculated maximum ambient temperature is 98.7°C at maximum power dissipation
with a 5-V supply and 4-Ω a load, see Figure 3. The TPA2031D1 is designed with thermal protection that turns
the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using
speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current
and increasing the efficiency of the amplifier.
ELIMINATING THE OUTPUT FILTER WITH THE TPA2031D1
This section focuses on why the user can eliminate the output filter with the TPA2031D1.
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Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave that is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore,
the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields
0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 36. Note that even at an average of 0 volts across the load (50% duty cycle), the current to the load is
high causing a high loss and thus causing a high supply current.
OUT+
OUT+5 V
Differential Voltage
Across Load
0V
-5 V
Current
Figure 36. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With no Input
TPA2031D1 Modulation Scheme
The TPA2031D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUT+ and OUT– are now in phase with each other with no input. The duty cycle of OUT+ is greater
than 50% and OUT– is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT–
is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the
switching period greatly reducing the switching current, which reduces any I2R losses in the load.
18
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OUT+
OUTDifferential
Voltage
Across
Load
Output = 0 V
+5 V
0V
-5 V
Current
OUT+
OUTDifferential
Voltage
Output > 0 V
+5 V
0V
Across
Load
-5 V
Current
Figure 37. The TPA2031D1 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VDD and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA2031D1 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker that results in less power
dissipated, which increases efficiency.
Effects of Applying a Square Wave Into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A
250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional to
1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency
is very small. However, damage could occur to the speaker if the voice coil is not designed to handle the
additional power. To size the speaker for added power, the ripple current dissipated in the load needs to be
calculated by subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at
maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the measured
efficiency, ηMEASURED, minus the theoretical efficiency, ηTHEORETICAL.
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P
–P
(at max output power)
SUP SUP THEORETICAL
P
P
P
+ SUP – SUP THEORETICAL (at max output power)
SPKR
P
P
OUT
OUT
P
SPKR
SPKR
+P
+P
ǒ
(19)
(20)
Ǔ
1
1
*
(at max output power)
OUT h MEASURED h THEORETICAL
(21)
R
hTHEORETICAL +
R
L
(at max output power)
) 2r
L
DS(on)
(22)
The maximum efficiency of the TPA2031D1 with a 3.6 V supply and an 8-Ω load is 86% from Equation 22. Using
equation Equation 21 with the efficiency at maximum power (84%), we see that there is an additional 17 mW
dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into
account when choosing the speaker.
When to Use an Output Filter
Design the TPA2031D1 without an output filter if the traces from amplifier to speaker are short. The TPA2031D1
passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less.
Wireless handsets and PDAs are great applications for class-D without a filter.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the
frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE
because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one
with high impedance at high frequencies, but very low impedance at low frequencies.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
Figure 38 and Figure 39 show typical ferrite bead and LC output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 38. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121)
33 µH
OUTP
1 µF
33 µH
OUTN
1 µF
Figure 39. Typical LC Output Filter, Cutoff Frequency of 27 kHz
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PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA2031D1YZFR
DSBGA
YZF
9
3000
180.0
8.4
TPA2031D1YZFT
DSBGA
YZF
9
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.65
1.65
0.81
4.0
8.0
Q1
1.65
1.65
0.81
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2031D1YZFR
DSBGA
YZF
9
3000
182.0
182.0
20.0
TPA2031D1YZFT
DSBGA
YZF
9
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0009
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
BALL TYP
0.35
0.15
0.05 C
1 TYP
SYMM
C
1
TYP
SYMM
B
0.5
TYP
A
9X
0.015
0.35
0.25
C A B
1
2
3
0.5 TYP
4219558/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YZF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
9X ( 0.245)
1
2
3
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.245)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
( 0.245)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219558/A 10/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
9X ( 0.25)
1
2
3
A
(0.5) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 40X
4219558/A 10/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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