Texas Instruments | 50-mW Ultralow-Voltage, Fixed-Gain Stereo Headphone Audio Power Amp (Rev. C) | Datasheet | Texas Instruments 50-mW Ultralow-Voltage, Fixed-Gain Stereo Headphone Audio Power Amp (Rev. C) Datasheet

Texas Instruments 50-mW Ultralow-Voltage, Fixed-Gain Stereo Headphone Audio Power Amp (Rev. C) Datasheet
SLOS331C − AUGUST 2000 − REVISED MARCH 2007
D
D
D
D
D
D
D
D
D
D
D or DGK PACKAGE
(TOP VIEW)
Minimal External Components Required
1.6-V to 3.6-V Supply Voltage Range
50-mW Stereo Output
Low Supply Current . . . 0.75 mA
Low Shutdown Current . . . 50 nA
Gain Set Internally to 2 dB
Pop Reduction Circuitry
Internal Mid-Rail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
− 3-mm y 5-mm MSOP Package (DGN)
− 5-mm y 6-mm SOIC Package (D)
− 2,5-mm y 2,5-mm MicroStar JuniorE BGA
Package (ZQY)
BYPASS
GND
SHUTDOWN
IN2−
1
8
2
7
3
6
4
5
IN1−
VO 1
VDD
VO 2
ZQY PACKAGE
(TOP VIEW)
BYPASS
GND
SHUTDOWN
IN2−
(A1)
(A4)
(B1)
(B4)
(C1)
(C4)
(D1)
(D4)
IN1−
VO 1
VDD
VO 2
GND
description
The TPA6101A2 is a stereo audio power amplifier packaged in an 8-pin SOIC package, an 8-pin MSOP
package, or a 15-ball BGA package, capable of delivering 50 mW of continuous RMS power per channel into
16-Ω loads. Amplifier gain is internally set to 2 dB (inverting) to save board space by eliminating six external
resistors.
The TPA6101A2 is optimized for battery applications because of its low supply current, shutdown current, and
THD+N. To obtain the low-supply-voltage range, the TPA6101A2 biases BYPASS to VDD/4.
When driving a 16-Ω load with 40-mW output power from 3.3 V, THD+N is 0.08% at 1 kHz, and less than 0.2%
across the audio band of 20 Hz to 20 kHz. For 30 mW into 32-Ω loads, the THD+N is reduced to less than 0.06%
at 1 kHz, and is less than 0.3% across the audio band of 20 Hz to 20 kHz.
typical application circuit
VDD
Audio
Input
RF
80 kΩ
RI
IN 1−
80 kΩ
CI
VDD/4
80 kΩ
−
+
VO1
−
+
VO2
VDD
CS
CC
BYPASS
CB
Audio
Input
RI
80 kΩ
IN 2−
CI
From Shutdown
Control Circuit
80 kΩ
SHUTDOWN
RF
80 kΩ
NOTE: All internal resistor
values are ±20%.
CC
Bias
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar BGA is a trademark of Texas Instruments.
Copyright  2007, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
SMALL OUTLINE (D)
MSOP (DGK)
BGA (ZQY)
MSOP
SYMBOLIZATION
BGA
SYMBOLIZATION
−40°C to 85°C
TPA6101A2D
TPA6101A2DGK
TPA6101A2ZQYR
AJM
AAQI
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
A1
I
Tap to voltage divider for internal mid-supply bias supply. BYPASS is set at VDD/4. Connect to a 0.1-µF
to 1-µF low-ESR capacitor for best performance.
2
B1
–
GND is the ground connection.
8
A4
I
IN1− is the inverting input for channel 1.
IN2−
4
D1
I
IN2− is the inverting input for channel 2.
SHUTDOWN
3
C1
I
Active-low input. When held low, the device is placed in a low-supply-current mode.
VDD
VO1
6
C4
–
7
B4
O
VDD is the supply voltage terminal.
VO1 is the audio output for channel 1.
VO2
5
D4
O
VO2 is the audio output for channel 2.
NAME
D,
DGK
ZQY
BYPASS
1
GND
IN1−
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
710 mW
5.68 mW/°C
454 mW
369 mW
DGK
469 mW
3.75 mW/°C
300 mW
244 mW
ZQY
2W
17.1 mW/°C
1.28 W
1.04 W
recommended operating conditions
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply voltage, VDD
MIN
MAX
1.6
3.6
0.6 VDD
High-level input voltage, VIH (SHUTDOWN)
Low-level input voltage, VIL (SHUTDOWN)
Operating free-air temperature, TA
2
–40
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• DALLAS, TEXAS 75265
UNIT
V
V
0.25 VDD
V
85
°C
dc electrical characteristics at TA = 25°C, VDD = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOO
PSRR
Output offset voltage
Power supply rejection ratio
AV = 2 dB
VDD = 3 V to 3.6 V
IDD
Supply current
SHUTDOWN = 3.6 V
IDD(SD)
Supply current in SHUTDOWN mode
SHUTDOWN = 0 V
|IIH|
High-level input current (SHUTDOWN)
|IIL|
Low-level input current (SHUTDOWN)
VDD = 3.6 V, VI = VDD
VDD = 3.6 V, VI = 0 V
ZI
Input impedance
MIN
TYP
MAX
5
40
72
UNIT
mV
dB
0.75
1.5
mA
50
250
nA
1
µA
1
80
µA
kΩ
ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 16 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G
Gain
2
dB
PO
THD+N
Output power (each channel)
THD ≤ 0.1%,
f = 1 kHz
Total harmonic distortion + noise
20 Hz−20 kHz
BOM
kSVR
Maximum output power BW
PO = 45 mW,
THD < 0.5%
50
mW
> 20
kHz
Supply ripple rejection ratio
f = 1 kHz
47
dB
SNR
Signal-to-noise ratio
PO = 50 mW
86
dB
Vn
Noise output voltage (no-noise weighting filter)
45
µV(rms)
0.4%
ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 32 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G
Gain
PO
THD+N
Output power (each channel)
THD ≤ 0.1%,
f = 1 kHz
Total harmonic distortion + noise
Maximum output power BW
PO = 30 mW,
THD < 0.4%
20 Hz−20 kHz
BOM
kSVR
> 20
kHz
Supply ripple rejection ratio
f = 1 kHz
47
dB
SNR
Signal-to-noise ratio
PO = 30 mW
86
dB
Vn
Noise output voltage (no-noise weighting filter)
50
µV(rms)
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2
dB
35
mW
0.4%
3
dc electrical characteristics at TA = 25°C, VDD = 1.6 V (unless otherwise noted)
PARAMETER
VOO
PSRR
Output offset voltage
TEST CONDITIONS
MIN
TYP
MAX
5
40
UNIT
Power supply rejection ratio
AV = 2 dB
VDD = 1.4 V to 1.8 V
80
mV
IDD
Supply current
SHUTDOWN = 1.6 V
0.65
1.2
IDD(SD)
|IIH|
Supply current in SHUTDOWN mode
SHUTDOWN = 0 V
50
250
nA
High-level input current (SHUTDOWN)
1
µA
|IIL|
Low-level input current (SHUTDOWN)
VDD = 1.6 V, VI = VDD
VDD = 1.6 V, VI = 0 V
1
µA
ZI
Input impedance
dB
80
mA
kΩ
ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 16 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G
Gain
2
PO
THD+N
Output power (each channel)
THD ≤ 0.5%,
f = 1 kHz
dB
10
mW
Total harmonic distortion + noise
Maximum output power BW
PO = 9.5 mW,
THD < 1%
20 Hz−20 kHz
BOM
kSVR
> 20
kHz
Supply ripple rejection ratio
f = 1 kHz
47
dB
SNR
Signal-to-noise ratio
PO = 10 mW
82
dB
Vn
Noise output voltage (no-noise weighting filter)
32
µV(rms)
0.06%
ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 32 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G
Gain
2
dB
PO
THD+N
Output power (each channel)
THD ≤ 0.5%,
f = 1 kHz
Total harmonic distortion + noise
20 Hz−20 kHz
BOM
kSVR
Maximum output power BW
PO = 6.5 mW,
THD < 1%
7.5
mW
> 20
kHz
Supply ripple rejection ratio
f = 1 kHz
47
dB
SNR
Signal-to-noise ratio
PO = 7.5 mW
84
dB
Vn
Noise output voltage (no-noise weighting filter)
32
µV(rms)
0.05%
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Frequency
4
vs Output power
2, 4, 6, 8, 10, 12
vs Output voltage
13, 14
vs Load resistance
15, 16
Supply ripple rejection ratio
vs Frequency
17, 18
Output noise voltage
vs Frequency
19, 20
Crosstalk
vs Frequency
21, 22
Closed−loop gain and phase
vs Frequency
23, 24, 25, 26
Supply current
vs Supply voltage
27
Power dissipation
vs Output power
28
THD+N
Total harmonic distortion plus noise
PO
kSVR
Output power
Vn
IDD
PD
1, 3, 5, 7, 9, 11
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• DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
10
VDD = 1.6 V
PO = 9.5 mW
CB = 1 µF
RL = 16 Ω
1
0.1
0.01
0.001
20
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
1k
f − Frequency − Hz
10 k 20 k
10
VDD = 1.6 V
CB = 1 µF
RL = 16 Ω
f = 1 kHz
1
0.1
0.01
0.001
1
5
10
PO − Output Power − mW
Figure 1
Figure 2
10
VDD = 1.6 V
PO = 6.5 mW
CB = 1 µF
RL = 32 Ω
0.1
0.01
0.001
20
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
1
1k
f − Frequency − Hz
40
10 k 20 k
10
VDD = 1.6 V
CB = 1 µF
RL = 32 Ω
f = 1 kHz
1
0.1
0.01
0.001
1
Figure 3
5
10
PO − Output Power − mW
40
Figure 4
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5
TYPICAL CHARACTERISTICS
10
VDD = 1.6 V
PO = 4.5 mW
CB = 1 µF
RL = 50 Ω
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10 k 20 k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10
VDD = 1.6 V
CB = 1 µF
RL = 50 Ω
f = 1 kHz
1
0.1
0.01
0.001
1
5
10
PO − Output Power − mW
Figure 5
Figure 6
10
VDD = 3.3 V
PO = 45 mW
CB = 1 µF
RL = 16 Ω
0.1
0.01
0.001
20
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
1
1k
f − Frequency − Hz
10 k 20 k
10
VDD = 3.3 V
CB = 1 µF
RL = 16 Ω
f = 1 kHz
1
0.1
0.01
0.001
1
Figure 7
6
40
10
PO − Output Power − mW
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
200
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10
VDD = 3.3 V
PO = 30 mW
CB = 1 µF
RL = 32 Ω
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10
VDD = 3.3 V
CB = 1 µF
RL = 32 Ω
f = 1 kHz
1
0.1
0.01
0.001
1
10 k 20 k
10
PO − Output Power − mW
Figure 9
VDD = 3.3 V
PO = 20 mW
CB = 1 µF
RL = 50 Ω
0.1
0.01
0.001
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
10
20
1k
200
Figure 10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
1
100
10 k 20 k
10
VDD = 3.3 V
CB = 1 µF
RL = 50 Ω
f = 1 kHz
1
0.1
0.01
0.001
1
f − Frequency − Hz
Figure 11
10
PO − Output Power − mW
100
200
Figure 12
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• DALLAS, TEXAS 75265
7
TYPICAL CHARACTERISTICS
10
VDD = 1.6 V
RL = 10 kΩ
CB = 1 µF
1
0.1
0.01
0.001
0
0.1
0.2
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT VOLTAGE
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT VOLTAGE
0.3 0.4 0.5 0.6 0.7
VO − Output Voltage − V
0.8
0.9
1
10
VDD = 3.3 V
RL = 10 kΩ
CB = 1 µF
1
0.1
0.01
0.001
0
0.2
Figure 13
1.2
1.4
44
48 50
Figure 14
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
15
150
VDD = 1.6 V
THD+N = 1%
Mode = Stereo
12
VDD = 3.6 V
THD+N = 1%
Mode = Stereo
125
Channel 1
PO− Output Power − mW
PO− Output Power − mW
0.4
0.6
0.8
1
VO − Output Voltage − V
9
Channel 2
6
100
Channel 1
75
50
Channel 2
3
25
0
16
20
24
28
32
36
40
RL − Load Resistance − Ω
44
48 50
0
16
20
Figure 15
8
24
28
32
36
40
RL − Load Resistance − Ω
Figure 16
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• DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
VDD = 1.6 V
CB = 1 µF
RL = 32 Ω
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
k SVR− Supply Ripple Rejection Ratio − dB
k SVR− Supply Ripple Rejection Ratio − dB
0
−10
−130
100
1k
f − Frequency − Hz
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
20
−140
20
VDD = 3.3 V
CB = 1 µF
RL = 32 Ω
−10
10 k 20 k
100
Figure 17
10 k 20 k
Figure 18
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
100
100
VDD = 1.6 V
CB = 1 µF
RL = 16 Ω
V n − Output Noise Voltage − µ V(rms)
V n − Output Noise Voltage − µ V(rms)
1k
f − Frequency − Hz
10
1
20
100
1k
f − Frequency − Hz
10 k 20 k
VDD = 3.3 V
CB = 1 µF
RL = 16 Ω
10
1
20
Figure 19
100
1k
f − Frequency − Hz
10 k 20 k
Figure 20
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9
TYPICAL CHARACTERISTICS
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
0
−10
−10
−20
−30
−30
−40
−40
−50
−50
Crosstalk − dB
Crosstalk − dB
−20
VDD = 1.6 V
PO = 4.5 mW
RL = 50 Ω
−60
−70
−80
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
−130
−130
−140
20
VDD = 3.3 V
PO = 20 mW
RL = 50 Ω
100
1k
f − Frequency − Hz
−140
20
10 k 20 k
100
Figure 21
1k
f − Frequency − Hz
Figure 22
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
40
30
Phase
150°
120°
90°
10
60°
0
30°
Gain
−10
0°
−20
−30°
−60°
−30
−90°
−40
−120°
−50
−60
10
−150°
100
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 23
10
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−180°
100 M
Phase
Closed-Loop Gain − dB
20
180°
VDD = 1.6 V
RL = 16 Ω
TA = 25°C
10 k 20 k
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
180°
40
30
Phase
150°
120°
90°
10
60°
0
30°
Gain
0°
−10
−30°
−20
Phase
Closed-Loop Gain − dB
20
VDD = 1.6 V
RL = 32 Ω
TA = 25°C
−60°
−30
−90°
−40
−120°
−50
−60
10
−150°
100
1k
10 k
100 k
1M
10 M
−180°
100 M
f − Frequency − Hz
Figure 24
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
180°
40
30
Phase
150°
120°
90°
10
60°
0
30°
Gain
−10
0°
−20
−30°
Phase
Closed-Loop Gain − dB
20
VDD = 3.3 V
RL = 16 Ω
TA = 25°C
−60°
−30
−90°
−40
−120°
−50
−60
10
−150°
100
1k
10 k
100 k
1M
10 M
−180°
100 M
f − Frequency − Hz
Figure 25
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11
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
180°
40
VDD = 3.3 V
RL = 32 Ω
TA = 25°C
30
150°
120°
90°
10
60°
0
30°
Gain
0°
−10
−30°
−20
Phase
Closed-Loop Gain − dB
20
Phase
−60°
−30
−90°
−40
−120°
−50
−150°
−60
10
100
1k
10 k
100 k
1M
10 M
−180°
100 M
f − Frequency − Hz
Figure 26
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
POWER DISSIPATION
vs
OUTPUT POWER
1
40
VDD Low-to-High
TA = 25°C
TA = 125°C
I DD− Supply Current − mA
0.8
TA = 25°C
0.7
0.6
TA = −40°C
0.5
0.4
0.3
0.2
30
25
50 Ω
15
10
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
0
0
10
VDD − Supply Voltage − V
20
30
Figure 28
POST OFFICE BOX 655303
40
50
PO − Output Power − mW
Figure 27
12
VDD = 3.3 V
32 Ω
20
5
0.1
0
16 Ω
35
PD − Power Dissipation − mW
0.9
• DALLAS, TEXAS 75265
60
70
APPLICATION INFORMATION
input capacitor, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency
determined in equation 1. RI is set internally and is fixed at 80 kΩ.
fc +
1
2p R I C I
(1)
The value of CI is important to consider, as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where the specification calls for a flat bass response down to 20 Hz. Equation 1 is
reconfigured as equation 2.
CI +
1
2p R I f c
(2)
In this example, CI is approximately 0.1 µF. A further consideration for this capacitor is the leakage path from
the input source through the input network (RI, CI) and the feedback resistor (RF) to the load. This leakage
current creates a dc-offset voltage at the input to the amplifier that reduces useful headroom. For this reason,
a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive
side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/4,
which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application.
power supply decoupling, CS
The TPA6101A2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For
filtering lower-frequency noise signals, a larger, aluminum electrolytic capacitor of 10 µF or greater placed near
the power amplifier is recommended.
midrail bypass capacitor, CB
The midrail bypass capacitor (CB) serves several important functions. During start-up, CB determines the rate
at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it
can not be heard). The second function is to reduce noise produced by the power supply caused by coupling
into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor
is fed from a 55-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship
shown in Euation 3 should be maintained.
ǒC B
1
v 1
ǒCI RIǓ
55 kΩǓ
(3)
As an example, consider a circuit where CB is 1 µF, CI is 0.1 µF, and RI is 80 kΩ. Inserting these values into
Euation 3 results in: 18.18 ≤ 125 which satisfies the rule. Bypass capacitor (CB) values of 0.47 µF to 1 µF and
ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
APPLICATION INFORMATION
output coupling capacitor, CC
In the typical single-supply, single-ended (SE) configuration, an output coupling capacitor (CC) is required to
block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling
capacitor, the output coupling capacitor and impedance of the load from a high-pass filter is governed by
Equation 4.
fc +
1
2p R L C C
(4)
The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the
low-frequency corner higher. Large values of CC are required to pass low-frequencies into the load. Consider
the example where a CC of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 1 summarizes the
frequency response characteristics of each configuration.
Table 1. Common Load Impedances vs Low-Frequency Output Characteristics in SE Mode
RL
CC
LOWEST FREQUENCY
32 Ω
68 µF
Ą73 Hz
10,000 Ω
68 µF
0.23 Hz
47,000 Ω
68 µF
0.05 Hz
As Table 1 indicates, headphone response is adequate and drive into line-level inputs (a home stereo for
example) is very good.
The output coupling capacitor required in single-supply SE mode also places additional constraints on the
selection of other components in the amplifier circuit. With the rules described earlier still valid, add the following
relationship:
ǒC B
1
v 1 Ơ 1
ǒCI RIǓ RLCC
55 kΩǓ
(5)
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application. A real capacitor can be modeled simply as
a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects
of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor
behaves like an ideal capacitor.
3.3-V versus 1.6-V operation
The TPA6101A2 was designed for operation over a supply range of 1.6 V to 3.6 V. There are no special
considerations for 1.6-V versus 3.3-V operation as far as supply bypassing, gain setting, or stability. Supply
current is slightly reduced from 0.75 mA (typical) to 0.65 mA (typical). The most important consideration is that
of output power. Each amplifier can produce a maxium output voltage swing within a few hundred millivolts of
the rails with a 10-kΩ load. However, this voltage swing decreases as the load resistance decreases, and the
rDS(on) of the output stage transistors becomes more significant. For example, for a 32-Ω load, the maximum
peak output voltage with VDD = 1.6 V is approximately 0.7 V with no clipping distortion. This reduced voltage
swing effectively reduces the maximum undistorted output power.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA6101A2D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
6101A2
TPA6101A2DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJM
TPA6101A2ZQYR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQY
15
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
-40 to 85
AAQI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPA6101A2DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPA6101A2ZQYR
BGA MI
CROSTA
R JUNI
OR
ZQY
15
2500
330.0
8.4
2.8
2.8
1.25
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA6101A2DGKR
VSSOP
TPA6101A2ZQYR
BGA MICROSTAR
JUNIOR
DGK
8
2500
358.0
335.0
35.0
ZQY
15
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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