Texas Instruments | 24-Bit 192-kHz Sampling Advanced-Segment Audio Stereo DAC (Rev. A) | Datasheet | Texas Instruments 24-Bit 192-kHz Sampling Advanced-Segment Audio Stereo DAC (Rev. A) Datasheet

Texas Instruments 24-Bit 192-kHz Sampling Advanced-Segment Audio Stereo DAC (Rev. A) Datasheet
("" "!1 "!-('%&
"!# )0$& &%"(#)%&
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
FEATURES
D Supports Both DSD and PCM Formats
D 24-Bit Resolution
D Analog Performance:
− Dynamic Range: 123 dB
− THD+N: 0.0005%
Differential Current Output: 4 mA p-p
D
D 8× Oversampling Digital Filter:
− Stop-Band Attenuation: –98 dB
− Pass-Band Ripple: ±0.0002 dB
Sampling Frequency: 10 kHz to 200 kHz
D
D System Clock: 128, 192, 256, 384, 512, or
768 fS With Autodetect
D Accepts 16-, 20-, and 24-Bit Audio Data
D PCM Data Formats: Standard, I2S, and
Left-Justified
D DSD Format Interface Available
D Interface Available for Optional External
Digital Filter or DSP
D TDMCA Interface Available
D User-Programmable Mode Controls:
D
D
− Digital Attenuation: 0 dB to –120 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
Compatible With DSD1792 (Pins and Mode
Controls)
Dual Supply Operation:
− 5-V Analog, 3.3-V Digital
D 5-V Tolerant Digital Inputs
D Small 28-Lead SSOP Package
APPLICATIONS
D A/V Receivers
D SACD Players
D DVD Players
D HDTV Receivers
D Car Audio Systems
D Digital Multi-Track Recorders
D Other Applications Requiring 24-Bit Audio
DESCRIPTION
The DSD1796 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI’s advanced-segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The DSD1796 provides balanced
current outputs, allowing the user to optimize analog
performance externally. The DSD1796 accepts the PCM
and DSD audio data formats, providing easy interfacing to
audio DSP and decoder chips. The DSD1796 also
interfaces with external digital filter devices (DF1704,
DF1706, PMD200). Sampling rates up to 200 kHz are
supported. A full set of user-programmable functions is
accessible through an SPI serial control port, which
supports register write and readback functions. The
DSD1796 also supports the time-division-multiplexed
command and audio (TDMCA) data format.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%&
'!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2.
"!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&.
Copyright  2006, Texas Instruments Incorporated
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE RANGE
PACKAGE
MARKING
DSD1796DB
28-lead SSOP
28DB
–25°C to 85°C
DSD1796
ORDERING
NUMBER
TRANSPORT
MEDIA
DSD1796DB
Tube
DSD1796DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
DSD1796
VCC1, VCC2L, VCC2R
VDD
Supply voltage
–0.3 V to 6.5 V
–0.3 V to 4 V
±0.1 V
Supply voltage differences: VCC1, VCC2L, VCC2R
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND
PLRCK, PDATA, PBCK, SCK, RST, MS(2), MDI, MC, DSDL(2), DSDR(2), DBCK
Digital input voltage
DSDL(3), DSDR(3), MS(3), MDO
Analog input voltage
±0.1 V
–0.3 V to 6.5 V
–0.3 V to (VDD + 0.3 V) < 4 V
–0.3 V to (VCC + 0.3 V) < 6.5 V
±10 mA
Input current (any pins except supplies)
Ambient temperature under bias
–40°C to 125°C
Storage temperature
–55°C to 150°C
Junction temperature
150°C
Lead temperature (soldering)
260°C, 5 s
Package temperature (IR reflow, peak)
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input mode
(3) Output mode
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless
otherwise noted
DSD1796DB
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
24
UNIT
Bits
DATA FORMAT (PCM Mode)
Audio data interface format
fS
Standard, I2S, left-justified
Audio data bit length
16-, 20-, 24-bit selectable
Audio data format
MSB first, 2s complement
Sampling frequency
System clock frequency
10
200
kHz
128, 192, 256, 384, 512, 768 fS
DATA FORMAT (DSD Mode)
Audio data interface format
DSD (direct stream digital)
Audio data bit length
fS
Sampling frequency
System clock frequency
2
1 bit
2.8224
2.8224
MHz
11.2896
MHz
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless
otherwise noted
DSD1796DB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
VIH
VIL
Input logic level
IIH
IIL
Input logic current
VIN = VDD
VIN = 0 V
VOH
VOL
Output logic level
IOH = –2 mA
IOL = 2 mA
IOHZ
High-impedance output logic current(1)
IOLZ
DYNAMIC PERFORMANCE (PCM MODE) (2)(3)
THD+N at VOUT = 0 dB
2
0.8
0.4
10
–10
fS = 44.1 kHz
fS = 96 kHz
0.0005%
123
120
123
EIAJ, A-weighted, fS = 192 kHz
123
Level linearity error
0.001%
116
dB
123
EIAJ, A-weighted, fS = 96 kHz
fS = 192 kHz
VOUT = –120 dB
µA
123
123
fS = 44.1 kHz
fS = 96 kHz
VDC
0.0015%
120
EIAJ, A-weighted, fS = 192 kHz
Channel separation
µA
0.001%
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Signal-to-noise ratio
2.4
VOUT = VDD
VOUT = 0 V
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Dynamic range
10
–10
VDC
dB
119
118
dB
117
±1
dB
DYNAMIC PERFORMANCE (MONO MODE) (2)(3)(4)
THD+N at VOUT = 0 dB
Dynamic range
Signal-to-noise ratio
fS = 44.1 kHz
fS = 96 kHz
0.0005%
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
0.0015%
0.001%
126
EIAJ, A-weighted, fS = 96 kHz
126
EIAJ, A-weighted, fS = 192 kHz
126
EIAJ, A-weighted, fS = 44.1 kHz
126
EIAJ, A-weighted, fS = 96 kHz
126
EIAJ, A-weighted, fS = 192 kHz
126
dB
dB
(1) Pin 13 (MDO)
(2) Filter condition:
THD+N: 20-Hz HPF, 20-kHz AES17 LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the
averaging mode.
(3) Dynamic performance and DC accuracy are specified at the output of the postamplifier as shown in Figure 32.
(4) Dynamic performance and DC accuracy are specified at the output of the measurement circuit as shown in Figure 34.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
3
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless
otherwise noted
DSD1796DB
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
MAX
DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHz, 64 fS)
THD+N at FS
2 V rms
Dynamic range
–60 dB, EIAJ, A-weighted
0.0007%
122
dB
Signal-to-noise ratio
EIAJ, A-weighted
122
dB
ANALOG OUTPUT
Gain error
–7
±2
7
% of FSR
Gain mismatch, channel-to-channel
–3
±0.5
3
% of FSR
–2
±0.5
2
% of FSR
Bipolar zero error
At BPZ
Output current
Full scale (0 dB)
Center current
At BPZ
4
mA p-p
–3.5
mA
DIGITAL FILTER PERFORMANCE
±0.1
De-emphasis error
dB
FILTER CHARACTERISTICS-1: SHARP ROLLOFF
Pass band
±0.0002 dB
0.454 fS
–3 dB
Stop band
0.49 fS
0.546 fS
±0.0002
Pass-band ripple
Stop-band attenuation
Stop band = 0.546 fS
–98
Delay time
dB
dB
38/fS
s
FILTER CHARACTERISTICS-2: SLOW ROLLOFF
Pass band
±0.001 dB
0.21 fS
0.448 fS
–3 dB
Stop band
0.79 fS
±0.001
Pass-band ripple
Stop-band attenuation
Delay time
Stop band = 0.732 fS
–80
dB
dB
s
(1) Filter condition:
THD+N: 20-Hz HPF, 20-kHz AES17 LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging
mode.
(2) Dynamic performance and DC accuracy are specified at the output of the postamplifier as shown in Figure 33.
4
38/fS
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V,, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless
otherwise noted
DSD1796DB
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
MAX
POWER SUPPLY REQUIREMENTS
VDD
VCC1
VCC2L
VCC2R
Voltage range
3
3.3
3.6
VDC
4.75
5
5.25
VDC
7
9
fS = 44.1 kHz
fS = 96 kHz
IDD
Supply current (1)
ICC
Power dissipation (1)
13
fS = 192 kHz
fS = 44.1 kHz
25
fS = 96 kHz
fS = 192 kHz
19
18
mA
23
mA
20
fS = 44.1 kHz
fS = 96 kHz
140
115
fS = 192 kHz
180
150
mW
TEMPERATURE RANGE
Operation temperature
–25
θJA
Thermal resistance
(1) Input is BPZ data.
28-pin SSOP
85
100
°C
°C/W
PIN ASSIGNMENTS
DSD1796
(TOP VIEW)
DSDL
DSDR
DBCK
PLRCK
PDATA
PBCK
SCK
DGND
VDD
MS
MDI
MC
MDO
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC2L
AGND3L
IOUTL–
IOUTL+
AGND2
VCC1
VCOML
VCOMR
IREF
AGND1
IOUTR–
IOUTR+
AGND3R
VCC2R
5
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Terminal Functions
TERMINAL
NAME
PIN
I/O
DESCRIPTIONS
AGND1
19
–
Analog ground (internal bias)
AGND2
24
–
Analog ground (internal bias)
AGND3L
27
–
Analog ground (L-channel DACFF)
AGND3R
16
–
DBCK
3
I
Analog ground (R-channel DACFF)
Bit clock input for DSD mode (1)
DGND
8
–
Digital ground
DSDL
1
I/O
L-channel audio data input for DSD mode
PCM mode zero flag for L-channel when in zero-flag output mode(2)
DSDR
2
I/O
R-channel audio data input for DSD mode
PCM mode zero flag for R-channel when in zero-flag output mode (2)
IOUTL+
IOUTL–
25
O
L-channel analog current output +
26
O
L-channel analog current output –
IOUTR+
IOUTR–
17
O
R-channel analog current output +
18
O
R-channel analog current output –
IREF
MC
20
–
12
I
Output current reference bias pin
Mode control clock input(1)
MDI
11
I
Mode control data input (1)
MDO
13
O
MS
10
I/O
Mode control readback data output (3)
Mode control chip-select input(2)
PBCK
6
I
Bit clock input for PCM mode (1)
PDATA
5
I
Serial audio data input for PCM mode (1)
PLRCK
4
I
RST
14
I
Left and right clock (fS) input for PCM mode (1)
Reset(1)
SCK
7
I
System clock input (1)
VCC1
VCC2L
23
–
Analog power supply, 5 V
28
–
Analog power supply (L-channel DACFF), 5 V
VCC2R
VCOML
15
–
Analog power supply (R-channel DACFF), 5 V
22
–
L-channel internal bias decoupling pin
VCOMR
21
–
R-channel internal bias decoupling pin
VDD
9
–
Digital power supply, 3.3 V
(1) Schmitt-trigger input, 5-V tolerant
(2) Schmitt-trigger input and output. 5-V tolerant input, and CMOS output
(3) 3-state output
6
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
IOUTL–
DBCK
DSDL
DSDR
PLRCK
Current
Segment
DAC
Audio
Data Input
I/F
IOUTL+
8
Oversampling
Digital
Filter
and
Function
Control
PBCK
PDATA
RST
VCOML
Advanced
Segment
DAC
Modulator
Bias
and
Vref
MDO
IREF
VCOMR
Current
Segment
DAC
MS
VOUTR
IOUTR+
I/V and Filter
VCC1
AGND3R
AGND3L
AGND1
VDD
DGND
SCK
AGND2
Power Supply
System Clock Manager
VCC2R
MC
I/V and Filter
IOUTR–
Function
Control
I/F
VCC2L
MDI
VOUTL
7
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
5
0.0005
4
0.0004
−20
3
0.0003
−40
Amplitude – dB
Amplitude – dB
2
0.0002
−60
−80
−100
1
0.0001
0
−1
–0.0001
−2
–0.0002
−120
−3
–0.0003
−140
−4
–0.0004
−160
0
1
2
3
4
−5
–0.0005
0.0
0.1
Frequency [× fS]
0.2
0.3
0.4
0.5
Frequency [× fS]
Figure 1. Frequency Response, Sharp Rolloff
Figure 2. Pass-Band Ripple, Sharp Rolloff
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
−2
−20
−4
−40
Amplitude – dB
Amplitude – dB
−6
−60
−80
−100
−8
−10
−12
−14
−120
−16
−140
−18
−160
0
1
2
3
4
Frequency [× fS]
Figure 3. Frequency Response, Slow Rolloff
8
−20
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency [× fS]
Figure 4. Transition Characteristics, Slow Rolloff
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
De-Emphasis Filter
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
0.5
fS = 32 kHz
−1
0.3
De-Emphasis Error – dB
−2
De-Emphasis Level – dB
fS = 32 kHz
0.4
−3
−4
−5
−6
−7
0.2
0.1
−0.0
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
0
2
4
6
f – Frequency – kHz
Figure 5
10
12
14
Figure 6
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
0.5
fS = 44.1 kHz
−1
fS = 44.1 kHz
0.4
0.3
De-Emphasis Error – dB
−2
De-Emphasis Level – dB
8
f – Frequency – kHz
−3
−4
−5
−6
−7
0.2
0.1
−0.0
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
f – Frequency – kHz
Figure 7
16
18
20
0
2
4
6
8
10
12
14
16
18
20
f – Frequency – kHz
Figure 8
9
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
De-Emphasis Filter (Continued)
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
0.5
fS = 48 kHz
−1
0.3
De-Emphasis Error – dB
De-Emphasis Level – dB
−2
−3
−4
−5
−6
−7
0.2
0.1
−0.0
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
f – Frequency – kHz
Figure 9
10
fS = 48 kHz
0.4
16
18
20
22
0
2
4
6
8
10
12
14
f – Frequency – kHz
Figure 10
16
18
20
22
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
126
124
Dynamic Range – dB
THD+N – Total Harmonic Distortion + Noise – %
0.01
0.001
fS = 192 kHz
fS = 48 kHz
4.75
5.00
5.25
fS = 192 kHz
120
116
4.50
5.50
VCC – Supply Voltage – V
5.00
5.25
5.50
Figure 12
SIGNAL-to-NOISE RATIO
vs
SUPPLY VOLTAGE
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
126
122
fS = 96 kHz
124
120
Channel Separation – dB
SNR – Signal-to-Noise Ratio – dB
4.75
VCC – Supply Voltage – V
Figure 11
122
fS = 48 kHz
fS = 192 kHz
120
118
116
4.50
fS = 48 kHz
122
118
fS = 96 kHz
0.0001
4.50
fS = 96 kHz
fS = 96 kHz
118
fS = 48 kHz
fS = 192 kHz
116
114
4.75
5.00
5.25
5.50
VCC – Supply Voltage – V
Figure 13
112
4.50
4.75
5.00
5.25
5.50
VCC – Supply Voltage – V
Figure 14
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit is Figure 32.
11
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
126
124
Dynamic Range – dB
THD+N – Total Harmonic Distortion + Noise – %
0.01
fS = 96 kHz
0.001
fS = 192 kHz
fS = 48 kHz
fS = 96 kHz
fS = 48 kHz
122
fS = 192 kHz
120
118
0.0001
−50
−25
0
25
50
75
116
−50
100
TA – Free-Air Temperature – °C
−25
Figure 15
75
100
75
100
122
124
fS = 96 kHz
120
fS = 96 kHz
122
fS = 192 kHz
Channel Separation – dB
SNR – Signal-to-Noise Ratio – dB
50
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
126
fS = 48 kHz
120
118
fS = 192 kHz
118
fS = 48 kHz
116
114
−25
0
25
50
75
100
TA – Free-Air Temperature – °C
Figure 17
NOTE: PCM mode, VCC = 5 V, VDD = 3.3 V, measurement circuit is Figure 32.
12
25
Figure 16
SIGNAL-to-NOISE RATIO
vs
FREE-AIR TEMPERATURE
116
−50
0
TA – Free-Air Temperature – °C
112
−50
−25
0
25
50
TA – Free-Air Temperature – °C
Figure 18
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
AMPLITUDE
vs
FREQUENCY
0
0
−20
−20
−40
−40
Amplitude – dB
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
2
4
6
8
10
12
14
16
18
20
0
10
20
f – Frequency – kHz
30
NOTE: PCM mode, fS = 48 kHz, 32768 point 8 average, TA = 25°C,
VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 32.
Figure 19. –60-db Output Spectrum, BW = 20 kHz
50
60
70
80
90 100
NOTE: PCM mode, fS = 96 kHz, 32768 point 8 average, TA = 25°C,
VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 32.
Figure 20. –60-db Output Spectrum, BW = 100 kHz
AMPLITUDE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
0
10
−20
1
−40
Amplitude – dB
THD+N – Total Harmonic Distortion + Noise – %
40
f – Frequency – kHz
0.1
0.01
−60
−80
−100
−120
0.001
−140
0.0001
−90 −80 −70 −60 −50 −40 −30 −20 −10
−160
0
Input Level – dBFS
0
2
4
6
8
10
12
14
16
18
20
f – Frequency – kHz
NOTE: PCM mode, fS = 48 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V, NOTE: DSD mode (FIR-2), 32768 point 8 average, TA = 25°C,
measurement circuit is Figure 32.
VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 33.
Figure 21. THD+N vs Input Level, PCM Mode
Figure 22. –60-db Output Spectrum, DSD Mode
13
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1796 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators.
The system clock is applied at the SCK input (pin 7). The DSD1796 has a system clock detection circuit that automatically
senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for
common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 fS, the system clock
frequency is required to be over 256 fS.
Figure 23 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators is an excellent
choice for providing the DSD1796 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
SAMPLING FREQUENCY
128 fS
192 fS
256 fS
32 kHz
4.096
6.144
8.192
384 fS
12.288
512 fS
16.384
768 fS
24.576
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
192 kHz
24.576
36.864
49.152
(1) This system clock rate is not supported for the given sampling frequency.
73.728
49.152
–(1)
73.728
–(1)
t(SCKH)
H
2V
System Clock (SCK)
0.8 V
L
t(SCKL)
PARAMETERS
t(SCY)
MIN
UNITS
13
ns
0.4t(SCY)
ns
t(SCKL) System clock pulse duration, LOW
0.4t(SCY)
ns
Figure 23. System Clock Input Timing
14
MAX
t(SCY) System clock pulse cycle time
t(SCKH) System clock pulse duration, HIGH
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Power-On and External Reset Functions
The DSD1796 includes a power-on reset function. Figure 24 shows the operation of this function. With VDD > 2 V, the
power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. After
the initialization period, the DSD1796 is set to its default reset state, as described in the MODE CONTROL REGISTERS
section of this data sheet.
The DSD1796 also includes an external reset capability using the RST input (pin 14). This allows an external controller
or master reset circuit to force the DSD1796 to initialize to its default reset state.
Figure 25 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST
pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The
external reset is especially useful in applications where there is a delay between the DSD1796 power up and system clock
activation.
VDD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
Figure 24. Power-On Reset Timing
RST (Pin 14)
1.4 V
t(RST)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
t(RST)
PARAMETERS
MIN
Reset pulse duration, LOW
20
MAX
UNITS
ns
Figure 25. External Reset Timing
15
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5). PBCK is the
serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of the audio
interface. Serial data is clocked into the DSD1796 on the rising edge of PBCK. PLRCK is the serial audio left/right word
clock.
The DSD1796 requires the synchronization of PLRCK and the system clock, but does not need a specific phase relation
between PLRCK and the system clock.
If the relationship between PLRCK and the system clock changes more than ±6 PBCK, internal operation is initialized within
1/fS and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the system clock
is completed.
PCM Audio Data Formats and Timing
The DSD1796 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The
data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0], in control register 18. The
default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio data. Figure 26 shows a detailed
timing diagram for the serial audio interface.
1.4 V
PLRCK
t(BCH)
t(BCL)
t(LB)
1.4 V
PBCK
t(BCY)
t(BL)
1.4 V
PDATA
t(DS)
t(DH)
PARAMETERS
MIN
UNITS
PBCK pulse cycle time
70
ns
PBCK pulse duration, LOW
30
ns
t(BCH)
t(BL)
PBCK pulse duration, HIGH
30
ns
PBCK rising edge to PLRCK edge
10
ns
t(LB)
t(DS)
PLRCK edge to PBCK rising edge
10
ns
PDATA setup time
10
ns
t(DH)
—
PDATA hold time
10
ns
PLRCK clock data
50% ± 2 bit clocks
Figure 26. Timing of Audio Interface
16
MAX
t(BCY)
t(BCL)
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW
1/fS
PLRCK
R-Channel
L-Channel
PBCK
Audio Data Word = 16-Bit
PDATA
14 15 16
1
2
MSB
15 16
1
2
15 16
LSB
Audio Data Word = 20-Bit
PDATA
18 19 20
1
2
19 20
1
2
19 20
LSB
MSB
Audio Data Word = 24-Bit
PDATA
22 23 24
1
2
23 24
1
2
23 24
LSB
MSB
(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
PLRCK
R-Channel
L-Channel
PBCK
Audio Data Word = 24-Bit
PDATA
1
2
23 24
1
2
23 24
1
2
LSB
MSB
(3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
PLRCK
L-Channel
R-Channel
PBCK
Audio Data Word = 16-Bit
PDATA
1
2
15 16
MSB
1
2
1
2
15 16
1
2
1
2
LSB
Audio Data Word = 24-Bit
PDATA
1
2
23 24
MSB
23 24
LSB
Figure 27. Audio Data Input Formats
17
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
External Digital Filter Interface and Timing
The DSD1796 supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows
the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific
Microsonics PMD200, or a programmable digital signal processor.
In the external DF mode, PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5) are defined as WDCK, the word clock; BCK,
the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using the DFTH
bit of control register 20, which functions to bypass the internal digital filter of the DSD1796.
When the DFMS bit of control register 19 is set, the DSD1796 can process stereo data. In this case, DSDL (pin 1) and DSDR
(pin 2) are defined as L-channel data and R-channel data input, respectively.
Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL
DIGITAL FILTER INTERFACE section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The DSD1796 supports the DSD format interface operation, which includes out-of-band noise filtering using an internal
analog FIR filter. The DSD format interface consists of a 3-wire synchronous serial port, which includes DBCK (pin 3), DSDL
(pin 1), and DSDR (pin 2). DBCK is the serial bit clock. DSDL and DSDR are the L-channel and R-channel DSD data input,
respectively. They are clocked into the DSD1796 on the rising edge of DBCK. PLRCK (pin 4) and PBCK (pin 6) must be
connected to GND in the DSD mode. The DSD format (DSD mode) interface is activated by setting the DSD bit of control
register 20.
Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
section of this data sheet.
TDMCA Interface
The DSD1796 supports the time-division-multiplexed command and audio (TDMCA) data format to enable control of and
communication with a number of external devices over a single serial interface.
Detailed information for the TDMCA format is provided in the TDMCA INTERFACE FORMAT section of this data sheet.
18
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial port, which operates asynchronously with the serial audio
interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.
The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output,
used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC
is the serial bit clock, used to shift data in and out of the control port; and MS is the mode control enable, used to enable
the internal mode register access.
Register Read/Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 28 shows the control data word format.
The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For read operations,
the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read
and write operations. The least significant eight bits, D[7:0], contain the data to be written to, or the data that was read from,
the register specified by IDX[6:0].
Figure 29 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1 state until
a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data on MDO. After the eighth
clock cycle has completed, the data from the indexed-mode control register appears on MDO during the read operation.
After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write
operation. To write or read subsequent data, MS must be set to 1 once.
LSB
MSB
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
Register Index (or Address)
D4
D3
D2
D1
D0
Register Data
Figure 28. Control Data Word Format for MDI
MS
MC
MDI
MDO
R/W
A6
A5
A4
A3
High Impedance
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
When Read Mode is Instructed
NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14–8 are used for the register
address. Bits 7–0 are used for register data.
Figure 29. Serial Control Format
19
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
t(MHH)
MS
1.4 V
t(MSS)
t(MCL)
t(MCH)
t(MSH)
MC
1.4 V
t(MCY)
LSB
MDI
t(MDS)
1.4 V
t(MOS)
t(MDH)
MDO
50% of VDD
PARAMETER
t(MCY)
t(MCL)
MC pulse cycle time
t(MCH)
t(MHH)
t(MSS)
t(MSH)
t(MDH)
t(MDS)
MIN
MAX
ns
MC low-level time
40
ns
MC high-level time
40
ns
MS high-level time
80
ns
MS falling edge to MC rising edge
MS hold time(1)
15
ns
15
ns
MDI hold time
15
ns
MDI setup time
15
t(MOS) MC falling edge to MDO stable
(1) MC rising edge for LSB to MS rising edge
Figure 30. Control Interface Timing
20
UNITS
100
ns
30
ns
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1796 includes a number of user-programmable functions which are accessed via mode control registers. The
registers are programmed using the serial control interface, which is previously desribed in the SERIAL CONTROL
INTERFACE section of this data sheet. Table 2 lists the available mode control functions, along with their default reset
conditions and associated register index.
Table 2. User-Programmable Function Controls
FUNCTION
DEFAULT
REGISTER
BIT
PCM
DSD
DF
BYPASS
Digital attenuation control
0 dB to –120 dB and mute, 0.5 dB step
0 dB
Register 16
Register 17
ATL[7:0] (for L-ch)
ATR[7:0] (for R-ch)
yes
Attenuation load control—Disabled, enabled
Attenuation disabled
24-bit I2S format
Register 18
ATLD
yes
Register 18
FMT[2:0]
yes
Sampling rate selection for de-emphasis
Disabled,44.1 kHz, 48 kHz, 32 kHz
De-emphasis disabled
Register 18
DMF[1:0]
yes
De-emphasis control—Disabled, enabled
De-emphasis disabled
Register 18
DME
yes
Soft mute control—Mute disabled, enabled
Mute disabled
Register 18
MUTE
yes
Output phase reversal—Normal, reverse
Normal
Register 19
REV
yes
Attenuation speed selection
×1 fS, ×(1/2)fS, ×(1/4)fS, ×(1/8)fS
DAC operation control—Enabled, disabled
×1 fS
Register 19
ATS[1:0]
yes
DAC operation enabled
Register 19
OPE
yes
Zero flag pin operation control
DSD data input, zero flag output
DSD data input
Register 19
ZOE
yes
Stereo DF bypass mode select
Monaural, stereo
Monaural
Register 19
DFMS
Digital filter rolloff selection
Sharp rolloff, slow rolloff
Sharp rolloff
Register 19
FLT
yes
Infinite zero mute control
Disabled, enabled
Disabled
Register 19
INZD
yes
System reset control
Reset operation , normal operation
Normal operation
Register 20
SRST
yes
yes
DSD interface mode control
DSD enabled, disabled
Disabled
Register 20
DSD
yes
yes
Digital-filter bypass control
DF enabled, DF bypass
DF enabled
Register 20
DFTH
yes
Monaural mode selection
Stereo, monaural
Stereo
Register 20
MONO
yes
yes
yes
Channel selection for monaural mode data
L-channel, R-channel
L-channel
Register 20
CHSL
yes
yes
yes
Delta-sigma oversampling rate selection
×64 fS, ×128 fS, ×32 fS
×64 fS
Register 20
OS[1:0]
yes
yes(2)
yes
PCM zero output enable
Enabled
Register 21
PCMZ
yes
DSD zero output enable
Disabled
Register 21
DZ[1:0]
Zero detection flag
Not zero, zero detected
Not zero = 0
Zero detected = 1
Register 22
ZFGL (for L-ch)
ZFGR (for R-ch)
yes
Device ID (at TDMCA)
–
Register 23
ID[4:0]
yes
Input audio data format selection
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
16-/24-bit I2S format
yes
yes(1)
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
FUNCTION AVAILABLE ONLY FOR READ
yes
yes
(1) When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.
(2) When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.
21
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Register Map
The mode control register map is shown in Table 3. Registers 16–21 include an R/W bit, which determines whether a
register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.
Table 3. Mode Control Register Map
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Register 17
R/W
0
0
1
0
0
0
1
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Register 18
R/W
0
0
1
0
0
1
0
ATLD
FMT2
FMT1
FMT0
DMF1
DMF0
DME
MUTE
Register 19
R/W
0
0
1
0
0
1
1
REV
ATS1
ATS0
OPE
ZOE
DFMS
FLT
INZD
Register 20
R/W
0
0
1
0
1
0
0
RSV
SRST
DSD
DFTH
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0
PCMZ
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
Register 23
R
0
0
1
0
1
1
1
RSV
RSV
RSV
ID4
ID3
ID2
ID1
ID0
Register Definitions
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Register 17
R/W
0
0
1
0
0
0
1
ATR7 ATR6
ATR5 ATR4
ATR3
ATR2
ATR1
ATR0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATx[7:0]: Digital Attenuation Level Setting
These bits are available for read and write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB steps.
Alternatively, the attenuator can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control register
18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The attenuation level
can be set using the following formula:
Attenuation level (dB) = 0.5 dB • (ATx[7:0] DEC – 255)
where ATx[7:0]DEC = 0 through 255
For ATx[7:0]DEC = 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation levels
for various settings:
22
ATx[7:0]
Decimal Value
Attenuation Level Setting
1111 1111b
255
0 dB, no attenuation (default)
1111 1110b
254
–0.5 dB
1111 1101b
253
–1.0 dB
L
L
0001 0000b
16
–119.5 dB
0000 1111b
15
–120.0 dB
0000 1110b
14
Mute
L
L
L
0000 0000b
0
Mute
L
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Register 18
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
R/W
0
0
1
0
0
1
0
ATLD
FMT2
FMT1
FMT0
B3
B2
DMF1 DMF0
B1
B0
DME
MUTE
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATLD: Attenuation Load Control
This bit is available for read and write.
Default value: 0
ATLD = 0
Attenuation control disabled (default)
ATLD = 1
Attenuation control enabled
The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the
attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and 17. When
ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.
FMT[2:0]: Audio Interface Data Format
These bits are available for read and write.
Default value: 101
FMT[2:0]
Audio Data Format Selection
000
16-bit standard format, right-justified data
001
20-bit standard format, right-justified data
010
24-bit standard format, right-justified data
011
24-bit MSB-first, left-justified format data
100
16-bit I2S-format data
101
24-bit I2S-format data (default)
110
Reserved
111
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the APPLICATION FOR
EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
These bits are available for read and write.
Default value: 00
DMF[1:0]
De-Emphasis Sampling Frequency Selection
00
Disabled (default)
01
48 kHz
10
44.1 kHz
11
32 kHz
The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is enabled
by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this
data sheet.
For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter response
plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet.
23
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
DME: Digital De-Emphasis Control
This bit is available for read and write.
Default value: 0
DME = 0
De-emphasis disabled (default)
DME = 1
De-emphasis enabled
The DME bit is used to enable or disable the de-emphasis function for both channels.
MUTE: Soft Mute Control
This bit is available for read and write.
Default value: 0
MUTE = 0
Mute disabled (default)
MUTE = 1
Mute enabled
The MUTE bit is used to enable or disable the soft mute function for both channels.
Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the attenuation
rate selected in the ATS register.
Register 19
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
0
0
1
0
0
1
1
REV
ATS1
ATS0
OPE
ZOE
DFMS
FLT
INZD
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
REV: Output Phase Reversal
This bit is available for read and write.
Default value: 0
REV = 0
Normal output (default)
REV = 1
Inverted output
The REV bit is used to invert the output phase for both channels.
ATS[1:0]: Attenuation Rate Select
These bits are available for read and write.
Default value: 00
ATS[1:0]
Attenuation Rate Selection
00
Every PLRCK (default)
01
PLRCK/2
10
PLRCK/4
11
PLRCK/8
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level transitions.
24
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
OPE: DAC Operation Control
This bit is available for read and write.
Default value: 0
OPE = 0
DAC operation enabled (default)
OPE = 1
DAC operation disabled
The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them
to the bipolar zero level (BPZ) even if digital audio data is present on the input.
ZOE: Zero Flag Pin Operation Control
This bit is available for read and write.
Default value: 0
ZOE = 0
DSD data input (default)
ZOE = 1
Zero flag output
The ZOE bit is used to change the DSDL (pin 1) and DSDR (pin 2) pin assignments. When the ZOE bit is set to 0, DSDL
and DSDR are inputs for L-channel and R-channel data. When the ZOE bit is set to 1, DSDL and DSDR become outputs
for the L-channel and R-channel zero flags, respectively. See the PCMZ and DZ[1:0] bit descriptions of register 21.
DFMS: Stereo DF Bypass Mode Select
This bit is available for read and write.
Default value: 0
DFMS = 0
Monaural (default)
DFMS = 1
Stereo input enabled
The DFMS bit is used to enable stereo operation in the DF bypass mode. In the DF bypass mode, when DFMS is set to
0, the pin for the input data is PDATA (pin 5) only, therefore the DSD1796 operates as a monaural DAC. When DFMS is
set to 1, the DSD1796 can operate as a stereo DAC with inputs of input L-channel and R-channel data on DSDL (pin 1)
and DSDR (pin 2), respectively.
FLT: Digital Filter Rolloff Control
This bit is available for read and write.
Default value: 0
FLT = 0
Sharp rolloff (default)
FLT = 1
Slow rolloff
The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown in the
TYPICAL PERFORMANCE CURVES section of this data sheet.
INZD: Infinite Zero Detect Mute Control
This bit is available for read and write.
Default value: 0
INZD = 0
Infinite zero detect mute disabled (default)
INZD = 1
Infinite zero detect mute enabled
The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs
to hold a bipolar zero level when the DSD1796 detects zero data in both channels continuously for 1024 sampling periods
(1/fS). The infinite zero detect mute function is not available in the DSD mode.
25
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Register 20
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
0
0
1
0
1
0
0
RSV
SRST
DSD
DFTH
MONO
CHSL
OS1
OS0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
SRST: System Reset Control
This bit is available for write only.
Default value: 0
SRST = 0
Normal operation (default)
SRST = 1
System reset operation (generate one reset pulse)
The SRST bit is used to reset the DSD1796 to the initial system condition.
DSD: DSD Interface Mode Control
This bit is available for read and write.
Default value: 0
DSD = 0
DSD interface mode disabled (default)
DSD = 1
DSD interface mode enabled
The DSD bit is used to enable or disable the DSD interface mode.
DFTH: Digital Filter Bypass (or Through Mode) Control
This bit is available for read and write.
Default value: 0
DFTH = 0
Digital filter enabled (default)
DFTH = 1
Digital filter bypassed for external digital filter
The DFTH bit is used to enable or disable the external digital filter interface mode.
MONO: Monaural Mode Selection
This bit is available for read and write.
Default value: 0
MONO = 0
Stereo mode (default)
MONO = 1
Monaural mode
The MONO function is used to change the operation mode from the normal stereo mode to the monaural mode. When the
monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel selection
is available for L-channel or R-channel data, determined by the CHSL bit as described immediately following.
CHSL: Channel Selection for Monaural Mode
This bit is available for read and write.
Default value: 0
CHSL = 0
L-channel selected (default)
CHSL = 1
R-channel selected
This bit is available when MONO = 1.
The CHSL bit selects L-channel or R-channel data to be used in monaural mode.
26
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
OS[1:0]
Operation Speed Select
00
64 times fS (default)
01
32 times fS
10
128 times fS
11
Reserved
The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer
to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming
to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use
of only a single type (cutoff frequency) of post low-pass filter. The 128-fS oversampling rate is not available at sampling rates
above 100 kHz. If the 128-fS oversampling rate is selected, a system clock of more than 256 fS is required.
In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.
Register 21
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0
PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
DZ[1:0]
Zero Output Enable
00
Disabled (default)
01
Even pattern detect
1x
96h pattern detect
The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. The
DSD1796 sets zero flags when the numbers of 1s and 0s are equal in every 8 bits of DSD input data, or the DSD input data
is 1001 0110 continuously for 23 ms.
PCMZ: PCM Zero Output Enable
These bits are available for read and write.
Default value: 1
PCMZ = 0
PCM zero output disabled
PCMZ = 1
PCM zero output enabled (default)
The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. The DSD1796
sets the zero flags when the input data is continuously zero for 1024 PLRCKs in the PCM mode or 1024 WDCKs in the
external filter mode.
Register 22
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
R: Read Mode Select
Value is always 1, specifying the readback mode.
27
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ZFGx: Zero-Detection Flag
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx = 0
Not zero
ZFGx = 1
Zero detected
When the DSD1796 detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding
channel(s).
Register 23
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R
0
0
1
0
1
1
1
RSV
RSV
RSV
ID4
ID3
ID2
ID1
ID0
R: Read Mode Select
Value is always 1, specifying the readback mode.
ID[4:0]: Device ID
The ID[4:0] bits hold a device ID in the TDMCA mode.
28
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
APPLICATION INFORMATION
TYPICAL CONNECTION DIAGRAM
Cf
5V
Rf
0.1 µF
PCM
Audio Data
Source
DSDL
VCC2L
28
2
DSDR
AGND3L
27
3
DBCK
IOUTL–
26
4
PLRCK
IOUTL+
25
5
PDATA
AGND2
24
6
PBCK
VCC1
23
7
SCK
VCOML
22
8
DGND
VCOMR
21
9
VDD
IREF
20
10 MS
AGND1
19
11 MDI
IOUTR–
18
12 MC
IOUTR+
17
AGND3R
16
VCC2R
15
+
Controller
13 MDO
Cf
Rf
5V
–
10 µF
+
Differential
to
Single
Converter
With
Low-Pass
Filter
VOUT
L-Channel
Differential
to
Single
Converter
With
Low-Pass
Filter
VOUT
R-Channel
+
Cf
47 µF
Rf
10 kΩ
–
+
Cf
0.1 µF
Rf
5V
+
14 RST
–
+
DSD1796
0.1 µF
10 µF
+
DSD
Audio Data
Source
1
10 µF
–
+
3.3 V
+
10 µF
Figure 31. Typical Application Circuit
APPLICATION CIRCUIT
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the DSD1796
is capable. This is because noise and distortion that are generated in an application circuit are not negligible.
In the third-order LPF circuit of Figure 32, the output level is 2.1 V rms and 123 dB S/N is achieved.
Figure 33 shows a circuit for the DSD mode, which is a fourth-order LPF in order to reduce the out-of-band noise.
I/V Section
The current of the DSD1796 on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 4 mA p-p at 0 dB (full scale).
The voltage output level of the I/V converter (Vi) is given by following equation:
Vi = 4 mA p-p × Rf (Rf : feedback resistance of I/V converter)
An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic
performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic
performance of the I/V section.
Differential Section
The DSD1796 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each
channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function.
The operational amplifier recommended for the differential circuit is the low-noise type.
29
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
C1
2700 pF
R1
820 Ω
VCC
VCC
C11
0.1 µF
C17
22 pF
7
IOUT–
5
2
8
–
3
R5
200 Ω
6
+
U1
NE5534
4
R3
220 Ω
C3
8200 pF
R7
180 Ω
C5
27000 pF
C15
0.1 µF
C19
22 pF
7
2
3
5
–
6
+
4
C12
0.1 µF
VEE
R4
220 Ω
R6
200 Ω
8
R8
180 Ω
R9
100 Ω
U3
NE5534
C16
0.1 µF
C4
8200 pF
VEE
C2
2700 pF
R2
820 Ω
VCC
C13
0.1 µF
C18
22 pF
7
IOUT+
2
3
5
–
8
6
+
4
U2
NE5534
VCC = 15 V
VEE = –15 V
fc = 50 kHz
C14
0.1 µF
VEE
Figure 32. Measurement Circuit for PCM
30
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
C1
2200 pF
R1
820 Ω
VCC
VCC
C11
0.1 µF
C17
22 pF
7
IOUT–
5
2
8
–
3
R5
150 Ω
6
+
R3
91 Ω
R10
120 Ω
C3
22000 pF
U1
NE5534
4
R8
75 Ω
C5
8200 pF
C4
27000 pF
C15
0.1 µF
C19
22 pF
7
2
3
5
–
6
+
4
C12
0.1 µF
VEE
R4
91 Ω
R9
75 Ω
R6
150 Ω
8
R11
120 Ω
R7
100 Ω
U3
NE5534
C16
0.1 µF
C6
8200 pF
VEE
C2
2200 pF
R2
820 Ω
VCC
C13
0.1 µF
C18
22 pF
7
IOUT+
2
3
5
–
8
6
+
4
U2
NE5534
VCC = 15 V
VEE = –15 V
fc = 50 kHz
C14
0.1 µF
VEE
Figure 33. Measurement Circuit for DSD
31
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
IOUTL– (Pin 26)
IOUT–
Figure 32
Circuit
IOUTL+ (Pin 25)
OUT+
IOUT+
3
1
2
IOUTR– (Pin 18)
IOUT–
Figure 32
Circuit
IOUTR+ (Pin 17)
IOUT+
OUT–
Balanced Out
Figure 34. Measurement Circuit for Monaural Mode
32
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DFMS = 0
External Filter Device
DSD1796
1
DSDL
2
DSDR
3
DBCK
WDCK (Word Clock)
4
PLRCK
DATA
5
PDATA
BCK
6
PBCK
SCK
7
SCK
DFMS = 1
External Filter Device
DSD1796
DATA_L
1
DSDL
DATA_R
2
DSDR
3
DBCK
4
PLRCK
5
PDATA
BCK
6
PBCK
SCK
7
SCK
WDCK (Word Clock)
Figure 35. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
33
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can
provide improved stop-band attenuation when compared to the internal digital filter of the DSD1796.
The DSD1796 supports several external digital filters, including:
D Texas Instruments DF1704 and DF1706
D Pacific Microsonics PMD200 HDCD filter/decoder IC
D Programmable digital signal processors
The external digital filter application mode is accessed by programming the following bit in the corresponding control
register:
D DFTH = 1 (register 20)
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 35.
The word clock (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, fS.
Pin Assignment When Using the External Digital Filter Interface
D
D
D
D
D
34
PLRCK (pin 4): WDCK as word clock input
PBCK (pin 6):
BCK as bit clock for audio data
PDATA (pin 5): DATA as monaural audio data input when the DFMS bit is not set to 1
DSDL (pin 1):
DATAL as L-channel audio data input when the DFMS bit is set to 1
DSDR (pin 2): DATAR as R-channel audio data input when the DFMS bit is set to 1
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Audio Format
The DSD1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit, and
24-bit audio data, as shown in Figure 36. The audio format is selected by the FMT[2:0] bits of control register 18.
1/4 fS or 1/8 fS
WDCK
BCK
Audio Data Word = 16-Bit
DATA,
DATAL, DATAR
15 16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
Audio Data Word = 20-Bit
DATA,
DATAL, DATAR
19 20
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
MSB
LSB
Audio Data Word = 24-Bit
DATA,
DATAL, DATAR
23 24
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
Figure 36. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
System Clock (SCK) and Interface Timing
The DSD1796 in an application using an external digital filter requires the synchronization of WDCK and the system clock.
The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL, and DATAR
is shown in Figure 37.
1.4 V
WDCK
t(BCH)
t(BCL)
t(LB)
1.4 V
BCK
t(BCY)
t(BL)
DATA
DATAL
DATAR
1.4 V
t(DS)
t(DH)
PARAMETER
t(BCY) BCK pulse cycle time
t(BCL) BCK pulse duration, LOW
MIN
MAX
UNITS
20
ns
7
ns
t(BCH) BCK pulse duration, HIGH
t(BL)
BCK rising edge to WDCK falling edge
7
ns
5
ns
t(LB)
t(DS)
WDCK falling edge to BCK rising edge
5
ns
DATA, DATAL, DATAR setup time
5
ns
t(DH)
DATA, DATAL, DATAR hold time
5
ns
Figure 37. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
35
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Functions Available in the External Digital Filter Mode
The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20. B4).
The external digital filter mode allows access to the majority of the DSD1796 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
–
–
–
–
–
–
–
–
Register 17
R/W
0
0
1
0
0
0
1
–
–
–
–
–
–
–
–
Register 18
R/W
0
0
1
0
0
1
0
–
FMT2
FMT1
FMT0
–
–
–
–
Register 19
R/W
0
0
1
0
0
1
1
REV
–
–
OPE
–
DFMS
–
INZD
Register 20
R/W
0
0
1
0
1
0
0
–
SRST
0
1
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
–
–
–
–
–
–
–
PCMZ
0
–
–
–
–
–
–
ZFGR
ZFGL
Register 22
R
0
0
1
0
1
1
NOTE: –: Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
Audio Data Format Select
000
16-bit right-justified format (default)
001
20-bit right-justified format
010
24-bit right-justified format
Other
N/A
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
8 times WDCK (default)
01
4 times WDCK
10
16 times WDCK
11
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the
delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects OS[1:0] = 00, then
the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×. The 16× WDCK
oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16× WDCK, the
system clock frequency must be over 256 fS.
36
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
DSD Decoder
DSD1796
DATA_L
1
DSDL
DATA_R
2
DSDR
Bit Clock
3
DBCK
4
PLRCK
5
PDATA
6
PBCK
7
SCK
System Clock (1)
(1) The system clock can be removed after setting the register to the DSD mode.
Figure 38. Connection Diagram in DSD Mode
Feature
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications.
The DSD mode is accessed by programming the following bit in the corresponding control register.
DSD = 1 (register 20)
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure. Four FIR
responses are available, and are selected by the DMF[1:0] bits of control register 18.
The DSD bit must be set before inputting DSD data; otherwise, the DSD1796 erroneously detects the TDMCA mode, and
commands are not accepted through the serial control interface.
Pin Assignment When Using the DSD Format Interface
Pins for DSD mode operation are:
D DSDL (pin 1): L-channel DSD data input
D DSDR (pin 2): R-channel DSD data input
D DBCK (pin 3): Bit clock for DSD data
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
37
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Requirements for Bit Clock and System Clock
In the DSD mode, the bit clock (DBCK) is required on pin 3 of the DSD1796. The frequency of the bit clock can be N times
the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the same setup-and hold-time
specifications as shown in Figure 40.
SCK is not necessary after the mode change to the DSD mode is complete.
t = 1/(64 × 44.1 kHz)
DBCK
DSDL
DSDR
D0
D1
D2
D3
D4
Figure 39. Normal Data Output Form From DSD Decoder
t(BCH)
t(BCL)
1.4 V
DBCK
t(BCY)
DSDL
DSDR
1.4 V
t(DS)
t(DH)
PARAMETER
t(BCY) DBCK pulse cycle time
t(BCH) DBCK high-level time
t(BCL) DBCK low-level time
t(DS) DSDL, DSDR setup time
t(DH) DSDL, DSDR hold time
(1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a sampling rate of DSD.)
Figure 40. Timing for DSD Audio Interface
38
MIN
85(1)
MAX
UNITS
ns
30
ns
30
ns
10
ns
10
ns
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain – dB
Gain – dB
fc = 185 kHz
Gain(1) = –6.6 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
500
f – Frequency – kHz
1000
1500
f – Frequency – kHz
Figure 41. DSD Filter-1, Low BW
Figure 42. DSD Filter-1, High BW
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain – dB
Gain – dB
fc = 90 kHz
Gain(1) = 0.3 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
500
f – Frequency – kHz
Figure 43. DSD Filter-2, Low BW
1000
1500
f – Frequency – kHz
Figure 44. DSD Filter-2, High BW
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.
39
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED)
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain – dB
Gain – dB
fc = 85 kHz
Gain(1) = –1.5 dB
−3
−30
−4
−40
−5
−50
−60
−6
0
50
100
150
0
200
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 45. DSD Filter-3, Low BW
Figure 46. DSD Filter-3, High BW
GAIN
vs
FREQUENCY
GAIN
vs
FREQUENCY
0
0
−1
−10
−2
−20
Gain – dB
Gain – dB
fc = 94 kHz
Gain(1) = –3.3 dB
−3
−30
−4
−40
−5
−50
−6
−60
0
50
100
150
200
0
f – Frequency – kHz
Figure 47. DSD Filter-4, Low BW
500
1000
f – Frequency – kHz
Figure 48. DSD Filter-4, High BW
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.
40
1500
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
The DSD interface mode is selected by setting DSD = 1 (register 20, B5).
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
–
–
–
–
–
–
–
–
Register 17
R/W
0
0
1
0
0
0
1
–
–
–
–
–
–
–
–
Register 18
R/W
0
0
1
0
0
1
0
–
–
–
–
DMF1
DMF0
–
–
Register 19
R/W
0
0
1
0
0
1
1
REV
–
–
OPE
–
–
–
–
Register 20
R/W
0
0
1
0
1
0
0
–
SRST
1
–
MONO
CHSL
OS1
OS0
Register 21
R
0
0
1
0
1
0
1
–
–
–
–
–
DZ1
DZ0
–
0
–
–
–
–
–
–
ZFGR
ZFGL
Register 22
R
0
0
1
0
1
1
:
NOTE –: Function is disabled. No operation even if data bit is set
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0]
Analog-FIR Performance Select
00
FIR-1 (default)
01
FIR-2
10
FIR-3
11
FIR-4
Plots for the four analog FIR filter responses are shown in the ANALOG FIR FILTER PERFORMANCE IN DSD MODE
section of this data sheet.
OS[1:0]: Analog-FIR Operation-Speed Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
fDBCK (default)
01
fDBCK/2
10
Reserved
11
fDBCK/4
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before setting
the DSD bit to 1.
41
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
TDMCA INTERFACE FORMAT
The DSD1796 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host control
serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any programmable devices.
The TDMCA format can transfer not only audio data but also command data, so that it can be used together with any kind
of device that supports the TDMCA format. The TDMCA frame consists of command field, extended command field, and
some audio data fields. Those audio data are transported to IN devices (such as a DAC) and/or from OUT devices (such
as an ADC). The DSD1796 is an IN device. LRCK and BCK are used with both IN and OUT devices so that the sample
frequency of all devices in a system must be the same. The TDMCA mode supports a maximum of 30 device IDs. The
maximum number of audio channels depends on the BCK frequency.
TDMCA Mode Determination
The DSD1796 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration of two
BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 49 shows the LRCK
and BCK timing that determines the TDMCA mode. The DSD1796 enters the TDMCA mode after two continuous TDMCA
frames. Any TDMCA commands can be issued during the next TDMCA frame after the TDMCA mode is entered.
Pre-TDMCA Frame
TDMCA Frame
Command
Accept
LRCK
2 BCK
BCK
Figure 49. LRCK and BCK Timing for Determination of TDMCA Mode
TDMCA Terminals
TDMCA requires six signals, of which four signals are for command and audio data interface, and one pair of signals which
are for daisy chaining. Those signals can be shared as shown in Table 4. The DO signal has a 3-state output so that it can
be connected directly to other devices.
Table 4. TDMCA Terminal Descriptions
TERMINAL
NAME
TDMCA
NAME
I/O
PLRCK
LRCK
I
TDMCA frame start signal. It must be the same as the sampling frequency.
42
DESCRIPTION
PBCK
BCK
I
TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK cycle.
PDATA
DI
I
TDMCA command and audio data input signal
MDO
DO
O
TDMCA command data 3-state output signal
MC
DCI
I
TDMCA daisy-chain input signal
MS
DCO
O
TDMCA daisy-chain output signal
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Device ID Determination
The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can
simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices.
The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device. The IN device has an input
port to receive audio data, the OUT device has an output port to supply audio data, the IN/OUT device has both input and
output ports for audio data, and the NO device has no port for audio data but needs command data from the host. A DAC
is an IN device, an ADC is an OUT device, a codec is an IN/OUT device, and a PLL is a NO device. The DSD1796 is an
IN device. For the host controller to distinguish the devices, each device is assigned its own device ID by the daisy chain.
The devices obtain their own device IDs automatically by connecting their DCI to the DCO of the preceding device and their
DCO to the DCI of the following device in the daisy chain. The daisy chains are categorized as the IN chain and the OUT
chain, which are completely independent and equivalent. Figure 50 shows an example daisy chain connection. If a system
needs to chain the DSD1796 and a NO device in the same IN or OUT chain, the NO device must be chained at the back
end of the chain because it does not require any audio data. Figure 51 shows an example of a TDMCA system including
an IN chain and an OUT chain with a TI DSP. For a device to get its own device ID, the DID signal must be set to 1 (see
the Command Field section for details), and LRCK and BCK must be driven in the TDMCA mode for all PCM devices which
are chained. The device at the top of the chain knows its device ID is 1 because its DCI is fixed HIGH. Other devices count
the BCK pulses and observe their own DCI signal to determine their position and ID. Figure 52 shows the initialization of
each device ID.
IN
DCO
DCI
DCO
DCI
NO Device
NO Device
DCO
•••
DCI
DCO
DCIo
OUT
DCOo
NO Device
IN/OUT
Device
OUT
DCIo
DCO
DCI
DCO
DCI
•••
•••
•••
NO Device
DCI
IN/OUT
Device
OUT Device
DCOi
IN
DCOo
IN Device
OUT Device
DCIi
DCOi
DCIi
•••
IN Device
DCO
DCI
DCO
DCI
IN Chain
OUT Chain
Figure 50. Daisy Chain Connection
43
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
DCII
LRCK
BCK
IN/OUT
Device
(DIX1700)
DCOI
DI
DCIO
DO
DCOO
Device ID = 1
LRCK
BCK
IN Device
(DSD1796)
DI
DO
LRCK
DCI
DCO
Device ID = 2
NO Device
DCI
BCK
DI
DO
DCO
Device ID = 3
•
•
•
FSX
FSR
CLKX
CLKR
DX
DR
LRCK
OUT Device
DCI
BCK
DI
DO
DCO
Device ID = 2
TI DSP
LRCK
OUT Device
DCI
BCK
DI
DO
DCO
Device ID = 3
•
•
•
Figure 51. IN Daisy Chain and OUT Daisy Chain Connection for a Multichip System
44
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
LRCK
BCK
DID
DI
Device ID = 1
DCO1
Device ID = 2
DCO1
DCI2
Command Field
Device ID = 3
DCO2
DCI3
•
•
•
•
•
•
Device ID = 30 DCO29
DCI30
58 BCKs
Figure 52. Device ID Determination Sequence
TDMCA Frame
In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All
of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field. The command
field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of the command field
is HIGH. If any EMD packets are transferred, no audio data follows the EMD packets. This frame is for quick system
initialization. All devices of a daisy chain should respond to the command field and extended command field. The DSD1796
has two audio channels that can be selected by OPE (register 19). If the OPE bit is not set HIGH, those audio channels
are transferred. Figure 53 shows the general TDMCA frame. If some DACs are enabled, but corresponding audio data
packets are not transferred, the analog outputs are unpredictable.
1/fS
LRCK
BCK
[For Initialization]
DI
CMD
EMD
EMD
EMD
EMD
EMD
CMD
CMD
CMD
CMD
CMD
Don’t
Care
CMD
Don’t
Care
CMD
32 Bits
DO
CMD
[For Operation]
DI
CMD
DO
CMD
Ch1
Ch1
Ch2
Ch3
Ch4
Ch(n)
Ch2
Ch3
Ch4
Ch(m)
Figure 53. General TDMCA Frame
45
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
1/fS (256 BCK Clocks)
7 Packets × 32 Bits
LRCK
BCK
DI
Ch1
CMD
Ch2
Ch3
Ch4
Ch5
Ch6
Don’t
Care
CMD
IN and OUT Channel Orders are Completely Independent
DO
Ch1
CMD
Ch2
Figure 54. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read
Command Field
The normal command field is defined as follows. When the DID bit (MSB) is 1, this frame is used only for device ID
determination, and all remaining bits in the field are ignored.
Command
31
30
29
DID
EMD
DCS
28
24
Device ID
23
22
R/W
16
15
Register ID
8
7
Data
0
Not Used
Bit 31: Device ID enable flag
The DSD1796 operates to get its own device ID for TDMCA initialization if this bit is HIGH.
Bit 30: Extended command enable flag
EMD packet is transferred if this bit is HIGH, otherwise skipped. Once this bit is HIGH, this frame does not contain any audio
data. This is for system initialization.
Bit 29: Daisy chain selection flag
HIGH designates OUT-chain devices, LOW designates IN-chain devices. The DSD1796 is an IN device, so the DCS bit
must be set to LOW.
Bits[28:24]: Device ID.
The device ID is 5 bits length, and it can be defined.These bits identify the order of a device in the IN or OUT daisy chain.
The top of the daisy chain defines device ID 1 and successive devices are numbered 2, 3, 4, etc. All devices for which the
DCI is fixed HIGH are also defined as ID 1. The maximum device ID is 30 each in the IN and OUT chains. If a device ID
of 0x1F is used, all devices are selected as broadcast when in the write mode. If a device ID of 0x00 is used, no device
is selected.
Bit 23: Command Read/Write flag
If this bit is HIGH, the command is a read operation.
Bits[22:16]: Register ID
It is 7 bits in length.
Bits[15:8]: Command data
It is 8 bits in length. Any valid data can be chosen for each register.
Bits[7:0]: Not used
These bits are never transported when a read operation is performed.
Extended command field
The extended command field is the same as the command field, except that it does not have a DID flag.
Extended Command
46
31
30
29
Rsvd
EMD
DCS
28
24
Device ID
23
R/W
22
16
Register ID
15
8
Data
7
0
Not Used
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Audio Fields
The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with 0s
as shown in the following example.
31
Audio Data
16
MSB
12
8
24 Bits
7
LSB
4 3
0
All 0s
TDMCA Register Requirements
TDMCA mode requires device ID and audio channel information, previously described. The OPE bit in register 19 indicates
audio channel availability and register 23 indicates the device ID. Register 23 is used only in the TDMCA mode. See the
mode control register map (Table 3).
Register Write/Read Operation
The command supports register write and read operations. If the command requests to read one register, the read data
is transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the positive edge of BCK,
and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle early to compensate for the output
delay caused by high impedance. Figure 55 shows the TDMCA write and read timing.
Register ID Phase
Data Phase
BCK
Read Mode and Proper Register ID
DI
DO
Write Data Retrieved, if Write Mode
Read Data Driven, if Read Mode
1 BCK Early
DOEN
(Internal)
Figure 55. TDMCA Write and Read Operation Timing
TDMCA Mode Operation
DCO specifies the owner of the next audio channel in TDMCA mode operation. When a device retrieves its own audio
channel data, DCO goes HIGH during the last audio channel period. Figure 56 shows the DCO output timing in TDMCA
mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the last audio channel of each
device. Therefore, DCI means the next audio channel is allocated.
If some devices are skipped due to no active audio channel, the skipped devices must notify the next device that the DCO
will be passed through the next DCI. Figure 57 and Figure 58 show DCO timing with skip operation. Figure 59 shows the
ac timing of the daisy chain signals.
47
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
1/fS (384 BCK Clocks)
9 Packets × 32 Bits
LRCK
BCK
IN Daisy Chain
CMD
DI
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch8
Don’t Care
DCI1
DID = 1
DID = 2
DID = 3
DID = 4
DCO1
DCI2
DCO2
DCI3
DCO3
DCI4
DCO4
Figure 56. DCO Output Timing of TDMCA Mode Operation
1/fS (256 BCK Clocks)
5 Packets × 32 Bits
LRCK
BCK
DI
CMD
Ch1
Ch2
Ch15
Ch16
Don’t Care
DCI
DID = 1
DCO
DCI
DID = 2
•
•
•
•
•
•
2 BCK Delay
DCO
•
•
•
14 BCK Delay
DCI
DID = 8
DCO
Figure 57. DCO Output Timing With Skip Operation
48
CMD
CMD
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
Command Packet
LRCK
BCK
DI
DID EMD
DCO1
DCO2
•
•
•
Figure 58. DCO Output Timing With Skip Operation (for Command Packet 1)
49
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
LRCK
t(LB)
t(BL)
BCK
t(BCY)
t(DS)
t(DH)
DI
t(DOE)
DO
t(DS)
t(DH)
DCI
t(COE)
DCO
PARAMETER
t(BCY) BCK pulse cycle time
t(LB)
LRCK setup time
MIN
MAX
UNITS
20
ns
0
ns
t(BL)
t(DS)
LRCK hold time
3
ns
DI setup time
0
ns
t(DH)
t(DS)
DI hold time
3
ns
DCI setup time
0
ns
3
ns
t(DH) DCI hold time
t(DOE) DO output delay(1)
t(COE) DCO output delay(1)
(1) Load capacitance is 10 pF.
Figure 59. AC Timing of Daisy Chain Signals
50
8
ns
6
ns
www.ti.com
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
ANALOG OUTPUT
Table 5 and Figure 60 show the relationship between the digital input code and analog output.
Table 5. Analog Output Current and Voltage
800000 (–FS)
000000 (BPZ)
7FFFFF (+FS)
IOUTN [mA]
IOUTP [mA]
–1.5
–3.5
–5.5
–5.5
–3.5
–1.5
VOUTN [V]
VOUTP [V]
–1.23
–2.87
–4.51
–4.51
–2.87
–1.23
VOUT [V]
–2.98
0
2.98
NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the
measurement circuit of Figure 32.
OUTPUT CURRENT
vs
INPUT CODE
0
IO – Output Current – mA
−1
−2
IOUTN
−3
−4
−5
IOUTP
−6
800000(–FS)
000000(BPZ)
7FFFFF(+FS)
Input Code – Hex
Figure 60. The Relationship Between Digital Input and Analog Output
51
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DSD1796DB
ACTIVE
SSOP
DB
28
47
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DSD1796DBG4
ACTIVE
SSOP
DB
28
47
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DSD1796DBR
ACTIVE
SSOP
DB
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DSD1796DBRG4
ACTIVE
SSOP
DB
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DSD1796DBR
Package Package Pins
Type Drawing
SSOP
DB
28
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
17.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.5
10.8
2.4
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DSD1796DBR
SSOP
DB
28
2000
336.6
336.6
28.6
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DSD1796DB
ACTIVE
SSOP
DB
28
47
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to -40
DSD1796
DSD1796DBR
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to -40
DSD1796
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DSD1796DBR
Package Package Pins
Type Drawing
SSOP
DB
28
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
17.4
Pack Materials-Page 1
8.5
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.8
2.4
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DSD1796DBR
SSOP
DB
28
2000
336.6
336.6
28.6
Pack Materials-Page 2
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
26X 0.65
28
1
2X
10.5
9.9
NOTE 3
8.45
14
15
28X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.15
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
15
14
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising