Texas Instruments | Four Channel Digital Audio Lip-Sync Delay with I2C Control (Rev. A) | Datasheet | Texas Instruments Four Channel Digital Audio Lip-Sync Delay with I2C Control (Rev. A) Datasheet

Texas Instruments Four Channel Digital Audio Lip-Sync Delay with I2C Control (Rev. A) Datasheet
1
05
A5
TP
TPA5051
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SLOS497A – JUNE 2006 – REVISED JULY 2006
FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Digital Audio Format: 16-24-bit I2S,
Right-Justified, Left-Justified
I2C Bus Controlled
Dual Serial Input Ports
Delay Time: 85 ms/ch at fs = 48 kHz
Delay Resolution: One Sample
Delay Memory Cleared on Power-Up or After
Delay Changes
– Eliminates Erroneous Data on Output
3.3 V Operation With 5 V Tolerant I/O and I2C
Control
Supports Audio Bit Clock Rates of 32 to 64 fs
with fs = 32 kHz–192 kHz
No External Crystal or Oscillator Required
– All Internal Clocks Generated From the
Audio Clock
Independent Clocks for Each Audio Input
Surface Mount 4mm × 4mm, 16-pin QFN
Package
High Definition Lip-Sync Delay
Flat Panel TV Lip-Sync Delay
Home Theater Rear Channel Effects
Wireless Speaker Front-Channel
Synchronization
DESCRIPTION
The TPA5051 accepts two serial audio inputs,
buffers the data for a selectable period of time, and
outputs the delayed audio data on two serial outputs.
One device allows delay of up to 85 ms/ch (fs = 48
kHz) to synchronize the audio stream to the video
stream in systems with complex video processing
algorithms. If more delay is needed, the devices can
be connected in series. Independent clocks can be
used for each audio input.
SIMPLIFIED APPLICATION DIAGRAM
Audio Processor
SCLK
LRCLK1
3.3 V
TAS5504A
+ TAS5122
TPA5051
VDD
BCLK1
Digital Amplfiier
BCLK1
GND
TAS3108
or
ATSC
Processor
SCLK
BCLK1
LRCLK1
LRCLK1
DATA1
DATA1
DATA_OUT1
DATA1
DATA2
DATA2
DATA_OUT2
DATA2
BCLK2
BCLK2
BCLK2
LRCLK2
LRCLK2
SDA
SCL
ADDx
(2:0)
LRCLK2
3
I2C Delay
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPA5051
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SLOS497A – JUNE 2006 – REVISED JULY 2006
PIN DESCRIPTIONS
BCLK1
DATA_OUT1
GND
VDD
16
15
14
13
RSA (QFN) PACKAGE
(TOP VIEW)
SCL
3
10
ADD0
SDA
4
9
DATA_OUT2
8
ADD1
BCLK2
11
7
2
LRCLK2
DATA1
6
ADD2
DATA2
12
5
1
GND
LRCLK1
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NO.
ADD0
10
I
I2C address select pin – LSB. 5V tolerant input.
ADD1
11
I
I2C address select pin. 5V tolerant input.
ADD2
12
I
I2C address select pin – MSB. 5V tolerant input.
BCLK1 (1)
16
I
Audio data bit clock input for serial input 1. 5V tolerant input.
BCLK2 (1)
8
I
Audio data bit clock input for serial input 2. 5V tolerant input.
DATA1
2
I
Audio serial data input for serial input 1. 5V tolerant input.
DATA2
6
I
Audio serial data input for serial input 2. 5V tolerant input.
DATA_OUT1
15
O
Delayed audio serial data output for channel 1.
DATA_OUT2
9
O
Delayed audio serial data output for channel 2.
GND
5, 14
P
Ground – All ground terminals must be tied to GND for proper operation
LRCLK1 (1)
1
I
Channel 1 left and right serial audio sampling rate clock (fs). 5V tolerant input.
LRCLK2 (1)
7
I
Channel 2 left and right serial audio sampling rate clock (fs). 5V tolerant input.
SCL
3
I
I2C communication bus clock input. 5V tolerant input.
SDA
4
I/O
I2C communication bus data input. 5V tolerant input.
VDD
13
P
Power supply interface.
-
Connect to ground. Must be soldered down in all applications to properly secure device on the
PCB.
Thermal Pad
(1)
2
I/O
NAME
Left and right channels may use different BCLK frequencies as well as different LRCLK (fs) frequencies.
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FUNCTIONAL BLOCK DIAGRAM
DATA1
DELAY
MEMORY
BCLK1
LRCLK1
DATA_OUT1
OUTPUT
BUFFER
INPUT
BUFFER
DATA2
DELAY
MEMORY
BCLK2
DATA_OUT2
LRCLK2
2
IC
ADDx (2:0)
2
CONTROL
3
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
VDD
Supply voltage
VI
Input voltage
(1)
DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0]
Continuous total power dissipation
VALUE
UNIT
–0.3 to 3.6
V
–0.3 to 5.5
V
See Dissipation Rating Table
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
–40 to 125
°C
Tstg
Storage temperature range
–65 to 125
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS (1)
(1)
PACKAGE
TA≤ 25°C
POWER RATING
DERATING
FACTOR
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
RSA
2.5 W
25 mW/°C
1.375 W
1.0 W
This data was taken using 1 oz trace copper and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad
must be soldered to a thermal land on the printed-circuit board. See TI technical briefs SCBA01D and SLUA271 for more information
about using the QFN thermal pad.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
VDD
Supply voltage
VDD
3
3.6
VIH
High-level input voltage
DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, SDA,
ADD[2:0]
2
VIL
Low-level input voltage
DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, SDA,
ADD[2:0]
TA
Operating free-air temperature
–40
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UNIT
V
V
0.8
V
85
°C
3
TPA5051
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DC CHARACTERISTICS
TA = 25°C, VDD = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDD
Supply current
VDD = 3.3 V, fs = 48 kHz, BCLK = 32 × fs
IOH
High-level output current DATA_OUT1 = DATA_OUT2 = 2.6 V
IOL
Low-level output current
DATA_OUT1 = DATA_OUT2 = 0.4 V
High-level input current
DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL,
SDA, Vi = 5.5V, VDD = 3V
IIH
IIL
Low-level input current
MIN
TYP
MAX
1.8
3
UNIT
mA
5
13
mA
5
13
mA
20
µA
ADD[2:0], Vi = 3.6V, VDD = 3.6V
5
µA
DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL,
SDA, ADD[2:0], Vi = 0V, VDD = 3.6V
1
µA
TIMING CHARACTERISTICS (1) (2)
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
400
kHz
tw(H)
Pulse duration, SCL high
0.6
µs
tw(L)
Pulse duration, SCL low
1.3
µs
tsu1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
10
ns
t(buf)
Bus free time between stop and start condition
1.3
µs
tsu2
Setup time, SCL to start condition
0.6
µs
th2
Hold time, start condition to SCL
0.6
µs
tsu3
Setup time, SCL to stop condition
0.6
µs
VPull-up = VDD
A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage.
tw(L)
tw(H)
SCL
t su1
th1
SDA
Figure 1. SCL and SDA Timing
SCL
th2
t(buf)
tsu2
tsu3
Start Condition
Stop Condition
SDA
Figure 2. Start and Stop Conditions Timing
4
MAX
Frequency, SCL
(1)
(2)
No wait states
TYP
fSCL
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Serial Audio Input Ports
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fSCLKIN Frequency, BCLK 32 × fs, 48 × fs, 64 × fs
MIN
TYP
1.024
MAX
UNIT
12.288
MHz
tsu1
Setup time, LRCLK to BCLK rising edge
10
ns
th1
Hold time, LRCLK from BCLK rising edge
10
ns
tsu2
Setup time, DATA to BCLK rising edge
10
ns
th2
Hold time, DATA from BCLK rising edge
10
ns
LRCLK frequency
32
48
BCLK duty cycle
50%
LRCLK duty cycle
50%
BCLK rising edges between LRCLK rising edges
LRCLK duty cycle = 50%
32
192
kHz
64
BCLK edges
BCLK
(Input)
th1
tsu1
LRCLK
(Input)
th2
tsu2
DATA
Figure 3. Serial Data Interface Timing
APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
The audio serial interface for the TPA5051 consists of two 3-wire synchronous serial ports. Each includes an
LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on
the DATA line into the serial shift register of the audio interface. Serial data is clocked into the TPA5051 on the
rising edge of BCLK. LRCLK is the serial audio left/right word clock, operated at the sampling frequency, fs. It is
used to latch serial data into the internal registers of the serial audio interface. BCLK can be operated at 32 to
64 times the sampling frequency for right-justified, left-justified, and I2S formats. Generally, both LRCLK and
BCLK should be synchronous to the system clock. However, the TPA5051 does not have a system clock, so the
only synchonization necessary is between BCLK and LRCLK.
AUDIO DATA FORMATS AND TIMING
The TPA5051 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The
data formats are shown in Figure 4. Data formats are selected using the I2C interface and register map (see
Table 1).
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APPLICATION INFORMATION (continued)
(1) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
L-Channel
LRCK
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
16-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
14 15 16
1
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
LSB
16-Bit Right-Justified, BCK = 32 f S
DATA
14 15 16
1
2
3
14 15 16
MSB
1
2
LSB
3
14 15 16
MSB
LSB
18-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
16 17 18
1
2
3
16 17 18
MSB
1
LSB
2
3
16 17 18
MSB
LSB
20-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
18 19 20
1
2
3
18 19 20
MSB
1
LSB
2
3
18 19 20
MSB
LSB
24-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
22 23 24
1
2
3
22 23 24
MSB
1
2
LSB
3
22 23 24
MSB
LSB
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
DATA
1
2
3
N–2 N–1
MSB
N
1
2
LSB
3
N–2 N–1
MSB
LSB
1
N
2
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
DATA
1
2
3
MSB
N–2 N–1
N
1
LSB
2
MSB
Figure 4. Audio Data Formats
6
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N–2 N–1
LSB
N
1
2
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APPLICATION INFORMATION (continued)
2
GENERAL I C OPERATION
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions.
A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 5. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then wait for an acknowledge condition. The TPA5051 holds SDA low during acknowledge clock
period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share
the same signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When
the bus level is 5 V, pull-up resistors between 1 kΩ and 2 kΩ in value must be used. For a bus level of 3.3 V,
higher resistor values, such as 10 kΩ, may be used.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 5. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the
last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence
is shown in Figure 5.
The 7-bit address for the TPA5051 is selectable using the 3 address pins (ADD0, ADD1, ADD2). Table 1 lists
the 8 possible slave addresses.
Table 1. I2C Slave Address
SELECTABLE ADDRESS BITS
FIXED ADDRESS
(4 MSB bits)
ADD2
ADD1
ADD0
1101
0
0
0
1101
0
0
1
1101
0
1
0
1101
0
1
1
1101
1
0
0
1101
1
0
1
1101
1
1
0
1101
1
1
1
SINGLE-AND MULTIPLE-BYTE TRANSFERS
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA5051 responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
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The TPA5051 supports sequential I2C addressing. For write transactions, if a register is issued followed by data
for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For
I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
SINGLE-BYTE WRITE
As shown is Figure 6, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TPA5051 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TPA5051 internal memory address being accessed. After
receiving the register byte, the TPA5051 again responds with an acknowledge bit. Next, the master device
transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the
TPA5051 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to
complete the single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
I2C Device Address and
Read/Write Bit
A5
A4
A3
A2
A1
A0 ACK D7
Acknowledge
D6
D5
Register
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
Figure 6. Single-Byte Write Transfer
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA5051 as shown in Figure 7. After receiving each data byte, the
TPA5051 responds with an acknowledge bit.
Register
Figure 7. Multiple-Byte Write Transfer
SINGLE-BYTE READ
As shown in Figure 8, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA5051 address and the read/write bit, the TPA5051 responds with an acknowledge bit.
The master then sends the internal memory address byte, after which the TPA5051 issues an acknowledge bit.
The master device transmits another start condition followed by the TPA5051 address and the read/write bit
again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA5051 transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a
not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
8
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Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A4
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
D6
I2C Device Address and
Read/Write Bit
Register
D1
D0 ACK
Stop
Condition
Data Byte
Figure 8. Single-Byte Read Transfer
MULTIPLE-BYTE READ
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA5051 to the master device as shown in Figure 9. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Acknowledge
A0 ACK
A6
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Register
Acknowledge
D0
ACK D7
First Data Byte
Acknowledge
Not
Acknowledge
D0 ACK D7
D0 ACK
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 9. Multiple-Byte Read Transfer
TPA5051 Operation
The following sections describe the registers configurable via I2C commands for the TPA5051.
Only a single decoupling capacitor (0.1 µF–1 µF) is required across VDD and GND. The ADDx terminals can be
directly connected to VDD or GND. Table 1 describes the I2C addresses selectable via the ADDx terminals. A
schematic implementation of the TPA5051 is shown in Figure 10.
3.3 V
0.1 mF
VDD
Digital Audio1
Word Clock1
DATA_OUT1
Delayed Audio1
DATA_OUT2
Delayed Audio2
2
DATA1
SDA
I C Data
LRCLK1
SCL
I C Clock
Bit Clock1
BCLK1
ADD0
Digital Audio2
DATA2
ADD1
LRCLK2
ADD2
2
2
Word Clock2
Bit Clock2
BCLK2
I C Address
Select
GND
GND
Figure 10. TPA5051 Schematic
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SERIAL CONTROL INTERFACE REGISTER SUMMARY
Table 2. Serial Control Register Summary
REGISTER
REGISTER NAME
NO. OF
BYTES
CONTENTS
INITIALIZATION
VALUE
0x01 (1)
Control Register
1
Description shown in subsequent section
00
0x02 (1)
Right Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x03 (1)
Right Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x04 (1)
Left Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x05 (1)
Left Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x06 (1)
Frame Delay
1
Description shown in subsequent section
00
0x07 (1)
RJ Packet Length
1
Description shown in subsequent section
00
0x08 (1)
Complete Update
1
Description shown in subsequent section
00
0x09 (2)
Control Register
1
Description shown in subsequent section
00
0x0A (2)
Right Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x0B (2)
Right Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x0C (2)
Left Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x0D (2)
Left Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x0E (2)
Frame Delay
1
Description shown in subsequent section
00
0x0F (2)
RJ Packet Length
1
Description shown in subsequent section
00
0x10 (2)
Complete Update
1
Description shown in subsequent section
00
I2C registers for serial data channel 1
I2C registers for serial data channel 2
(1)
(2)
CONTROL REGISTER (0x01, 0x09)
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I2S,
Right-Justified, or Left-Justified).
Table 3. Control Registers (0x01, 0x09) (1)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
X
X
X
X
–
–
Left and Right channel are active.
0
1
X
X
X
X
–
–
Left channel is MUTED.
1
0
X
X
X
X
–
–
Right channel is MUTED.
1
1
X
X
X
X
–
–
Left and Right channel are MUTED.
–
–
X
X
X
X
0
0
I2S data format
–
–
X
X
X
X
0
1
Right-justified data format (see PACKET LENGTH register 0x07)
–
–
X
X
X
X
1
0
Left-justified data format
–
–
X
X
X
X
1
1
Bypass mode – data is passed straight through without delay.
(1)
FUNCTION
Default values are in bold.
AUDIO DELAY REGISTERS (0x02–0x05, 0x0A–0x0D)
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and
lower registers as specified in Table 1. A multiple byte transfer should be performed starting with the control
register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.
The decimal value of D0–D13 equals the number of samples to delay. The maximum number of delayed
samples per channel is 4095 for the TPA5051. This equates to 85.3 ms ([4095 × (1/Fs)] at 48 kHz) of delay per
channel.
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Table 4. Audio Delay Registers (0x02–0x05, 0x0A–0x0D) (1)
D13
D12
D11–D2
D1
D0
0
0
0
0
0
Left and Right audio is passed to output with no delay.
0
0
0
0
1
Left and Right audio is delayed by 1 sample (1/Fs = delay time)
1
1
1
1
1
Left and Right audio is delayed by 4095 samples (4095/Fs = delay time)
(1)
FUNCTION
Default values are in bold.
FRAME DELAY REGISTERS (0x06, 0x0E)
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,
the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delay
based on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
The total audio delay time is calculated by the following formula:
Audio Delay (in samples) = int [# Delay Frames × (1/Frame Rate) × Audio Sample Rate]
If the result of the formula above is greater than the maximum number of delay samples (4095 for TPA5051),
then the value is limited to this maximum before passing to the delay block.
Table 5. Frame Delay Registers (0x06, 0x0E) (1)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Settings in this register are masked and audio delay is determined by
settings in the right/left audio delay registers.
1
Right/left audio delay registers are masked and delay is determined by settings in
this register.
(1)
0
Frame rate = 50 Hz
1
Frame rate = 59.94 Hz
0
0
0
Audio sample rate = 32 kHz
0
0
1
Audio sample rate = 44.1 kHz
0
1
0
Audio sample rate = 48 kHz
0
1
1
Audio sample rate = 88.2 kHz
1
0
0
Audio sample rate = 96 kHz
1
0
1
Audio sample rate = 176.4 kHz
1
1
0
Audio sample rate = 192 kHz
1
1
1
Audio sample rate = 192 kHz
0
0
0
Delay frames = 1
0
0
1
Delay frames = 2
1
1
1
Delay frames = 8
Default values are in bold.
RJ PACKET LENGTH REGISTERS (0x07, 0x0F)
This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of the
useable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions must
be greater than or equal to the packet length selected in this register. The maximum packet length value is 24
bits. Any setting greater whose numerical value is greater than 24 bits is limited to the maximum 24 bits.
Table 6. RJ Package Length (0x07, 0x0F) (1)
(1)
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
Packet length = 0 bits
FUNCTION
0
0
0
0
0
1
Packet length = 1 bits
0
1
1
X
X
X
Packet length = 24 bits
Default values are in bold.
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11
TPA5051
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SLOS497A – JUNE 2006 – REVISED JULY 2006
COMPLETE UPDATE REGISTER (0x08, 0x10)
Since the audio delay values are divided among several registers, it is likely that multiple writes would be
necessary to configure the device. This may cause interruptions in the audio stream and unwanted pops and
clicks might occur as register data is passed to delay functional block.
To avoid this from happening, the Complete Update register is used to transfer the user settings from the
register file to the delay functional block when a 1 is written to the LSB. For example, if the right delay is set to
35 samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until 35
samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data have
passed.
The Complete Update register must also be used when either the stream type is changed or the RJ packet
length is changed. If a complete update command is not issued, the changes will not take effect.
Note that the individual channels can be muted using the upper bits of the Control Registers without writing to
the Complete Update registers.
Table 7. Complete Update Registers (0x08, 0x10) (1)
D7–D1
(1)
D0
FUNCTION
X
0
No data from the register settings is passed to the delay block.
X
1
Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block.
Default values are in bold.
APPLICATION EXAMPLES
Connecting Two Devices in Series to Increase the Delay
It is sometimes desirable to increase the delay time beyond which one device can provide. In such cases,
several TPA5051 devices can be placed in series to increase the delay. A maximum of eight devices can be
placed in series. This is because each device has eight I2 address settings. Under no circumstances should two
TPA5051 devices share the same I2S address. See Figure 11.
0.1 mF
LRCLK1
LRCLK1
LRCLK1
DATA1
DATA1
DATA2
DATA2
BCLK2
DATA_OUT1
DATA1
DATA_OUT2
DATA2
BCLK2
LRCLK2
LRCLK2
DATA_OUT1
DATA_OUT2
DATA1
DATA2
BCLK2
LRCLK2
LRCLK2
BCLK2
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ADD0
SCL
ADD1
SDA
ADD2
ADD0
SCL
ADD1
SDA
SCL
SCLK
Figure 11. Two Devices Connected in Series
12
BCLK1
LRCLK1
2 kW
SDA
ADD2
2 kW
BCLK1
Audio
Amplifier
GND
BCLK1
VDD
VDD
BCLK1
GND
0.1 mF
Audio
Processor
SCLK
TPA5051
www.ti.com
SLOS497A – JUNE 2006 – REVISED JULY 2006
2
I C Examples
The following are some examples of I2C commands used to read or write to the TPA5051. For all conditions,
assume the address of the TPA5051 is set to 001.
Single Byte Write
In this example, the TPA5051 is set to mute both left and right channels of DATA1, and to operate in I2S mode.
Start
D2
ACK
TPA5051 Address and
Write
01
ACK
C0
Register Address
ACK
Stop
Data
NOTE:
Because no complete update command was issued in this example, the stream type
change will not take effect until a 1 is written to the Complete Update register.
Multiple Byte Write
In this example, the TPA5051 is set to make both the left and right channels of both DATA1 and DATA2 active.
DATA1 is set to operate in I2S mode, delay the right channel by 1024 samples, and delay the left channel by
2048 samples. DATA2 is set to operate in the Right-Justified mode with a packet length of 16 bits. It is to delay
the audio signal by 40 ms using the Frame Delay function. Assume the audio sample rate (fs) = 48 kHz, and the
Frame rate = 50 Hz. This is a sequential write, so all registers must have data written to them.
Start
D2
ACK
TPA5051 Address and
Write
08
Register Address
(Control Register
DATA1)
ACK
Data
(Control Register
DATA2)
91
Data
(Frame Delay
DATA2)
ACK
ACK
00
ACK
00
ACK
10
Data
(RJ Packet = 16 Bits
DATA2)
00
04
ACK
00
ACK
00
ACK
Data
(RJ Packet = 0 Bits
DATA1)
ACK
Data
(Right Delay Lower Bits
DATA2)
01
ACK
Data
(Right Delay Upper Bits
DATA1)
Data
(Frame Delay
DATA1)
Data
(Right Delay Upper Bits
DATA2)
ACK
00
Data
(Control Register
DATA1)
Data
(Left Delay Lower Bits
DATA1)
Data
(Left Delay Upper Bits
DATA1)
10
ACK
01
ACK
00
00
ACK
Data
(Right Delay Lower Bits
DATA1)
01
ACK
Data
(Complete Update
DATA1)
ACK
Data
(Left Delay Upper Bits
DATA2)
00
ACK
Data
(Left Delay Lower Bits
DATA2)
Stop
Data
(Complete Update
DATA2)
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TPA5051
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SLOS497A – JUNE 2006 – REVISED JULY 2006
Combination of Single Byte Writes
In this example, DATA1 set to operate in the I2S mode, and DATA2 is set to mute.
Start
D2
ACK
TPA5051 Address and
Write
Start
D2
01
09
00
ACK
Register Address
(Control Register
DATA2)
ACK
Stop
Data
(Control Register
DATA1)
Register Address
(Control Register
DATA1)
ACK
TPA5051 Address and
Write
ACK
C0
ACK
Stop
Data
(Control Register
DATA2)
Note that in every circumstance where a delay or stream type is written into the memory of the TPA5051, a 1
must be written to the Complete Update registers for the change to take effect. In this example, the stream type
change made to DATA1 would not take effect. This does not apply to muting, which occurs in the Control
registers.
Single Byte Read
In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx) by is
read by the master device, the master device issues a Not Acknowledge, before stopping the communication.
Start
D2
TPA5051 Address and
Write
14
ACK
01
Register Address
(Control Register
DATA1)
ACK
Start
D3
ACK
TPA5051 Address and
Read
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XX
Data Read
(Control Register
DATA1)
No
ACK
Stop
TPA5051
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SLOS497A – JUNE 2006 – REVISED JULY 2006
Multiple Byte Read
Often, when it is necessary to read what is contained in one register, it is necessary to determine what
information is contained in all registers. In such a case, a sequential read should be used. In situations where
data must be read from a register at the beginning (0x01), and a register towards the end (0x0E), a sequential
read is likely to be faster to implement than multiple single byte reads.
In this example, a sequential read is initiated with the Control Register (0x01), and ends with the Frame Delay
Register (0x0E).
Start
D2
ACK
TPA5051 Address and
Write
XX
ACK
01
Start
Register Address
(Control Register
DATA1)
ACK
Data Read
(Right Delay Upper Bits
DATA1)
XX
Data Read
(RJ Packet Length
DATA1)
XX
Data Read
(Left Delay Upper Bits
DATA2)
TPA5051 Address and
Read
ACK
XX
Data Read
(Right Delay Lower Bits
DATA1)
ACK
ACK
XX
ACK
XX
Data Read
(Left Delay Lower Bits
DATA2)
XX
XX
XX
Data Read
(Control Register
DATA1)
ACK
XX
ACK
Data Read
(Right Delay Upper Bits
DATA2)
NO ACK
XX
ACK
Data Read
(Frame Delay
DATA1)
Data Read
(Left Delay Lower Bits
DATA1)
ACK
ACK
XX
XX
ACK
Data Read
(Left Delay Upper Bits
DATA1)
Data Read
(Control Register
DATA2)
Data Read
(Complete Update
DATA1)
ACK
ACK
D3
XX
ACK
Data Read
(Right Delay Lower Bits
DATA2)
Stop
Data Read
(Frame Delay
DATA2)
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15
TPA5051
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SLOS497A – JUNE 2006 – REVISED JULY 2006
DEVICE CURRENT CONSUMPTION
The TPA5051 draws different amounts of supply current depending upon the conditions under which it is
operated. As VDD increases, so too does IDD. Likewise, as VDD decreases, IDD decreases. The same is true of
the sampling frequency, fs. An increase in fs causes an increase in IDD. Figure 12 illustrates the relationship
between operating condition and typical supply current.
SUPPLY CURRENT
vs
SAMPLING FREQUENCY
5
IDD - Supply Current - mA
4.5
BCLK = 64 fs
Data = 24 bit
VDD = 3.6 V
4
3.5
3
2.5
VDD = 3.3 V
2
VDD = 3 V
1.5
1
0.5
0
32
52
72
92
112
132
152
172
fs - Sampling Frequency - kHz
Figure 12. Typical Supply Current
16
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192
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA5051RSAR
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA
5051
TPA5051RSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA
5051
TPA5051RSATG4
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA
5051
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPA5051RSAR
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TPA5051RSAT
QFN
RSA
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA5051RSAR
QFN
RSA
16
3000
367.0
367.0
35.0
TPA5051RSAT
QFN
RSA
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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