Texas Instruments | PCM4104: High-Performance, 24-Bit, 216kHz Sampling, Four-Channel Audio D/A Conv (Rev. C) | Datasheet | Texas Instruments PCM4104: High-Performance, 24-Bit, 216kHz Sampling, Four-Channel Audio D/A Conv (Rev. C) Datasheet

Texas Instruments PCM4104: High-Performance, 24-Bit, 216kHz Sampling, Four-Channel Audio D/A Conv (Rev. C) Datasheet
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
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FEATURES
D Four High-Performance, Multi-Level,
Delta-Sigma Digital-to-Analog Converters
D Differential Voltage Outputs
− Full-Scale Output (Differential): 6.15VPP
D Supports Sampling Frequencies up to 216kHz
D Typical Dynamic Performance (24-Bit Data)
D
D
D
− Dynamic Range (A-Weighted): 118dB
− THD+N: −100dB
Linear Phase, 8x Oversampling Digital
Interpolation Filter
Digital De-Emphasis Filters for 32kHz,
44.1kHz, and 48kHz Sampling Rates
Soft Mute Function
− All-Channel Mute via the MUTE Input Pin
− Per-Channel Mute Available in Software
Mode
The PCM4104 is a high-performance, four-channel
digital-to-analog (D/A) converter designed for use in
professional audio applications. The PCM4104 supports
16- to 24-bit linear PCM input data, with sampling
frequencies up to 216kHz. The PCM4104 features lower
power consumption than most comparable stereo audio
D/A converters, making it ideal for use in high channel
count applications by lowering the overall power budget
required for the D/A conversion sub-system.
− Attenuation Range: 0dB to −119.5dB
− 256 Steps with 0.5dB per Step
D Output Phase Inversion (Software Mode Only)
D Zero Data Mute (Software Mode Only)
D Audio Serial Port
D Standalone or Software-Controlled
Configuration Modes
D Four-Wire Serial Peripheral Interface (SPIE)
Port Provides Control Register Access in
Software Mode
D Power Supplies: +5V Analog, +3.3V Digital
D Power Dissipation
− 203mW typical with fS = 48kHz
− 220mW typical with fS = 96kHz
− 236mW typical with fS = 192kHz
D Power-Down Modes
D Small 48-Lead TQFP Package
APPLICATIONS
D Digital Mixing Consoles
D Digital Audio Workstations
D Digital Audio Effects Processors
D Broadcast Studio Equipment
D Surround-Sound Processors
D High-End A/V Receivers
DESCRIPTION
D Digital Attenuation (Software Mode Only)
− Supports Left-Justified, Right-Justified,
I2SE, and TDM Data Formats
− Accepts 16-, 18-, 20, and 24-Bit Two’s
Complement PCM Audio Data
The PCM4104 features delta-sigma architecture,
employing a high-performance multi-level modulator
combined with a switched capacitor output filter. This
architecture yields lower out-of-band noise and a high
tolerance to system clock phase jitter. Differential voltage
outputs are provided for each channel and are well-suited
to high-performance audio applications. The differential
outputs are easily converted to a single-ended output
using an external op amp IC.
The PCM4104 includes a flexible audio serial port
interface, which supports standard and time division
multiplexed (TDM) formats. Support for TDM formats
simplifies interfacing to DSP serial ports, while supporting
a cascade connection for two PCM4104 devices. In
addition, the PCM4104 offers two configuration modes:
Standalone and Software-Controlled. The Standalone
mode provides dedicated control pins for configuring a
subset of the available PCM4104 functions, while
Software mode utilizes a serial peripheral interface (SPI)
port for accessing the complete feature set via internal
control registers.
The PCM4104 operates from a +5V analog power supply
and a +3.3V digital power supply. The digital I/O is
compatible with +3.3V logic families. The PCM4104 is
available in a TQFP-48 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2003−2004, Texas Instruments Incorporated
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
ORDERING INFORMATION(1)
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PCM4104
TQFP-48
PFB
−10°C to +70°C
PCM4104PFB
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PCM4104PFBT
Tape and Reel, 250
PCM4104PFBR
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to
our web site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PCM4104
UNIT
VCC
VDD
+6.0
V
Supply voltage
+3.6
V
Ground voltage difference
Any AGND-to-AGND and AGND-to-DGND
±0.1
V
Digital input voltage
FS0, FS1, FMT0, FMT1, FMT2, CDOUT,
CDIN, CCLK, CS, DATA0, DATA1, BCK,
LRCK, SCKI, SUB, DEM0, DEM1, MUTE,
RST, MODE
−0.3 to (VDD + 0.3)
V
±10
mA
−10 to +70
°C
Input current (any pin except supplies)
Operating temperature range
Storage temperature range, TSTG
−65 to +150
°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
2
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
PCM4104
PARAMETER
CONDITIONS
MIN
RESOLUTION
TYP
MAX
24
UNITS
Bits
DATA FORMAT
Left or Right Justified, I2S, and TDM
Audio data formats
Audio data word length
16
Binary data format
24
Bits
Two’s Complement Binary, MSB First
CLOCK RATES AND TIMING
System clock frequency
fSCKI
Sampling frequency
fS
SPI port data clock
Single rate sampling mode
6.144
36.864
MHz
Dual rate sampling mode
13.824
36.864
MHz
Quad rate sampling mode
13.824
36.864
MHz
Single rate sampling mode
24
54
kHz
Dual rate sampling mode
54
108
kHz
Quad rate sampling mode
108
216
kHz
24
MHz
fCCLK
SPI port data clock high time
tCCLKH
15
ns
SPI port data clock low time
tCCLKL
15
ns
DIGITAL INPUT/OUTPUT
Input logic level
Input logic current
Output logic level
VIH
2.0
V
VIL
0.8
V
IIH
VIN = VDD
1
10
µA
IIL
VIN = 0V
1
−10
µA
VOH
IOH = −2mA
VOL
IOH = +2mA
2.4
V
0.4
V
ANALOG OUTPUTS
Full-scale output voltage, differential
RL = 600Ω
Bipolar zero voltage
Output impedance
Switched capacitor filter frequency response
f = 20kHz, all sampling modes
6.15
VPP
2.5
V
5
Ohms
−0.2
dB
Gain error
0.5
% FSR
Gain mismatch, channel-to-channel
0.6
% FSR
1
mV
2.5
V
Bipolar zero error
VCOM1 and VCOM2 output voltage
VCOM1 and VCOM2 output current
VCC = +5V
200
µA
3
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
PCM4104
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
−100
−94
dB
DYNAMIC PERFORMANCE WITH 24-BIT DATA(1)
fS = 48kHz
f = 1kHz at 0dBFS
Total harmonic distortion + noise
THD+N
f = 1kHz at −60dBFS
Dynamic range, A-weighted
f = 1kHz at −60dBFS
Idle channel SNR, A-weighted
All zero input data
Idle channel SNR, unweighted
All zero input data
Channel separation
f = 1kHz at 0dBFS for active channel
112
100
−56
dB
118
dB
119
dB
116
dB
110
dB
fS = 96kHz
f = 1kHz at 0dBFS, BW = 10Hz to 40kHz
−100
dB
f = 1kHz at −60dBFS, BW = 10Hz to 40kHz
−53
dB
Dynamic range, A-weighted
f = 1kHz at −60dBFS
118
dB
Idle channel SNR, A-weighted
All zero input data
119
dB
Idle channel SNR, unweighted
All zero input data, BW = 10Hz to 40kHz
113
dB
Channel separation
f = 1kHz at 0dBFS for active channel
110
dB
Total harmonic distortion + noise
THD+N
fs = 192kHz
f = 1kHz at 0dBFS, BW = 10Hz to 40kHz
−97
dB
f = 1kHz at −60dBFS, BW = 10Hz to 40kHz
−53
dB
Dynamic range, A-weighted
f = 1kHz at −60dBFS
118
dB
Idle channel SNR, A-weighted
All zero input data
118
dB
Idle channel SNR, unweighted
All zero input data, BW = 10Hz to 40kHz
113
dB
Channel separation
f = 1kHz at 0dBFS for active channel
110
dB
f = 1kHz at 0dBFS
−92
dB
f = 1kHz at −60dBFS
−33
dB
Total harmonic distortion + noise
THD+N
DYNAMIC PERFORMANCE WITH 16-BIT DATA
fs = 44.1kHz
Total harmonic distortion + noise
THD+N
Dynamic Range, A-weighted
f = 1kHz at −60dBFS
96
dB
Idle channel SNR, A-weighted(2)
All zero input data
118
dB
Idle channel SNR, unweighted(2)
All zero input data
115
dB
(1) Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. Input data word
length is 24 bits with triangular PDF dither added for dynamic range and THD+N tests. Idle channel SNR is measured with both the soft and
zero data mute functions disabled and 0% full-scale input data with no dither applied. The measurement bandwidth is limited by using the Audio
Precision 10Hz high-pass filter in combination with either the AES17 20kHz low-pass filter or AES17 40kHz low-pass filter. All A-weighted
measurements are performed using the Audio Precision A-weighting filter in combination with either the 22kHz or 80kHz low-pass filter.
Measurement mode is set to RMS for all parameters. The AVERAGE measurement mode will yield better typical performance numbers.
(2) Idle Channel SNR is not limited by word length.
4
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
PCM4104
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
±0.002dB
0.454fS
Hz
−3dB
0.487fS
Hz
DIGITAL FILTERS
Passband
Stop Band
0.546fs
Hz
±0.002
Passband ripple
Stopband attenuation
0.546fs
−75
0.567fs
−82
Group delay
dB
dB
dB
29/fS
De-emphasis filter error
sec
0.1
dB
POWER SUPPLY
Supply Range
Analog supply, VCC
+4.75
+5.0
+5.25
V
Digital supply, VDD
+3.0
+3.3
+3.6
V
Power down current
Power-down supply current, ICC + IDD
Quiescent current
Analog supply, ICC
Digital supply, IDD
VCC = +5V, VDD = +3.3V
RST = low, system and audio clocks off
1
mA
System and audio clocks applied, all 0s data
VCC = +5V, fS =48kHz
32
VCC = +5V, fS =96kHz
32
40
mA
VCC = +5V, fS =192kHz
32
mA
VDD = +3.3V, fS =48kHz
13
VDD = +3.3V, fS =96kHz
18
mA
VDD = +3.3V, fS =192kHz
23
mA
17
mA
mA
VCC = +5V, VDD = +3.3V
Total power dissipation
fS = 48kHz
203
256
mW
fS = 96kHz
220
mW
fS = 192kHz
236
mW
5
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
PIN ASSIGNMENTS
VCOM2
43
VOUT3+
44
VOUT3−
VREF2+
45
VCC2
VCC1
46
VREF3+
VOUT2−
47
VREF3−
VOUT2+
48
VREF2−
VCOM1
TQFP PACKAGE
(TOP VIEW)
42
41
40
39
38
37
VOUT1+
1
36 VOUT4+
VOUT1−
2
35 VOUT4−
AGND1
3
34 AGND2
VREF1−
4
33 VREF4−
VREF1+
5
32 VREF4+
NC
6
NC
7
30 NC
MODE
8
29 FS1
RST
9
28 FS0
31 NC
PCM4104
16
17
18
19
20
21
VDD
DGND
CS
22
23
24
CDOUT
15
CDIN
14
CCLK
13
DATA1
25 FMT0
DATA0
DEM0 12
LRCK
26 FMT1
BCK
DEM1 11
SCKI
27 FMT2
SUB
MUTE 10
Terminal Functions
TERMINAL
NAME
NO.
I/O
VOUT1+
VOUT1−
1
Output
Channel 1 Analog Output, Noninverted
2
Output
Channel 1 Analog Output, Inverted
AGND1
3
Ground
Analog Ground
VREF1−
4
Input
Channel 1 Low Reference Voltage; Connect to AGND
VREF1+
5
Input
Channel 1 High Reference Voltage; Connect to VCC
NC
6
NC
7
MODE
8
Input
Operating Mode (0 = Standalone, 1= Software Controlled)
RST
9
Input
Reset/Power Down (Active Low)
MUTE
10
Input
All−Channel Soft Mute (Active High)
DEM1
11
Input
Digital De-Emphasis Filter Configuration
DEM0
12
Input
Digital De-Emphasis Filter Configuration
SUB
13
Input
Sub-Frame Assignment (TDM Formats Only)
SCKI
14
Input
System Clock
6
DESCRIPTION
No Internal Connection
No Internal Connection
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
BCK
15
Input
Audio Bit (or Data) Clock
DESCRIPTION
LRCK
16
Input
Audio Left/Right (or Word) Clock
DATA0
17
Input
Audio Data for Channels 1 and 2 (I2S, Left/Right Justified formats)
or Audio Data for Channels 1 Through 4 for TDM Formats
DATA1
18
Input
Audio Data for Channels 3 and 4 (I2S, Left/Right Justified formats)
VDD
19
Power
Digital Power Supply, +3.3V
DGND
20
Ground
Digital Ground
CS
21
Input
Serial Peripheral Interface (SPI) Chip Select (Active Low)
CCLK
22
Input
Serial Peripheral Interface (SPI) Data Clock
CDIN
23
Input
Serial Peripheral Interface (SPI) Data Input
CDOUT
24
Output
FMT0
25
Input
Audio Data Format Configuration
FMT1
26
Input
Audio Data Format Configuration
FMT2
27
Input
Audio Data Format Configuration
FS0
28
Input
Sampling Mode Configuration
FS1
29
Input
Sampling Mode Configuration
NC
30
No Internal Connection
NC
31
No Internal Connection
VREF4+
32
Input
Channel 4 High Reference Voltage; Connect to VCC
VREF4−
33
Input
Channel 4 Low Reference Voltage; Connect to AGND
AGND2
34
Ground
Analog Ground
VOUT4−
35
Output
Channel 4 Analog Output, Inverted
VOUT4+
36
Output
Channel 4 Analog Output, Noninverted
VCOM2
37
Output
DC Common-Mode Voltage for Channels 3 and 4, +2.5V nominal
VOUT3+
38
Output
Channel 3 Analog Output, Noninverted
VOUT3−
39
Output
Channel 3 Analog Output, Inverted
VCC2
40
Power
Analog Power Supply, +5V
VREF3+
41
Input
Channel 3 High Reference Voltage; Connect to VCC
VREF3−
42
Input
Channel 3 Low Reference Voltage,; Connect to AGND
VREF2−
43
Input
Channel 2 Low Reference Voltage; Connect to AGND
VREF2+
44
Input
Channel 2 High Reference Voltage; Connect to VCC
VCC1
45
Power
Analog Power Supply, +5V
VOUT2−
46
Output
Channel 2 Analog Output, Inverted
VOUT2+
47
Output
Channel 2 Analog Output, Noninverted
VCOM1
48
Output
DC Common-Mode Voltage for Channels 1 and 2, +2.5V nominal
Serial Peripheral Interface (SPI) Data Output
7
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
FFT PLOT
fS = 48kHz
fIN = 1kHz
0dBFS Amplitude
24−Bit Data
Amplitude (dB)
Amplitude (dB)
FFT PLOT
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
20
100
1k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
10k 20k
fS = 48kHz
fIN = 1kHz
−20dBFS Amplitude
24−Bit Data
20
100
Frequency (Hz)
Amplitude (dB)
Amplitude (dB)
fS = 48kHz
fIN = 1kHz
−60dBFS Amplitude
24−Bit Data
20
100
1k
10k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
20
20k
100
Amplitude (dB)
Amplitude (dB)
1k
Frequency (Hz)
8
10k
20k
FFT PLOT
fS = 96kHz
fIN = 1kHz
0dBFS Amplitude
24−Bit Data
100
1k
Frequency (Hz)
FFT PLOT
20
20k
fS = 48kHz
Idle Channel Input
24−Bit Data
Frequency (Hz)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
10k
FFT PLOT
FFT PLOT
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
1k
Frequency (Hz)
10k
40k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
fS = 96kHz
fIN = 1kHz
−20dBFS Amplitude
24−Bit Data
20
100
1k
Frequency (Hz)
10k
40k
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
FFT PLOT
fS = 96kHz
fIN = 1kHz
−60dBFS Amplitude
24−Bit Data
Amplitude (dB)
Amplitude (dB)
FFT PLOT
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
20
100
1k
10k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
40k
fS = 96kHz
Idle Channel Input
24−Bit Data
20
100
Frequency (Hz)
fS = 192kHz
fIN = 1kHz
0dBFS Amplitude
24−Bit Data
20
100
1k
10k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
40k
20
100
Amplitude (dB)
Amplitude (dB)
1k
Frequency (Hz)
10k
40k
10k
40k
FFT PLOT
fS = 192kHz
fIN = 1kHz
−60dBFS Amplitude
24−Bit Data
100
1k
Frequency (Hz)
FFT PLOT
20
40k
fS = 192kHz
fIN = 1kHz
−20dBFS Amplitude
24−Bit Data
Frequency (Hz)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
10k
FFT PLOT
Amplitude (dB)
Amplitude (dB)
FFT PLOT
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
1k
Frequency (Hz)
10k
40k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
fS = 192kHz
Idle Channel Input
24−Bit Data
20
100
1k
Frequency (Hz)
9
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
FFT PLOT
fS = 44.1kHz
fIN = 1kHz
0dBFS Amplitude
16−Bit Data
Amplitude (dB)
20
100
1k
10k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
20k
fS = 44.1kHz
fIN = 1kHz
−20dBFS Amplitude
16−Bit Data
20
100
1k
Frequency (Hz)
fS = 44.1kHz
fIN = 1kHz
−60dBFS Amplitude
16−Bit Data
20
100
1k
10k
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
20k
20
100
1k
THD+N vs AMPLITUDE
−80
fS = 48kHz
fIN = 1kHz
24−Bit Data
−85
−90
−95
−105
Amplitude (dBFS)
Amplitude (dBFS)
0
−10
−20
−30
−40
−50
−60
−70
−80
−100
−110
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−120
−130
−120
−140
−115
−150
−115
−120
−110
−130
−105
−100
−140
−100
−110
10
fS = 96kHz
fIN = 1kHz
24−Bit Data
−150
−95
THD+N (dB)
THD+N (dB)
−90
20k
Frequency (Hz)
THD+N vs AMPLITUDE
−85
10k
fS = 44.1kHz
Idle Channel Input
16−Bit Data
Frequency (Hz)
−80
20k
FFT PLOT
Amplitude (dB)
Amplitude (dB)
FFT PLOT
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
10k
Frequency (Hz)
−90
Amplitude (dB)
FFT PLOT
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
THD+N vs AMPLITUDE
−80
THD+N vs AMPLITUDE
−80
fS = 192kHz
fIN = 1kHz
24−Bit Data
−85
−90
−90
−95
Amplitude (dBFS)
FREQUENCY RESPONSE
0
−10
−20
−30
−40
−50
−60
−70
PASSBAND RIPPLE
0.003
−20
0.002
−40
−60
Amplitude (dB)
Amplitude (dB)
−80
Amplitude (dBFS)
0
−80
−100
−120
0.001
0
−0.001
−0.002
−140
−160
−0.003
0
1
2
3
4
0
0.1
0.2
Frequency (x fS)
0.3
0.4
0.5
Frequency (x fS)
DE−EMPHASIS FILTER RESPONSE (fS = 32kHz)
DE−EMPHASIS ERROR (f S = 32kHz)
0.0
0.5
−1.0
0.4
−2.0
0.3
−3.0
0.2
−4.0
0.1
Error (dB)
Level (dB)
−90
−150
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−120
−130
−120
−140
−115
−150
−115
−100
−110
−110
−110
−105
−120
−105
−100
−130
−100
−140
THD+N (dB)
−95
THD+N (dB)
fS = 44.1kHz
fIN = 1kHz
16−Bit Data
−85
−5.0
−6.0
0.0
−0.1
−7.0
−0.2
−8.0
−0.3
−9.0
−0.4
−0.5
−10.0
0
2
4
6
8
Frequency (kHz)
10
12
14
0
2
4
6
8
10
12
14
Frequency (kHz)
11
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TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
DE−EMPHASIS ERROR (f S = 44.1kHz)
0.5
−1.0
0.4
−2.0
0.3
−3.0
0.2
−4.0
0.1
Error (dB)
Level (dB)
DE−EMPHASIS FILTER RESPONSE (fS = 44.1kHz)
0.0
−5.0
−6.0
0.0
−0.1
−7.0
−0.2
−8.0
−0.3
−9.0
−0.4
−0.5
−10.0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
Frequency (kHz)
10
12
14
16
18
20
18
22
DE− EMPHASIS ERROR (fS = 48kHz)
0.0
0.5
−1.0
0.4
−2.0
0.3
−3.0
0.2
−4.0
0.1
Error (dB)
Level (dB)
DE− EMPHASIS FILTER RESPONSE (fS = 48kHz)
−5.0
−6.0
0.0
−0.1
−7.0
−0.2
−8.0
−0.3
−9.0
−0.4
−0.5
−10.0
0
2
4
6
8
10
12
Frequency (kHz)
12
8
Frequency (kHz)
14
16
18
22
0
2
4
6
8
10
12
Frequency (kHz)
14
16
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
PRODUCT OVERVIEW
The PCM4104 is a high-performance, four-channel D/A
converter designed for professional audio systems. The
PCM4104 supports 16- to 24-bit linear PCM input data and
sampling frequencies up to 216kHz. The PCM4104
utilizes an 8x oversampling digital interpolation filter,
followed by a multi-level delta-sigma modulator with a
single pole switched capacitor output filter. This
architecture provides excellent dynamic and sonic
performance, as well as high tolerance to clock phase
jitter. Functional block diagrams, showing both
Standalone and Software modes, are shown in Figure 1
and Figure 2.
The PCM4104 incorporates a flexible audio serial port,
which accepts 16- to 24-bit PCM audio data in both
standard audio formats (Left Justified, Right Justified, and
Philips I2S) and TDM data formats. The TDM formats are
especially useful for interfacing to the synchronous serial
ports of digital signal processors. The TDM formats
support daisy-chaining of two PCM4104 devices on a
single three-wire serial interface (for sampling frequencies
up to 108kHz), forming a high-performance eight-channel
D/A conversion system.
The PCM4104 offers two modes for configuration control:
Software and Standalone. Software mode makes use of a
four-wire SPI port to access internal control registers,
allowing configuration of the full PCM4104 feature set.
Standalone mode offers a more limited subset of the
functions available in Software mode, while allowing for a
simplified pin-programmed configuration mode.
VREF1+
LRCK
BCK
DATA0
DATA1
D/A Converter
and
Output Filter
Audio
Serial
Port
VOUT1+
VOUT1−
VREF1−
VCOM1
VREF2+
RST
MUTE
DEM0
DEM1
SUB
FMT0
FMT1
FMT2
FS0
FS1
MODE
D/A Converter
and
Output Filter
Control
VOUT2+
VOUT2−
VREF2−
Digital
Filtering
and
Functions
VREF3+
D/A Converter
and
Output Filter
VOUT3+
VOUT3−
VREF3−
VCOM2
VREF4+
SCKI
System Clock
and
Timing
D/A Converter
and
Output Filter
VOUT4+
VOUT4−
VREF4−
VDD
DGND
Digital
Power
Analog
Power
VCC 1
AGND1
VCC21
AGND2
Figure 1. Functional Block Diagram for Standalone Mode
13
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VREF1+
LRCK
BCK
DATA0
DATA1
D/A Converter
and
Output Filter
Audio
Serial
Port
VOUT1+
VOUT1−
VREF1−
VCOM1
VREF2+
D/A Converter
and
Output Filter
RST
MUTE
SUB
CS
CCLK
CDIN
CDOUT
MODE
Control
and
SPI Port
VOUT2+
VOUT2−
VREF2−
Digital
Filtering
and
Functions
VREF3+
D/A Converter
and
Output Filter
VOUT3+
VOUT3−
VREF3−
VDD
VCOM2
VREF4+
SCKI
System Clock
and
Timing
D/A Converter
and
Output Filter
VOUT4+
VOUT4−
VREF4−
VDD
DGND
Digital
Power
Analog
Power
VCC1
AGND1
VCC21
AGND2
Figure 2. PCM4104 Functional Block Diagram for Software Mode
ANALOG OUTPUTS
The PCM4104 provides four differential voltage outputs,
corresponding to audio channels 1 through 4. VOUT1+ (pin
1) and VOUT1− (pin 2) correspond to Channel 1. VOUT2+
(pin 47) and VOUT2− (pin 46) correspond to Channel 2.
VOUT3+ (pin 38) and VOUT3− (pin 39) correspond to
Channel 3. VOUT4+ (pin 36) and VOUT4− (pin 35)
correspond to Channel 4.
Each differential output is typically capable of providing
6.15V full-scale (differential) into a 600Ω output load. The
output pins are internally biased to the common-mode (or
bipolar zero) voltage, which is nominally VCC/2. The output
section of each D/A converter channel includes a
single-pole, switched capacitor low-pass filter circuit. The
switched capacitor filter response tracks with the sampling
frequency of the D/A converter and provides attenuation of
the out-of-band noise produced by the delta-sigma
modulator. An external two-pole continuous time filter is
14
recommended to further reduce the out-of-band noise
energy and to band limit the output spectrum to
frequencies suitable for audio reproduction. Refer to the
Applications Information section of this data sheet for
recommended output filter circuits.
VOLTAGE REFERENCES
The PCM4104 includes high and low reference pins for
each output channel. VREF1+ (pin 5) and VREF1− (pin 4)
correspond to Channel 1. VREF2+ (pin 44) and VREF2− (pin
43) correspond to Channel 2. VREF3+ (pin 41) and VREF3−
(pin 42) correspond to Channel 3. VREF4+ (pin 32) and
VREF4− (pin 33) correspond to Channel 4.
The high reference (+) pin may be connected to the
corresponding VCC supply or an external +5.0V reference,
while the low reference (−) pin is connected to analog
ground. A 0.01µF bypass capacitor should be placed
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
between the corresponding high and low reference pins.
An X7R ceramic chip capacitor is recommended for this
purpose. In some cases, a larger capacitor may need to be
placed in parallel with the 0.01µF capacitor, with the value
of the larger capacitor being dependent upon the
low-frequency power-supply noise present in the system.
Typical values may range from 1µF to 10µF. Low ESR
tantalum or multilayer ceramic chip capacitors are
recommended. Figure 3 illustrates the recommended
connections for the reference pins.
VREF+(1)
VREF
The PCM4104 can operate in one of three sampling
modes: Single Rate, Dual Rate, or Quad Rate. Sampling
modes are selected by using the FS[1:0] bits in Control
Register 6 in Software mode, or by using the FS0 (pin 28)
and FS1 (pin 29) inputs in Standalone mode.
The Single Rate mode allows sampling frequencies up to
and including 54kHz. The D/A converter performs 128x
oversampling of the input data in Single Rate mode.
The Dual Rate mode allows sampling frequencies greater
than 54kHz, up to and including 108kHz. The D/A
converter performs 64x oversampling of the input data in
Dual Rate mode.
VCC
0.01µF
SAMPLING MODES
0.1µF to 10µF
− (1)
The Quad Rate mode allows sampling frequencies greater
than 108kHz, up to and including 216kHz. The D/A
converter performs 32x oversampling of the input data in
Quad Rate mode.
VCOM1
Refer to Table 1 for examples of system clock
requirements for common sampling frequencies.
VCOM2
0.1µF
0.1µF
SYSTEM CLOCK REQUIREMENTS
(1) Capacitor(s) required for each of the four reference pairs.
Figure 3. Recommended Connections for Voltage
Reference and Common-Mode Output Pins
In addition to the reference pins, there are two
common-mode voltage output pins, VCOM1 (pin 48) and
VCOM2 (pin 37). These pins are nominally set to a value
equal to VCC/2 by internal voltage dividers. The VCOM1 pin
is common to both Channels 1 and 2, while the VCOM2 pin
is common to Channels 3 and 4. A 0.1µF X7R ceramic chip
capacitor should be connected between the
common-mode output pin and analog ground. The
common-mode outputs are used primarily to bias external
output circuitry.
The PCM4104 requires a system clock, applied at the
SCKI (pin 14) input. The system clock operates at an
integer multiple of the input sampling frequency, or fS. The
multiples supported include 128fS, 192fS, 256fS, 384fS,
512fS, or 768fS. The system clock frequency is dependent
upon the sampling mode. Table 1 shows the required
system clock frequencies for common audio sampling
frequencies. Figure 4 shows the system clock timing
requirements.
Although the architecture of the PCM4104 is tolerant to
phase jitter on the system clock, it is recommended that
the user provide a low jitter clock (100 picoseconds or less)
for optimal performance.
Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates
SAMPLING MODE
SAMPLING FREQUENCY, fS
(kHz)
SYSTEM CLOCK FREQUENCY (MHz)
128fS
192fS
256fS
384fS
512fS
768fS
Single Rate
32
n/a
n/a
8.192
12.288
16.384
24.576
Single Rate
44.1
n/a
n/a
11.2896
16.9344
22.5792
33.8688
Single Rate
48
n/a
n/a
12.288
18.432
24.576
36.864
Dual Rate
88.2
n/a
n/a
22.5792
33.8688
n/a
n/a
Dual Rate
96
n/a
n/a
24.576
36.864
n/a
n/a
Quad Rate
176.4
22.5792
33.8688
n/a
n/a
n/a
n/a
Quad Rate
192
24.576
36.864
n/a
n/a
n/a
n/a
15
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
t SCKIH
SCKI
t SCKIL
t SCKI
PARAMETER
DESCRIPTION
MIN
t SCKI
System Clock Period
26
t SCKIH
System Clock High Pulse Time
12
ns
t SCKIL
System Clock Low Pulse Time
12
ns
MAX
UNITS
ns
Figure 4. System Clock Timing Requirements
RESET OPERATION
The PCM4104 includes three reset functions: power-on,
external, and software-controlled. This section describes
each of the three reset functions.
On power up, the internal reset signal is forced low, forcing
the PCM4104 into a reset state. The power-on reset circuit
monitors the VDD, VCC1, and VCC2 power supplies. When
VDD exceeds +2.0V (margin of error is ±400mV) and VCC1
and VCC2 exceed +4.0V (margin of error is ±400mV), the
internal reset signal is forced high. The PCM4104 then
waits for the system clock input (SCKI) to become active.
Once the system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. When the
initialization sequence is completed, the PCM4104 is
ready to accept audio data at the audio serial port. Figure 5
shows the power-on reset sequence timing.
If the PCM4104 is configured for Software mode control
via the SPI port, all control registers will be reset to their
default state during the initialization sequence. In both
16
Standalone and Software modes, the analog outputs for all
four channels are muted during the reset and initialization
sequence. While in mute state, the analog output pins are
driven to the bipolar zero voltage, or VCC/2.
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST input (pin 9). The RST input is active low, and requires
a minimum low pulse width of 40 nanoseconds. The
low-to-high transition of the applied reset signal will force
an initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 6 illustrates
the reset sequence initiated when using the RST input.
A reset initialization sequence is available in Software
mode, using the RST bit in Control Register 6. The RST bit
is active high. When RST is set to 1, a reset sequence is
initiated in the same fashion as an external reset applied
at the RST input.
Figure 7 shows the state of the analog outputs for the
PCM4104 before, during and after the reset operations.
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~ 4.0V
VCC1
VCC2
0V
VDD
~ 2.0V
0V
Internal
Reset
1024 System Clock Periods
Required for Initialization
0V
SCKI
0V
System Clock
Indeterminate
or Inactive
Figure 5. Power-Up Reset Timing
t RSTL > 40ns
RST
0V
Internal
Reset
1024 System Clock Periods
Required for Initialization
0V
SCKI
0V
Figure 6. External Reset Timing
Internal
Reset
Analog
Outputs
HI
LO
Outputs are On
Outputs are Muted
Outputs are Muted
for 1024 SCKI Periods
Outputs are On
Initialization
Period
Figure 7. Analog Output State for Reset Operations
17
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POWER-DOWN OPERATION
The PCM4104 can be forced to a power-down state by
applying a low level to the RST input for a minimum of
65,536 system clock cycles. In power-down mode, all
internal clocks are stopped, and analog outputs are set to
a high-impedance state. The system clock can then be
removed to conserve additional power. In the case of
system clock restart when exiting the power-down state,
the clock should be restarted prior to a low-to-high
transition of the reset signal at the RST input. The
low-to-high transition of the reset signal initiates a reset
sequence, as described in the Reset Operation section of
this data sheet.
In Software mode, two additional power-down controls are
provided. The PDN12 and PDN34 bits are located in
Control Register 6 and may be used to power-down
channel pairs, with PDN12 corresponding to channels 1
and 2, and PDN34 corresponding to channels 3 and 4.
This allows the user to conserve power when a channel
pair is not in use. The power-down function is the same as
described in the previous paragraph for the corresponding
channel pair. Unlike the power-down function
implemented using the RST input, setting a power-down
bit will immediately power down the corresponding
channel pair.
When exiting power-down mode, either by forcing the RST
input high or by setting the PDN12 or PDN34 bits low, the
analog outputs will transition from the high-impedance
state to the mute state, with the output level set to the
bipolar zero voltage. There may be a small transient
created by this transition, since internal capacitor charge
can initially force the output to a voltage above or below
bipolar zero, or external circuitry can pull the outputs to
some other voltage level. Figure 8 illustrates the state of
the analog outputs before, during, and after a power-down
event.
VDD
RST
0V
Analog
Outputs
Outputs are On
Outputs are
Muted
Outputs are
High Impedance
65,536
SCKI Periods
Outputs Transition
from High Impedance
to Muted State
Outputs are On
1024
SCKI Periods
Required for
Initialization
HI
PDN12
PDN34
Analog
Outputs
LO
Outputs are On
Outputs are
High Impedance
Outputs Transition
from High Impedance
to Muted State
1024
SCKI Periods
Required for
Initialization
Figure 8. Analog Output State for Power-Down Operations
18
Outputs are On
Outputs are On
Transitioning
to Driven State
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
AUDIO SERIAL PORT
The audio serial port provides a common interface to
digital signal processors, digital interface receivers (AES3,
S/PDIF), and other digital audio devices. The port
operates as a slave to the processor, receiver, or other
clock generation circuitry. Figure 9 illustrates a typical
audio serial port connection to a processor or receiver. The
audio serial port is comprised of four signal pins: BCK (pin
15), LRCK (pin 16), DATA0 (pin 17), and DATA1 (pin 18).
DSP
FSX
CLKX
PCM4104
LRCK
BCK
DX0
DATA0
DX1
DATA1
SCKI
System Clock
Figure 9. Audio Serial Port Connections for Left
Justified, Right Justified, and I2S Formats.
The LRCK pin functions as either the left/right word clock
or the frame synchronization clock, depending upon the
data format selected. The LRCK frequency is equal to the
input sampling frequency (44.1kHz, 48kHz, 96kHz, etc.).
The BCK pin functions as the serial data clock input. This
input is referred to as the bit clock. The bit clock runs at an
integer multiple of the input sampling frequency. Typical
multiples include 32, 48, 64, 96, 128, 192, and 256,
depending upon the data format, word length, and system
clock frequency selected.
The DATA0 and DATA1 pins are the audio data inputs.
When using Left Justified, Right Justified, or I2S data
formats, the DATA0 pin carries the audio data for channels
1 and 2, while the DATA1 pin carries the audio data for
channels 3 and 4. When using TDM data formats, DATA0
carries the audio data for all four channels, while the
DATA1 input is ignored.
The audio serial port data formats are shown in Figure 10,
Figure 13, and Figure 14. Data formats are selected by
using the FMT[2:0] bits in Control Register 7 in Software
mode, or by using the FMT0 (pin 25), FMT1 (pin 26), and
FMT2 (pin 27) inputs in Standalone mode. In Software
mode, the user may also select the phase (normal or
inverted) for the LRCK input, as well as the data sampling
edge for the BCK input (either rising or falling edge). The
reset default conditions for the Software mode are normal
phase for LRCK and rising edge data sampling for BCK.
The Left Justified, Right Justified, and I2S data formats are
similar to one another, with differences in data justification
and word length. The PCM audio data must be two’s
complement binary, MSB first. Figure 10 provides
illustrations for these data formats.
The TDM formats carry the information for four or eight
channels on a single data line. The DATA0 input (pin 17)
is used as the data input for the TDM formats. The data is
carried in a time division multiplexed fashion; hence, the
TDM acronym used to describe this format. Figure 12
shows the TDM connection of two PCM4104 devices. The
data for each channel is assigned one of the time slots in
the TDM frame, as shown in Figure 13 and Figure 14. The
sub−frame assignment for each PCM4104 is determined
by the state of the SUB input (pin 13). When SUB is forced
low, the device is assigned to sub-frame 0. When SUB is
forced high, the device is assigned to sub-frame 1.
19
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Ch. 1 (DATA0) or Ch. 3 (DATA1)
Ch. 2 (DATA0) or Ch. 4 (DATA1)
LRCK
BCK
MSB
DATA0
DATA1
LSB
MSB
LSB
(a) Left−Justified Data Format
LRCK
BCK
DATA0
DATA1
MSB
LSB
MSB
LSB
(b) Right−Justified Data Format
LRCK
BCK
DATA0
DATA1
LSB
MSB
MSB
(c)
I2S
LSB
Data Format
1/fS
Figure 10. Left Justified, Right Justified, and I2S Data Formats
LRCK
t LRBKD
t BKLRD
BCK
(BCKE = 0)
t BCKP
t BCKHL
BCK
(BCKE = 1)
DATA0
DATA1
t DS
t DH
PA R A M E TER
t BCKP
t BCKHL
t LRBKD
t BKLRD
t DS
t DH
−
D ES C R IP T IO N
M IN
MAX
U N ITS
BCK Cycle Time
70
ns
BCK High/Low Time
LRCK Edge to BCK Sampling Edge Delay
BCK Sampling Edge to LRCK Edge Delay
30
10
10
ns
ns
ns
Data Setup Time
Data Hold Time
LRCK Duty Cycle
10
10
50
ns
ns
%
Figure 11. Audio Serial Port Timing for Left Justified, Right Justified, and I2S Data Formats.
20
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Device #1
(Sub−Frame 0)
DSP
PCM4104
FSX
LRCK
CLKX
BCK
DX
DATA0
SUB
SCKI
Device #2
(Sub−Frame 1)
PCM4104
LRCK
BCK
DATA0
SUB
SCKI
VCC
System Clock
Figure 12. TDM Connection
TDM Data Formats − Long Frame
Supported for Single and Dual Rate Sampling Modes Only
LRCK
Normal, Zero BCK Delay
LRCK
Normal, One BCK Delay
LRCK
Inverted, Zero BCK Delay
LRCK
Inverted, One BCK Delay
DATA0
Supports 8 Channels, or
two PCM4104 devices.
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Ch. 1
Ch. 2
Ch. 3
Ch. 4
Ch. 1
Ch. 2
Ch. 3
Ch. 4
Sub−Frame 0
(SUB = 0)
Sub−Frame 1
(SUB = 1)
One Frame
BCK = 192f S or 256fS
In the case of BCK = 192fS , each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.
In the case of BCK = 256fS , each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don’t care bits.
Audio data is always presented in two’s complement, MSB−first format.
Figure 13. TDM Data Formats: Long Frame
21
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
TDM Data Formats − Short Frame
All Sampling Modes Supported
LRCK
Normal, Zero BCK Delay
LRCK
Normal, One BCK Delay
LRCK
Inverted, Zero BCK Delay
LRCK
Inverted, One BCK Delay
DATA0
Supports 4 Channels, or
one PCM4104 device.
Slot 1
Slot 2
Slot 3
Slot 4
Ch. 1
Ch. 2
Ch. 3
Ch. 4
One Frame
BCK = 96fS or 128fS
(the SUB pin is ignored when using a Short Frame)
In the case of BCK = 96fS, each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.
In the case of BCK = 128fS, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don’t care bits.
Audio data is always presented in two’s complement, MSB−first format.
Figure 14. TDM Data Formats: Short Frame
One Frame
t LRCKP
t BNF
LRCK
t BKBF
t LRBKD
BCK
(BCKE = 0)
BCK
(BCKE = 1)
DATA0
t DS
t DH
PA R A M E T ER
D E SC R IPT IO N
MAX
U N IT S
LRCK pulse width
1/fBCK
ns
t LRBKD
LRCK active edge to BCK sampling edge delay
12
ns
t DS
Data setup time
10
ns
t DH
Data hold time
ns
t BNF
LRCK transition before new frame
10
1/fBCK
t BKBF
BCK sampling edge to new frame delay
12
ns
Figure 15. TDM Timing
22
M IN
t LRCKP
ns
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
STANDALONE MODE CONFIGURATION
Soft Mute Function
Standalone mode is selected by forcing the MODE input
(pin 8) low. Standalone mode operation provides a subset
of the functions available in Software mode, while
providing an option for a simplified control model.
Standalone configuration is accomplished by either
hardwiring or driving a small set of input pins with external
logic or switches. Standalone mode functions include
sampling mode and audio data format selection, an
all-channel soft mute function, and digital de-emphasis
filtering. The following paragraphs provide a brief
description of each function available when using
Standalone mode.
The MUTE input (pin 10) may be used in either the
Standalone or Software modes to simultaneously mute the
four output channels. The soft mute function slowly ramps
the digital output attenuation from its current setting to the
mute level, minimizing or eliminating audible artifacts.
Table 4 summarizes MUTE function operation.
Table 4. Mute Function Configuration
MUTE
ANALOG OUTPUTS
0
On (mute disabled)
1
Muted
Sampling Mode
The sampling mode is selected using the FS0 (pin 28) and
FS1 (pin 29) inputs. A more detailed discussion of the
sampling modes was provided in an earlier section of this
data sheet. Table 2 summarizes the sampling mode
configuration for Standalone mode.
Table 2. Sampling Mode Configuration
FS1
FS0
SAMPLING MODE
0
0
Single Rate
0
1
Dual Rate
1
0
Quad Rate
1
1
− Not Used −
Audio Data Format
The audio data format is selected using the FMT0 (pin 25),
FMT1 (pin 26), and FMT2 (pin 27) inputs. A detailed
discussion of the audio serial port operation and the
corresponding data formats was provided in the Audio
Serial Port section on page 19. For Standalone mode, the
LRCK polarity is always normal, while the serial audio data
is always sampled on the rising edge of the BCK clock.
Table 3 shows the audio data format configuration for
Standalone mode.
Table 3. Audio Data Format Configuration
FMT2
FMT1
FMT0
AUDIO DATA FORMAT
0
0
0
0
0
1
24-bit left justified
24-bit I2S
0
1
0
TDM with zero BCK delay
0
1
1
TDM with one BCK delay
1
0
0
24-bit right justified
1
0
1
20-bit right justified
1
1
0
18-bit right justified
1
1
1
16-bit right justified
Digital De-Emphasis
This is a global digital function (common to all four
channels) and provides de-emphasis of the higher
frequency content within the 20kHz audio band.
De-emphasis is required when the input audio data has
been pre-emphasized. Pre-emphasis entails increasing
the amplitude of the higher frequency components in the
20kHz audio band using a standardized filter function in
order to enhance the high-frequency response. The
PCM4104 de-emphasis filters implement the standard
50/15µs de-emphasis transfer function commonly used in
digital audio applications.
De-emphasis filtering is available for three input sampling
frequencies in Single Rate sampling mode: 32kHz,
44.1kHz, and 48kHz. De-emphasis is not available when
operating in Dual or Quad Rate sampling modes. The
de-emphasis filter is selected using the DEM0 (pin 12) and
DEM1 (pin 11) inputs. Table 5 illustrates the de-emphasis
filter configuration for Standalone mode.
Table 5. Digital De-Emphasis Configuration
DEM1
DEM0
DIGITAL DE-EMPHASIS MODE
0
0
Off (de-emphasis disabled)
0
1
48kHz
1
0
44.1kHz
1
1
32kHz
23
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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
SOFTWARE MODE CONFIGURATION
Output Phase Reversal
Software mode is selected by forcing the MODE input
(pin 8) high. Software mode operation provides full access
to the features of the PCM4104 by allowing the writing and
reading of on-chip control registers. This is accomplished
using the four-wire SPI port. The following paragraphs
provide a brief description of each function available when
using Software mode.
The PCM4104 includes an output phase reversal function,
which provides the ability to invert the output phase for all
four channels, either for testing or for matching various
output circuit configurations. This function is controlled
using the PHASE bit, located within Control Register 5.
The output phase is set to noninverted by default on power
up or reset.
Digital Attenuation
Sampling Mode
The audio signal for each channel can be attenuated in the
digital domain using this function. Attenuation settings
from 0dB (unity gain) to −119.5dB are provided in 0.5dB
steps. In addition, the attenuation level may be set to the
mute state. The rate of change for the digital attenuation
function is one 0.5dB step for every eight LRCK periods.
Each channel has its own independent attenuation control,
accessed using control registers 1 through 4. The reset
default setting for all channels is 0dB, or unity gain (no
attenuation applied).
Sampling mode configuration was discussed earlier in this
data sheet, with Table 1 providing a reference for common
sampling and system clock frequencies. The FS0 and FS1
bits located in Control Register 6 are used to set the
sampling mode. The sampling mode defaults to Single
Rate on power up or reset.
Digital De-Emphasis
The de-emphasis function is accessed through Control
Register 5 using the DEM[1:0] bits. The reset default
setting is that the de-emphasis is disabled for all four
channels. De-emphasis filter operation is described in the
Standalone Mode Configuration section of this data sheet.
Soft Mute
Each of the four D/A converter channels has its own
independent soft mute control, located in Control Register
5.
The reset default is normal output for all four channels with
the soft mute function disabled. The MUTE input (pin 10)
also functions in Software mode, with a high input forcing
soft mute on all four channels.
Zero Data Mute
The PCM4104 includes a zero data detection and mute
function in Software mode. This function automatically
mutes a given channel when 1024 consecutive LRCK
periods of all zero data are detected for that channel. The
zero data mute function is enabled and disabled using the
ZDM bit in Control Register 5. The zero data mute function
is disabled by default on power up or reset.
24
Power-Down Modes
The power-down control bits are located in Control
Register 6. These bits are used to power down pairs of D/A
converters within the PCM4104. The PDN12 bit is used to
power down channels 1 and 2, while the PDN34 bit is used
to power down channels 3 and 4. When a channel pair is
powered down, it ignores the audio data inputs and sets its
outputs to a high-impedance state. By default, the
power-down bits are disabled on power up or reset.
Software Reset
This reset function allows a reset sequence to be initiated
under software control. All control registers are reset to
their default state. The reset bit, RST, is located in Control
Register 6. Setting this bit to 1 initiates a one-time reset
sequence. The RST bit is cleared by the initialization
sequence.
Audio Data Formats, LRCK Polarity, and BCK
Sampling Edge
Control Register 7 is used to configure the PCM4104 audio
serial port. Audio serial port operation was discussed
previously in this data sheet; refer to that section for more
details regarding the functions controlled by this register.
The control register definitions provide additional
information regarding the register functions and their
default settings.
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SERIAL PERIPHERAL INTERFACE (SPI) PORT
OPERATION
The SPI port is a four-wire synchronous serial interface
that is used to access the on-chip control registers when
the PCM4104 is configured for Software mode operation.
The CDIN input (pin 23) is the serial data input for the port,
while CDOUT (pin 24) is used for reading back control
register contents in a serial fashion. The CS input (pin 21)
functions as the chip select input, and must be forced low
for register write or read access. The CCLK input (pin 22)
functions as the serial data clock, used to clock data in and
out of the port. Data is clocked into the port on the rising
edge of CCLK, while data is clocked out of the port on the
falling edge of CCLK.
There are three modes of operation supported for the SPI
port: Single Register, Continuous, and Auto-Increment.
The Single Register and Continuous modes are similar to
one another. In Continuous mode, instead of bringing the
CS input high after writing or reading a single register, the
CS input is held low and a new control byte is issued with
a new address for the next write or read operation.
Continuous mode allows multiple, sequential or
nonsequential register addresses to be read or written in
succession, as shown in Figure 16.
Auto-Increment mode is designed for writing or reading
multiple sequential register addresses. After the first
register is written or read, the register address is
Set CS = 1 here for Single Register Operations
automatically incremented by 1, so the next write or read
operation is performed without issuing another control
byte, as shown in Figure 17.
Control Byte (or Byte 0)
The control byte, or byte 0, is the first byte written to the
PCM4104 SPI port when performing a write or read
operation. The control byte includes bits that define the
operation to be performed (read or write), the
auto-increment mode status, and the control register
address.
The Read/Write bit, R/W, is set to 0 to indicate a register
write operation, or set to 1 for a register read operation.
The Increment bit, INC, enables or disables the
Auto-Increment mode of operation. When this bit is set to
a 0, auto-increment operation is disabled, and the
operation performed is either Single Register or
Continuous. Setting the INC bit to 1 enables
Auto-Increment operation.
A two-bit key code, 10B, follows the INC bit and must be
present in order for any operation to take place on the
control port. Any other combination for these bits will result
in the port ignoring the write or read request.
The four-bit address field, A[3:0], is used to specify the
control register address for the read or write operation, or
the starting address for an Auto-Increment write or read
operation.
Keep CS = 0 for writing or reading multiple registers in Continuous mode
CS
CDIN
Control Byte
Register Data
Control Byte
byte 0
byte 1
byte 0
Register Data
CDOUT
High Impedance
byte 1
Register Data
byte 1
byte N
Register Data
High Impedance
byte 2
byte N
CCLK
Control Byte Definition (Byte 0)
MSB
R/W INC
LSB
1
0
A3
A2
A1
A0
Register Address
Auto −Increment Control: Set to 0 for Single Register or Continuous Operation
Read/WriteControl: 0 = Write
1 = Read
Figure 16. Single Register and Continuous Write or Read Operation
25
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Keep CS = 0 for Auto−Increment Operation
CS
Control Byte
Register Data
byte 0
byte 1
High Impedance
byte 1
CDIN
byte 2
byte 3
byte N
byte 2
byte 3
byte N
Register Data
CDOUT
CCLK
Control Byte Definition (Byte 0)
MSB
LSB
R/W INC
1
0
A3
A2
A1
A0
Register Address
Auto−Increment Control: Set to 1 for Auto−Increment Operation
Read/WriteControl: 0 = Write
1 = Read
Figure 17. Auto-Increment Write or Read Operation
tDS
tDH
tCH
CS
CCLK
CDIN
CDOUT
MSB
High Impedance (Hi Z)
LSB
MSB
t DO
tCSZ
PARAMETER
DESCRIPTION
MIN
tDS
CDIN Data Setup Time
5
ns
tDH
CDIN Data Hold Time
2
ns
tCH
CS Hold Time
2
ns
t DO
CDOUT Data Delay Time
5
ns
tCSZ
CS High to CDOUT Hi Z
5
ns
Figure 18. SPI Port Timing
26
MAX
UNIT
Hi Z
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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)
The PCM4104 includes a small set of control registers, which are utilized to configure the full set of on-chip functions in
Software mode. The register map is shown in Table 6. Register 0 is reserved for factory use and should not be written to
for normal operation. Register 0 defaults to all zero data on power up or reset.
Table 6. Control Register Map
CONTROL REGISTER ADDRESS
(HEX)
MSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
0
0
0
0
0
0
0
0
0
1
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
2
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
3
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
4
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
5
MUT4
MUT3
MUT2
MUT1
ZDM
PHASE
DEM1
DEM0
6
RST
0
0
0
PDN34
PDN12
FS1
FS0
7
0
0
BCKE
LRCKP
0
FMT2
FMT1
FMT0
Register 1: Attenuation Control Register − Channel 1
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
This register controls the digital output attenuation for Channel 1.
Default: AT1[7:0] = 255, or 0dB
Let N = AT1[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)
For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
Register 2: Attenuation Control Register – Channel 2
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
This register controls the digital output attenuation for Channel 2.
Default: AT2[7:0] = 255, or 0dB
Let N = AT2[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)
For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
Register 3: Attenuation Control Register – Channel 3
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
This register controls the digital output attenuation for Channel 3.
Default: AT3[7:0] = 255, or 0dB
Let N = AT3[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)
For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
27
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Register 4: Attenuation Control Register – Channel 4
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
This register controls the digital output attenuation for Channel 4.
Default: AT4[7:0] = 255, or 0dB
Let N = AT4[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)
For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
Register 5: Function Control Register
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
MUT4
MUT3
MUT2
MUT1
ZDM
PHASE
DEM1
DEM0
This register controls various D/A converter functions, including de-emphasis filtering, output phase reversal, zero data
mute, and per-channel soft muting.
DEM[1:0]
Digital De-Emphasis
De-emphasis is available for Single Rate mode only.
De-emphasis is disabled for Dual and Quad Rate modes.
PHASE
DEM1
DEM0
0
0
De-emphasis disabled (default)
0
1
De-emphasis for fS = 48kHz
1
0
De-emphasis for fS = 44.1kHz
1
1
De-emphasis for fS = 32kHz
Output Phase
PHASE
ZDM
Output Phase
0
Noninverted (default)
1
Inverted
Zero Data Mute
ZDM
MUT[4:1]
De-Emphasis Selection
Zero Mute
0
Disabled (default)
1
Enabled
Soft Mute
MUTx
D/A Converter Output
0
On (default)
1
Muted
NOTE: x = channel number.
28
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Register 6: System Control Register
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
RST
0
0
0
PDN34
PDN12
FS1
FS0
This register controls various system level functions of the PCM4104, including sampling mode, power down, and soft
reset.
FS[1:0]
PDN12
Sampling Mode
FS1
FS0
0
0
Single Rate (default)
0
1
Dual Rate
1
0
Quad Rate
1
1
− Not Used −
Power-Down for Channels 1 and 2
PDN12
PDN34
Power Down for Channels 1 and 2
0
Disabled (default)
1
Enabled
Power Down for Channels 3 and 4
PDN34
RST
Sampling Mode
Power Down for Channels 3 and 4
0
Disabled (default)
1
Enabled
Software Reset (value defaults to 0)
Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external reset
applied at the RST input (pin 9).
Register 7: Audio Serial Port Control Register
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
0
0
BCKE
LRCKP
0
FMT2
FMT1
FMT0
This register is used to control the data format and clock polarity for the PCM4104 audio serial port.
FMT[2:0]
Audio Data Format
FMT2
FMT1
DEM0 Data Format
0
0
0
24-bit left justified (default)
0
0
1
24-bit I2S
0
1
0
TDM with zero BCK delay
0
1
1
TDM with one BCK delay
1
0
0
24-bit right justified
1
0
1
20-bit right justified
1
1
0
18-bit right justified
1
1
1
16-bit right justified
LRCKP
LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0.
BCKE
BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.
29
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APPLICATIONS INFORMATION
This section provides practical information for system and
hardware engineers that are designing in the PCM4104.
BASIC CIRCUIT CONFIGURATIONS
Figure 19 and Figure 20 show typical circuit configurations
for the PCM4104 operated in Standalone and Software
modes. Power supply bypass and reference decoupling
capacitors should be placed as close to the corresponding
PCM4104 pins as possible. A common ground is shown in
both figures, with the analog and digital ground pins
connected to a common plane. Separate power supplies
are utilized for the analog and digital sections, with +5V
required for the PCM4104 analog supplies and +3.3V
required for the digital supply.
The configuration of the output filter circuit is dependent
upon whether a single-ended or differential output is
required. Single-ended outputs are commonly used in
consumer playback systems, while differential or balanced
outputs are used in many professional audio applications,
such as recording or broadcast studios and live sound
systems.
Figure 21 illustrates an active filter circuit that uses a single
op amp to provide both 2nd-order low-pass filtering and
differential to single-ended signal conversion. This circuit
is used on the PCM4104EVM evaluation circuit and meets
the published typical Electrical Characteristics for dynamic
performance. The single-ended output is convenient for
connecting to both headphone and power amplifiers when
used for listening tests.
The +5V analog supply may be derived from a higher
valued, positive analog power supply using a linear
voltage regulator, such as the REG103 available from
Texas Instruments. The +3.3V digital supply can be
derived from a primary +5V digital supply using a linear
voltage regulator, such as the REG1117, also from TI. The
PCM4104EVM evaluation module provides an example of
how the common ground with separate supply approach
can be successfully implemented. The PCM4104EVM
User’s Guide includes schematics and PCB layout plots
for reference. The evaluation module is available through
Texas Instruments’ distributors and sales representatives,
or may be ordered online through the TI eStore, which can
be accessed through the TI home page at
http://www.ti.com.
The quality of the op amp used is this circuit is important,
as many devices will degrade the dynamic range and/or
total harmonic distortion plus noise (THD+N)
specifications for the PCM4104. An NE5534A is shown in
Figure 21 and provides both low noise and distortion.
Bipolar input op amps with equivalent specifications
should produce similar measurement results. Devices that
exhibit higher equivalent input noise voltage, such as the
Texas Instruments OPA134 or OPA604 families, will
produce
lower
dynamic
range
measurements
(approximately 1dB to 2dB lower than the typical
PCM4104 specification), while having little or no impact on
the THD+N specification when measuring a full-scale
output level.
The master clock generator supplies the system clock for
the PCM4104, as well as the audio data source, such as
a digital signal processor. The LRCK and BCK audio
clocks should be derived from the system clock, in order
to ensure synchronous operation.
Figure 22 illustrates a fully-differential output filter circuit
suitable for use with the PCM4104. The OPA1632 from
Texas Instruments provides the fully differential signal path
in this circuit. The OPA1632 features very low noise and
distortion, making it suitable for high-end audio
applications.
ANALOG OUTPUT FILTER CIRCUITS
An external output filter is recommended for each
differential output pair. The external output filter further
reduces the out-of-band noise energy produced by the
delta-sigma modulator, while providing band limiting
suitable for audio reproduction. A 2nd-order Butterworth
low-pass filter circuit with a −3dB corner frequency from
50kHz to 180kHz is recommended.
30
Texas Instruments provides a free software tool,
FilterProt, used to assist in the design of active filter
circuits. The software supports design of multiple
feedback (MFB), Sallen-Key, and fully differential filter
circuits. FilterPro is available from the TI web site.
Additionally, TI document number SBAF001A, also
available from the TI web site, provides pertinent
application information regarding the proper usage of the
FilterPro program.
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To Analog Output Filters(1)
48
VOUT1+
VOUT1−
47
46
45
44
43
42
41
40
39
38
VCOM2
VOUT3+
VOUT3−
VCC2
VREF3+
VREF3−
VREF2−
VREF2+
VCC1
VOUT2−
VOUT2+
VCOM1
(2)
37
1
36
2
35
3
34
4
33
5
32
AGND1
VREF1−
(2)
VREF1+
VOUT4−
AGND2
NC
VREF4−
VREF4+
(2)
NC
6
31
PCM4104
NC
NC
7
30
8
29
9
28
MODE
FS1
RST
FS0
MUTE
FMT2
10
27
11
26
12
25
DEM1
FMT1
DEM0
From
Logic,
µP,
or DSP
FMT0
23
24
CDOUT
22
CDIN
21
CCLK
20
CS
19
DGND
18
VDD
17
DATA1
16
DATA0
15
LRCK
14
BCK
SUB
13
SCKI
From
Logic,
µP,
or DSP
VOUT4+
+5.0V
+3.3V
Pin 19
0.1µF
+
10µF
Master
Clock
Generator
Pin 40
Audio Data Source
0.1µF
+
Pin 45
10µF
0.1µF
+
10µF
(1) Refer to Figure 21 and Figure 22 in this document.
(2) Refer to Figure 3 in this document for external connection requirements.
Figure 19. Typical Standalone Mode Configuration
31
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To Analog Output Filters(1)
48
VOUT1+
VOUT1−
47
46
45
44
43
42
41
40
39
VCOM2
VOUT3+
VOUT3−
VCC2
VREF3+
VREF3−
VREF2−
VREF2+
VCC1
VOUT2−
VOUT2+
VCOM1
(2)
38
37
1
36
2
35
3
34
4
33
5
32
6
31
AGND1
VREF1−
(2)
VREF1+
VREF4−
VREF4+
(2)
NC
PCM4104
NC
NC
7
30
8
29
9
28
10
27
11
26
12
25
MODE
FS1
RST
FS0
MUTE
FMT2
DEM1
FMT1
DEM0
FMT0
Master
Clock
Generator
Audio Data Source
23
24
CDOUT
22
CDIN
21
CCLK
20
CS
19
DGND
18
VDD
17
DATA1
16
DATA0
15
LRCK
14
BCK
SUB
13
SCKI
From
Logic or
Host Control
VOUT4−
AGND2
NC
+3.3V
VOUT4+
Host Control
+5.0V
+3.3V
Pin 19
0.1µF
+
Pin 40
10µF
0.1µF
(1) Refer to Figure 21 and Figure 22 in this document.
(2) Refer to Figure 3 in this document for external connection requirements.
Figure 20. Typical Software Mode Configuration
32
+
Pin 45
10µF
0.1µF
+
10µF
$%
www.ti.com
SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004
1kΩ
560pF
+12V
10µF
+
0.1µF
PCM4104
VOUTn−
100µF
+
VOUTn+
22pF 100µF
+
604Ω
499Ω
2
7
100Ω
604Ω
2200pF
499Ω
NE5534A
4
1kΩ
Filtered
Output
6
3
0.1µF
RCA or 1/4−inch
Phone Jack
560pF
10µF
n = 1, 2, 3, or 4
+
−12V
Figure 21. Single-Ended Output Filter Circuit
1kΩ
560pF
−15V
10µF
+
0.1µF
PCM4104
VOUTn+
VOUTn−
Filtered
Output
6
7
100µF
+
604Ω
22pF 100µF
+
604Ω
499Ω
8
EN
2200pF
5
1
VOCM
3
1
OPA1632
499Ω
100Ω
100Ω
4
2
3
2
Male XLR
Connector
10µF
n = 1, 2, 3, or 4
0.1µF
+
+15V
560pF
1kΩ
Figure 22. Differential Output Filter Circuit
33
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCM4104PFBR
ACTIVE
TQFP
PFB
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4104
PCM4104PFBT
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4104
PCM4104PFBTG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4104
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Apr-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PCM4104PFBR
TQFP
PFB
48
2000
330.0
16.8
9.6
9.6
1.5
12.0
16.0
Q2
PCM4104PFBT
TQFP
PFB
48
250
180.0
17.0
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Apr-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM4104PFBR
TQFP
PFB
48
2000
367.0
367.0
38.0
PCM4104PFBT
TQFP
PFB
48
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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• DALLAS, TEXAS 75265
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