Texas Instruments | TAS5122: 30-W Stereo Digital Amplifier Power Stage (Rev. E) | Datasheet | Texas Instruments TAS5122: 30-W Stereo Digital Amplifier Power Stage (Rev. E) Datasheet

Texas Instruments TAS5122: 30-W Stereo Digital Amplifier Power Stage (Rev. E) Datasheet
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
TM
FEATURES
APPLICATIONS
D DVD Receiver
D Home Theatre
D Mini/Micro Component Systems
D Internet Music Appliance
DESCRIPTION
D 2 × 30 W (BTL) Into 6 Ω at 1 kHz
D 95-dB Dynamic Range (in System With
TAS5026)
D < 0.2% THD+N (in System – 30 W RMS Into
The TAS5122 is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-Ω
speakers at up to 30 W per channel. The device
incorporates TI’s PurePath Digitalt technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple, passive demodulation filter to deliver
high-quality,
high-efficiency,
true-digital
audio
amplification.
6-Ω Resistive Load)
D Device Power Efficiency Typical >90% Into
6-Ω Load
D Self-Protection Design (Including
Undervoltage, Overtemperature, and Short
Conditions) With Error Reports
D Internal Gate Drive Supply Voltage Regulator
D EMI Compliant When Used With
Recommended System Design
The efficiency of this digital amplifier is typically greater
than 90%. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5122, safeguarding the device and speakers against
fault conditions that could damage the system.
THD + NOISE vs OUTPUT POWER
THD + NOISE vs FREQUENCY
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
RL = 6 Ω
TC = 75°C
0.1
0.01
40m
100m
1
10
40
PO − Output Power − W
RL = 6 Ω
TC = 75°C
PO = 30 W
0.1
PO = 10 W
PO = 1 W
0.01
20
100
1k
10k 20k
f − Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
Copyright  2004, Texas Instruments Incorporated
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
Terminal Assignment
TAS5122
The TAS5122 is offered in a thermally enhanced 56-pin
DCA package (thermal pad is on the bottom). Output of the
DCA package is highly dependent on thermal design. See
the Thermal Information section. Therefore, it is important
to design the heatsink carefully.
UNITS
DVDD to DGND
–0.3 V to 4.2 V
GVDD to GND
28 V
PVDD_X to GND (dc voltage)
28 V
OUT_X to GND (dc voltage)
28 V
BST_X to GND (dc voltage)
GREG to GND (2)
14.2 V
40 V
PWM_XP, RESET, M1, M2, M3, SD,
OTW
DCA PACKAGE
(TOP VIEW)
GND
GND
GREG
DVDD
GND
DGND
GND
PWM_AP
PWM_AM
RESET_AB
PWM_BM
PWM_BP
DREG
M1
M2
M3
DREG_RTN
PWM_CP
PWM_CM
RESET_CD
PWM_DM
PWM_DP
SD_AB
SD_CD
OTW
GREG
GND
GND
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GVDD
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND
GND
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND
GND
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD
GND
–0.3 V to DVDD + 0.3 V
Maximum operating junction
temperature, TJ
–40°C to 150°C
Storage temperature
–40°C to 125°C
(1) Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device
reliability.
(2) GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V.
ORDERING INFORMATION
TA
0°C to 70°C
PACKAGE
DESCRIPTION
TAS5122DCA
56-pin small TSSOP
PACKAGE DISSIPATION RATINGS
PACKAGE
RθJC
(°C/W)
RθJA
(°C/W)
56-pin DCA TSSOP
1.14
See Note 1
(1) The TAS5122 package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, RθJA, a system parameter that characterizes the
thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
RθJA values are provided in the Thermal Information section. This
example provides additional information regarding the power
dissipation ratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed.
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
FUNCTION(1)
DESCRIPTION
BST_A
54
P
HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B
43
P
HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C
42
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
31
P
HS bootstrap supply (BST), external capacitor to OUT_D required
DGND
6
P
Digital I/O reference ground
DREG
13
P
Digital supply voltage regulator decoupling pin, capacitor connected to GND
DREG_RTN
17
P
Digital supply voltage regulator decoupling return pin
DVDD
4
P
I/O reference supply input (3.3 V)
1, 2, 5,
P
Power ground (I/O reference ground – pin 22)
GND
7, 27, 28,
29, 36, 37,
48, 49, 56
GREG
3, 26
P
Gate drive voltage regulator decoupling pin, capacitor to GND
GVDD
30, 55
P
Voltage supply to on−chip gate drive and digital supply voltage regulators
M1
14
I
Mode selection pin
M2
15
I
Mode selection pin
M3
16
I
Mode selection pin
OTW
25
O
Overtemperature warning output, open drain with internal pullup
OUT_A
50, 51
O
Output, half-bridge A
OUT_B
46, 47
O
Output, half-bridge B
OUT_C
38, 39
O
Output, half-bridge C
OUT_D
34, 35
O
Output, half-bridge D
PVDD_A
52, 53
P
Power supply input for half-bridge A
PVDD_B
44, 45
P
Power supply input for half-bridge B
PVDD_C
40, 41
P
Power supply input for half-bridge C
PVDD_D
32, 33
P
Power supply input for half-bridge D
PWM_AM
9
I
Input signal (negative), half-bridge A
PWM_AP
8
I
Input signal (positive), half-bridge A
PWM_BM
11
I
Input signal (negative), half-bridge B
PWM_BP
12
I
Input signal (positive), half-bridge B
PWM_CM
19
I
Input signal (negative), half-bridge C
PWM_CP
18
I
Input signal (positive), half-bridge C
PWM_DM
21
I
Input signal (negative), half-bridge D
PWM_DP
22
I
Input signal (positive), half-bridge D
RESET_AB
10
I
Reset signal, active low
RESET_CD
20
I
Reset signal, active low
SD_AB
23
O
Shutdown signal for half-bridges A and B
O
Shutdown signal for half-bridges C and D
24
SD_CD
(1) I = input, O = output, P = power
3
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
BST_A
GREG
PVDD_A
Gate
Drive
PWM_AP
PWM
Receiver
OUT_A
Timing
Control
Gate
Drive
GND
Protection A
BST_B
RESET
GREG
PVDD_B
Protection B
Gate
Drive
PWM_BP
PWM
Receiver
OUT_B
Timing
Control
Gate
Drive
GND
To
Protection
Blocks
DREG
GVDD
OTW
SD
GREG
OT
GREG
Protection
DREG
GREG
UVP
DREG_RTN
DREG_RTN
BST_C
GREG
PVDD_C
Gate
Drive
PWM_CP
PWM
Receiver
OUT_C
Timing
Control
Gate
Drive
GND
Protection C
BST_D
RESET
GREG
PVDD_D
Protection D
Gate
Drive
PWM_DP
PWM
Receiver
OUT_D
Timing
Control
Gate
Drive
GND
4
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
RECOMMENDED OPERATING CONDITIONS
DVDD
Digital supply (1)
GVDD
Supply for internal gate drive and logic
regulators
PVDD_x
Half-bridge supply
MIN
TYP
MAX
UNIT
Relative to DGND
3
3.3
3.6
V
Relative to GND
16
23
25.5
V
Relative to GND, RL= 6 Ω to 8 Ω
0
23
25.5
V
125
_C
TJ
Junction temperature
(1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
0
ELECTRICAL CHARACTERISTICS
PVDD_X = 23 V, GVDD = 23 V, DVDD = 3.3 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise
noted. AC performance is recorded as a chipset with TAS5010 as the PWM processor and TAS5122 as the power stage.
SYMBOL
PARAMETER
TCase=
75°C
UNITS
MIN/TYP/
MAX
RL = 8 Ω, unclipped,
AES17 filter
24
W
Typ
RL = 8 Ω, THD = 10%,
AES17 filter
29
W
Typ
RL = 6 Ω, THD = 0.4%,
AES17 filter
30
W
Typ
RL = 6 Ω, THD = 10%,
AES17 filter
37
W
Typ
TEST CONDITIONS
TYPICAL
TA=25°C
TA=25°C
AC PERFORMANCE, BTL MODE, 1 kHz
PO
THD+N
Output power
Total harmonic distortion + noise
Vn
Output RMS noise
SNR
Signal-to-noise ratio
DR
Dynamic range
Po = 1 W/ channel, RL = 6 Ω,
AES17 filter
0.05%
Typ
Po = 10 W/channel, RL = 6 Ω,
AES17 filter
0.05%
Typ
Po = 30 W/channel, RL = 6 Ω,
AES17 filter
0.2%
Typ
A-weighted, mute, RL = 6 Ω,
20 Hz to 20 kHz, AES17 filter
240
µV
Max
95
dB
Typ
95
dB
Typ
f = 1 kHz, A-weighted,
RL = 6 Ω,, AES17 filter
f = 1 kHz, A-weighted,
RL = 6 Ω,, AES17 filter
INTERNAL VOLTAGE REGULATOR
DREG
Voltage regulator
Io = 1 mA,
PVDD = 18 V−30.5 V
3.1
V
Typ
GREG
Voltage regulator
Io = 1.2 mA,
PVDD = 18 V−30.5 V
13.4
V
Typ
IGVDD
GVDD supply current, operating
fS = 384 kHz, no load, 50%
duty cycle
24 (1)
mA
Max
IDVDD
DVDD supply current, operating
fS = 384 kHz, no load
5
mA
Max
155
mΩ
Max
155
mΩ
Max
1
OUTPUT STAGE MOSFETs
RDSon,LS Forward on-resistance, LS
TJ = 25°C
RDSon,HS Forward on-resistance, HS
TJ = 25°C
(1) Measured with TI standard manufacturing hardware configuration
5
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS
PVDD_x = 23 V, GVDD = 23 V, DVDD = 3.3 V, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted
SYMBOL
PARAMETER
TEST CONDITIONS
TYPICAL
TA=25°C
TA=25°C
TCase=
75°C
UNITS
MIN/TYP/
MAX
INPUT/OUTPUT PROTECTION
Vuvp,G
Undervoltage protection limit, GVDD
7.4
OTW
Overtemperature warning
125
OTE
Overtemperature error
150
OC
Overcurrent protection
6.9
V
Min
7.9
V
Max
°C
Typ
°C
Typ
5.0
A
Min
2
V
Min
DVDD
V
Max
Max
STATIC DIGITAL SPECIFICATION
PWM_AP, PWM_BP, M1, M2, M3, SD,
OTW
VIH
High-level input voltage
VIL
Low-level input voltage
Leakage
Input leakage current
0.8
V
−10
µA
Min
10
µA
Max
22.5
kΩ
Min
0.4
V
Max
OTW/SHUTDOWN (SD)
Internally pullup R from OTW/SD to
DVDD
VOL
6
Low-level output voltage
30
IO = 4 mA
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION (BTL)
Gate-Drive
Power Supply
External Power Supply
H-Bridge
Power Supply
TAS5122
1
1 µF
56
GND
GND
2
55
GND
GVDD
3
GREG
4
53
OTW
PVDD_D
SD_CD
PVDD_D
SD_AB
OUT_D
PWM_DP
OUT_D
5
6
ERR_RCVY
49
PWM_DM
11
12
100 nF
PWM PROCESSOR
TAS50xx
13
14
PWM_CM
PWM_CP
GND
PWM_AP_2
DREG_RTN
PVDD_C
M3
PVDD_C
M2
BST_C
M1
BST_B
PWM_BP
PVDD_B
PWM_BM
OUT_B
RESET_AB
OUT_B
PWM_AM
GND
PWM_AP
GND
LPCB(2)
1000 µF
42 1.5 Ω × 2
33 nF
LPCB(2)
100 nF
37
(1) 10 µH
1.5 Ω
4.7 kΩ
470 nF 100 nF
36
GND
DGND
35
1.5 Ω
34
(1)
OUT_A
OUT_A
DVDD
PVDD_A
31
GREG
100 nF 4.7 kΩ
PVDD_A
32
25
10 µH
100 nF
33
24
BST_A
27
28
33 nF
43
38
GND
1 µF
44
39
23
26
100 nF 4.7 kΩ
40
21
100 nF
10 µH
100 nF
PVDD_B
20
22
(1)
41
DREG
19
100 Ω
1.5 Ω
46
45
18
VALID_2
47
OUT_C
17
PWM_AM_2
4.7 kΩ
470 nF 100 nF
OUT_C
15
16
(1) 10 µH
1.5 Ω
48
RESET_CD
10
100 nF
GND
9
VALID_1
LPCB(2)
52
50
8
PWM_AM_1
100 nF
33 nF
51
7
PWM_AP_1
54 1.5 Ω
BST_D
GND
GVDD
GND
GND
33 nF
LPCB(2)
1000 µF
30 1.5 Ω
29
100 nF
(1) Voltage Clamp 30 V, PN SMAJ28A, MFG MICROSEMI
(2) LPCB: Track in the PCB (1 mm wide and 50 mm long)
7
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From
PWM
Processor
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
Figure 1. Typical Single-Ended Design With TAS5122 DCA
8
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
RL = 6 Ω
TC = 75°C
TAS5122SE
1
0.1
TAS5122BTL
0.01
500m
1
10
RL = 6 Ω
TC = 75°C
PO = 30 W
0.1
PO = 10 W
PO = 1 W
0.01
20
50
100
PO − Output Power − W
Figure 2
10k 20k
Figure 3
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
−60 dBFS FFT
1
THD+N − Total Harmonic Distortion + Noise − %
0
RL = 6 Ω
FFT = −60 dB
TC = 75°C
TAS5010 PWM Processor Device
−20
Noise Amplitude − dBr
1k
f − Frequency − Hz
−40
−60
−80
−100
−120
−140
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 4
16
18
20
22
RL = 6 Ω
TC = 75°C
0.1
0.01
40m
100m
1
10
40
PO − Output Power − W
Figure 5
9
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
OUTPUT POWER
vs
H-BRIDGE VOLTAGE
SYSTEM OUTPUT STAGE EFFICIENCY
vs
OUTPUT POWER
55
100
50
η − System Output Stage Efficiency − %
TC = 75°C
PO − Output Power − W
45
40
35
30
25
RL = 6 Ω
20
15
RL = 8 Ω
10
5
0
90
80
70
60
50
40
30
20
f = 1 kHz
RL = 6 Ω
TC = 75°C
10
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
0
5
10
VDD − Supply Voltage − V
Figure 6
20
25
30
Figure 7
POWER LOSS
vs
OUTPUT POWER
OUTPUT POWER
vs
CASE TEMPERATURE
5
40
f = 1 kHz
RL = 6 Ω
TC = 75°C
38
PVDD = 23 V
RL = 6 Ω
36
PO − Output Power − W
4
Ptot − Power Loss − W
15
PO − Output Power − W
3
2
1
34
32
Channel 2
Channel 1
30
28
26
24
22
0
20
0
5
10
15
20
PO − Output Power − W
Figure 8
10
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130
TC − Case Temperature − °C
Figure 9
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
AMPLITUDE
vs
FREQUENCY
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
3.0
200
2.5
190
Amplitude − dBr
1.5
ron − On-State Resistance − mΩ
2.0
RL = 8 Ω
1.0
RL = 6 Ω
0.5
0.0
−0.5
−1.0
−1.5
−2.0
180
170
160
150
140
130
−2.5
−3.0
10
120
100
1k
f − Frequency − Hz
Figure 10
10k
50k
0
10
20
30
40
50
60
70
80
90 100
TJ − Junction Temperature − °C
Figure 11
11
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages,
GVDD and PVDD_x.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turnon
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal low-dropout
regulators (LDRs) to 3.3 V.
The gate-driver LDR can be bypassed for reducing idle
loss in the device by shorting GREG to GVDD and directly
feeding in 12 V. This can be useful in an application where
thermal conduction of heat from the device is difficult.
Bypassing the LDR reduces power dissipation.
PVDD_x is the H-bridge power supply pin. Two power pins
exist for each half-bridge to handle the current density. It
is important that the circuitry recommendations
concerning the PVDD_x pins are followed carefully both
topologyand
layout-wise.
For
topology
recommendations, see the System Configuration Used for
Characterization
section.
Following
these
recommendations is important for parameters like EMI,
reliability, and performance.
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
> 1 ms
> 1 ms
RESET
not charged. To comply with the click and pop scheme and
use of non-TI PWM processors, it is recommended to use
a 4-kΩ pulldown resistor on each PWM output node to
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor (see the System
Configuration Used for Characterization section).
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
power stage bootstrap capacitor is charged.
RESET can now be released if the modulator is powered
up and streaming PWM signals to the power stage
PWM_xP.
A constant HIGH dc level on PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually ran out of BST capacitor energy and might
damage the device.
An unknown state of the PWM output signals from the
processor is illegal and should be avoided, which in
practice means that the PWM processor must be powered
up and initialized before RESET is deasserted HIGH to the
power stage.
Powering Down
For powering down the power stage, an opposite
approach is necessary. RESET must be asserted LOW
before the valid PWM signal is removed.
When TI PWM processors are used with TI power stages,
the correct timing control of RESET and PWM_xP is
performed by the modulator.
Precaution
The TAS5122 must always start up in the high-impedance
(Hi-Z) state. In this state, the bootstrap (BST) capacitor is
precharged by a resistor on each PWM output node to
ground. See System Configuration Used for
Characterization. This ensures that the power stage is
ready for receiving PWM pulses, indicating either HIGHor LOW-side turnon after RESET is deasserted to the
power stage.
With the following pulldown and BST capacitor size, the
charge time is:
GVDD(1)
PVDD_x(1)
PWM_xP
(1) PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are at this point
12
C = 33 nF, R = 4.7 kΩ
R × C × 5 = 775.5 µs
After GVDD has been applied, it takes approximately
800 µs to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms, the
power stage BST is charged and ready. RESET can now
be released if the PWM modulator is ready and is
streaming valid PWM signals to the power stage. Valid
PWM signals are switching PWM signals with a frequency
between 350−400 kHz. A constant HIGH level on the
PWM_xP forces the high-side MOSFET ON until it
eventually runs out of BST capacitor energy. Putting the
device in this condition should be avoided.
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SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
In practice this means that the DVDD-to-PWM processor
should be stable and initialization should be completed
before RESET is deasserted to the power stage.
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other PWM processor device. The pin is open-drain with
an internal pullup to DVDD.
The logic output is, as shown in the following table, a
combination of the device state and RESET input:
SD
RESET
0
0
Not used
DESCRIPTION
0
1
Device in protection mode, i.e., UVP and/or OC
and/or OT error
1(2)
0
Device set high-impedance (Hi-Z), SD forced high
1
1
Overcurrent (OC) Protection
The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Demodulation Filter Design in the
Application Information section of this data sheet for
design constraints.
Overtemperature (OT) Protection
A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125°C. The OT protection circuit is shared by all
half-bridges.
Undervoltage (UV) Protection
Normal operation
(2) SD is pulled high when RESET is asserted low independent
of chip state (i.e., protection mode). This is desirable to
maintain compatibility with some TI PWM processors.
Temperature Warning Pin: OTW
The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup to DVDD.
OTW
The device can be recovered by toggling RESET low and
then high, after all errors are cleared.
DESCRIPTION
0
Junction temperature higher than 125°C
1
Junction temperature lower than 125°C
Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.
Reset Functions
The functions of the reset input are:
D
Reset is used for reenabling operation after a
latching error event (PMODE1).
D
Reset is used for disabling output stage
switching (mute function).
The error latch is cleared on the falling edge of reset and
normal operation is resumed when reset goes high.
Overall Reporting
The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.
Table 1. Error Signal Decoding
OTW
SD
DESCRIPTION
0
0
Overtemperature error (OTE)
0
1
Overtemperature warning (OTW)
1
0
Overcurrent (OC) or undervoltage (UVP) error
1
1
Normal operation, no errors/warnings
Chip Protection
The TAS5122 protection function is implemented in a
closed loop with, for example, a system controller or other
TI PWM processor device. The TAS5122 contains three
individual systems protecting the device against fault
conditions. All of the error events covered result in the
output stage being set in a high-impedance state (Hi-Z) for
maximum protection of the device and connected
equipment.
PROTECTION MODE
Autorecovery (AR) After Errors (PMODE0)
In autorecovery mode (PMODE0), the TAS5122 is
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time the
device auto-recovers, i.e., operation is automatically
resumed provided that the system is fully operational.
The autorecovery timing is set by counting PWM input
cycles, i.e., the timing is relative to the switching frequency.
The AR system is common to both half-bridges.
Timing and Function
The function of the autorecovery circuit is as follows:
1. An error event occurs and sets the
protection latch (output stage goes Hi-Z).
2. The counter is started.
13
www.ti.com
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
3. After n/2 cycles, the protection latch is
cleared but the output stage remains Hi-Z
(identical to pulling RESET low).
4. After n cycles, operation is resumed
(identical to pulling RESET high) (n = 512).
Error
Protection
Latch
Shutdown
APPLICATION INFORMATION
DEMODULATION FILTER DESIGN AND
SPIKE CONSIDERATIONS
The output square wave is susceptible to overshoots
(voltage spikes). The spike characteristics depend on
many elements, including silicon design and application
design and layout. The device should be able to handle
narrow spike pulses, less than 65 ns, up to 65 volts peak.
For more detailed information, see TI application report
SLEA025.
The PurePath Digital amplifier outputs are driven by
heavy-duty DMOS transistors in an H-bridge
configuration. These transistors are either off or fully on,
which reduces the DMOS transistor on-state resistance,
RDSon, and the power dissipated in the device, thereby
increasing efficiency.
SD
Autorecovery
PWM
Counter
AR-RESET
Figure 12. Autorecovery Function
Latching Shutdown on All Errors (PMODE1)
In latching shutdown mode, all error situations result in a
permanent shutdown (output stage Hi-Z). Reenabling can
be done by toggling the RESET pin.
The result is a square-wave output signal with a duty cycle
that is proportional to the amplitude of the audio signal. It
is recommended that a second-order LC filter be used to
recover the audio signal. For this application, EMI is
considered important; therefore, the selected filter is the
full-output type shown in Figure 13.
TAS51xx
Output A
L
R(Load)
C1A
All Protection Systems Disabled (PMODE2)
In PMODE2, all protection systems are disabled. This
mode is purely intended for testing and characterization
purposes and thus not recommended for normal device
operation.
C2
C1B
Output B
L
MODE Pins Selection
The protection mode is selected by shorting M1/M2 to
DREG or DGND according to Table 2.
Table 2. Protection Mode Selection
M1
M2
0
0
Reserved
PROTECTION MODE
0
1
Latching shutdown on all errors (PMODE1)
1
0
Reserved
1
1
Reserved
The output configuration mode is selected by shorting the
M3 pin to DREG or DGND according to Table 3.
Table 3. Output Mode Selection
M3
14
OUTPUT MODE
0
Bridge-tied load output stage (BTL)
1
Reserved
Figure 13. Demodulation Filter (AD Mode)
The main purpose of the output filter is to attenuate the
high-frequency switching component of the PurePath
Digital amplifier while preserving the signals in the audio
band.
Design of the demodulation filter affects the performance
of the power amplifier significantly. As a result, to ensure
proper operation of the overcurrent (OC) protection circuit
and meet the device THD+N specifications, the selection
of the inductors used in the output filter must be considered
according to the following. The rule is that the inductance
should remain stable within the range of peak current seen
at maximum output power and deliver at least 5 µH of
inductance at 15 A.
If this rule is observed, the TAS5122 does not have
distortion issues due to the output inductors, and
overcurrent conditions do not occur due to inductor
saturation in the output filter.
www.ti.com
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
Another parameter to be considered is the idle current loss
in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for
dissipation is less than 0.05.
In general, 10-µH inductors suffice for most applications.
The frequency response of the amplifier is slightly altered
by the change in output load resistance; however, unless
tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10 µH.
The graph in Figure 14 displays the inductance vs current
characteristics of two inductors that are recommended for
use with the TAS5122.
INDUCTANCE
vs
CURRENT
THERMAL INFORMATION
RθJA is a system thermal resistance from junction to
ambient air. As such, it is a system parameter with roughly
the following components:
D
RθJC (the thermal resistance from junction to
case, or in this case the metal pad)
D
D
Thermal grease thermal resistance
Heatsink thermal resistance
RθJC has been provided in the Package Dissipation
Ratings section.
The thermal grease thermal resistance can be calculated
from the exposed pad area and the thermal grease
manufacturer’s area thermal resistance (expressed in
°C-in2/W). The area thermal resistance of the example
thermal grease with a 0.002-inch-thick layer is about 0.1
°C-in2/W. The approximate exposed pad area is as
follows:
56-pin HTSSOP
11
DFB1310A
0.045 in2
Dividing the example thermal grease area resistance by
the surface area gives the actual resistance through the
thermal grease for both ICs inside the package:
10
L - Inductance - µH
9
56-pin HTSSOP
DASL983XX-1023
8
2.27 °C/W
The thermal resistance of thermal pads is generally
considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance.
Neither pads nor tape should be used with either of these
two packages. A thin layer of thermal grease with careful
clamping of the heatsink is recommended. It may be
difficult to achieve a layer 0.001 inch thick or less, so the
modeling below is done with a 0.002-inch-thick layer,
which may be more representative of production thermal
grease thickness.
7
6
5
4
0
5
10
15
I - Current - A
Figure 14. Inductance Saturation
Heatsink thermal resistance is generally predicted by the
heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.
Thus, for a single monaural IC, the system RθJA = RθJC +
thermal grease resistance + heatsink resistance.
The selection of the capacitor that is placed across the
output of each inductor (C2 in Figure 13) is simple. To
complete the output filter, use a 0.47-µF capacitor with a
voltage rating at least twice the voltage applied to the
output stage (PVDD).
DCA THERMAL INFORMATION
This capacitor should be a good quality polyester dielectric
such as a Wima MKS2-047ufd/100/10 or equivalent.
The PowerPAD package (thermally enhanced
HTSSOP) combines fine-pitch, surface-mount technology
with thermal performance comparable to much larger
power packages.
In order to minimize the EMI effect of unbalanced ripple
loss in the inductors, 0.1-µF, 50-V, SMD capacitors (X7R
or better) (C1A and C1B in Figure 13) should be added
from the output of each inductor to ground.
The thermally enhanced DCA package is based on the
56-pin HTSSOP, but includes a thermal pad (see
Figure 15) to provide an effective thermal contact between
the IC and the PCB.
The PowerPAD package is designed to optimize the heat
transfer to the PWB. Because of the small size and limited
mass of an HTSSOP package, thermal enhancement is
15
www.ti.com
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
achieved by improving the thermal conduction paths that
remove heat from the component. The thermal pad is
formed using a patented lead-frame design and
manufacturing technique to provide a direct connection to
the heat-generating IC. When this pad is soldered or
otherwise thermally coupled to an external heat dissipater,
high power dissipation in the ultrathin, fine-pitch,
surface-mount package can be reliably achieved.
soldered to the board) should be similar to the design in the
following figures. The cooling approach is to conduct the
dissipated heat into the via pads on the board, through the
vias in the board, and into a heatsink (aluminum bar) (if
necessary).
Figure 15 shows a recommended land pattern on the
PCB.
Thermal Methodology for the DCA 56-Pin,
2y15-W, 8-W Package
The thermal design for the DCA part (e.g., thermal pad
Copper Layer − Component Side
Solder
PowerPAD
TAS5122DCA
5y11 Vias (f 0.3 mm)
4 mm
8 mm
Figure 15. Recommended Land Pattern
The lower via pad area, slightly larger than the IC pad itself,
is exposed with a window in the solder resist on the bottom
surface of the board. It is not coated with solder during the
board construction to maintain a flat surface. In production,
this can be accomplished with a peelable solder mask.
An aluminum bar is used to keep the through-hole leads
16
from shorting to the chassis. The thermal compound
shown has a pad-to-aluminum bar thermal resistance of
about 3.2°C/W.
The chassis provides the only heatsink to air and is chosen
as representative of a typical production cooling approach.
www.ti.com
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
Insulating
Front Panel
Stereo
Amplifier
Board
Insulating
Back Panel
Plastic Top
PCB (3.65C/W)
56-Pin DCA Package
(1.145C/W)
ÔÔ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÔÔ
Wakefield Type 126
Thermal Compound
Under Via Pads
(3.2°C/W)
1 mm
8-mm y 10-mm y 40-mm
Aluminum Bar
(0.09°C/W)
Wakefield Type 126
Thermal Compound
(0.1°C/W)
Aluminum Chassis 7.2 in. y 1 in. y 0.1 in. Thick
Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W)
Figure 16. 56-Pin DCA Package Cross-Sectional View (Side)
Plastic Top
PCB (3.6°C/W)
Stereo
Amplifier
Board
56-Pin DCA Package
(1.14°C/W)
(2 Places)
4-40 Machine Screw
With Star Washer
and Nut
(3 Places)
ÔÔ
ÔÔ
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÖÖ
ÖÖ
ÔÔ
ÔÔ
Wakefield Type 126
Thermal Compound
(0.1°C/W)
Aluminum Chassis 7.2 in. y. 1 in y 0.1 in. Thick
Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W)
Wakefield Type 126
Thermal Compound
Under Via Pads
(3.2°C/W)
8-mm y 10-mm y 40-mm
Aluminum Bar
(0.09°C/W)
Figure 17. Spatial Separation With Multiple Packages
The land pattern recommendation shown in Figure 15 is
for optimal performance with aluminum bar thermal
resistance of 0.09°C/W. The following table shows the
decrease in thermal resistance through the PCB with a
corresponding increase in the land pattern size. Use the
table for thermal design tradeoffs.
17
www.ti.com
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
LAND PATTERN
the output stage prior to operation is in the
high-impedance state, this is done by having a
passive pulldown resistor on each speaker
output to GND (see System Configuration Used
for Characterization).
PCB THERMAL
RESISTANCE
7×13 vias (5×10 mm)
2.2°C/W
5×11 vias (4×8 mm)
3.6°C/W
Other things that can affect the audible click level:
Thermal
Pad
8,20 mm
7,20 mm
D
The spectrum of the click seems to follow the
speaker impedance vs frequency curve—the
higher the impedance, the higher the click
energy.
D
Crossover filters used between woofer and
tweeter in a speaker can have high impedance
in the audio band, which should be avoided if
possible.
Another way to look at it is that the speaker impulse
response is a major contributor to how the click energy is
shaped in the audio band and how audible the click is.
The following mode transitions feature click and pop
reduction in Texas Instruments PWM processors.
STATE
3,90 mm
2,98 mm
Normal(1)
→ Mute
Yes
Mute
→ Normal(1)
Yes
Normal(1)
Error recovery
→
(ERRCVY)
Yes
Error recovery
Normal(1)
→ Normal(1)
Yes
→ Hard reset
→ Normal(1)
Yes
Hard reset
(1) Normal = switching
Figure 18. Thermal Pad Dimensions for DCA
Package
CLICK AND
POP REDUCED
No
REFERENCES
1.
TAS5000 Digital Audio PWM Processor data
manual (SLAS270)
TI modulators feature a pop and click reduction system
that controls the timing when switching starts and stops.
2.
True Digital Audio Amplifier TAS5001 Digital Audio
PWM Processor data sheet (SLES009)
Going from nonswitching to switching operation causes a
spectral energy burst to occur within the audio bandwidth,
which is heard in the speaker as an audible click, for
instance, after having asserted RESET LH during a
system start-up.
3.
True Digital Audio Amplifier TAS5010 Digital Audio
PWM Processor data sheet (SLAS328)
4.
True Digital Audio Amplifier TAS5012 Digital Audio
PWM Processor data sheet (SLES006)
5.
TAS5026 Six-Channel Digital Audio
Processor data manual (SLES041)
PWM
6.
TAS5036A Six-Channel Digital Audio
Processor data manual (SLES061)
PWM
7.
TAS3103 Digital Audio Processor With 3D Effects
data manual (SLES038)
8.
Digital Audio Measurements application report
(SLAA114)
9.
System Design Considerations for True Digital
Audio Power Amplifiers application report
(SLAA117)
CLICK AND POP REDUCTION
To make this system work properly, the following design
rules must be followed when using the TAS5122 power
stage:
D
D
18
The relative timing between the PWM_AP/M_x
signals and their corresponding VALID_x signal
should not be skewed by inserting delays,
because this increases the audible amplitude
level of the click.
The output stage must start switching from a
fully discharged output filter capacitor. Because
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TAS5122DCA
ACTIVE
HTSSOP
DCA
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TAS5122
TAS5122DCAR
ACTIVE
HTSSOP
DCA
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TAS5122
TAS5122DCARG4
ACTIVE
HTSSOP
DCA
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TAS5122
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5122DCAR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DCA
56
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5122DCAR
HTSSOP
DCA
56
2000
350.0
350.0
43.0
Pack Materials-Page 2
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