Texas Instruments | PGA2320: Stereo Audio Volume Control (Rev. B) | Datasheet | Texas Instruments PGA2320: Stereo Audio Volume Control (Rev. B) Datasheet

Texas Instruments PGA2320: Stereo Audio Volume Control (Rev. B) Datasheet
PGA2320
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
Stereo Audio Volume Control
FEATURES
D DIGITALLY-CONTROLLED ANALOG VOLUME
CONTROL:
Two Independent Audio Channels
Serial Control Interface
Zero Crossing Detection
Mute Function
D WIDE GAIN AND ATTENUATION RANGE:
+31.5dB to −95.5dB with 0.5dB Steps
D LOW NOISE AND DISTORTION:
D
120dB Dynamic Range
0.0003% THD+N at 1kHz
LOW INTERCHANNEL CROSSTALK:
−126dBFS
NOISE-FREE LEVEL TRANSITIONS
POWER SUPPLIES: +15V Analog, +5V Digital
D
D
D AVAILABLE IN SOL−16 PACKAGE
D PIN-FOR-PIN COMPATIBLE WITH THE
PGA2310
APPLICATIONS
D
D
D
D
D
D
D
D
AUDIO AMPLIFIERS
MIXING CONSOLES
MULTI-TRACK RECORDERS
BROADCAST STUDIO EQUIPMENT
MUSICAL INSTRUMENTS
EFFECTS PROCESSORS
A/V RECEIVERS
CAR AUDIO SYSTEMS
DESCRIPTION
The PGA2320 is a high-performance, stereo audio volume
control designed for professional and high-end consumer
audio systems. The ability to operate from ±15V analog
power supplies enables the PGA2320 to process input
signals with large voltage swings, thereby preserving the
dynamic range available in the overall signal path. Using
high performance operational amplifier stages internal to
the PGA2320 yields low noise and distortion, while
providing the capability to drive 600Ω loads directly
without buffering. The three-wire serial control interface
allows for connection to a wide variety of host controllers,
in addition to support for daisy-chaining of multiple
PGA2320 devices.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2004, Texas Instruments Incorporated
! ! www.ti.com
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PGA2320
UNIT
VA+
VA−
+15.5
V
−15.5
V
VD+
+5.5
V
Analog input voltage
0 to VA+, VA−
V
Digital input voltage
−0.3 to VD+
V
Operating temperature range
−40 to +85
°C
Storage temperature range
−65 to +150
°C
Junction temperature
+150
°C
Lead temperature (soldering, 10s)
+300
°C
Supply voltage
Package temperature (IR, reflow, 10s)
+235
°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this data
sheet.
2
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted.
PGA2320
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS
Step Size
Gain Error
Gain Setting = 31.5dB
0.5
dB
±0.1
dB
±0.1
dB
Input Resistance
12
kΩ
Input Capacitance
18
pF
Gain Matching
AC CHARACTERISTICS
THD+N
Dynamic Range
VIN = 10VPP, f = 1kHz
VIN = AGND, Gain = 0dB
Voltage Range, Input and Output
Output Noise
Interchannel Crosstalk
0.0003
115
120
(VA−) + 0.86
VIN = AGND, Gain = 0dB
f = 1kHz
0.001
10.5
%
dB
(VA+) − 0.86
17.5
−126
V
µVRMS
dBFS
OUTPUT BUFFER
Offset Voltage
VIN = AGND, Gain = 0dB
1
Load Capacitance Stability
7.5
1000
mV
pF
Short-Circuit Current
75
mA
Unity-Gain Bandwidth, Small Signal
1
MHz
DIGITAL CHARACTERISTICS
High-Level Input Voltage, VIH
+2.0
Low-Level Input Voltage, VIL
−0.3
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
IO = 200µA
IO = −2mA
VD+
0.8
(VD+) − 1.0
Input Leakage Current
V
V
V
1
0.4
V
10
µA
6.25
MHz
SWITCHING CHARACTERISTICS
Serial Clock (SCLK) Frequency
tSCLK
tPH
80
ns
Serial Clock (SCLK) Pulse Width
High
tPL
80
ns
MUTE Pulse Width Low
tMI
2.0
ms
tSDS
tSDH
20
ns
20
ns
tCSCR
tCFCS
90
ns
35
ns
Serial Clock (SCLK) Pulse Width Low
0
Input Timing
SDI Setup Time
SDI Hold Time
CS Falling to SCLK Rising
SCLK Falling to CS Rising
Output Timing
CS Low to SDO Active
SCLK Falling to SDO Data Valid
tCSO
tCFDO
35
ns
60
ns
POWER SUPPLY
Operating Voltage
VA+
VA−
VD+
Quiescent Current
+4.5
+15
+15.5
V
−4.5
−15
−15.5
V
+4.5
+5
+5.5
V
IA+
IA−
VA+ = +15V
VA− = −15V
11
16
mA
11
16
mA
ID+
VD+ = +5V
0.6
1.5
mA
3
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
PIN CONFIGURATION
PIN ASSIGNMENTS
Top View
ZCEN
16
VINL
NAME
FUNCTION
1
ZCEN
Zero Crossing Enable Input (Active High)
2
CS
Chip-Select Input (Active Low)
3
SDI
Serial Data input
4
Digital Power Supply, +5V
5
VD+
DGND
6
SCLK
Serial Clock Input
Digital Ground
CS
2
15
AGNDL
SDI
3
14
VOUTL
7
SDO
Serial Data Output
VD+
4
13
VA−
8
MUTE
Mute Control Input (Active Low)
9
VINR
AGNDR
Analog Input, Right Channel
Analog Output, Right Channel
PGA2320
DGND
5
12
VA+
SCLK
6
11
VOUTR
11
SDO
7
10
AGNDR
12
VOUTR
VA+
13
VA−
Analog Power Supply, −15V
14
Analog Output, Left Channel
15
VOUTL
AGNDL
16
VINL
MUTE
4
1
PIN
8
9
VINR
10
Analog Ground, Right Channel
Analog Power Supply, +15V
Analog Ground, Left Channel
Analog Input, Left Channel
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted.
THD+N vs INPUT AMPLITUDE
(Gain = 0dB, f = 1kHz)
FREQUENCY RESPONSE (0dB = 6.0VRMS)
GAIN = 0dB
0.1
1.0
0.8
0.6
0.01
0.2
THD+N (%)
Amplitude (dB)
0.4
0
−0.2
−0.4
0.001
−0.6
−0.8
−1.0
10
100
1k
10k
0.0001
100m
100k 200k
1
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 3.0VRMS , RL = 100kΩ)
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 3.0VRMS , RL = 600Ω)
0.01
THD+N (%)
THD+N (%)
0.01
0.001
0.0001
0.001
0.0001
20
100
1k
10k
20k
20
100
1k
10k
Input Frequency (Hz)
Input Frequency (Hz)
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 8.5VRMS , RL = 100kΩ)
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 8.5VRMS , RL = 600Ω)
20k
0.01
THD+N (%)
0.01
THD+N (%)
10
Input Amplitude (VRMS)
Frequency (Hz)
0.001
0.0001
0.001
0.0001
20
100
1k
Input Frequency (Hz)
10k
20k
20
100
1k
10k
20k
Input Frequency (Hz)
5
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted.
Crosstalk (dB)
CROSSTALK OR CHANNEL SEPARATION
vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 8.5VRMS)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
20
100
1k
Input Frequency (Hz)
6
10k
20k
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
GENERAL DESCRIPTION
The PGA2320 is a stereo audio volume control. It may be
used in a wide array of professional and consumer audio
equipment. The PGA2320 is fabricated in a mixed-signal
BiCMOS process in order to take advantage of the
superior analog characteristics that the process offers.
The heart of the PGA2320 is a resistor network, an analog
switch array, and a high-performance bipolar op amp
stage. The switches are used to select taps in the resistor
network that, in turn, determine the gain of the amplifier
stage. Switch selections are programmed using a serial
control port. The serial port allows connection to a wide
variety of host controllers. Figure 1 shows a functional
block diagram of the PGA2320.
ANALOG INPUTS AND
OUTPUTS
The PGA2320 includes two independent channels,
referred to as the left and right channels. Each channel has
a corresponding input and output pin. The input and output
pins are unbalanced, or referenced to analog ground
(either AGNDR or AGNDL). The inputs are named VINR
(pin 9) and VINL (pin 16), while the outputs are named
VOUTR (pin 11) and VOUTL (pin 14).
It is important to drive the PGA2320 with a low source
impedance. If a source impedance of greater than 600Ω is
used, the distortion performance of the PGA2320 will
begin to degrade.
POWER-UP STATE
On power up, all internal flip-flops are reset. The gain byte
value for both the left and right channels are set to 00HEX,
or mute condition. The gain will remain at this setting until
the host controller programs new settings for each channel
via the serial control port.
VINL
16
14
8
VOUTL
MUTE
MUX
8
1
8
AGNDL
AGNDR
2
15
Serial
Control
Port
10
6
3
7
ZCEN
CS
SCLK
SDI
SDO
8
8
MUX
11
VINR
9
12
VA+
13
VA −
4
VOUTR
5
VD+ DGND
Figure 1. PGA2320 Block Diagram
7
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
gain settings. Data is formatted as MSB first, straight
binary code. SCLK is the serial clock input. Data is clocked
into SDI on the rising edge of SCLK.
SERIAL CONTROL PORT
The serial control port is utilized to program the gain
settings for the PGA2320. The serial control port includes
three input pins and one output pin. The inputs include CS
(pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin
is SDO (pin 7).
SDO is the serial data output pin, and is used when
daisy-chaining multiple PGA2320 devices. Daisy-chain
operation is described in detail later in this section. SDO
is a tristate output, and assumes a high impedance state
when CS is high.
The CS pin functions as the chip select input. Data may be
written to the PGA2320 only when CS is low. SDI is the
serial data input pin. Control data is provided as a 16-bit
word at the SDI pin, 8 bits each for the left and right channel
The protocol for the serial control port is shown in Figure 2.
See Figure 3 for detailed timing specifications of the serial
control port.
CS
SCLK
SDI
R7
R6
R5
R4
R3
R2
R1
R0
L7
L6
L5
L4
L3
L2
L1
L0
SDO
R7
R6
R5
R4
R3
R2
R1
R0
L7
L6
L5
L4
L3
L2
L1
L0
Gain Byte Format is MSB First, Straight Binary
R0 is the Least Significant Bit of the Right Channel Gain Byte
R7 is the Most Significant Bit of the Right Channel Gain Byte
L0 is the Least Significant Bit of the Left Channel Gain Byte
L7 is the Most Significant Bit of the Left Channel Gain Byte
SDI is latched on the rising edge of SCLK
SDO transitions on the falling edge of SCLK
Figure 2. Serial Interface Protocol
8
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
GAIN SETTINGS
For N = 1 to 255:
The gain for each channel is set by its corresponding 8-bit
code, either R[7:0] or L[7:0]; see Figure 2. The gain code
data is straight binary format. If we let N equal the decimal
equivalent of R[7:0] or L[7:0], then the following
relationships exist for the gain settings:
Gain (dB) = 31.5 − [0.5 • (255 − N)]
This results in a gain range of +31.5dB (with N = 255) to
−95.5dB (with N = 1).
Changes in gain setting may be made with or without zero
crossing detection. The operation of the zero crossing
detector and timeout circuitry is discussed later in this data
sheet.
For N = 0:
Mute Condition. The input multiplexer is connected to
analog ground (AGNDR or AGNDL).
CS
tCSCR
t SDS
tCFCS
SCLK
tSDH
SDI
MSB
SDO
tCSO
tCFDO
Figure 3. Serial Interface Timing Requirements
9
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
DAISY-CHAINING MULTIPLE
PGA2320 DEVICES
In order to reduce the number of control signals required
to support multiple PGA2320 devices on a printed circuit
board, the serial control port supports daisy-chaining of
multiple PGA2320 devices. Figure 4 shows the
connection requirements for daisy-chain operation. This
arrangement allows a three-wire serial interface to control
many PGA2320 devices.
As shown in Figure 4, the SDO pin from device #1 is
connected to the SDI input of device #2, and is repeated
for additional devices. This configuration in turn forms a
large shift register, in which gain data may be written for all
PGA2320s connected to the serial bus. The length of the
shift register is 16 x N bits, where N is equal to the number
of PGA2320 devices included in the chain. The CS input
must remain low for 16 x N SCLK periods, where N is the
number of devices connected in the chain, in order to allow
enough SCLK cycles to load all devices.
ZERO CROSSING DETECTION
The PGA2320 includes a zero crossing detection function
that can provide for noise-free level transitions. The
concept is to change gain settings on a zero crossing of the
input signal, thus minimizing audible glitches. This
function is enabled or disabled using the ZCEN input
(pin 1). When ZCEN is low, zero crossing detection is
disabled. When ZCEN is high, zero crossing detection will
be enabled.
The zero crossing detection takes effect with a change in
gain setting for a corresponding channel. The new gain
setting will not be latched until either two zero crossings
are detected, or a timeout period of 16ms has elapsed
without detecting two zero crossings. In the case of a
timeout, the new gain setting takes effect with no attempt
to minimize audible artifacts.
Controller
SCLK
SDI
CS
Audio
Input
VINL
VINR
PGA2320
#1
SDO
VOUTL
VOUTR
SDI
SCLK
100kΩ
CS
Audio
Input
100kΩ
VINL
VINR
PGA2320
#2
SDO
VOUTL
VOUTR
SDI
SCLK
CS
Audio
Input
VINL
VINR
PGA2320
#3
VOUTL
SDO
VOUTR
Figure 4. Daisy-Chaining Multiple PGA2320 Devices
10
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
MUTE FUNCTION
APPLICATIONS INFORMATION
The PGA2320 includes a mute function. This function may
be activated by either the MUTE input (pin 8), or by setting
the gain byte value for one or both channels to 00HEX. The
MUTE pin may be used to mute both channels, while the
gain setting may be used to selectively mute the left and
right channels. Muting is accomplished by switching the
input multiplexer to analog ground (AGNDR or AGNDL)
with zero crossing enabled.
This section includes additional information that is
pertinent to designing the PGA2320 into an end
application.
RECOMMENDED CONNECTION DIAGRAM
Figure 5 depicts the recommended connections for the
PGA2320. Power-supply bypass capacitors should be
placed as close to the PGA2320 package as physically
possible.
The MUTE pin is active low. When MUTE is low, each
channel will be muted following the next zero crossing
event or timeout that occurs on that channel. If MUTE
becomes active while CS is also active, the mute will take
effect once the CS pin goes high. When the MUTE pin is
high, the PGA2320 operates normally, with the mute
function disabled.
+5V Digital
ZCEN
CS
1
16
2
15
3
14
VINL
SDI
VOUTL
C3
4
C1
Controller
C2
13
− 15V Analog
PGA2320
5
SCLK
C4
+15V Analog
12
6
11
7
10
8
9
C5
C6
VOUTR
SDO
MUTE
To
Additional
PGA2320s
VINR
C2, C3, C5 = 0.1µF ceramic or metal film.
C1, C4, C6 = 10µF tantalum or aluminum electrolytic.
DGND
AGND
Figure 5. Recommended Connection Diagram
11
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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
PRINTED CIRCUIT BOARD LAYOUT
GUIDELINES
It is recommended that the ground planes for the digital
and analog sections of the printed circuit board (PCB) be
separate from one another. The planes should be
connected at a single point. Figure 6 shows the
recommended PCB floor plan for the PGA2320.
Analog Power
Digital Power
+5V
DGND
Host
The PGA2320 is mounted so that it straddles the split between the digital and analog ground planes. Pins 1 through
8 are oriented to the digital side of the board, while pins 9
through 16 are on the analog side of the board.
AGND
− 15V
+15V
Analog
Inputs
and
Outputs
PGA2320
DIGITAL GROUND PLANE
Digital
Ground
ANALOG GROUND PLANE
Analog
Ground
Figure 6. Typical PCB Layout Floor Plan
12
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
PGA2320IDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PGA2320I
PGA2320IDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PGA2320I
PGA2320IDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PGA2320I
PGA2320IDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PGA2320I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PGA2320IDWR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PGA2320IDWR
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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