Texas Instruments | 50-mW Ultralow Voltage Stereo Headphone Audio Power Amplifier (Rev. B) | Datasheet | Texas Instruments 50-mW Ultralow Voltage Stereo Headphone Audio Power Amplifier (Rev. B) Datasheet

Texas Instruments 50-mW Ultralow Voltage Stereo Headphone Audio Power Amplifier (Rev. B) Datasheet
TPA6100A2D
www.ti.com
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
50-mW ULTRALOW VOLTAGE STEREO HEADPHONE AUDIO POWER AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
(1)
50-mW Stereo Output
Low Supply Current . . . 0.75 mA
Low Shutdown Current . . . 50 nA
Pin Compatible With LM4881 and TPA102
Pop Reduction Circuitry
Internal Midrail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
– MSOP and SOIC
1.6-V to 3.6-V Supply Voltage Range
D PACKAGE
(TOP VIEW)
BYPASS
GND
SHUTDOWN
IN2–
(1)
1
8
2
7
3
6
4
5
IN1–
VO1
VDD
VO2
DGK PACKAGE
(TOP VIEW)
BYPASS
GND
SHUTDOWN
IN2–
1
8
2
7
3
6
4
5
IN1–
VO1
VDD
VO2
The polarity of the SHUTDOWN pin is reversed.
DESCRIPTION
The TPA6100A2D is a stereo audio power amplifier packaged in either an 8-pin SOIC package or an 8-pin
MSOP package capable of delivering 50 mW of continuous RMS power per channel into 16-Ω loads. Amplifier
gain is externally configured by a means of three resistors per input channel and does not require external
compensation for settings of 1 to 10.
The TPA6100A2D is optimized for battery applications because of its low supply current, shutdown current, and
THD+N. To obtain the low-supply voltage range, the TPA6100A2D biases BYPASS to VDD/4. A resistor with a
resistance equal to RF must be added from the inputs to ground to allow the output to be biased at VDD/2.
When driving a 16-Ω load with 45-mW output power from 3.3 V, THD+N is 0.04% at 1 kHz, and less than 0.2%
across the audio band of 20 Hz to 20 kHz. For 28 mW into 32-Ω loads, the THD+N is reduced to less than 0.03%
at 1 kHz, and is less than 0.2% across the audio band of 20 Hz to 20 kHz.
TYPICAL APPLICATION CIRCUIT
VDD
RF
Audio
Input
6
VDD
CS
VDD/4
RI
8
IN 1−
1
BYPASS
4
IN 2−
R
CI
VO1
−
+
7
CC
CB
Audio
Input
RI
R
CI
VO2
−
+
5
CC
From Shutdown
Control Circuit
3
SHUTDOWN
Bias
Control
2
RF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
TPA6100A2D
www.ti.com
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
SMALL OUTLINE (D)
MSOP(DGK)
MSOP
SYMBOLIZATION
TPA6100A2D
TPA6100A2DGK
AJL
–40°C to 85°C
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
BYPASS
1
I
Tap to voltage divider for internal mid-supply bias supply. BYPASS is set at VDD/4. Connect to a 0.1-µF
to 1-µF low-ESR capacitor for best performance.
GND
2
I
GND is the ground connection.
IN1-
8
I
IN1- is the inverting input for channel 1.
IN2-
4
I
IN2- is the inverting input for channel 2.
SHUTDOWN
3
I
Active-low input. When held low, the device is placed in a low supply current mode.
VDD
6
I
VDD is the supply voltage terminal.
VO1
7
O
VO1 is the audio output for channel 1.
VO2
5
O
VO2 is the audio output for channel 2.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Supply voltage
VI
Input voltage
4V
–0.3 V to VDD + 0.3 V
Continuous total power dissipation
Internally limited
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond thoselisted under "absolute maximum ratings” may cause permanent damage to thedevice. These are stress ratings
only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating
conditions” is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
710 mW
5.68 mW/°C
454 mW
369 mW
DGK
469 mW
3.75 mW/°C
300 mW
244 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
VDD Supply voltage
1.6
3.6
V
TA
Operating free-air temperature
–40
85
°C
VIH
High-level input voltage
SHUTDOWN
VIL
Low-level input voltage
SHUTDOWN
2
0.6 x VDD
0.25 x VDD
UNIT
V
TPA6100A2D
www.ti.com
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
DC ELECTRICAL CHARACTERISTICS
at TA = 25°C, VDD = 3.6 V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOO
Output offset voltage
AV = 2 V/V
PSRR
Power supply rejection ratio
VDD = 3.0 V to 3.6 V
IDD
Supply current
SHUTDOWN = 3.6 V
IDD(SD)
Supply current in SHUTDOWN mode
SHUTDOWN = 0 V
|IIH|
High-level input current (SHUTDOWN)
VDD = 3.6 V,
|IIL|
Low-level input current (SHUTDOWN)
VDD = 3.6 V,
ZI
Input impedance (IN1-, IN2-)
MIN
TYP MAX
5
UNIT
40
mV
0.75
2.0
mA
50
250
nA
VI = VDD
1
µA
VI = 0 V
1
72
dB
>1
µA
MΩ
AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 16 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PO
Output power (each channel)
THD ≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 45 mW, 20 Hz–20 kHz
0.2%
BOM
Maximum output power BW
G = 1, THD < 0.5%
> 20
kHz
kSVR
Supply ripple rejection
f = 1 kHz
52
dB
SNR
Signal-to-noise ratio
PO = 50 mW
90
dB
Vn
Noise output voltage (no noise-weighting filter)
28
µV(rms)
50
mW
AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 32 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PO
Output power (each channel)
THD ≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 30 mW, 20 Hz–20 kHz
0.2%
BOM
Maximum output power BW
G = 1, THD < 0.2%
> 20
kHz
kSVR
Supply ripple rejection
f = 1 kHz
52
dB
SNR
Signal-to-noise ratio
PO = 35 mW
91
dB
Vn
Noise output voltage (no noise-weighting filter)
28
µV(rms)
35
mW
3
TPA6100A2D
www.ti.com
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
DC ELECTRICAL CHARACTERISTICS
at TA = 25°C, VDD = 1.6 V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5
40
mV
VOO
Output offset voltage
AV = 2 V/V
PSRR
Power supply rejection ratio
VDD = 1.5 V to 1.7 V
80
IDD
Supply current
SHUTDOWN = 1.6 V
1.2
1.5
mA
IDD(SD)
Supply current in SHUTDOWN mode
SHUTDOWN = 0 V
50
250
nA
|IIH|
High-level input current (SHUTDOWN)
VDD = 1.6 V,
VI= VDD
1
µA
|IIL|
Low-level input current (SHUTDOWN)
VDD = 1.6 V,
VI= 0 V
1
ZI
Input impedance (IN1-, IN2-)
dB
>1
µA
MΩ
AC OPERATING CHARACTERISTICS
VDD = 1.6 V, TA = 25°C, RL = 16 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
9.5
UNIT
PO
Output power (each channel)
THD≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 9.5 mW, 20 Hz–20 kHz
0.4%
mW
BOM
Maximum output power BW
G = 0 dB, THD < 0.4%
> 20
kHz
kSVR
Supply ripple rejection
f = 1 kHz
53
dB
SNR
Signal-to-noise ratio
PO = 9.5 mW
86
dB
Vn
Noise output voltage (no noise-weighting filter)
18
µV(rms)
AC OPERATING CHARACTERISTICS
VDD = 1.6 V, TA = 25°C, RL = 32 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
PO
Output power (each channel)
THD≤ 0.1%, f = 1 kHz
THD+N
Total harmonic distortion + noise
PO = 6.5 mW, 20 Hz–20 kHz
0.3%
BOM
Maximum output power BW
G = 0 dB, THD < 0.3%
> 20
kHz
kSVR
Supply ripple rejection
f = 1 kHz
53
dB
SNR
Signal-to-noise ratio
PO = 7.1 mW
88
dB
Vn
Noise output voltage (no noise-weighting filter)
18
µV(rms)
4
7.1
MAX
mW
TPA6100A2D
www.ti.com
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION
GAIN SETTING RESISTORS, RF, RI,and R
The voltage gain for the TPA6100A2D is set by resistors RF and RI according to Equation 1.
Gain RF
RI
or Gain (dB) 20 log
RF
RI
(1)
Given that the TPA6100A2D is an MOS amplifier, the input impedance is high. Consequently, input leakage
currents are not generally a concern, although noise in the circuit increases as the value of RF increases. In
addition, a certain range of RF values is required for proper start-up operation of the amplifier. Taken together, it
is recommended that the effective impedance seen by the inverting node of the amplifier be set between 5 kΩ
and 20 kΩ. The effective impedance is calculated in Equation 2.
R FR I
Effective Impedance RF RI
(2)
As an example, consider an input resistance of 20 kΩ and a feedback resistor of 20 kΩ. The gain of the amplifier
would be –1 and the effective impedance at the inverting terminal would be 10 kΩ, which is within the
recommended range.
For high-performance applications, metal film resistors are recommended because they tend to have lower noise
levels than carbon resistors. For values of RF above 50 kΩ, the amplifier tends to become unstable due to a pole
formed from RF and the inherent input capacitance of the MOS input structure. For this reason, a small
compensation capacitor of approximately 5 pF should be placed in parallel with RF. In effect, this creates a
low-pass filter network with the cutoff frequency defined in Equation 3.
1
fc 2 R F CF
(3)
For example, if RF is 100 kΩ and CF is 5 pF, then fc is 318 kHz, which is well outside the audio range.
For maximum signal swing and output power at low supply voltages like 1.6 V to 3.3 V, BYPASS is biased to
VDD/4. However, to allow the output to be biased at VDD/2, a resistor, R, equal to RF must be placed from the
negative input to ground.
INPUT CAPACITOR, CI
In the typical application, an input capacitor, CI, is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency
determined in Equation 4.
1
fc 2 R I CI
(4)
The value of CI is important to consider, as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where RI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz.
Equation 4 is reconfigured as Equation 5.
1
CI 2 R I f c
(5)
In this example, CI is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier
that reduces useful headroom, especially in high-gain applications (>10). For this reason a low-leakage tantalum
or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications, as the dc level there is held at VDD/4, which is likely higher
than the source dc level. It is important to confirm the capacitor polarity in the application.
5
TPA6100A2D
www.ti.com
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
POWER SUPPLY DECOUPLING, CS
The TPA6100A2D is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the power
amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, CB
The midrail bypass capacitor (CB) serves several important functions. During start-up, CB determines the rate at
which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it can
not be heard). The second function is to reduce noise produced by the power supply caused by coupling into the
output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is fed
from a 55-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in
Equation 6 should be maintained.
1
1
C B 55 kΩ C I R I
(6)
As an example, consider a circuit where CB is 1 µF, CI is 1 µF, and RI is 20 kΩ. Inserting these values into
Equation 6 results in: 18.18 ≤ 50 which satisfies the rule. Bypass capacitor (CB) values of 0.47-µF to 1-µF
ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.
OUTPUT COUPLING CAPACITOR, CC
In the typical single-supply, single-ended (SE) configuration, an output coupling capacitor (CC) is required to
block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling
capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by
Equation 7.
1
fc 2 R L CC
(7)
The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the
low-frequency corner higher. Large values of CC are required to pass low frequencies into the load. Consider the
example where a CC of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 1 summarizes the frequency
response characteristics of each configuration.
Table 1. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
RL
CC
LOWEST FREQUENCY
32 Ω
68 µF
73 Hz
10,000 Ω
68 µF
0.23 Hz
47,000 Ω
68 µF
0.05 Hz
As Table 1 indicates, headphone response is adequate and drive into line level inputs (a home stereo for
example) is good.
The output coupling capacitor required in single-supply, SE mode also places additional constraints on the
selection of other components in the amplifier circuit. With the rules described earlier still valid, add the following
relationship:
6
TPA6100A2D
www.ti.com
1
C B 55 kΩ
SLOS269B – JUNE 2000 – REVISED SEPTEMBER 2004
1
C I R I
1
R LC C
(8)
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application. A real capacitor can be modeled simply as a
resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves
like an ideal capacitor.
3.3-V VERSUS 1.6-V OPERATION
The TPA6100A2D was designed for operation over a supply range of 1.6 V to 3.6 V. There are no special
considerations for 1.6-V versus 3.3-V operation as far as supply bypassing, gain setting, or stability. The most
important consideration is that of output power. Each amplifier can produce a maxium output voltage swing within
a few hundred millivolts of the rails with a 10-kΩ load. However, this voltage swing decreases as the load
resistance decreases and the rDS(on) as the output stage transistors becomes more significant. For example, for a
32-Ω load, the maximum peak output voltage with VDD = 1.6 V is approximately 0.7 V with no clipping distortion.
This reduced voltage swing effectively reduces the maximum undistorted output power.
7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA6100A2D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
6100A2
TPA6100A2DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJL
TPA6100A2DGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJL
TPA6100A2DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJL
TPA6100A2DGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJL
TPA6100A2DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
6100A2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPA6100A2DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPA6100A2DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA6100A2DGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
TPA6100A2DR
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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