Texas Instruments | TPA102: 150-mW Stereo Audio Power Amplifier (Rev. D) | Datasheet | Texas Instruments TPA102: 150-mW Stereo Audio Power Amplifier (Rev. D) Datasheet

Texas Instruments TPA102: 150-mW Stereo Audio Power Amplifier (Rev. D) Datasheet
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
150-mW STEREO AUDIO POWER AMPLIFIER
FEATURES
•
•
•
•
•
•
•
DGN PACKAGE
(TOP VIEW)
150 mW Stereo Output
PC Power Supply Compatible
– Fully Specified for 3.3 V and 5 V Operation
– Operation to 2.5 V
Pop Reduction Circuitry
Internal Mid-Rail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
– PowerPAD™ MSOP
Pin Compatible With LM4881
BYPASS
GND
SHUTDOWN
IN2–
1
8
2
7
3
6
4
5
IN1–
VO1
VDD
VO2
DESCRIPTION
The TPA102 is a stereo audio power amplifier packaged in an 8-pin PowerPAD™ MSOP package capable of
delivering 150 mW of continuous RMS power per channel into 8-Ω loads. Amplifier gain is externally configured
by means of two resistors per input channel and does not require external compensation for settings of 1 to 10.
THD+N when driving an 8-Ω load from 5 V is 0.1% at 1 kHz, and less than 2% across the audio band of 20 Hz to
20 kHz. For 32-Ω loads, the THD+N is reduced to less than 0.06% at 1 kHz, and is less than 1% across the
audio band of 20 Hz to 20 kHz. For 10-kΩ loads, the THD+N performance is 0.01% at 1 kHz, and less than
0.02% across the audio band of 20 Hz to 20 kHz.
TYPICAL APPLICATION CIRCUIT
325 kΩ
325 kΩ
VDD 6
VDD
RF
CS
VDD/2
Audio
Input
RI
8
IN1–
1
BYPASS
4
IN2–
CI
–
+
VO1 7
–
+
VO2 5
CC
CB
Audio
Input
RI
CI
From Shutdown
Control Circuit
3
SHUTDOWN
CC
Bias
Control
2
RF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2004, Texas Instruments Incorporated
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
TA
-40°C to 85°C
(1)
PACKAGED DEVICE
MSOP (1)
MSOP Symbolization
TPA102DGN
TI AAC
The DGN package is available inleft-ended tape and reel only (e.g., TPA102DGNR).
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BYPASS
1
I
Tap to voltage divider for internal mid-supply bias supply. Connect to a 0.1 µF to 1 µF low ESR capacitor
for best performance.
GND
2
I
GND is the ground connection.
IN1–
8
I
IN1- is the inverting input for channel 1.
IN2–
4
I
IN2- is the inverting input for channel 2.
SHUTDOWN
3
I
Puts the device in a low quiescent current mode when held high.
VDD
6
I
VDD is the supply voltage terminal.
VO1
7
O
VO1 is the audio output for channel 1.
VO2
5
O
VO2 is the audio output for channel 2.
Thermal Pad
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Supply voltage
VI
Input voltage
6V
–0.3 V to VDD + 0.3 V
Continuous total power dissipation
Internally limited
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond thoselisted under "absolute maximum ratings” may cause permanent damage to thedevice. These are stress ratings
only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating
conditions” is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability.
DISSIPATION RATING TABLE
(1)
2
PACKAGE
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGN
2.14 W (1)
17.1 mW/°C
1.37 W
1.11 W
See the Texas Instrumentsdocument, PowerPAD Thermally EnhancedPackage Application Report (SLMA002), for more information on
thePowerPAD package. The thermal data was measured on a PCB layout based on theinformation in the section entitled
TexasInstruments Recommended Board for PowerPAD on page 33 of the beforementioned document.
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
VDD
Supply voltage
2.5
5.5
V
TA
Operating free-air temperature
-40
85
°C
VIH
High-level input voltage (SHUTDOWN)
VIL
Low-level input voltage (SHUTDOWN)
0.80 × VDD
UNIT
V
0.25 × VDD
V
TYP MAX
UNIT
DC ELECTRICAL CHARACTERISTICS
at TA = 25°C, VDD = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOO
Output offset voltage (measured between output and BYPASS terminal)
Av = 2 V/V
PSRR
Power supply rejection ratio
VDD = 3.2 V to 3.4 V
83
10
mV
IDD
Supply current
SHUTDOWN = 0 V
1.5
3
mA
IDD(SD)
Supply current in SHUTDOWN mode
SHUTDOWN = VDD
ZI
Input impedance
10
50
dB
>1
µA
MΩ
AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 8Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
70 (1)
UNIT
PO
Output power (each channel)
THD≤ 0.1%
THD+N
Total harmonic distortion + noise
PO = 70 mW, 20–20 kHz
2%
BOM
Maximum output power BW
G = 10, THD <5%
>20
Phase margin
Open loop
58°
Supply ripple rejection ratio
f = 1 kHz
68
dB
Channel/channel output separation
f = 1 kHz
86
dB
SNR
Signal-to-noise ratio
PO = 100 mW
100
dB
Vn
Noise output voltage
9.5
µV(rms)
(1)
mW
kHz
Measured at 1kHz
DC ELECTRICAL CHARACTERISTICS
at TA = 25°C, VDD = 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VOO
Output offset voltage
Av = 2 V/V
PSRR
Power supply rejection ratio
VDD = 4.9 V to 5.1 V
76
IDD
Supply current
SHUTDOWN = 0 V
IDD(SD)
Supply current in SHUTDOWN mode
SHUTDOWN = VDD
|IIH|
High-level input current (SHUTDOWN)
VDD = 5.5 V, VI = VDD
|IIL|
Low-level input current (SHUTDOWN)
VDD = 5.5 V, VI = 0 V
ZI
Input impedance
MAX
UNIT
10
mV
1.5
3
mA
60
100
µA
1
µA
dB
1
>1
µA
MΩ
3
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
AC OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 8Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
70 (1)
UNIT
PO
Output power (each channel)
THD≤ 0.1%
THD+N
Total harmonic distortion + noise
PO = 150 mW, 20–20 kHz
2%
BOM
Maximum output power BW
G = 10, THD <5%
>20
Phase margin
Open loop
56°
Supply ripple rejection ratio
f = 1 kHz
68
dB
Channel/Channel output separation
f = 1 kHz
86
dB
SNR
Signal-to-noise ratio
PO = 150 mW
100
dB
Vn
Noise output voltage
9.5
µV(rms)
(1)
mW
kHz
Measured at 1kHz
AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 32Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PO
Output power (each channel)
THD ≤ 0.1%
40 (1)
THD+N
Total harmonic distortion + noise
PO = 30 mW, 20–20 kHz
0.5%
BOM
Maximum output power BW
AV = 10, THD <2%
>20
Phase margin
Open loop
58°
Supply ripple rejection ratio
f = 1 kHz
68
dB
97
dB
Channel/channel output separation
f = 1 kHz
SNR
Signal-to-noise ratio
PO = 100 mW
Vn
Noise output voltage
(1)
mW
kHz
100
dB
9.5
µV(rms)
Measured at 1kHz
AC OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 32Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
mW
PO
Output power (each channel)
THD≤ 0.1%
40 (1)
THD+N
Total harmonic distortion + noise
PO = 60 mW, 20–20 kHz
0.4%
BOM
Maximum output power BW
AV = 10, THD <2%
>20
Phase margin
Open loop
56°
Supply ripple rejection ratio
f = 1 kHz
68
dB
Channel/channel output separation
f = 1 kHz
97
dB
SNR
Signal-to-noise ratio
PO = 150 mW
100
dB
Vn
Noise output voltage
9.5
µV(rms)
(1)
4
Measured at 1kHz
kHz
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
THD+N
Vn
Total harmonic distortion plus noise
vs Frequency
1, 2, 4, 5, 7, 8, 10, 11, 13, 14, 16, 17, 34, 36
vs Power output
3, 6, 9, 12, 15, 18
Power supply rejection ratio
vs Frequency
19, 20
Output noise voltage
vs Frequency
21, 22
Crosstalk
vs Frequency
23-26, 37, 38
Mute attenuation
vs Frequency
27, 28
vs Frequency
29, 30
Open-loop gain
Phase margin
Output power
vs Load resistance
31, 32
IDD
Supply current
vs Supply voltage
33
SNR
Signal-to-noise ratio
vs Voltage gain
35
vs Frequency
39-44
vs Output power
45, 46
Closed-loop gain
Phase
Power dissipation
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
1
VDD = 3.3 V
PO = 30 mW
CB = 1 µ F
RL = 32 Ω
AV = −5 V/V
AV =− 10 V/V
0.1
AV = −1 V/V
0.01
0.001
20
100
1k
f − Frequency − Hz
Figure 1.
10k 20k
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
1
0.1
VDD = 3.3 V
AV = −1 V/V
RL = 32 Ω
CB = 1 µ F
PO = 15 mW
PO = 10 mW
0.01
PO = 30 mW
0.001
20
100
1k
10k 20k
f − Frequency − Hz
Figure 2.
5
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VDD = 3.3 V
RL = 32 Ω
AV = −1 V/V
CB = 1 µF
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
20 kHz
10 kHz
1
0.1
1 kHz
20 Hz
10
AV = −10 V/V
AV = −5 V/V
0.1
0.01
AV = −1 V/V
0.001
20
0.01
1
1
VDD = 5 V
PO = 60 mW
RL = 32 Ω
CB = 1 µF
50
100
PO − Output Power − mW
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
VDD = 5 V
RL = 32 Ω
AV = −1 V/V
CB = 1 µF
1
PO = 30 mW
PO = 15 mW
0.01
PO = 60 mW
0.001
20
100
1k
f − Frequency − Hz
Figure 5.
6
10k 20k
Figure 3.
10
0.1
1k
f − Frequency − Hz
10k 20k
VDD = 5 V
AV = −1 V/V
RL = 32 Ω
CB = 1 µF
20 kHz
1
10 kHz
0.1
1 kHz
20 Hz
0.01
0.002
0.01
PO − Output Power − W
Figure 6.
0.1
0.2
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VDD = 3.3 V
RL = 10 kΩ
PO = 100 µF
CB = 1 µF
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
1
AV = −5 V/V
0.1
0.01
AV = −2 V/V
0.001
20
100
1k
VDD = 3.3 V
RL = 10 kΩ
AV = −1 V/V
CB = 1 µF
1
0.1
PO = 45 µW
0.01
0.001
20
10k 20k
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
10
VDD = 3.3 V
RL = 10 kΩ
AV = −1 V/V
CB = 1 µF
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
PO = 90 µW
PO = 130 µW
1
0.1
20 Hz
10 kHz
0.01
20 Hz
1 kHz
0.001
5
10
100
PO − Output Power − µW
Figure 9.
200
1
VDD = 5 V
RL = 10 kΩ
PO = 300 µW
CB = 1 µF
0.1
AV = −5 V/V
AV = −1 V/V
0.01
AV = −2 V/V
0.001
20
100
1k
10k 20k
f − Frequency − Hz
Figure 10.
7
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
1
10
VDD = 5 V
RL = 10 kΩ
AV = −1 V/V
CB = 1 µF
PO = 300 µW
0.1
PO = 200 µW
0.01
PO = 100 µW
0.001
20
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
VDD = 5 V
RL = 10 kΩ
AV = −1 V/V
CB = 1 µ F
1
0.1
20 Hz
20 kHz
0.01
10 kHz 1 kHz
0.001
100
1k
10k 20k
5
500
Figure 12.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VDD = 3.3 V
PO = 75 mW
RL = 8 Ω
CB = 1 µF
1
AV = −5 V/V
AV = −2 V/V
0.1
AV = −1 V/V
0.01
0.001
100
1k
f − Frequency − Hz
Figure 13.
10k 20k
THD+N −Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
100
Figure 11.
2
20
8
10
PO − Output Power − µW
f − Frequency − Hz
VDD = 3.3 V
RL = 8 Ω
AV = −1 V/V
PO = 30 mW
1
PO = 15 mW
0.1
0.01
PO = 75 mW
0.001
20
100
1k
f − Frequency − Hz
Figure 14.
10k 20k
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VDD = 3.3 V
RL = 8 Ω
AV = −1 V/V
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
20 kHz
10 kHz
1
1 kHz
0.1
20 Hz
0.01
10m
0.1
2
VDD = 5 V
PO = 100 mW
RL = 8 Ω
CB = 1 µF
1
AV = −1 V/V
0.01
0.001
100
Figure 16.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
POWER OUTPUT
10
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10k 20k
Figure 15.
10
VDD = 5 V
RL = 8 Ω
AV = −1 V/V
PO = 30 mW
1
PO = 60 mW
0.01
PO = 10 mW
0.001
20
1k
f − Frequency − Hz
PO − Output Power − W
0.1
AV = −5 V/V
0.1
20
0.3
AV = −2 V/V
100
1k
f − Frequency − Hz
Figure 17.
10k 20k
VDD = 5 V
RL = 8 Ω
AV = −1 V/V
20 kHz
1
10 kHz
1 kHz
0.1
20 Hz
0.01
10m
0.1
1
PO − Output Power − W
Figure 18.
9
TPA102
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
0
VDD = 3.3 V
RL = 8 Ω to 10 kΩ
−20
CB = 0.1 µF
−30
CB = 1 µF
−40
−50
−60
CB = 2 µF
−70
Bypass = 1.65 V
−20
−50
CB = 2 µF
−60
−70
−90
−90
1k
CB = 1 µF
−40
−80
100
CB = 0.1 µF
−30
−80
−100
20
VDD = 5 V
RL = 8 Ω to 10 kΩ
−10
Supply Ripple Rejection − dB
Supply Ripple Rejection − dB
−10
Bypass = 2.5 V
−100
20
10k 20k
100
f − Frequency − Hz
Figure 19.
Figure 20.
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
Vn − Output Noise Voltage − µV(rms)
Vn − Output Noise Voltage − µV(rms)
10
VDD = 3.3 V
BW = 10 Hz to 22 kHz
AV = −1 V/V
RL = 8 Ω to 10 kΩ
100
1k
f − Frequency − Hz
Figure 21.
10
10k 20k
20
20
1
20
1k
f − Frequency − Hz
10k 20k
10
VDD = 5 V
BW = 10 Hz to 22 kHz
RL = 8 Ω to 10 kΩ
AV = −1 V/V
1
20
100
1k
f − Frequency − Hz
Figure 22.
10k 20k
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
−50
−60
−70
Crosstalk − dB
−75
−60
−65
−80
IN 2 TO OUT 1
−85
−90
−95
−70
−75
IN 2 TO OUT 1
−80
−85
−100
IN 1 TO OUT 2
−90
IN 1 TO OUT 2
−105
−110
20
PO = 100 mW
VDD = 3.3 V
RL = 8 Ω
CB = 1 µF
AV = −1 V/V
−55
Crosstalk − dB
−65
PO = 25 mW
VDD = 3.3 V
RL = 32 Ω
CB = 1 µF
AV = −1 V/V
−95
−100
100
1k
10k 20k
20
100
f − Frequency − Hz
Figure 23.
Figure 24.
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
−60
10k 20k
−50
VDD = 5 V
PO = 25 mW
CB = 1 µF
RL = 32 Ω
AV = −1 V/V
−65
−75
−80
−85
−55
−60
−65
Crosstalk − dB
−65
Crosstalk − dB
1k
f − Frequency − Hz
IN 2 TO OUT 1
−90
−95
VDD = 5 V
PO = 100 mW
CB = 1 µF
RL = 8 Ω
AV = −1 V/V
−70
IN 2 TO OUT 1
−75
−80
−85
−100
−90
IN 1 TO OUT 2
IN 1 TO OUT 2
−105
−110
20
−95
100
1k
f − Frequency − Hz
Figure 25.
10k 20k
−100
20
100
1k
10k 20k
f − Frequency − Hz
Figure 26.
11
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
MUTE ATTENUATION
vs
FREQUENCY
MUTE ATTENUATION
vs
FREQUENCY
0
−20
−30
−40
−50
−60
−70
−30
−40
−50
−60
−70
−80
−80
−90
−90
−100
20
100
1k
VDD = 5 V
CB = 1 µF
RL = 32 Ω
−100
20
10k 20k
100
f − Frequency − Hz
1k
Figure 27.
Figure 28.
OPEN-LOOP GAIN AND PHASE MARGIN
vs
FREQUENCY
OPEN-LOOP GAIN AND PHASE MARGIN
vs
FREQUENCY
150°
100
100
150°
VDD = 3.3 V
No Load
40
90°
60°
Gain
20
30°
0
Open-Loop Gain − dB
Phase
60
120°
80
φ m − Phase Margin
Open-Loop Gain − dB
VDD = 5 V
No Load
120°
80
−20
Phase
60
40
90°
60°
Gain
20
30°
0
0°
0°
10
100
1k
10k
f − Frequency − Hz
100k
−30°
10M
−20
100
1k
10k
100k
f − Frequency − Hz
Figure 29.
12
10k 20k
f − Frequency − Hz
φ m − Phase Margin
Mute Attenuation − dB
−20
−10
Mute Attenuation − dB
−10
0
VDD = 3.3 V
RL = 32 Ω
CB = 1 µF
Figure 30.
1M
−30°
10M
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SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
300
120
THD+N = 1 %
VDD = 3.3 V
AV = −1 V/V
250
PO − Output Power − mW
PO − Output Power − mW
100
THD+N = 1 %
VDD = 5 V
AV = −1 V/V
80
60
40
200
150
100
50
20
0
0
8
16
24
32
40
48
56
8
64
RL − Load Resistance − Ω
40
48
64
56
Figure 32.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion Plus Noise − %
I DD − Supply Current − mA
32
Figure 31.
1.2
1
0.8
0.6
0.4
0.2
0
3
24
RL − Load Resistance − Ω
1.4
2.5
16
3.5
4
4.5
VDD − Supply Voltage − V
Figure 33.
5
5.5
1
VI = 1 V
AV = −1 V/V
RL = 10 kΩ
CB = 1 µF
0.1
0.01
0.001
20
100
1k
10k 20k
f − Frequency − Hz
Figure 34.
13
TPA102
www.ti.com
SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
SIGNAL-TO-NOISE RATIO
vs
VOLTAGE GAIN
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion Plus Noise − %
104
SNR − Signal−to-Noise Ratio − dB
VI = 1 V
102
100
98
96
94
92
1
2
3
4
5
6
7
8
9
1
VDD = 5 V
AV = −1 V/V
RL = 10 kΩ
CB = 1 µF
0.1
0.01
0.001
20
10
100
Figure 35.
Figure 36.
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
−60
VDD = 5 V
VO = 1 V
RL = 10 kΩ
CB = 1 µF
−70
VDD = 3.3 V
VO = 1 V
RL = 10 kΩ
CB = 1 µF
−80
−80
−90
Crosstalk − dB
Crosstalk − dB
10k 20k
−60
−70
−100
IN2 to OUT1
−110
−120
−90
−100
IN2 to OUT1
−110
−120
−130
−130
IN1 to OUT2
−140
IN1 to OUT2
−140
−150
−150
20
100
1k
f − Frequency − Hz
Figure 37.
14
1k
f − Frequency − Hz
AV − Voltage Gain − V/V
10k 20k
20
100
1k
f − Frequency − Hz
Figure 38.
10k 20k
TPA102
www.ti.com
SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
200°
200°
180°
180°
Phase
160°
140°
Phase
160°
140°
120°
20
10
80°
Gain
0
−10
10
100
1k
10k
100k
1M
30
100°
80°
20
10
Gain
0
−10
10
100
f − Frequency − Hz
1k
10k
100k
Figure 39.
Figure 40.
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
200°
200°
180°
Phase
180°
Phase
160°
Phase
160°
140°
140°
80°
60°
0
−20
10
100
1k
10k
f − Frequency − Hz
Figure 41.
VDD = 3.3 V
RI = 20 kΩ
RF = 20 kΩ
RL = 10 kΩ
CI = 1 µF
AV = −1 V/V
100°
Gain
20
120°
100k
1M
Closed-Loop Gain − dB
Closed-Loop Gain − dB
120°
VDD = 3.3 V
RI = 20 kΩ
RF = 20 kΩ
RL = 8 Ω
CI = 1 µF
AV = −1 V/V
40
1M
f − Frequency − Hz
Phase
30
VDD = 5 V
RI = 20 kΩ
RF = 20 kΩ
RL = 32 Ω
CI = 1 µF
AV = −1 V/V
100°
Closed-Loop Gain − dB
Closed-Loop Gain − d B
120°
VDD = 3.3 V
RI = 20 kΩ
RF = 20 kΩ
RL = 32 Ω
CI = 1 µF
AV = −1 V/V
Phase
Phase
30
20
10
100°
80°
Gain
0
−10
10
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 42.
15
TPA102
www.ti.com
SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
200°
200°
160°
VDD = 5 V
RI = 20 kΩ
RF = 20 kΩ
RL = 8 Ω
CI = 1 µF
AV = −1 V/V
120°
Closed-Loop Gain − dB
60°
40°
Gain
20
0
−20
10
100
1k
10k
100k
30
10
Gain
−10
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 43.
Figure 44.
POWER DISSIPATION/AMPLIFIER
vs
OUTPUT POWER
POWER DISSIPATION/AMPLIFIER
vs
OUTPUT POWER
80
180
VDD = 3.3 V
VDD = 5 V
8Ω
70
8Ω
160
140
Amplifier Power − mW
60
Amplifier Power − mW
80°
0
f − Frequency − Hz
50
40
16 Ω
30
32 Ω
20
120
100
16 Ω
80
60
32 Ω
40
64 Ω
10
64 Ω
20
0
0
0
20
40
60
80 100 120 140 160 180
Load Power − mW
Figure 45.
16
100°
20
10
1M
120°
VDD = 5 V
RI = 20 kΩ
RF = 20 kΩ
RL = 10 kΩ
CI = 1 µF
AV = −1 V/V
100°
80°
160°
140°
Phase
140°
Closed-Loop Gain − dB
180°
Phase
Phase
180°
Phase
200
0
20
40
60
80 100 120 140 160 180
Load Power − mW
Figure 46.
200
TPA102
www.ti.com
SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION
f c(highpass) GAIN SETTING RESISTORS, Rf and Ri
The gain for the TPA102 is set by resistors Rf and Ri
according to Equation 1.
Gain Rf
Ri
(1)
Given that the TPA102 is a MOS amplifier, the input
impedance is very high. Consequently input leakage
currents are not generally a concern. However, noise
in the circuit increases as the value of Rf increases.
In addition, a certain range of Rf values is required for
proper start-up operation of the amplifier. Considering
these factors, it is recommended that the effective
impedance seen by the inverting node of the amplifier
be set between 5 kΩ and 20 kΩ. The effective
impedance is calculated using Equation 2.
Effective Impedance R fR i
Rf Ri
(2)
For example, if the input resistance is 20 kΩ and the
feedback resistor is 20 kΩ, the gain of the amplifier is
-1, and the effective impedance at the inverting
terminal is 10 kΩ, a value within the recommended
range.
For high performance applications, metal-film resistors are recommended because they tend to have
lower noise levels than carbon resistors. For values
of Rf above 50 kΩ, the amplifier tends to become
unstable due to a pole formed from Rf and the
inherent input capacitance of the MOS input structure. For this reason, a small compensation capacitor
of approximately 5 pF should be placed in parallel
with Rf. This, in effect, creates a low-pass filter
network with the cutoff frequency defined by
Equation 3.
f c(lowpass) 1
2 R f CF
(3)
For example, if Rf is 100 kΩ and CF is 5 pF then
fc(lowpass) is 318 kHz, which is well outside the audio
range.
1
2 R i Ci
(4)
The value of Ci directly affects the bass (low frequency) performance of the circuit. Consider the
example where Ri is 20 kΩ and the specification calls
for a flat bass response down to 20 Hz. Equation 4 is
reconfigured as Equation 5.
Ci 1
2 R i f c(highpass)
(5)
In this example, Ci is 0.40 µF, so one would likely
choose a value in the range of 0.47 µF to 1 µF. A
further consideration for this capacitor is the leakage
path from the input source through the input network
formed by Ri, Ci, and the feedback resistor (Rf) to the
load. This leakage current creates a dc offset voltage
at the input to the amplifier that reduces useful
headroom, especially in high-gain applications (gain
>10). For this reason a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized
capacitors are used, connect the positive side of the
capacitor to the amplifier input in most applications.
The dc level there is held at VDD/2—likely higher than
the source dc level. It is important to confirm the
capacitor polarity in the application.
POWER SUPPLY DECOUPLING, C(S)
The TPA102 is a high-performance CMOS audio
amplifier that requires adequate power-supply decoupling to minimize the output total harmonic distortion (THD). Power-supply decoupling also prevents
oscillations when long lead lengths are used between
the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different
types that target different types of noise on the power
supply leads. For higher frequency transients, spikes,
or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, placed as close as possible to the
device VDD lead, works best. For filtering
lower-frequency noise signals, a larger aluminum
electrolytic capacitor of 10 µF or greater placed near
the power amplifier is recommended.
INPUT CAPACITOR, Ci
In the typical application, an input capacitor, Ci, is
required to allow the amplifier to bias the input signal
to the proper dc level for optimum operation. In this
case, Ci and Ri form a high-pass filter with the corner
frequency determined in Equation 4.
17
TPA102
www.ti.com
SLOS213D – AUGUST 1998 – REVISED SEPTEMBER 2004
MIDRAIL BYPASS CAPACITOR, C(B)
The midrail bypass capacitor, C(B), serves several
important functions. During start up, C(B) determines
the rate at which the amplifier starts up. This helps to
push the start-up pop noise into the subaudible range
(so low it can not be heard). The second function is to
reduce noise produced by the power supply caused
by coupling into the output drive signal. This noise is
from the midrail generation circuit internal to the
amplifier. The capacitor is fed from a 230-kΩ source
inside the amplifier. To keep the start-up pop as low
as possible, maintain the relationship shown in
Equation 6.
1
C(B) 230 kΩ
1
C i R i
(6)
Consider an example circuit where C(B) is 1 µF, Ci is
1 µF, and Ri is 20 kΩ. Subsitituting these values into
the equation 9 results in: 6.25 ≤ 50 which satisfies the
rule. Bypass capacitor, C(B), values of 0.1 µF to 1 µF
ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.
OUTPUT COUPLING CAPACITOR, C(C)
In a typical single-supply, single-ended (SE) configuration, an output coupling capacitor (C(C)) is required
to block the dc bias at the output of the amplifier, thus
preventing dc currents in the load. As with the input
coupling capacitor, the output coupling capacitor and
impedance of the load form a high-pass filter
governed by Equation 7.
fc 1
2 R L C(C)
(7)
The main disadvantage, from a performance standpoint, is that the typically-small load impedance drives
the low-frequency corner higher. Large values of C(C)
are required to pass low frequencies into the load.
Consider the example where a C(C) of 68 µF is
chosen and loads vary from 32 Ω to 47 kΩ. Table 1
summarizes the frequency response characteristics
of each configuration.
18
Table 1. Common Load Impedances vs LowFrequency Output Characteristics in SE Mode
RL
C(C)
LOWEST FREQUENCY
32 Ω
68 µF
73 Hz
10,000 Ω
68 µF
0.23 Hz
47,000 Ω
68 µF
0.05 Hz
As Table 1 indicates, headphone response is adequate, and drive into line level inputs (a home stereo
for example) is very good.
The output coupling capacitor required in
single-supply SE mode also places additional constraints on the selection of other components in the
amplifier circuit. With the rules described earlier still
valid, add the following relationship:
1
C(B) 230 kΩ
1
C i R i
1
RLC (C)
(8)
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout
this application. A real capacitor can be modeled
simply as a resistor in series with an ideal capacitor.
The voltage drop across this resistor minimizes the
beneficial effects of the capacitor in the circuit. The
lower the equivalent value of this resistance, the
more the real capacitor behaves like an ideal capacitor.
5-V VERSUS 3.3-V OPERATION
The TPA102 was designed for operation over a
supply range of 2.5 V to 5.5 V. This data sheet
provides full specifications for 5-V and 3.3-V operation, since these are considered to be the two most
common supply voltages. There are no special considerations for 3.3-V versus 5-V operation as far as
supply bypassing, gain setting, or stability. The most
important consideration is that of output power. Each
amplifier in theTPA102 can produce a maximum
voltage swing of VDD– 1 V. This means, for 3.3-V
operation, clipping starts to occur when VO(PP) = 2.3 V
as opposed when VO(PP) = 4 V while operating at 5 V.
The reduced voltage swing subsequently reduces
maximum output power into the load before distortion
becomes significant.
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA102DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AAC
TPA102DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AAC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA102DGNR
Package Package Pins
Type Drawing
SPQ
HVSSOP
2500
DGN
8
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA102DGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Copyright © 2019, Texas Instruments Incorporated
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