Texas Instruments | TPA741: 700-mW Mono Low-Voltage Audio Power Amplifier w/Differential Inputs (Rev. C) | Datasheet | Texas Instruments TPA741: 700-mW Mono Low-Voltage Audio Power Amplifier w/Differential Inputs (Rev. C) Datasheet

Texas Instruments TPA741: 700-mW Mono Low-Voltage Audio Power Amplifier w/Differential Inputs (Rev. C) Datasheet
TPA741
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
700-mW MONO LOW-VOLTAGE AUDIO POWER
AMPLIFIER WITH DIFFERENTIAL INPUTS
FEATURES
•
•
•
•
•
•
DESCRIPTION
Fully Specified for 3.3-V and 5-V Operation
Wide Power Supply Compatibility 2.5 V - 5.5 V
Output Power for RL = 8 Ω
– 700 mW at VDD = 5 V
– 250 mW at VDD = 3.3 V
Integrated Depop Circuitry
Thermal and Short-Circuit Protection
Surface-Mount Packaging
– SOIC
– PowerPAD™ MSOP
The TPA741 is a bridge-tied load (BTL) audio power
amplifier developed especially for low-voltage applications where internal speakers are required.
Operating with a 3.3-V supply, the TPA741 can
deliver 250-mW of continuous power into a BTL 8-Ω
load at less than 0.6% THD+N throughout voice band
frequencies. Although this device is characterized out
to 20 kHz, its operation is optimized for narrower
band applications such as wireless communications.
The BTL configuration eliminates the need for external coupling capacitors on the output in most applications, which is particularly important for small
battery-powered equipment. This device features a
shutdown mode for power-sensitive applications with
a supply current of 7 µA during shutdown. The
TPA741 is available in an 8-pin SOIC surface-mount
package and the surface-mount PowerPAD™ MSOP,
which reduces board space by 50% and height by
40%.
D OR DGN PACKAGE
(TOP VIEW)
SHUTDOWN
BYPASS
IN+
IN–
1
8
2
7
3
6
4
5
VO–
GND
VDD
VO+
VDD 6
VDD
RF
VDD/2
Audio
Input
RI
CI
4
IN–
3
IN+
2
BYPASS
CS
–
VO+ 5
+
CB
–
VO– 8
+
700 mW
7
GND
From System Control
1
SHUTDOWN
Bias
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
TPA741
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
–40°C to 85°C
(1)
(2)
MSOP (2)
(DGN)
MSOP SYMBOLIZATION
(D)
TPA741D
TPA741DGN
AJD
SMALL
OUTLINE (1)
In the D package, the maximum output power is thermally limited to 350 mW; 700-mW peaks can be driven, as long as the RMS value
is less than 350 mW.
The D and DGN packages are available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g.,
TPA741DR).
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
I
BYPASS is the tap to the voltage divider for internal mid-supply bias. This terminal should be connected
to a 0.1-µF to 2.2-µF capacitor when used as an audio amplifier.
BYPASS
2
GND
7
IN-
4
I
IN- is the inverting input. IN- is typically used as the audio input terminal.
IN+
3
I
IN+ is the noninverting input. IN+ is typically tied to the BYPASS terminal for SE operations.
SHUTDOWN
1
I
SHUTDOWN places the entire device in shutdown mode when held high.
VDD
6
VO+
5
O
VO+ is the positive BTL output.
VO-
8
O
VO- is the negative BTL output.
GND is the ground connection.
VDD is the supply voltage terminal.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Supply voltage
VI
Input voltage
6v
–0.3 V to VDD +0.3 V
Continuous total power dissipation
Internally limited (see Dissipation Rating Table)
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
(1)
2
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
D
725 mW
5.8 mW/°C
464 mW
377 mW
DGN
2.14 W (1)
17.1 mW/°C
1.37 W
1.11 W
See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(SLMA002), for more information on the PowerPAD package. The thermal data was measured on a
PCB layout based on the information in the section entitled Texas Instruments Recommended Board
for PowerPAD of that document.
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage,
VIH
High-level voltage (SHUTDOWN)
VIL
Low-level voltage (SHUTDOWN)
TA
Operating free-air temperature
MIN
MAX
2.5
5.5
UNIT
V
0.9VDD
V
0.1VDD
V
85
°C
MAX
UNIT
–40
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured differentially)
SHUTDOWN = 0 V, RL = 8 Ω, RF = 10 kΩ
PSRR
Power supply rejection ratio
VDD = 3.2 V to 3.4 V
IDD
Supply current
SHUTDOWN = 0 V, RF = 10 kΩ
IDD(SD)
Supply current, shutdown mode
(see Figure 6)
SHUTDOWN = VDD, RF = 10 kΩ
MIN
TYP
20
mV
1.35
2.5
mA
7
50
µA
85
dB
|IIH|
SHUTDOWN, VDD = 3.3 V, Vi = 3.3 V
1
µA
|IIL|
SHUTDOWN, VDD = 3.3 V, Vi = 0 V
1
µA
OPERATING CONDITIONS
VDD = 3.3 V, TA = 25°C, RL = 8 Ω
PARAMETER
See (1)
TEST CONDITIONS
MIN
TYP MAX
UNIT
250
mW
PO
Output power,
THD = 0.5%,
See Figure 9
THD + N
Total harmonic distortion plus noise
PO = 250 mW,
f = 200 Hz to 4 kHz, See Figure 7
BOM
Maximum output power bandwidth
AV = -2 V/V,
THD = 2%, See Figure 7
20
kHz
B1
Unity-gain bandwidth
Open loop,
See Figure 15
1.4
MHz
kSVR
Supply ripple rejection ratio
f = 1 kHz,
CB = 1 µF, See Figure 2
79
dB
Vn
Noise output voltage
AV = -1 V/V,
CB = 0.1 µF, See Figure 19
17
µV(rms)
(1)
0.55%
Output power is measured at the output terminals of the device at f = 1 kHz.
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
|VOS|
TEST CONDITIONS
MIN
TYP
Output offset voltage (measured differentially) SHUTDOWN = 0 V, RL = 8 Ω, RF = 10 kΩ
MAX
UNIT
20
mV
PSRR Power supply rejection ratio
VDD = 4.9 V to 5.1 V
IDD
Supply current
SHUTDOWN = 0 V, RF = 10 kΩ
1.45
78
2.5
mA
dB
IDD(SD)
Supply current, shutdown mode (see Figure 4)
SHUTDOWN = VDD, RF = 10 kΩ
50
100
µA
|IIH|
SHUTDOWN, VDD = 5.5 V, Vi = VDD
1
µA
|IIL|
SHUTDOWN, VDD = 5.5 V, Vi = 0 V
1
µA
3
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 8Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
700 (1)
Output power
THD = 0.5%,
THD + N
Total harmonic distortion plus noise
PO = 250 mW, f = 200 Hz to 4 kHz,
See Figure 11
BOM
Maximum output power bandwidth
AV = -2 V/V,
THD = 2%, See Figure 11
20
kHz
B1
Unity-gain bandwidth
Open loop,
See Figure 16
1.4
MHz
kSVR
Supply ripple rejection ratio
f = 1 kHz,
CB = 1 µF, See Figure 2
80
dB
Vn
Noise output voltage
AV = -1 V/V,
CB = 0.1 µF, See Figure 20
17
µV(rms)
(1)
See Figure 13
UNIT
PO
mW
0.5%
The DGN package, properly mounted, can conduct 700-mW RMS power continuously. The D package can only conduct 350-mW RMS
power continuously with peaks to 700 mW.
PARAMETER MEASUREMENT INFORMATION
VDD 6
RF
VDD/2
Audio
Input
RI
CI
4
IN–
3
IN+
2
BYPASS
–
VO+ 5
+
RL = 8 Ω
CB
–
VO– 8
+
7
GND
1
SHUTDOWN
Bias
Control
Figure 1. BTL Mode Test Circuit
4
VDD
CS
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
kSVR
Supply ripple rejection ratio
vs Frequency
IDD
Supply current
vs Supply voltage
3, 4
PO
Output power
vs Supply voltage
5
THD+N
2
vs Load resistance
Total harmonic distortion plus noise
6
vs Frequency
7, 8, 11, 12
vs Output power
9, 10, 13, 14
Open-loop gain and phase
vs Frequency
15, 16
Closed-loop gain and phase
vs Frequency
17, 18
Vn
Output noise voltage
vs Frequency
19, 20
PD
Power dissipation
vs Output power
21, 22
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
−10
1.8
RL = 8 Ω
CB = 1 µF
SHUTDOWN = 0 V
RF = 10 kΩ
1.6
−20
I DD − Supply Current − mA
k SVR − Supply Ripple Rejection Ratio − dB
0
−30
−40
−50
−60
−70
−80
VDD = 3.3 V
−100
20
100
1k
f − Frequency − Hz
Figure 2.
1.2
1
0.8
VDD = 5 V
−90
1.4
10k
20k
0.6
2.5
3
3.5
4
4.5
5
5.5
VDD − Supply Voltage − V
Figure 3.
5
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
90
1000
SHUTDOWN = VDD
RF = 10 kΩ
80
THD+N 1%
f = 1 kHz
800
PO − Output Power − mW
I DD − Supply Current − µ A
70
60
50
40
30
20
600
RL = 8 Ω
RL = 32 Ω
400
200
10
0
2.5
3
3.5
4
4.5
5
0
2.5
5.5
3
3.5
VDD − Supply Voltage − V
5
5.5
Figure 5.
OUTPUT POWER
vs
LOAD RESISTANCE
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N −Total Harmonic Distortion + Noise − %
THD+N = 1%
f = 1 kHz
700
PO − Output Power − mW
4.5
Figure 4.
800
600
VDD = 5 V
500
400
300
VDD = 3.3 V
200
100
0
8
16
24
32
40
48
RL − Load Resistance − Ω
Figure 6.
6
4
VDD − Supply Voltage − V
56
64
VDD = 3.3 V
PO = 250 mW
RL = 8 Ω
AV = −20 V/V
1
AV = −10 V/V
AV = −2 V/V
0.1
0.01
20
100
1k
f − Frequency − Hz
Figure 7.
10k
20k
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
VDD = 3.3 V
RL = 8 Ω
AV = −2 V/V
PO = 50 mW
1
0.1
PO = 125 mW
PO = 250 mW
0.01
20
10k
0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
f − Frequency − Hz
PO − Output Power − W
Figure 8.
Figure 9.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
0.4
10
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
RL = 8 Ω
20k
f = 20 kHz
f = 10 kHz
f = 1 kHz
0.1
f = 20 Hz
0.01
0.01
1
0.01
1k
100
10
1
VDD = 3.3 V
f = 1 kHz
AV = −2 V/V
VDD = 3.3 V
RL = 8 Ω
CB = 1 µF
AV = −2 V/V
0.1
PO − Output Power − W
Figure 10.
1
VDD = 5 V
PO = 700 mW
RL = 8 Ω
AV = −20 V/V
1
AV = −10 V/V
AV =− 2 V/V
0.1
0.01
20
100
1k
10k
20k
f − Frequency − Hz
Figure 11.
7
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
PO = 50 mW
1
PO = 700 mW
0.1
PO = 350 mW
0.01
20
1k
100
10k
VDD = 5 V
f = 1 kHz
AV = −2 V/V
1
RL = 8 Ω
0.1
0.01
0.1
20k
0.2
f − Frequency − Hz
0.5
0.6
Figure 13.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
180°
VDD = 3.3 V
RL = Open
Open-Loop Gain − dB
f = 20 kHz
1
f = 10 kHz
f = 1 kHz
f = 20 Hz
140°
Phase
100°
50
60°
40
20°
30
Gain
20
−20°
10
−60°
0
−100°
VDD = 5 V
RL = 8 Ω
CB = 1 µF
AV = −2 V/V
−10
−140°
−20
−30
−180°
1
0.1
1
101
102
f − Frequency − kHz
PO − Output Power − W
Figure 14.
8
1
0.9
80
60
0.01
0.01
0.8
Figure 12.
70
0.1
0.7
PO − Output Power − W
10
THD+N −Total Harmonic Distortion + Noise − %
0.4
0.3
Phase
VDD = 5 V
RL = 8 Ω
AV = −2 V/V
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
Figure 15.
103
104
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OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
1
180°
VDD = 5 V
RL = Open
70
140°
60°
40
20°
30
Gain
−20°
10
Phase
Open-Loop Gain − dB
50
−60°
Closed-Loop Gain − dB
100°
Phase
170°
0.5
60
20
180°
Phase
0.75
0.25
0
160°
Gain
−0.25
150°
−0.5
−0.75
140°
−1
−1.25
0
−100°
−1.5
−140°
−1.75
−10
−20
−30
1
101
102
103
VDD = 3.3 V
RL = 8 Ω
PO = 250 mW
−2
101
−180°
104
Phase
80
130°
120°
102
103
104
105
106
f − Frequency − Hz
f − Frequency − kHz
Figure 16.
Figure 17.
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
1
180°
100
Phase
0.75
160°
Gain
150°
−0.5
−0.75
140°
−1
−1.25
−1.5
−1.75
−2
101
VDD = 5 V
RL = 8 Ω
PO = 700 mW
102
130°
103
104
f − Frequency − Hz
105
Phase
Closed-Loop Gain − dB
0
−0.25
Vn − Output Noise Voltage − µV
170°
0.5
0.25
VDD = 3.3 V
BW = 22 Hz to 22 kHz
RL = 8 Ω or 32 Ω
AV = −1 V/V
VO BTL
Vo+
10
120°
106
1
20
100
1k
10k
20k
f − Frequency − Hz
Figure 18.
Figure 19.
9
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OUTPUT NOISE VOLTAGE
vs
FREQUENCY
350
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 8 Ω or 32 Ω
AV = −1 V/V
VDD = 3.3 V
RL = 8 Ω
300
PD − Power Dissipation − mW
Vn − Output Noise Voltage − µV
100
POWER DISSIPATION
vs
OUTPUT POWER
VO BTL
Vo+
10
250
200
150
100
RL = 32 Ω
50
1
20
100
1k
10k
0
20k
0
200
f − Frequency − Hz
Figure 20.
Figure 21.
POWER DISSIPATION
vs
OUTPUT POWER
800
VDD = 5 V
RL = 8 Ω
PD − Power Dissipation − mW
700
600
500
400
300
200
RL = 32 Ω
100
0
0
200
400
600
800
PD − Output Power − mW
Figure 22.
10
400
PD − Output Power − mW
1000
600
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APPLICATION INFORMATION
BRIDGE-TIED LOAD
Figure 23 shows a linear audio power amplifier (APA) in a BTL configuration. The TPA741 BTL amplifier consists
of two linear amplifiers driving both ends of the load. There are several potential benefits to this differential drive
configuration, but initially consider power to the load. The differential drive to the speaker means that as one side
is slewing up, the other side is slewing down, and vice versa. This, in effect, doubles the voltage swing on the
load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation, where voltage is
squared, yields 4× the output power from the same supply rail and load impedance (see Equation 1).
V
O(PP)
V
(rms)
2 2
2
V
(rms)
Power R
L
(1)
VDD
VO(PP)
RL
2x VO(PP)
VDD
–VO(PP)
Figure 23. Bridge-Tied Load Configuration
In a typical portable handheld equipment sound channel operating at 3.3 V, bridging raises the power into an 8-Ω
speaker from a singled-ended (SE, ground reference) limit of 62.5 mW to 250 mW. In sound power that is a 6-dB
improvement, which is loudness that can be heard. In addition to increased power, there are frequency response
concerns. Consider the single-supply, SE configuration shown in Figure 24. A coupling capacitor is required to
block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to
1000 µF), so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of
limiting low-frequency performance of the system. This frequency-limiting effect is due to the high-pass filter
network created with the speaker impedance and the coupling capacitance and is calculated with Equation 2.
1
fc 2 R C
L C
(2)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
11
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APPLICATION INFORMATION (continued)
VDD
–3 dB
VO(PP)
CC
RL
VO(PP)
fc
Figure 24. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of a SE
configuration. Internal dissipation versus output power is discussed further in the thermal considerations section.
BTL AMPLIFIER EFFICIENCY
Linear amplifiers are notoriously inefficient. The primary cause of these inefficiencies is voltage drop across the
output stage transistors. There are two components of the internal voltage drop. One is the headroom or dc
voltage drop that varies inversely to output power. The second component is due to the sine-wave nature of the
output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD.
The internal voltage drop multiplied by the RMS value of the supply current, IDDrms, determines the internal
power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out being equal to the ratio of power from the power supply
to the power delivered to the load. To accurately calculate the RMS values of power in the load and in the
amplifier, the current and voltage waveform shapes must first be understood (see Figure 25).
VO
IDD
IDD(RMS)
VL(RMS)
Figure 25. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application, the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
12
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APPLICATION INFORMATION (continued)
P
Efficiency where
V
P
V
L
L(RMS)
L
SUP
2
L(RMS)
R
L
Vp
2
2R
L
VP
2
P SUP V
I DD(RMS) P
DD
I DD(RMS) V DD 2VP
RL
2V P
RL
Efficiency of a BTL configuration (3)
2 PLR L VP
4V DD
4V DD
12
(4)
Table 1 employs Equation 4 to calculate efficiencies for three different output power levels. The efficiency of the
amplifier is quite low for lower power levels and rises sharply as power to the load is increased, resulting in a
nearly flat internal power dissipation over the normal operating range. The internal dissipation at full output power
is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power
supply design.
Table 1. Efficiency vs Output Power in 3.3-V, 8-Ω, BTL Systems
(1)
OUTPUT POWER
(W)
EFFICIENCY
(%)
PEAK VOLTAGE
(V)
INTERNAL
DISSIPATION
(W)
0.125
33.6
1.41
0.26
0.25
47.6
2.00
0.29
0.375
58.3
2.45 (1)
0.28
High-peak voltage values cause the THD to increase.
A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. In Equation 4, VDD is in the denominator. This indicates
that as VDD goes down, efficiency goes up.
13
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SLOS316C – JUNE 2000 – REVISED JUNE 2004
APPLICATION SCHEMATICS
Figure 26 is a schematic diagram of a typical handheld audio application circuit, configured for a gain of –10 V/V.
VDD 6
RF
50 kΩ
Audio
Input
RI
10 kΩ
CI
4
IN–
3
IN+
2
BYPASS
VDD
CS
VDD/2
1 µF
–
VO+ 5
+
CB
2.2 µF
–
VO– 8
+
700 mW
7
GND
1
From System Control
SHUTDOWN
Bias
Control
Figure 26. TPA741 Application Circuit
Figure 27 is a schematic diagram of a typical handheld audio application circuit, configured for a gain of –10 V/V
with a differential input.
VDD 6
RF
50 kΩ
Audio
Input–
RI
10 kΩ
CI
RI
10 kΩ
Audio
Input+
VDD/2
4
IN–
3
IN+
1 µF
–
VO+ 5
+
RF
50 kΩ
2
CI
VDD
CS
BYPASS
CB
–
2.2 µF
VO– 8
+
700 mW
7
GND
From System Control
1
SHUTDOWN
Bias
Control
Figure 27. TPA741 Application Circuit With Differential Input
It is important to note that using the additional RF resistor connected between IN+ and BYPASS will cause VDD/2
to shift slightly, which could influence the THD+N performance of the amplifier. Although an additional external
operational amplifier could be used to buffer BYPASS from RF, tests in the laboratory have shown that the
THD+N performance is only minimally affected by operating in the fully differential mode as shown in Figure 27.
The following sections discuss the selection of the components used in Figure 26 and Figure 27.
14
TPA741
www.ti.com
SLOS316C – JUNE 2000 – REVISED JUNE 2004
COMPONENT SELECTION
Gain-Setting Resistors, RF and RI
The gain for each audio input of the TPA741 is set by resistors RF and RI according to Equation 5 for BTL mode.
R
BTL gain 2
F
R
I
(5)
BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the
voltage swing across the load. Given that the TPA741 is an MOS amplifier, the input impedance is high;
consequently, input leakage currents are not generally a concern, although noise in the circuit increases as the
value of RF increases. In addition, a certain range of RF values is required for proper start-up operation of the
amplifier. Taken together, it is recommended that the effective impedance seen by the inverting node of the
amplifier be set between 5 kΩ and 20 kΩ. The effective impedance is calculated in Equation 6.
R R
F I
Effective impedance R R
F
I
(6)
As an example, consider an input resistance of 10 kΩ and a feedback resistor of 50 kΩ. The BTL gain of the
amplifier would be -10 V/V and the effective impedance at the inverting terminal would be 8.3 kΩ, which is well
within the recommended range.
For high-performance applications, metal film resistors are recommended because they tend to have lower noise
levels than carbon resistors. For values of RF above 50 kΩ, the amplifier tends to become unstable due to a pole
formed from RF and the inherent input capacitance of the MOS input structure. For this reason, a small
compensation capacitor of approximately 5 pF should be placed in parallel with RF when RF is greater than 50
kΩ. This, in effect, creates a low-pass filter network with the cutoff frequency defined in Equation 7.
−3 dB
fc 1
2 R C
F F
(7)
fc
(7)
For example, if RF is 100 kΩ and CF is 5 pF, then fc is 318 kHz, which is well outside of the audio range.
Input Capacitor, CI
In the typical application an input capacitor, CI, is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency
determined in Equation 8.
15
TPA741
www.ti.com
SLOS316C – JUNE 2000 – REVISED JUNE 2004
−3 dB
fc fc
1
2 R C
I I
(8)
The value of CI is important to consider as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 40 Hz.
Equation 8 is reconfigured as Equation 9.
1
C I
2 R f c
I
(9)
In this example, CI is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier
that reduces useful headroom, especially in high-gain applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher
than the source dc level. It is important to confirm the capacitor polarity in the application.
Power Supply Decoupling, CS
The TPA741 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by
using two capacitors of different types that target different types of noise on the power supply leads. For higher
frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering lower
frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater, placed near the audio
power amplifier is recommended.
Midrail Bypass Capacitor, CB
The midrail bypass capacitor, CB, is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CB determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and THD +
N. The capacitor is fed from a 250-kΩ source inside the amplifier. To keep the start-up pop as low as possible,
the relationship shown in Equation 10 should be maintained. This ensures that the input capacitor is fully charged
before the bypass capacitor is fully charged and the amplifier starts up.
10
1
CB 250 kΩ RF RI CI
(10)
As an example, consider a circuit where CB is 2.2 µF, CI is 0.47 µF, RF is 50 kΩ, and RI is 10 kΩ. Inserting these
values into the Equation 10 we get:
18.2 ≤ 35.5
which satisfies the rule. Bypass capacitor, CB, values of 0.1-µF to 2.2-µF ceramic or tantalum low-ESRcapacitors
are recommended for the best THD and noise performance.
16
TPA741
www.ti.com
SLOS316C – JUNE 2000 – REVISED JUNE 2004
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance, the more the real capacitor behaves like an ideal capacitor.
5-V Versus 3.3-V OPERATION
The TPA741 operates over a supply range of 2.5 V to 5.5 V. This data sheet provides full specifications for 5-V
and 3.3-V operation, as these are considered to be the two most common standard voltages. There are no
special considerations for 3.3-V versus 5-V operation with respect to supply bypassing, gain setting, or stability.
The most important consideration is that of output power. Each amplifier in TPA741 can produce a maximum
voltage swing of VDD - 1 V. This means, for 3.3-V operation, clipping starts to occur when VO(PP) = 2.3 V, as
opposed to VO(PP) = 4 V for 5-V operation. The reduced voltage swing subsequently reduces maximum output
power into an 8-Ω load before distortion becomes significant.
Operation from 3.3-V supplies, as can be shown from the efficiency formula in Equation 4, consumes
approximately two-thirds the supply power of operation from 5-V supplies for a given output-power level.
HEADROOM AND THERMAL CONSIDERATIONS
Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions.
A typical music CD requires 12 dB to 15 dB of dynamic headroom to pass the loudest portions without distortion
as compared with the average power output. From the TPA741 data sheet, one can see that when the TPA741
is operating from a 5-V supply into a 8-Ω speaker that 700-mW peaks are available. Converting watts to dB:
P
P
10Log W 10Log 700 mW –1.5 dB
dB
P
1W
ref
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
1.5 dB – 15 dB = –16.5 (15-dB headroom)
1.5 dB – 12 dB = –13.5 (12-dB headroom)
1.5 dB – 9 dB = –10.5 (9-dB headroom)
1.5 dB – 6 dB = –7.5 (6-dB headroom)
1.5 dB – 3 dB = –4.5 (3-dB headroom)
Converting dB back into watts:
P W 10PdB10 x P
ref
= 22 mW (15-dB headroom)
= 44 mW (12-dB headroom)
= 88 mW (9-dB headroom)
= 175 mW (6-dB headroom)
= 350 mW (3- dB headroom)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the absolute worst case, which is 700 mW of continuous power output with 0 dB of
headroom, against 12-dB and 15-dB applications drastically affects maximum ambient temperature ratings for
the system. Using the power dissipation curves for a 5-V, 8-Ω system, the internal dissipation in the TPA741 and
maximum ambient temperatures is shown in Table 2.
17
TPA741
www.ti.com
SLOS316C – JUNE 2000 – REVISED JUNE 2004
Table 2. TPA741 Power Rating, 5-V, 8-Ω, BTL
PEAK OUTPUT
POWER
(mW)
D PACKAGE
(SOIC)
DGN PACKAGE
(MSOP)
MAXIMUM AMBIENT
TEMPERATURE
(0° CFM)
MAXIMUM AMBIENT
TEMPERATURE
(0° CFM)
AVERAGE
OUTPUT POWER
POWER
DISSIPATION
(mW)
700
700 mW
675
34°C
110°C
700
350 mW (3 dB)
595
47°C
115°C
700
176 mW (6 dB)
475
68°C
122°C
700
88 mW (9 dB)
350
89°C
125°C
700
44 mW (12 dB)
225
111°C
125°C
Table 2 shows that the TPA741 can be used to its full 700-mW rating without any heat sinking in still air up to
110°C and 34°C for the DGN package (MSOP) and D package (SOIC), respectively.
18
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA741D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPA741
TPA741DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJD
TPA741DGNG4
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJD
TPA741DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJD
TPA741DGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJD
TPA741DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPA741
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA741DGNR
HVSSOP
DGN
8
2500
330.0
12.4
TPA741DR
SOIC
D
8
2500
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.3
3.4
1.4
8.0
12.0
Q1
6.4
5.2
2.1
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA741DGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
TPA741DR
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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