Texas Instruments | TPA302: 300-mW Stereo Audio Power Amplifier (Rev. C) | Datasheet | Texas Instruments TPA302: 300-mW Stereo Audio Power Amplifier (Rev. C) Datasheet

Texas Instruments TPA302: 300-mW Stereo Audio Power Amplifier (Rev. C) Datasheet
TPA302
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
300-mW STEREO AUDIO POWER AMPLIFIER
•
•
•
•
•
•
•
300-mW Stereo Output
PC Power Supply Compatibility 5-V and
3.3-V Specified Operation
Shutdown Control
Internal Midrail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
Functional Equivalent of the LM4880
D PACKAGE
(TOP VIEW)
VO1
SHUTDOWN
BYPASS
IN2
1
8
2
7
3
6
4
5
IN1
GND
VDD
VO2
DESCRIPTION
The TPA302 is a stereo audio power amplifier capable of delivering 250 mW of continuous average power into
an 8-Ω load at less than 0.06% THD+N from a 5-V power supply or up to 300 mW at 1% THD+N. The TPA302
has high current outputs for driving small unpowered speakers at 8 Ω or headphones at 32 Ω. For headphone
applications driving 32-Ω loads, the TPA302 delivers 60 mW of continuous average power at less than 0.06%
THD+N. The amplifier features a shutdown function for power-sensitive applications as well as internal thermal
and short-circuit protection. The amplifier is available in an 8-pin SOIC (D) package that reduces board space
and facilitates automated assembly.
TYPICAL APPLICATION CIRCUIT
VDD 6
RF
Audio
Input
VDD
CS
VDD/2
RI
8
IN 1
3
BYPASS
4
IN 2
CI
VO1 1
−
+
CC
CB
Audio
Input
RI
CI
2
VO2 5
−
+
SHUTDOWN
CC
Bias
Control
7
RF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated
TPA302
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PACKAGED DEVICES
(1)
TA
SMALL OUTLINE (1)
(D)
–40°C to 85°C
TPA302D
The D packages are available taped and reeled. To order a taped
and reeled part, add the suffix R (e.g., TPA302DR)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Supply voltage
VI
Input voltage
6V
–0.3 V to VDD + 0.3 V
Continuous total power dissipation
Internally limited (see Dissipation Rating Table)
TJ
Operating junction temperature range
–40°C to 150° C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
731 mW
5.8 mW/°C
460 mW
380 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
VDD
Supply voltage
2.7
5.5
V
TA
Operating free-air temperature
–40
85
°C
DC ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 3.3 V (unless otherwise noted)
PARAMETER
IDD
Supply current
VIO
Input offset voltage
PSRR
Power supply rejection ratio
IDD(SD)
Quiescent current in shutdown
2
TEST CONDITION
VDD = 3.2 V to 3.4 V
MIN
TYP MAX
UNIT
2.25
5
mA
5
20
mV
20
µA
55
0.6
dB
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
THD < 0.08%
PO
Output power
Gain = –1,
f = 1 kHz
BOM
Maximum output power bandwidth
Gain = 10,
B1
Unity gain bandwidth
Channel separation
Vn
TYP MAX
UNIT
100
THD < 1%
125
THD < 0.08%,
RL = 32 Ω
25
THD < 1%,
RL = 32 Ω
35
1% THD
mW
20
kHz
Open loop
1.5
MHz
f = 1 kHz
75
dB
Supply ripple rejection ratio
f = 1 kHz
45
dB
Noise output voltage
Gain = –1
10
µVrms
DC ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
IDD
Supply current
4
10
mA
VOO
Output offset voltage
5
20
mV
PSRR
Power supply rejection ratio
IDD(SD)
Quiescent current in shutdown
VDD = 4.9 V to 5.1 V
65
dB
0.6
µA
AC OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX
THD < 0.06%
250
THD < 1%
300
UNIT
PO
Output power
Gain = –1,
f = 1 kHz
BOM
Maximum output power bandwidth
Gain = 10,
20
kHz
B1
Unity gain bandwidth
Open loop
1.5
MHz
Channel separation
f = 1 kHz
75
dB
Supply ripple rejection ratio
f = 1 kHz
45
dB
Noise output voltage
Gain = -1
10
µVrms
Vn
THD < 0.06%,
RL = 32 Ω
60
THD < 1%,
RL = 32 Ω
80
1% THD
mW
3
TPA302
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
TYPICAL APPLICATION
RF
6
VDD
CB
Stereo Audio
Input
RI
8 IN1-
R
VO1
3 BYPASS
CI
CC
1
CB
From Shutdown
Control Circuit (TPA4860)
2
RI
L
RL
Bias
Control
Stereo
4 IN2-
VO2
CI
RF
4
RL
5
CC
250 mW per Channel at RL = 8 Ω
60 mW per Channel at RL = 32 Ω
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Frequency
1-3, 7-9, 13-15, 19-21
THD+N
Total harmonic distortion plus noise
IDD
Supply current
Vn
Output noise voltage
vs Frequency
Maximum package power dissipation
vs Free-air temperature
Power dissipation
vs Output power
30, 31
Maximum output power
vs Free-air temperature
32, 33
POmax
PO
vs Output power
4-6, 10-12 16-18, 22-24
vs Supply voltage
25
vs Free-air temperature
Output power
26
27, 28
29
vs Load resistance
34
vs Supply voltage
35
Open-loop response
36
Closed-loop response
37
Crosstalk
vs Frequency
38, 39
Supply ripple rejection ratio
vs Frequency
40, 41
10
VCC = 5 V
PO = 250 mW
RL = 8 Ω
AV = −1 V/V
1
VO2
0.1
VO1
0.010
20
100
1k
f − Frequency − Hz
Figure 1.
10 k 20 k
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 5 V
PO = 250 mW
RL = 8 Ω
AV = − 5 V/V
1
VO2
VO1
0.1
0.010
20
100
1k
10 k 20 k
f − Frequency − Hz
Figure 2.
5
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 5 V
PO = 250 mW
RL = 8 Ω
AV = −10 V/V
1
VO1
VO2
0.1
0.010
20
100
1k
10 k 20 k
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 5 V
f = 20 Hz
RL = 8 Ω
AV = −1 V/V
1
0.1
VO2
VO1
0.010
0.01
0.1
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 5 V
f = 1 kHz
RL = 8 Ω
AV = −1 V/V
1
0.1
VO1
VO2
0.010
0.01
0.1
PO − Output Power − W
Figure 5.
6
PO − Output Power − W
1
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
1
10
VCC = 5 V
f = 20 kHz
RL = 8 Ω
AV = −1 V/V
1
VO1
VO2
0.1
0.010
0.01
0.1
PO − Output Power − W
Figure 6.
1
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
10
10
VCC = 5 V
PO = 60 mW
RL = 32 Ω
AV = −1 V/V
1
0.1
VO1
VO2
0.010
20
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
100
1k
10 k 20 k
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 5 V
PO = 60 mW
RL = 32 Ω
AV = −5 V/V
1
VO1
VO2
0.1
0.010
20
100
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
VCC = 5 V
PO = 60 mW
RL = 32 Ω
AV = −10 V/V
1
VO1
VO2
0.1
100
1k
f − Frequency − Hz
Figure 9.
10 k 20 k
THD + N − Total Harmonic Distortion Plus Noise − %
Figure 7.
10
THD + N − Total Harmonic Distortion Plus Noise − %
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
0.010
20
1k
10
VCC = 5 V
f = 20 Hz
RL = 32 Ω
AV = −1 V/V
1
VO2
0.1
VO1
0.010
0.01
0.1
1
PO − Output Power − W
Figure 10.
7
TPA302
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD + N − Total Harmonic Distortion Plus Noise − %
10
VCC = 5 V
f = 1 kHz
RL = 32 Ω
AV = −1 V/V
1
0.1
VO1
0.010
0.01
VO2
0.1
1
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 5 V
f = 20 kHz
RL = 32 Ω
AV = −1 V/V
1
VO1
VO2
0.1
0.010
0.01
Figure 12.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 3.3 V
PO = 100 mW
RL = 8 Ω
AV = −1 V/V
1
VO1
0.1
VO2
100
1k
f − Frequency − Hz
Figure 13.
8
1
Figure 11.
10
0.010
20
0.1
PO − Output Power − W
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
10 k 20 k
10
VCC = 3.3 V
PO = 100 mW
RL = 8 Ω
AV = −5 V/V
1
VO1
VO2
0.1
0.010
20
100
1k
f − Frequency − Hz
Figure 14.
10 k 20 k
TPA302
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 3.3 V
PO = 100 mW
RL = 8 Ω
AV = −10 V/V
1
VO1
VO2
0.1
0.010
20
100
1k
10 k 20 k
10
VCC = 3.3 V
f = 20 Hz
RL = 8 Ω
AV = −1 V/V
1
VO1
0.1
VO2
0.010
0.01
1
Figure 15.
Figure 16.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 3.3 V
f = 1 kHz
RL = 8 Ω
AV = −1 V/V
1
VO1
0.1
VO2
0.010
0.01
0.1
PO − Output Power − W
Figure 17.
1
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
0.1
PO − Output Power − W
f − Frequency − Hz
10
VCC = 3.3 V
f = 20 kHz
RL = 8 Ω
AV = −1 V/V
VO1
1
VO2
0.1
0.010
0.01
0.1
1
PO − Output Power − W
Figure 18.
9
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
10
VCC = 3.3 V
PO = 25 mW
RL = 32 Ω
AV = −1 V/V
1
VO2
0.1
VO1
0.010
20
100
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1k
10 k 20 k
10
VCC = 3.3 V
PO = 25 mW
RL = 32 Ω
AV = −5 V/V
1
VO1
VO2
0.1
0.010
20
100
Figure 20.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
VCC = 3.3 V
PO = 25 mW
RL = 32 Ω
AV = −10 V/V
1
VO1
VO2
0.1
100
1k
f − Frequency − Hz
Figure 21.
10
10 k 20 k
Figure 19.
10
0.010
20
1k
f − Frequency − Hz
10 k 20 k
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
10
VCC = 3.3 V
f = 20 Hz
RL = 32 Ω
AV = −1 V/V
1
VO2
0.1
0.010
0.01
VO1
0.1
PO − Output Power − W
Figure 22.
1
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SLOS174C – JANUARY 1997 – REVISED JUNE 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 3.3 V
f = 1 kHz
RL = 32 Ω
AV = −1 V/V
1
VO1
0.1
VO2
0.010
0.01
0.1
1
THD + N − Total Harmonic Distortion Plus Noise − %
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 3.3 V
f = 20 kHz
RL = 32 Ω
AV = −1 V/V
VO1
1
VO2
0.1
0.010
0.01
0.1
PO − Output Power − W
1
PO − Output Power − W
Figure 23.
Figure 24.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT DISTRIBUTION
vs
FREE-AIR TEMPERATURE
5
6
TA = 25°C
5V
4.5
3.5
3
2.5
2
5V
5V
4
3
Typ
2
Typ
Typ
Min
Min
Max
Min
3.3 V
Max
Min
3.3 V
Typ
Max
Typ
Min
Typ
Max
Min
3.3 V
1
1.5
1
2.5
Max
Max
4
I DD − Supply Current − mA
I DD − Supply Current − mA
5
3
3.5
4
4.5
VDD − Supply Voltage − V
Figure 25.
5
5.5
0
−50
−25
0
25
50
75
TA − Free-Air Temperature − °C
100
Figure 26.
11
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OUTPUT NOISE VOLTAGE
vs
FREQUENCY
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
1000
1000
VCC = 3.3 V
V n − Output Noise Voltage − µ V
V n − Output Noise Voltage − µ V
VCC = 5 V
100
VO1
10
VO2
1
20
100
1k
100
10
1
20
10 k 20 k
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 27.
Figure 28.
MAXIMUM PACKAGE POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
POWER DISSIPATION
vs
OUTPUT POWER
1
10 k 20 k
0.75
0.75
Power Dissipation − W
Maximum Package Power Dissipation − W
VDD = 5 V
0.5
RL = 8 Ω
0.25
0.25
RL = 16 Ω
0
−25
Two Channels Active
0
0
25
50
75
100 125 150
TA − Free-Air Temperature − °C
Figure 29.
12
0.5
175
0
0.25
0.5
PO − Output Power − W
Figure 30.
0.75
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POWER DISSIPATION
vs
OUTPUT POWER
MAXIMUM OUTPUT POWER
vs
FREE-AIR TEMPERATURE
0.3
160
VDD = 3.3 V
Two Channels Active
140
T A − Free-Air Temperature − °C
Power Dissipation − W
0.25
0.2
RL = 8 Ω
0.15
0.1
RL = 16 Ω
0.05
RL = 16 Ω
120
RL = 8 Ω
100
80
60
40
0
20
0
0.05
0.1
0.15
0.2
0.25
PO − Output Power − W
0.3
0.35
0
0.25
0.5
PO max − Maximum Output Power − W
Figure 31.
Figure 32.
MAXIMUM OUTPUT POWER
vs
FREE-AIR TEMPERATURE
OUTPUT POWER
vs
LOAD RESISTANCE
0.75
400
150
350
RL = 16 Ω
140
PO − Output Power − mW
T A − Free-Air Temperature − °C
VDD = 5 V
Two Channels Active
RL = 8 Ω
130
120
300
250
200
VDD = 5 V
150
100
110
VDD = 3.3 V
50
VDD = 3.3 V
Two Channels Active
0
100
0
0.075
0.15
PO max − Maximum Output Power − W
Figure 33.
0.225
5
10
15
20
25 30
35
40
RL − Load Resistance − Ω
45
50
Figure 34.
13
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OUTPUT POWER
vs
SUPPLY VOLTAGE
OPEN-LOOP RESPONSE
450
20°
70
THD = 1%
400
Gain
60
50
250
−20°
40
RL = 8 Ω
200
Phase
30
−40°
Phase
300
Gain − dB
PO − Output Power − mW
0°
350
20
−60°
150
10
100
RL = 32 Ω
−80°
0
50
0
2.5
−10
3
3.5
4
4.5
VDD − Supply Voltage − V
5
10
5.5
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 35.
Figure 36.
CLOSED-LOOP RESPONSE
CROSSTALK
vs
FREQUENCY
20
−100°
10 M 100 M
200°
0
Gain
−10
VDD = 5 V
Phase
−20
0
100°
−100°
−40
Crosstalk − dB
0°
−20
Phase
Gain − dB
−30
−40
−50
V02 to V01
(b to a)
−60
−70
−80
V01 to V02
(a to b)
−90
−60
10
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 37.
14
−200°
10 M 100 M
−100
10
100
1k
f − Frequency − Hz
Figure 38.
10 k
100 k
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CROSSTALK
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
0
VDD = 5 V
VDD = 3.3 V
− 10
Supply Ripple Rejection Ratio − dB
− 10
− 20
− 40
− 50
V02 to V01
(b to a)
− 60
− 70
− 80
V01 to VO2
(a to b)
− 90
− 100
10
100
1k
− 30
− 40
VO2
− 50
VO1
− 60
− 70
− 80
− 90
10 k
− 100
100
100 k
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 39.
Figure 40.
10 k
20 k
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
VDD = 3.3 V
− 10
Supply Ripple Rejection Ratio − dB
Crosstalk − dB
− 30
− 20
− 20
− 30
− 40
VO2
− 50
VO1
− 60
− 70
− 80
− 90
− 100
100
1k
10 k
20 k
f − Frequency − Hz
Figure 41.
15
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APPLICATION INFORMATION
SELECTION OF COMPONENTS
Figure 42 is a schematic diagram of a typical application circuit.
50 kΩ
CF
50 kΩ
VDD 6
VDD = 5 V
RF
CS
VDD/2
Audio
Input
RI
8
IN 1
3
BYPASS
4
IN 2
CI
VO1 1
CC
RL
CB
Audio
Input
RI
VO2 5
CC
CI
RL
CF
RF
2
SHUTDOWN (see Note A)
Bias
Control
7
NOTE A: SHUTDOWN must be held low for normal operation and asserted high for shutdown mode.
Figure 42. TPA302 Typical Notebook Computer Application Circuit
Gain Setting Resistors, RF and RI
The gain for the TPA302 is set by resistors RF and RI according to Equation 1.
Gain RF
RI
(1)
Given that the TPA302 is an MOS amplifier, the input impedance is high; consequently, input leakage currents
are not generally a concern, although noise in the circuit increases as the value of RF increases. In addition, a
certain range of RF values is required for proper start-up operation of the amplifier. Taken together, it is
recommended that the effective impedance seen by the inverting node of the amplifier be set between 5 kΩ and
20 kΩ. The effective impedance is calculated in Equation 2.
R FR I
Effective Impedance RF RI
(2)
As an example, consider an input resistance of 10 kΩ and a feedback resistor of 50 kΩ. The gain of the amplifier
would be –5 and the effective impedance at the inverting terminal would be 8.3 kΩ, which is within the
recommended range.
16
TPA302
www.ti.com
SLOS174C – JANUARY 1997 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
For high-performance applications, metal film resistors are recommended because they tend to have lower noise
levels than carbon resistors. For values of RF above 50 kΩ, the amplifier tends to become unstable due to a pole
formed from RF and the inherent input capacitance of the MOS input structure. For this reason, a small
compensation capacitor of approximately 5 pF should be placed in parallel with RF. In effect, this creates a
low-pass filter network with the cutoff frequency defined in Equation 3.
1
f c(lowpass) 2 R F CF
(3)
For example, if RF is 100 kΩ and CF is 5 pF, then fc(lowpass) is 318 kHz, which is well outside of the audio range.
Input Capacitor, CI
In the typical application, input capacitor CI is required to allow the amplifier to bias the input signal to the proper
dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency
determined in Equation 4.
1
f c(highpass) 2 R I CI
(4)
The value of CI is important to consider as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 40 Hz.
Equation 4 is reconfigured as Equation 5.
1
CI 2 R I f c(highpass)
(5)
In this example, CI is 0.4 µF; so, one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier
that reduces useful headroom, especially in high-gain applications (>10). For this reason, a low-leakage tantalum
or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
Power Supply Decoupling, CS
The TPA302 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the power
amplifier is recommended.
Midrail Bypass Capacitor, CB
The midrail bypass capacitor, CB, serves several important functions. During startup or recovery from shutdown
mode, CB determines the rate at which the amplifier starts up. This helps to push the start-up pop noise into the
subaudible range (so low it cannot be heard). The second function is to reduce noise produced by the power
supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to
the amplifier. The capacitor is fed from a 25-kΩ source inside the amplifier. To keep the start-up pop as low as
possible, the relationship shown in Equation 6 should be maintained.
1
1
C B 25 kΩ C I R I
(6)
As an example, consider a circuit where CB is 0.1 µF, CI is 0.22 µF and RI is 10 kΩ. Inserting these values into
Equation 6 results in: 400 ≤ 454 which satisfies the rule. Recommended values for bypass capacitor CB are
0.1-µF to 1-µF, ceramic or tantalum low-ESR, for the best THD and noise performance.
17
TPA302
www.ti.com
SLOS174C – JANUARY 1997 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
OUTPUT COUPLING CAPACITOR, CC
In the typical single-supply, single-ended (SE) configuration, an output coupling capacitor (CC) is required to
block the dc bias at the output of the amplifier thus preventing dc currents in the load. As with the input coupling
capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by
Equation 7.
1
fc 2 R L CC
(7)
The main disadvantage, from a performance standpoint, is that the load impedances are typically small, which
drives the low-frequency corner higher. Large values of CC are required to pass low frequencies into the load.
Consider the example where a CC of 68 µF is chosen and loads vary from 8 Ω, 32 Ω, and 47 kΩ. Table 1
summarizes the frequency response characteristics of each configuration.
Table 1. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
RL
CC
LOWEST FREQUENCY
8Ω
68 µF
293 Hz
32 Ω
68 µF
73 Hz
47,000 Ω
68 µF
0.05 Hz
As Table 1 indicates, most of the bass response is attenuated into 8-Ω loads while headphone response is
adequate and drive into line level inputs (a home stereo for example) is good.
The output coupling capacitor required in single-supply, SE mode also places additional constraints on the
selection of other components in the amplifier circuit. The rules described previously still hold with the addition of
the following relationship:
1
1 1
C 25 kΩ C R RLC C
B
I I
(8)
SHUTDOWN MODE
The TPA302 employs a shutdown mode of operation designed to reduce quiescent supply current, IDD(q), to the
absolute minimum level during periods of nonuse for battery-power conservation. For example, during device
sleep modes or when other audio-drive currents are used (i.e., headphone mode), the speaker drive is not
required. The SHUTDOWN input terminal should be held low during normal operation when the amplifier is in
use. Pulling SHUTDOWN high causes the outputs to mute and the amplifier to enter a low-current state,
IDD ~ 0.6 µA. SHUTDOWN should never be left unconnected because amplifier operation would be
unpredictable.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real capacitor can be modeled
simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the
beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real
capacitor behaves like an ideal capacitor.
18
TPA302
www.ti.com
SLOS174C – JANUARY 1997 – REVISED JUNE 2004
THERMAL CONSIDERATIONS
A prime consideration when designing an audio amplifier circuit is internal power dissipation in the device. The
curve in Figure 43 provides an easy way to determine what output power can be expected out of the TPA302 for
a given system ambient temperature in designs using 5-V supplies. This curve assumes no forced airflow or
additional heat sinking.
160
VDD = 5 V
Two Channels Active
TA - Free-Air Temperature -
°C
140
RL = 16 Ω
120
RL = 8 Ω
100
80
60
40
20
0
0.25
0.5
0.75
PO max - Maximum Output Power - W
Figure 43. Free-Air Temperature Versus Maximum Output Power
5-V VERSUS 3.3-V OPERATION
The TPA302 was designed for operation over a supply range of 2.7 V to 5.5 V. This data sheet provides full
specifications for 5-V and 3.3-V operation because they are considered to be the two most common standard
voltages. There are no special considerations for 3.3-V versus 5-V operation as far as supply bypassing, gain
setting, or stability. Supply current is slightly reduced from 4 mA (typical) to 2.25 mA (typical). The most important
consideration is that of output power. Each amplifier in the TPA302 can produce a maximum voltage swing of
VDD – 1 V. This means, for 3.3-V operation, clipping starts to occur when VO(PP) = 2.3 V as opposed when
VO(PP) = 4 V while operating at 5 V. The reduced voltage swing subsequently reduces maximum output power
into the load before distortion begins to become significant.
19
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPA302D
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
75
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
TPA302
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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