Texas Instruments | TPA2008D2: 3-W Stereo Class-D Audio Power Amplifier w/DC Vol Control (Rev. C) | Datasheet | Texas Instruments TPA2008D2: 3-W Stereo Class-D Audio Power Amplifier w/DC Vol Control (Rev. C) Datasheet

Texas Instruments TPA2008D2: 3-W Stereo Class-D Audio Power Amplifier w/DC Vol Control (Rev. C) Datasheet
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
3-W STEREO CLASS-D AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL
FEATURES
•
•
•
•
•
•
•
DESCRIPTION
3 W Per Channel into 3-Ω Speakers
(THD+N = 10%)
– < 0.045% THD at 1.5 W, 1 kHz, 3-Ω Load
DC Volume Control With 2-dB Steps From
-38 dB to 20 dB
Filter Free Modulation Scheme Operates
Without a Large and Expensive LC Output
Filter
Extremely Efficient Third Generation 5-V
Class-D Technology
– Low Supply Current, 7 mA
– Low Shutdown Control, 1 µA
– Low Noise Floor, -80 dBV
– Maximum Efficiency into 3 Ω, 78%
– Maximum Efficiency into 8 Ω, 88%
– PSRR, -70 dB
Integrated Depop Circuitry
Operating Temperature Range, -40°C to 85°C
Space-Saving, Surface Mount PowerPAD™
Package
APPLICATIONS
•
•
•
•
The TPA2008D2 is a third generation 5-V class-D
amplifier from Texas Instruments. Improvements to
previous generation devices include: dc volume control, lower supply current, lower noise floor, higher
efficiency, smaller packaging, and fewer external
components. Most notably, a new filter-free class-D
modulation technique allows the TPA2008D2 to directly drive the speakers, without needing a low-pass
output filter consisting of two inductors and three
capacitors per channel. Eliminating this output filter
saves approximately 30% in system cost and 75% in
PCB area.
The improvements and functionality make this device
ideal for LCD projectors, LCD monitors, powered
speakers, and other applications that demand more
battery life, reduced board space, and functionality
that surpasses currently available class-D devices.
A chip-level shutdown control limits total supply
current to 1 µA, making the device ideal for battery-powered applications. Protection circuitry increases device reliability: thermal and short circuit.
Undervoltage shutdown saves battery power for more
essential devices when battery voltage drops to low
levels.
The TPA2008D2 is available in a 24-pin TSSOP
PowerPAD™package.
LCD Projectors
LCD Monitors
Powered Speakers
Battery Operated and Space Constrained
Systems
EFFICIENCY
vs
OUTPUT POWER
100
8 Ω Speaker
90
4 Ω Speaker
Efficiency − %
80
3 Ω Speaker
70
60
50
40
30
VDD = 5 V
No Filter
20
10
0
0
0.5
1
1.5
2
2.5
PO − Output Power − W
3
3.5
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
10
VDD = 5 V
RL = 3 Ω
Gain = 0 dB
f = 1 kHz
1
f = 20 kHz
0.1
f = 20 Hz
0.01
0.01
0.1
1
4
PO − Output Power − W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPA2008D2
www.ti.com
SLOS413C – JULY 2003 – REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
TSSOP PowerPAD (PWP) (1)
(1)
Device
TPA2008D2PWP (1)
Package Designator
PWP (1)
The PWP package is available taped and reeled. To order a taped
and reeled part, add the suffix R to the part number (e.g.,
TPA2008D2PWPR).
PWP PACKAGE
(TOP VIEW)
LINN
LINP
SHUTDOWN
PVDDL
LOUTP
PGNDL
PGNDL
LOUTN
PVDDL
COSC
ROSC
AGND
2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RINN
RINP
BYPASS
PVDDR
ROUTP
PGNDR
PGNDR
ROUTN
PVDDR
NC
VOLUME
VDD
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
DESCRIPTION
AGND
12
-
Analog ground
BYPASS
22
I
Tap to voltage divider for internal mid-supply bias generator used for internal analog reference.
COSC
10
I
A capacitor connected to this terminal sets the oscillation frequency in conjunction with ROSC. For
proper operation, connect a 220-pF capacitor from COSC to ground.
LINN
1
I
Negative differential audio input for left channel
LINP
2
I
Positive differential audio input for left channel
LOUTN
8
O
Negative audio output for left channel
LOUTP
5
O
Positive audio output for left channel
NC
15
I
No connection
PGNDL
6, 7
-
Power ground for left channel H-bridge
PGNDR
18, 19
-
Power ground for right channel H-bridge
PVDDL
4, 9
PVDDR
16, 21
Power supply for left channel H-bridge
Power supply for right channel H-bridge
RINN
24
I
Positive differential audio input for right channel
RINP
23
I
Negative differential audio input for right channel
ROSC
11
I
A resistor connected to the ROSC terminal sets the oscillation frequency in conjunction with COSC. For
proper operation, connect a 120-kΩ resistor from ROSC to ground.
ROUTN
17
O
Negative output for right channel
ROUTP
20
O
Positive output for right channel
SHUTDOWN
3
I
Places the amplifer in shutdown mode if a TTL logic low is placed on this terminal; normal operation if a
TTL logic high is placed on this terminal.
VDD
13
-
Analog power supply
VOLUME
14
I
DC volume control for setting the gain on the internal amplifiers. The dc voltage range is 0 to VDD.
-
-
Connect to analog ground and the power grounds must be soldered down in all applications to properly
secure device on the PCB.
Thermal Pad
3
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
PVDD
VDD
Gain
Adj.
RINN
Gate
Drive
ROUTN
PGND
PVDD
Gate
Drive
Gain
Adj.
RINP
ROUTP
PGND
SHUTDOWN
Volume
Control
VOLUME
Biases
and
References
Startup
Protection
Logic
Ramp
Generator
COSC
Short
Circuit
Protection
Short
Circuit
Protection
VDD
ROSC
Thermal
BYPASS
PVDD
LINP
Gain
Adj.
Gate
Drive
LOUTP
PGND
PVDD
LINN
Gain
Adj.
Gate
Drive
LOUTN
PGND
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
VDD,PVDD
Supply voltage range
VI (RINN, RINP, LINN,
LINP, VOLUME)
Input voltage range
Continuous total power dissipation
-0.3 V to 6 V
0 V to VDD
See Dissipation Rating Table
TA
Operating free-air temperature range
-40°C to 85°C
TJ
Operating junction temperature range
-40°C to 150°C
Tstg
Storage temperature range
-65°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
4
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
DISSIPATION RATINGS TABLE
PACKAGE
TA≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
PWP
2.18 W
21.8 mW/°C
1.2 W
872 mW
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Supply voltage
Volume terminal voltage
VIH
High-level input voltage
SHUTDOWN
VIL
Low-level input voltage
SHUTDOWN
MAX
UNIT
4.5
5.5
V
0
VDD
V
2
V
0.8
V
PWM frequency
200
300
kHz
TA
Operating free-air temperature
-40
85
°C
TJ
Operating junction temperature
125
°C
ELECTRICAL CHARACTERISTICS
TA= 25°C, VDD = PVDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOS |
Output offset voltage (measured differentially)
VI = 0 V, AV = 20 dB, RL = 8Ω
PSRR
Power supply rejection ratio
VDD = PVDD = 4.5 V to 5.5 V
| IIH |
High-level input current
VDD = PVDD = 5.5 V, VI= VDD = PVDD
| IIL |
Low-level input current
VDD = PVDD = 5.5 V, VI = 0 V
IDD
Supply current
No filter (no load)
IDD(max)
RMS supply current at max power
RL = 3 Ω, PO = 2.5 W/channel (stereo)
IDD(SD)
Supply current in shutdown mode
SHUTDOWN = 0 V
Drain-source on-state resistance
VDD = 5 V, IO = 500 mA,
TJ= 25°C
rds(on)
MIN
TYP MAX
5
25
mV
1
µA
-70
7
UNIT
dB
1
µA
15
mA
1.8
A
50 1000
High side
450
600
Low side
450
600
TYP
MAX
nA
mΩ
OPERATING CHARACTERISTICS
TA= 25°C, VDD = PVDD = 5 V, RL = 3 Ω, Gain = 0 dB (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f = 1 kHz, RL = 3 Ω, Stereo
operation
THD+N = 1%
MIN
2.5
UNITS
PO
Output power
THD+N
Total harmonic distortion plus noise
BOM
Maximum output power bandwidth
THD = 5%
20
kHz
SNR
Signal-to-noise ratio
Maximum output at THD+N <0.5%
96
dB
150
°C
20
°C
THD+N = 10%
PO = 2.2 W, f = 20 Hz to 20 kHz
PO = 1.5 W, f = 1 kHz
Thermal hysteresis
Integrated noise floor
20 Hz to 20 kHz, inputs ac
grounded
W
<0.3%
0.045%
Thermal trip point
Vn
3
Volume = 0 dB
42
Volume = 20 dB
85
µVrms
5
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
Table 1. TYPICAL DC VOLUME CONTROL
VOLTAGE ON VOLUME PIN
(V)
(INCREASING OR FIXED GAIN)
VOLTAGE ON VOLUME PIN
(V)
(DECREASING GAIN)
TYPICAL GAIN OF AMPLIFIER
(dB) (1)
0-0.33
0.31-0
-38 (2)
0.34-0.42
0.43-0.32
-37
0.43-0.52
0.54-0.44
-35
0.53-0.63
0.64-0.55
-33
0.64-0.75
0.75-0.65
-31
0.76-0.86
0.86-0.76
-29
0.87-0.97
0.97-0.87
-27
0.98-1.07
1.08-0.98
-25
1.08-1.18
1.19-1.09
-23
1.19-1.30
1.32-1.20
-21
1.31-1.41
1.42-1.33
-19
1.42-1.52
1.53-1.43
-17
1.53-1.63
1.63-1.54
-15
1.64-1.75
1.75-1.64
-13
1.76-1.85
1.84-1.76
-12
1.86-1.96
1.96-1.85
-10
1.97-2.07
2.09-1.97
-8
2.08-2.18
2.19-2.10
-6
2.19-2.30
2.33-2.20
-4
2.31-2.40
2.43-2.34
-2
2.41-2.52
2.49-2.44
0 (2)
2.53-2.63
2.62-2.50
2
2.64-2.75
2.75-2.63
4
2.76-2.87
2.85-2.76
6
2.88-2.98
2.99-2.86
8
2.99-3.10
3.12-3.00
10
3.11-3.22
3.25-3.13
12
3.23-3.33
3.36-3.26
14
3.34-3.47
3.48-3.37
16
3.48-3.69
3.64-3.49
18
3.70-VDD
VDD-3.65
20 (2)
(1)
(2)
The typical part-to-part gain variation can be as large as ±2 dB (one gain step).
Tested in production.
The volume control circuitry of the TPA2008D2 is internally referenced to the VDD and AGND terminals. Any
common-mode noise between the VOLUME terminal and these terminals will be sensed by the volume control
circuitry. If the noise exceeds the step size voltage, the gain will change. In order to minimize this effect, care
must be taken to ensure the signal driving the VOLUME terminal is referenced to the VDD and AGND terminals
of the TPA2008D2. See section titled, “Special Layout Considerations” for more details.
6
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Efficiency
vs Output power
1, 2
vs Frequency
3-5
vs Output power
6-8
THD+N
Total harmonic distortion + noise
kSVR
Supply ripple rejection ratio
vs Frequency
9
Crosstalk
vs Frequency
10
CMRR
Common-mode rejection ratio
vs Frequency
11
Ri
Input resistance
vs Gain setting
12
EFFICIENCY
vs
OUTPUT POWER
EFFICIENCY
vs
OUTPUT POWER
100
100
8-Ω Speaker
90
8-Ω Speaker
90
4-Ω Speaker
4-Ω Speaker
80
80
3-Ω Speaker
60
50
40
30
60
50
40
30
20
20
VDD = 5 V
No Filter
10
0
3-Ω Speaker
70
Efficiency − %
Efficiency − %
70
VDD = 5 V
Ferrite Bead Filter
10
0
0.5
1
1.5
2
2.5
3
3.5
0
0
0.5
1
1.5
2
2.5
PO − Output Power − W
PO − Output Power − W
Figure 1.
Figure 2.
3
3.5
7
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
VDD = 5 V
RL = 3 Ω
Gain = 0 dB
PO = 2.2 W
0.1
PO = 300 mW
PO = 1.2 W
0.01
20
100
1k
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
10k 20k
VDD = 5 V
RL = 4 Ω
Gain = 0 dB
PO = 2 W
0.1
PO = 250 mW
PO = 1 W
0.01
20
100
1k
f − Frequency − Hz
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
VDD = 5 V
RL = 8 Ω
Gain = 0 dB
PO = 1 W
0.1
PO = 50 mW
0.01
PO = 500 mW
100
1k
f − Frequency − Hz
Figure 5.
8
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
0.001
20
10k 20k
f − Frequency − Hz
10k 20k
10
1
VDD = 5 V
RL = 3 Ω
Gain = 0 dB
f = 1 kHz
f = 20 kHz
0.1
f = 20 Hz
0.01
0.01
0.1
PO − Output Power − W
Figure 6.
1
4
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VDD = 5 V
RL = 4 Ω
Gain = 0 dB
1
f = 1 kHz
0.1
f = 20 Hz
f = 20 kHz
0.01
0.01
0.1
1
VDD = 5 V
RL = 8 Ω
Gain = 0 dB
1
f = 1 kHz
f = 20 kHz
0.01
0.01
3
0.1
PO − Output Power − W
Figure 7.
Figure 8.
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
−40
VDD = 5 V
Gain = 20 dB
C(BYPASS) = 1 µF
−50
−55
Crosstalk − dB
kSVR − Supply Ripple Rejection Ratio − dB
2
−30
VDD = 5 V
C(BYPASS) = 1 µF
−50
−60
−65
1
PO − Output Power − W
−40
−45
f = 20 Hz
0.1
RL = 4 Ω
RL = 3 Ω
−70
−60
−70
PO = 2 W,
RL = 4 Ω
PO = 1 W,
RL = 8 Ω
−80
−90
RL = 8 Ω
−75
−80
20
−100
100
1k
10k 20k
−110
20
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 9.
Figure 10.
10k 20k
9
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
INPUT RESISTANCE
vs
GAIN SETTING
300
VDD = 5 V
RL = 8 Ω
C(BYPASS) = 1 µF
250
−55
Ri − Input Resistance − kΩ
CMRR − Common-Mode rejection Ratio − dB
−50
−60
−65
150
100
50
−70
20
100
1k
f − Frequency − Hz
Figure 11.
10
200
10k 20k
0
−40
VDD = 5 V
BTL Load = 8Ω
C(BYPASS) = 1 µF
−30
−20
−10
0
Gain Setting − dB
Figure 12.
10
20
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION
APPLICATION CIRCUIT
TPA2008D2
1 LINN
LIN−
0.1 µF
LIN+
0.1 µF
System
Control
2 LINP
3
4
5
6
VDD
LOUT+
GND
7
1 µF
10 µF
8
9
LOUT−
10
11
220 pF
120 kΩ
12
SHUTDOWN
PVDD
LOUTP
PGND
PGND
LOUTN
PVDD
RINN
RINP
BYPASS
PVDD
ROUTP
PGND
PGND
ROUTN
PVDD
COSC
NC
ROSC
VOLUME
AGND
VDD
24
RIN−
23 0.1 µF
RIN+
22
0.1 µF
21
1 µF
20
ROUT+
19
GND
1 µF
18
17
ROUT−
16
VDD
15
14
VOLUME
13
VDD
1 µF
GND
Figure 13. TPA2008D2 In A Stereo Configuration With Differential Inputs
11
TPA2008D2
SLOS413C – JULY 2003 – REVISED MAY 2004
www.ti.com
APPLICATION INFORMATION (continued)
TRADITIONAL CLASS-D MODULATION SCHEME
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 14. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
resulting in a high I2R loss, thus causing a high supply current.
OUTP
OUTN
+5 V
Differential Voltage
Across Load
0V
−5 V
Current
Figure 14. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
12
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
TPA2008D2 MODULATION SCHEME
The TPA2008D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+5 V
0V
−5 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+5 V
0V
Across
Load
−5 V
Current
Figure 15. The TPA2008D2 Output Voltage and Current Waveforms Into an Inductive Load
EFFICIENCY: LC FILTER REQUIRED WITH THE TRADITIONAL CLASS-D MODULATION SCHEME
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VDD, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA2008D2 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.
13
TPA2008D2
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SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
EFFECTS OF APPLYING A SQUARE WAVE INTO A SPEAKER
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for
frequencies beyond the audio band.
Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency
switching current. The amount of power dissipated in the speaker may be estimated by first considering the
overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the
dominant loss in the system, then the maximum theoretical efficiency for the TPA2008D2 with an 4-Ω load is as
follows:
Efficiency (theoretical, %) R R r
100% 4(4 0.45) 100% 89.9%
L
L
ds(on)
(1)
The maximum measured output power is approximately 2.5 W with a 5-V power supply. The total theoretical
power supplied (P(total)) for this worst-case condition would therefore be as follows:
P
(total)
P Efficiency 2.5 W 0.899 2.781 W
O
(2)
The efficiency measured in the lab using a 4-Ω speaker was 80%. The power not accounted for as dissipated
across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power:
Other losses P
(total)
(measured) P
(total)
(theoretical) 3.025 2.781 0.244 W
(3)
The quiescent supply current at 5 V is measured to be 7 mA. It can be assumed that the quiescent current
encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any
remaining power is dissipated in the speaker and is calculated as follows:
P
(dis)
0.244 W (5 V 7 mA) 0.209 W
(4)
Note that these calculations are for the worst-case condition of 2.5 W delivered to the speaker. Since the
0.209 W is only 7.4% of the power delivered to the speaker, it may be concluded that the amount of power
actually dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the
specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the
power generated from a clipping waveform.
WHEN TO USE AN OUTPUT FILTER
Design the TPA2008D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Many applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from
the amplifier to the speaker.
14
TPA2008D2
www.ti.com
SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
15 µH
OUTP
L1
15 µH
C1
C2
0.22 µF
1 µF
OUTN
C3
L2
0.22 µF
Figure 16. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 4Ω
33 µH
OUTP
L1
33 µH
OUTN
L2
C1
C2
0.1 µF
0.47 µF
C3
0.1 µF
Figure 17. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 8 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 18. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
15
TPA2008D2
www.ti.com
SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
VOLUME CONTROL OPERATION
The VOLUME pin controls the volume of the TPA2008D2. It is controlled with a dc voltage, which should not
exceed VDD. Table 1 lists the voltage on the VOLUME pin and the corresponding gain.
The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME
terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that
the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation of
the volume control can be found in Figure 19. The graph focuses on three gain steps with the trip points defined
in the first and second columns of Table 1. The dotted lines represent the hysteresis about each gain step.
Decreasing Voltage on
VOLUME Terminal
Gain − dB
2
0
Increasing Voltage on
VOLUME Terminal
−2
2.44
2.53
2.41
2.50
Voltage on VOLUME Pin − V
Figure 19. DC Volume Control Operation
SPECIAL LAYOUT CONSIDERATIONS
The voltage on the VOLUME pin must closely track that of the supply voltage, VDD. As the output power is
increased, the noise on the power supply will increase. The noise seen by the PVDD pin must also be seen by the
VOLUME pin. It is for that reason that absolutely no capacitor should be placed on the VOLUME pin. Additional
steps should be taken to reduce the line capacitance on the VOLUME pin, such as reducing line length. Any
capacitance on the VOLUME pin will act as a filter, thus making the voltage seen by the VOLUME pin and VDD
different. If the difference is large enough, the amplifier will change gain steps.
A star point should be used for power, where the supply voltage for VDD, PVDD, and the volume circuitry can be
taken. This point is typically at the bulk decoupling capacitor. The trace connecting the star point to a
potentiometer or a DAC should be short. The trace connecting the potentiometer or DAC to the VOLUME pin
should be kept as short and straight as possible.
As with the VDD, a star ground should likewise be used. There should exist on the board a point where AGND
and PGND converge. This should be the only place where the two grounds are connected. The ground used for
the volume control should be AGND. If a potentiometer is to be used to control the volume of the device, it
should be connected to AGND. A DAC that has a ground reference should have a short trace to AGND from its
ground reference input.
For an example of proper board layout, please refer to the TPA2008D2 EVM User's Guide, document number
SLOU116.
16
TPA2008D2
www.ti.com
SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
SELECTION OF COSC AND ROSC
The switching frequency is determined using the values of the components connected to ROSC (pin 11) and
COSC (pin 10) and may be calculated with the following equation:
fOSC = 6.6 / (ROSC x COSC)
(5)
The frequency may be varied from 200 kHz to 300 kHz by adjusting the values chosen for ROSC and COSC. The
recommended values are COSC = 220 pF, ROSC= 120 kΩ for a switching frequency of 250 kHz.
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over five times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB
or cutoff frequency also changes by over five times.
Rf
Ci
IN
Input
Signal
Ri
The -3-dB frequency can be calculated using equation Equation 6. See Figure 12. Note that due to process
variation, the input resistance, Ri, can change by up to 20%.
1
f
3 dB
2 C R
i i
(6)
INPUT CAPACITOR, Ci
In a typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input resistance of the amplifier (Ri) form a
high-pass filter with the corner frequency determined in equation Equation 7.
−3 dB
fc 1
2 R C
i i
fc
(7)
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where Ri is 50 kΩ and the specification calls for a flat bass response down to 30 Hz. Equation
Equation 5 is reconfigured as equation Equation 8.
1
C i
2 R f c
i
(8)
In this example, Ci is 0.1 µF, so one would likely choose a value in the range of 0.1 µF to 1 µF. Figure 12 can be
used to determine the input impedance for a given gain and can serve to aid in the calculation of Ci.
17
TPA2008D2
SLOS413C – JULY 2003 – REVISED MAY 2004
www.ti.com
APPLICATION INFORMATION (continued)
A further consideration for this capacitor is the leakage path from the input source through the input network (Ci)
and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the
amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage
tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the
capacitor should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely
higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
Ci must be 10 times smaller than the bypass capacitor to reduce clicking and popping noise from power on/off
and entering and leaving shutdown. After sizing Ci for a given cutoff frequency, size the bypass capacitor to 10
times that of the input capacitor.
Ci ≤ CBYP / 10
(9)
POWER SUPPLY DECOUPLING, CS
The TPA2008D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD terminal works best. For
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, CBYP
The midrail bypass capacitor (CBYP) is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor (CBYP) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for
the best THD and noise performance.
Increasing the bypass capacitor reduces clicking and popping noise from power on/off and entering and leaving
shutdown. To have minimal pop, CBYP should be 10 times larger than Ci.
CBYP ≥ 10 × Ci
(10)
DIFFERENTIAL INPUT
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA2008D2 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA2008D2 with a single-ended
source, ac ground either input through a capacitor and apply the audio signal to the remaining input. In a
single-ended input application, the unused input should be ac-grounded at the audio source instead of at the
device input for best noise performance.
SHUTDOWN MODES
The TPA2008D2 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, IDD(SD) = 1 µA. SHUTDOWN should never be left
unconnected because the amplifier state would be unpredictable.
18
TPA2008D2
www.ti.com
SLOS413C – JULY 2003 – REVISED MAY 2004
APPLICATION INFORMATION (continued)
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance
the more the real capacitor behaves like an ideal capacitor.
SHORT-CIRCUIT PROTECTION
The TPA2008D2 has short circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VDD shorts. When a short-circuit is detected on the
outputs, the part immediately goes into shutdown. This is a latched fault and must be reset by cycling the voltage
on the SHUTDOWN pin to a logic low and back to the logic high, or by cycling the power off and then back on.
This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not
removed, the protection circuitry activates again.
LOW-SUPPLY VOLTAGE DETECTION
The TPA2008D2 incorporates circuitry designed to detect when the supply voltage is low. When the supply
voltage reaches 1.8 V or below, the TPA2008D2 goes into a state of shutdown. The current consumption drops
from millamperes to microamperes, leaving the remaining battery power for more essential devices such as
microprocessors. When the supply voltage level returns to normal, the device comes out of its shutdown state
and starts to draw current again. Note that even though the device is drawing several milliamperes of current, it
is not operationally functional until VDD≥ 4.5 V.
THERMAL PROTECTION
Thermal protection on the TPA2008D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are
disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by
20°C. The device begins normal operation at this point with no external system interaction.
THERMAL CONSIDERATIONS: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE
To calculate the maximum ambient temperature, the following equation may be used:
TAmax = TJ – ΘJAPDissipated
where: TJ = 125°C
ΘJA = 45.87°C/W
(11)
(The derating factor for the 24-pin PWP package is given in the dissipation rating table.)
To estimate the power dissipation, the following equation may be used:
PDissipated = PO(average) x ((1 / Efficiency) – 1)
Efficiency = ~85% for an 8-Ω load
= ~80% for a 4-Ω load
= ~75% for a 3-Ω load
(12)
Example. What is the maximum ambient temperature for an application that requires the TPA2008D2 to drive 2
W into a 4-Ω speaker (stereo)?
PDissipated = 4 W x ((1 / 0.8) - 1) = 1 W
(PO = 2 W x 2)
TAmax = 125°C - (45.87°C/W x 1 W) = 79.13°C
19
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA2008D2PWP
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA2008D2
TPA2008D2PWPR
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA2008D2
TPA2008D2PWPRG4
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA2008D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA2008D2PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2008D2PWPR
HTSSOP
PWP
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 24
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
4.4 x 7.6, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 2.200
PLASTIC SMALL OUTLINE
6.6
TYP
6.2
PIN 1 ID
AREA
A
SEATING PLANE
0.1 C
22X 0.65
24
1
C
2X
7.15
7.9
7.7
NOTE 3
12
B
13
24X
4.5
4.3
0.30
0.19
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
(1)
2.40
1.65
DETAIL A
TYPICAL
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
( 0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
BASED ON
0.125 THICK
STENCIL
SYMM
22X (0.65)
13
12
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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