Texas Instruments | 2-W Stereo Audio Power Amplifier with I2C Bus (Rev. C) | Datasheet | Texas Instruments 2-W Stereo Audio Power Amplifier with I2C Bus (Rev. C) Datasheet

Texas Instruments 2-W Stereo Audio Power Amplifier with I2C Bus (Rev. C) Datasheet
SLOS327C − AUGUST 2000 − REVISED MAY 2001
D
D
D
D
D
D
D
D
D
D
D
D
I2C Bus Controllable
2-W/Ch Output Power Into 4-Ω Load
Low Supply Current and Shutdown Current
Depop Circuitry
Digital Volume Control From 20 dB to
−60 dB
Internal Gain Control, Which Eliminates
External Gain-Setting Resistors
Fully Differential Input
Stereo Input MUX
PC-Beep Input
Compatible With PC 99 Desktop Line-Out
Into 10-kΩ Load
Compatible With PC 99 Portable Into 8-Ω
Load
Surface-Mount Power Packaging
24-Pin TSSOP PowerPAD
PWP PACKAGE
(TOP VIEW)
GND
LOUT+
PC-BEEP
ADDRESS0
LIN
LLINEIN
LHPIN
PVDD
RIN
ADDRESS1
SE/BTL
ROUT+
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LOUT−
SCL
SHUTDOWN
BYPASS
VDD
PVDD
RLINEIN
RHPIN
I2CVDD
SDA
ROUT−
GND
description
The TPA0172 is a stereo audio power amplifier in a 24-pin TSSOP thermally enhanced package capable of
delivering 2 W of continuous RMS power per channel into 4-Ω loads. This device utilizes the I2C bus to control
its functionality, which minimizes the number of external components needed, simplifies the design, and frees
up board space for other features. When driving 1 W into 8-Ω speakers, the TPA0172 has less than 0.2% THD+N
from 20 Hz to 20 kHz.
Included within this device is integrated depop circuitry that virtually eliminates transients that cause noise in
the speakers at power up, power down, and while transitioning in and out of shutdown mode.
The overall gain of the amplifier is controlled digitally by the volume control registers which are programmed
via the I2C interface. At power up, the amplifier defaults to –60 dB in BTL mode, or –66 dB in SE mode. There
are four registers that contain the gains: left BTL, right BTL, left SE, and right SE. Each register contains six bits,
which allows 64 gain steps from –60 dB to 20 dB in 1.25-dB steps, and two bits that mute the amplifier.
The TPA0172 only consumes 6.5 mA of supply current during normal operation. A shutdown mode is included
that reduces supply current to less than 15 µA.
The PowerPAD package (PWP) delivers a level of thermal performance that was previously achievable on
TO-200-type packages. Thermal impedances of approximately 35°C/W are truly realized in multilayer PCB
applications. This allows the TPA0172 to operate at full power into 8-Ω loads at ambient temperatures of 85°C.
AVAILABLE OPTIONS
TA
PACKAGED DEVICE
TSSOP†
(PWP)
−40°C to 85°C
TPA0172PWP
† The PWP package is available taped and reeled. To order a taped and reeled part,
add the suffix R to the part number (e.g., TPA0172PWPR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
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1
SLOS327C − AUGUST 2000 − REVISED MAY 2001
functional block diagram
RHPIN
RLINEIN
R
MUX
64-Step
Volume
Control
−
ROUT+
+
RIN
ADDRESS0
ADDRESS1
I2CVDD
SCL
SDA
PC-BEEP
I2C
CONTROL
+
ROUT−
−
PCBeep
Power
Management
SE/BTL
LHPIN
LLINEIN
MUX
Control
L
MUX
Depop
Circuitry
PVDD
VDD
BYPASS
SHUTDOWN
GND
64-Step
Volume
Control
−
LOUT+
+
LIN
+
LOUT−
−
2
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SLOS327C − AUGUST 2000 − REVISED MAY 2001
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Bit 0 of user-setable portion of device’s I2C address.
Bit 1 of user-setable portion of device’s I2C address.
ADDRESS0
4
I
ADDRESS1
10
I
BYPASS
21
Tap to voltage divider for internal midsupply bias generator.
GND
1, 13
Ground connection for circuitry. Connect to thermal pad
LHPIN
7
I
Left-channel headphone input, selected when SE/BTL is held high, or programmed via I2C.
LIN
5
I
LLINEIN
6
I
Common left input for fully differential input. AC ground for single-ended inputs.
Left-channel line input, selected when SE/BTL is held low, or programmed via I2C.
LOUT+
2
O
Left-channel positive output in BTL mode, and positive output in SE mode.
LOUT−
24
O
Left-channel negative output in BTL mode, and high impedance in SE mode.
PC-BEEP
3
I
The input for PC-BEEP mode which is enabled when a > 1-V (peak-to-peak) square wave is input to this
terminal, when PCB ENABLE is held high, or programmed via I2C. If not used, ground this terminal.
I2CVDD
16
I
The voltage on this terminal sets the trip points for the I2C interface. If the system I2C bus is running at 3.3 V,
then tie this terminal to 3.3 V. If the system I2C bus is running at 5 V, then tie this terminal to 5 V.
PVDD
RHPIN
8, 19
I
Power supply
17
I
Right-channel headphone input, selected when SE/BTL is held high, or programmed via I2C.
RIN
9
I
RLINEIN
18
I
Common right input for fully differential input. AC ground for single-ended inputs.
Right-channel line input, selected when SE/BTL is held low, or programmed via I2C.
ROUT+
12
O
Right-channel positive output in BTL mode, and positive output in SE mode.
ROUT−
14
O
SCL
23
I
Right-channel negative output in BTL mode, and high impedance in SE mode.
I2C clock line
SDA
15
SE/BTL
11
I
Input MUX control input. When this terminal is held high, the LHPIN or RHPIN, and the SE output are
selected. When this terminal is held low, the LLINEIN or RLINEIN, and the BTL output are selected. This
functionality can also be programmed via I2C.
SHUTDOWN
22
I
When held low, this terminal places the device in the shutdown mode, except for the PC-BEEP input and the
I2C bus.
VDD
20
I
Power supply
Serial data line of the I2C bus. Pullup resistor must comply with the I2C standard: minimum value = 3 kΩ,
maximum value = 19 kΩ. Pull up to I2CVDD
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SLOS327C − AUGUST 2000 − REVISED MAY 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Bus voltage, I2CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD 0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . Internally Limited (see Dissipation Rating Table)
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
PWP
TA ≤ 25°C
2.7 W‡
DERATING FACTOR
21.8 mW/°C
TA = 70°C
1.7 W
TA = 85°C
1.4 W
‡ See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(literature number SLMA002), for more information on the PowerPAD package. The thermal data was
measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended
Board for PowerPAD on page 33 of the before mentioned document.
recommended operating conditions
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Supply voltage, VDD
Bus voltage, I2CVDD (see Note1)
SE/BTL
MAX
4.5
5.5
V
3
5.5
V
2
ADDRESS0, ADDRESS1
SDA, SCL
V
3.5
0.7 I2CVDD
SE/BTL
Low-level input voltage, VIL
UNIT
4
SHUTDOWN
High-level input voltage, VIH
MIN
3
SHUTDOWN
0.8
ADDRESS0, ADDRESS1
0.8
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SDA, SCL
0.3 I2CVDD
Operating free-air temperature, TA
−40
NOTE 1: I2CVDD must be less than or equal to VDD.
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85
°C
SLOS327C − AUGUST 2000 − REVISED MAY 2001
electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise
noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured differentially)
PSRR
Power supply rejection ratio
VI = 0 V,
AV = 20 dB
VDD = 4.5 V to 5.5 V
|IIH|
High-level input current
VDD = 5.5 V,
|IIL|
Low-level input current
VDD = 5.5 V,
Zi
IDD
Input impedance
IDD(SD)
Supply current, shutdown mode
MIN
TYP
MAX
UNIT
20
mV
VI = VDD
1
µA
VI = 0 V
1
µA
8
12
mA
PC-BEEP = 0 V
15
35
µA
PC-BEEP = VDD/2
50
90
µA
75
dB
7.5
Supply current
BTL mode
kΩ
operating characteristics, VDD = 5 V, TA = 25°C, RL = 4 Ω, Gain = 20 dB, BTL mode (unless otherwise
noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
PO
THD + N
Output power
THD = 0.08%,
f = 1 kHz
Total harmonic distortion plus noise
f = 20 Hz to 20 kHz
BOM
Maximum output power bandwidth
PO = 1 W,
THD = 1%
Supply ripple rejection ratio
f = 1 kHz,
Noise output voltage
CB = 0.47 µF,
f = 20 Hz to 20 kHz,
Gain = 6 dB BTL, 0 dB SE
Vn
MIN
TYP
MAX
UNIT
2
W
0.3%
>20
F
CB = 0.47 µF
BTL mode
−58
SE mode
−52
BTL mode
29
SE mode
23
kHz
dB
µVRMS
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output power
1, 2, 4, 6
THD+N
Total harmonic distortion plus noise
Vn
Output noise voltage
vs Frequency
7
Supply ripple rejection ratio
vs Frequency
8, 9
Crosstalk
vs Frequency
10, 11
Shutdown attenuation
vs Frequency
vs Frequency
Closed loop response
PO
PD
3, 5,
12
13, 14
Output power
Power dissipation
vs Load resistance
15, 16
vs Output power
17, 18
vs Ambient temperature
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5
SLOS327C − AUGUST 2000 − REVISED MAY 2001
TYPICAL CHARACTERISTICS
10
1
RL = 4 Ω
RL = 8 Ω
0.1
0.01
AV = 20 to 0 dB
f = 1 kHz
Mode = BTL
0.001
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
10
RL = 4 Ω
AV = 20 to 0 dB
Mode = BTL
1
f = 20 kHz
f = 20 Hz
0.1
f = 1 kHz
0.01
1m
10m
100m
1
PO − Output Power − W
PO − Output Power − W
Figure 1
Figure 2
10
RL = 8 Ω
AV = 20 to 0 dB
Mode = BTL
1
PO = 1 W
0.01
0.001
20
100
1k
f − Frequency − Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
0.1
10k 20k
10
RL = 8 Ω
AV = 20 to 0 dB
Mode = BTL
1
f = 20 kHz
f = 20 Hz
0.1
f = 1 kHz
0.01
1m
10m
100m
PO − Output Power − W
Figure 3
6
10
Figure 4
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1
10
SLOS327C − AUGUST 2000 − REVISED MAY 2001
TYPICAL CHARACTERISTICS
10
RL = 32 Ω
AV = 14 to 0 dB
Mode = SE
1
0.1
PO = 75 mW
0.01
0.001
20
100
1k
10k 20k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10
RL = 32 Ω
AV = 14 to 0 dB
Mode = SE
1
f = 20 kHz
0.1
f = 1 kHz
0.01
1m
10m
f − Frequency − Hz
Figure 6
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
VDD = 5 V,
RL = 8 Ω,
Mode = BTL,
Right Channel
60
AV = 20 dB
40
30
20
10
0
10
RL = 8 Ω
CB = 0.47 µF
Mode = BTL
−10
AV = 6 dB
100
1k
f − Frequency − Hz
10 k 20 k
Supply Ripple Rejection Ratio − dB
V n − Output Noise Voltage − µ V RMS
80
50
100m 200m 500m
PO − Output Power − W
Figure 5
70
f = 20 Hz
−20
−30
AV = 20 dB
−40
−50
−60
−70
−80
AV = 6 dB
−90
−100
20
Figure 7
100
1k
f − Frequency − Hz
10k 20k
Figure 8
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SLOS327C − AUGUST 2000 − REVISED MAY 2001
TYPICAL CHARACTERISTICS
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
−20
PO = 1 W
RL = 8 Ω
AV = 20 dB
Mode = BTL
−20
−40
−30
Crosstalk − dB
Supply Ripple Rejection Ratio − dB
−10
0
RL = 32 Ω
CB = 0.47 µF
Mode = SE
−40
AV = 6 dB
−50
−60
−70
−60
−80
Left to Right
−100
−80
AV = 14 dB
Right to Left
−120
−90
−100
20
−140
100
1k
f − Frequency − Hz
10k 20k
20
100
Figure 9
10k
20k
Figure 10
CROSSTALK
vs
FREQUENCY
SHUTDOWN ATTENUATION
vs
FREQUENCY
0
0
PO = 1 W
RL = 8 Ω
AV = 6 dB
Mode = BTL
−20
Shutdown Attenuation − dB
−20
−40
Crosstalk − dB
1k
f − Frequency − Hz
−60
−80
−100
Left to Right
VI = 100 mVRMS
RL = 8 Ω,
Mode = BTL
−40
−60
−80
−100
−120
Right to Left
−140
20
100
1k
f − Frequency − Hz
10k
20k
−120
20
Figure 11
8
100
1k
f − Frequency − Hz
Figure 12
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• DALLAS, TEXAS 75265
10k 20k
SLOS327C − AUGUST 2000 − REVISED MAY 2001
TYPICAL CHARACTERISTICS
CLOSED LOOP RESPONSE
30
180
20
Gain
90
0
Phase
−10
0
Phase
Gain − dB
10
−20
−30
−40
−50
10
VDD = 5 V,
RL = 8 Ω,
Mode = BTL,
AV = 20 dB
100
−90
1k
10k
100k
−180
1M
f − Frequency − Hz
Figure 13
CLOSED LOOP RESPONSE
180°
30
20
Gain
90°
0
Phase
0°
−10
Phase
Gain − dB
10
−20
−30
−40
−50
10
VDD = 5 V,
RL = 32 Ω,
Mode = SE,
AV = 14 dB
−90°
−180°
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 14
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SLOS327C − AUGUST 2000 − REVISED MAY 2001
TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
1
3
THD+N = 1%
AV = +20 to 0 dB
Mode = BTL
0.8
PO − Output Power − W
PO − Output Power − W
2.5
THD+N = 1%
AV = +20 to 0 dB
Mode = SE
0.9
2
1.5
1
0.7
0.6
0.5
0.4
0.3
0.2
0.5
0.1
0
0
8
16
24
32
40
48
RL − Load Resistance − Ω
56
0
64
0
8
Figure 15
0.4
3Ω
1.6
0.35
1.4
PD − Power Dissipation − W
PD − Power Dissipation − W
64
POWER DISSIPATION
vs
OUTPUT POWER
1.8
4Ω
1.2
1
0.8
0.6
8Ω
0.4
0.5
1
1.5
PO − Output Power − W
2
4Ω
0.3
0.25
0.2
8Ω
0.15
0.1
32 Ω
f = 1 kHz
Mode = BTL
Each Channel
0.2
f = 1 kHz
Mode = SE
Each Channel
0.05
2.5
0
0
0.1
Figure 17
10
56
Figure 16
POWER DISSIPATION
vs
OUTPUT POWER
0
0
16
24
32
40
48
RL − Load Resistance − Ω
0.3
0.2
0.4
0.5
0.6
PO − Output Power − W
Figure 18
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0.7
0.8
SLOS327C − AUGUST 2000 − REVISED MAY 2001
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
AMBIENT TEMPERATURE
7
ΘJA1 = 45.9°C/W
ΘJA2 = 45.2°C/W
ΘJA3 = 31.2°C/W
ΘJA4 = 18.6°C/W
ΘJA4
PD − Power Dissipation − W
6
5
4
ΘJA3
3
ΘJA1,2
2
1
0
−40 −20
20 40 60 80 100 120 140 160
0
TA − Ambient Temperature − °C
Figure 19
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SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
selection of components
Figure 20 and Figure 21 are schematic diagrams of typical notebook computer application circuits.
Right CIRHP
Head− 0.47 µF
phone
Input
17 RHPIN
Signal
CIRLINE
R
Right 0.47 µF
MUX
18
RLINEIN
Line
Input
9 RIN
Signal
CRIN
0.47 µF
PC-BEEP
Input
Signal CPCB
0.47 µF
3 PC-BEEP
11 SE/BTL
I2C Address
To I2C Bus
I2C
Bus Voltage
Left CILHP
Head− 0.47 µF
phone
Input
Signal
CILLINE
Left 0.47 µF
Line
Input
Signal
4
A0
10
A1
15
23
SDA
SCL
16
I2CVDD
7
6
5
64-Step
Volume
Control
−
+
ROUT+
12
−
+
ROUT−
14
PCBeep
PVDD
MUX
Control
PVDD
VDD
19
Control
Depop
Circuitry
Power
Management
VDD
20
BYPASS
SHUTDOWN
21
VDD
CSR
0.1 µF
VDD
CSR
0.1 µF
22
−
+
LOUT+
−
+
LOUT−
24
64-Step
Volume
Control
1 kΩ
100 kΩ
CBYP
0.47 µF
To
System
Control
1,13
2
GND
VDD
See Note A
10 µF
I2C
L
MUX
8
10 µF
LHPIN
LLINEIN
COUTR
330 µF
1 kΩ
COUTR
330 µF
LIN
CLIN
0.47 µF
100 kΩ
NOTE A: A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger
electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 20. Typical TPA0172 Application Circuit Using Single-Ended Inputs and Input MUX
12
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selection of components (continued)
CRHP−
0.47 µF
17
CRLINE−
Right
0.47 µF
Negative
18
Differential
Input Signal
CRIN+
Right
0.47 µF
Positive
9
Differential
Input Signal
PC-BEEP
Input Signal C
PCB
0.47 µF
3
RHPIN
R
MUX
RLINEIN
I2C Address
I2C Bus Voltage
CLHP−
0.47 µF
15
23
4
10
16
7
Left
Negative
Differential
Input
CLLINE−
Signal
0.47 µF
PC-BEEP
CLIN+
Left
0.47 µF
Positive
Differential
Input Signal
5
ROUT+
12
−
+
ROUT−
PVDD
14
SDA
SCL
A0
A1
I2CVDD
PCBeep
10 µF
VDD
VDD
1 kΩ
100 kΩ
PVDD
19
See Note A
10 µF
Depop
Circuitry
I2C
Control
VDD
CSR
0.1 µF
VDD
20
VDD
BYPASS
SHUTDOWN
21
CSR
0.1 µF
Power
Management
22
−
+
LOUT+
CBYP
To
0.47 µF
System
Control
1,13
2
−
+
LOUT−
24
LHPIN
LLINEIN
COUTR
330 µF
8
MUX
Control
L
MUX
6
−
+
RIN
11 SE/BTL
To I2C Bus
64-Step
Volume
Control
GND
64-Step
Volume
Control
1 kΩ
COUTR
330 µF
LIN
100 kΩ
NOTE A: A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger
electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 21. Typical TPA0172 Application Circuit Using Differential Inputs
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APPLICATION INFORMATION
input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB
or cutoff frequency will also change by over six times.
Rf
C
Input Signal
RI
IN
The −3-dB frequency can be calculated using equation 1.
f
–3 dB
+
1
2p CR I
(1)
input capacitor, CI
In the typical application an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in equation 2.
−3 dB
f c(highpass) +
(2)
1
2 pZ I C I
fc
The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where ZI is 710 kΩ and the specification calls for a flat-bass response down to 45 Hz.
Equation 2 is reconfigured as equation 3.
1
C +
I
2p Z f c
I
14
(3)
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input capacitor, CI (continued)
In this example, CI is 0.47 µF so one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (CI) and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
power supply decoupling, CS
The TPA0172 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device VDD lead works best. For
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier is recommended.
midrail bypass capacitor, CBYP
The midrail bypass capacitor (CBYP) is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply which is caused by coupling into the output drive
signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as degraded
PSRR and THD+N.
Bypass capacitor (CBYP) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended
for the best THD and noise performance.
output coupling capacitor, CC
In the typical single-supply SE configuration, an output coupling capacitor (CC) is required to block the dc bias
at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the
output coupling capacitor and impedance of the load form a high-pass filter governed by equation 4.
−3 dB
f c(high) +
1
2 pR L C C
(4)
fc
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives
the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low
frequencies into the load. Consider the example where a CC of 330 µF is chosen and loads vary from 3 Ω,
4 Ω, 8 Ω, 32 Ω, 10 kΩ, and 47 kΩ. Table 1 summarizes the frequency response characteristics of each
configuration.
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output coupling capacitor, CC (continued)
Table 1. Common Load Impedances vs Low Frequency Output Characteristics in SE Mode
RL
CC
LOWEST FREQUENCY
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
32 Ω
330 µF
Ą15 Hz
10,000 Ω
330 µF
0.05 Hz
47,000 Ω
330 µF
0.01 Hz
As Table 1 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate,
headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
bridged-tied load versus single-ended mode
Figure 22 shows a linear audio power amplifier (APA) in a bridged-tied load (BTL) configuration. The TPA0172
BTL amplifier consists of two class-AB amplifiers driving both ends of the load. There are several potential
benefits to this differential drive configuration, but initially consider power to the load. The differential drive to
the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect
doubles the voltage swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the
power equation, where voltage is squared, yields 4× the output power from the same supply rail and load
impedance (see equation 5).
V
V
(rms)
+
V
Power +
16
O(PP)
2 Ǹ2
(5)
2
(rms)
R
L
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bridged-tied load versus single-ended mode (continued)
VDD
VO(PP)
2x VO(PP)
RL
VDD
−VO(PP)
Figure 22. Bridge-Tied Load Configuration
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement —
which is loudness that can be heard. In addition to increased power, there are frequency response concerns.
Consider the single-supply SE configuration shown in Figure 23. A coupling capacitor is required to block the
dc offset voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF),
so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting
low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network
created with the speaker impedance and the coupling capacitance and is calculated using equation 6.
fc +
1
2 pR L C C
(6)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
VDD
−3 dB
VO(PP)
CC
RL
VO(PP)
fc
Figure 23. Single-Ended Configuration and Frequency Response
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bridged-tied load versus single-ended mode (continued)
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal
considerations section.
single-ended operation
In SE mode, the load is driven from the primary amplifier output for each channel (OUT+, terminals 2 and 12).
The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative
outputs in a high-impedance state and reduces the amplifier’s gain to 1 V/V.
BTL amplifier efficiency
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage
drop that varies inversely to output power. The second component is due to the sinewave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the RMS value of the supply current (IDDrms) determines the internal power
dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 24).
IDD
VO
IDD(avg)
V(LRMS)
Figure 24. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
Efficiency of a BTL amplifier +
Where:
PL +
and
18
P
SUP
V L rms 2
RL
+ V
PL
(7)
P SUP
2
V
V
, and V LRMS + P , therefore, P L + P
Ǹ2
2 RL
avg and I avg + 1
p
DD DD
DD
I
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R
L
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APPLICATION INFORMATION
BTL amplifier efficiency (continued)
Therefore,
P SUP +
2 V DD V P
p RL
substituting PL and PSUP into equation 7,
2
Efficiency of a BTL amplifier +
Where:
VP +
VP
2 RL
2 V DD V P
p RL
+
p VP
4 V DD
Ǹ2 PL RL
Therefore,
h BTL +
p
Ǹ2 PL RL
(8)
4 V DD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
Table 2 employs equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting
in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at
full output power is less than in the half power range. Calculating the efficiency for a specific system is the key
to proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, the maximum
draw on the power supply is almost 3.25 W.
Table 2. Efficiency vs Output Power in 5-V, 8-Ω BTL Systems
OUTPUT POWER
(W)
EFFICIENCY
(%)
PEAK VOLTAGE
(V)
INTERNAL DISSIPATION
(W)
0.25
0.5
31.4
2
0.55
44.4
2.83
1
0.62
62.8
4
0.59
4.47†
0.53
1.25
70.2
† High peak voltages cause the THD to increase.
A final point to remember about class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to the utmost advantage when possible. Note that in equation 8, VDD is in the denominator.
This indicates that as VDD goes down, efficiency goes up.
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APPLICATION INFORMATION
crest factor and thermal considerations
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power
output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest
factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. When the TPA0172 is operating from a 5-V
supply into a 3-Ω speaker, 4-W peaks are available. To convert watts to dB use equation 9.
P dB + 10Log
ǒ Ǔ
PW
P ref
ǒ Ǔ
+ 10Log 4W + 6 dB
1W
(9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
6 dB − 15 dB = −9 dB (15-dB crest factor)
6 dB − 12 dB = −6 dB (12-dB crest factor)
6 dB − 9 dB = −3 dB (9-dB crest factor)
6 dB − 6 dB = 0 dB (6-dB crest factor)
6 dB − 3 dB = 3 dB (3-dB crest factor)
To convert dB back to watts use equation 10.
P W + 10 PdBń10
P ref
(10)
+ 63 mW (18-dB crest factor)
+ 125 mW (15-dB crest factor)
+ 250 mW (12-dB crest factor)
+ 500 mW (9-dB crest factor)
+ 1000 mW (6-dB crest factor)
+ 2000 mW (3-dB crest factor)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the absolute worst case, which is 2 W of continuous power output with a 3-dB crest
factor, against 12-dB and 15-dB applications drastically affects maximum ambient temperature ratings for the
system. Using the power dissipation curves for a 5-V, 3-Ω system, the internal dissipation in the TPA0172 and
maximum ambient temperatures are shown in Table 3.
Table 3. TPA0172 Power Rating, 5-V, 3-Ω Stereo
20
PEAK OUTPUT POWER
(W)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
4
2 W (3 dB)
1.7
4
1000 mW (6 dB)
1.6
6°C
4
500 mW (9 dB)
1.4
24°C
4
250 mW (12 dB)
1.1
51°C
4
125 mW (15 dB)
0.8
78°C
4
63 mW (18 dB)
0.6
96°C
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SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
crest factor and thermal considerations (continued)
Table 4. TPA0172 Power Rating, 5-V, 8-Ω Stereo
PEAK OUTPUT POWER
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE
2.5 W
1250 mW (3-dB crest factor)
0.55
100°C
2.5 W
1000 mW (4-dB crest factor)
0.62
94°C
2.5 W
500 mW (7-dB crest factor)
0.59
97°C
2.5 W
250 mW (10-dB crest factor)
0.53
102°C
The maximum dissipated power (PD(max)) is reached at a much lower output power level for an 8-Ω load than
for a 3-Ω load. As a result, use equation 11 for calculating PD(max) for an 8-Ω application.
P D(max) +
2V 2
DD
(11)
p 2R L
However, in the case of a 3-Ω load, the PD(max) occurs at a point well above the normal operating power level.
The amplifier may therefore be operated at a higher ambient temperature than required by the PD(max) formula
for a 3-Ω load.
The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor
for the PWP package is shown in the dissipation rating table. To convert this to ΘJA use equation 12.
Θ JA +
1
1
+
0.022
Derating Factor
+ 45°CńW
(12)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are
per channel so the dissipated power needs to be doubled for two channel operation. Given the maximum
allowable junction temperature (ΘJA) and the total internal dissipation, the maximum ambient temperature can
be calculated using equation 13. The maximum recommended junction temperature for the TPA0172 is 150°C.
The internal dissipation figures are taken from the power dissipation vs output power graphs.
T A Max + T J Max * Θ JA P D
+ 150 * 45 (0.6 2) + 96°C (15-dB crest factor)
(13)
NOTE:
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per channel.
Tables 3 and 4 show that for some applications no airflow is required to keep junction temperatures in the
specified range. The TPA0172 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Tables 3 and 4 were calculated for maximum
listening volume without distortion. When the output level is reduced, the numbers in the table change
significantly. Also, using 8-Ω speakers significantly increases the thermal performance by increasing amplifier
efficiency.
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APPLICATION INFORMATION
SE/BTL operation
The ability of the TPA0172 to easily switch between BTL and SE modes is one of its most important cost saving
features. This feature eliminates the requirement for an additional headphone amplifier in applications where
internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated.
Internal to the TPA0172, two separate amplifiers drive OUT+ and OUT−. The SE/BTL input controls the
operation of the follower amplifier that drives LOUT− and ROUT−. When SE/BTL is held low, the amplifier is
on and the TPA0172 is in the BTL mode. When SE/BTL is held high, the OUT− amplifiers are in a high output
impedance state, which configures the TPA0172 as an SE driver for LOUT+ and ROUT+. IDD is reduced by
approximately one-half in SE mode. Control of the SE/BTL input can be from a logic-level CMOS source (see
recommended operating conditions for levels) or, more typically, from a resistor divider network as shown in
Figure 25.
The SE/BTL pin also selects the audio input and gain registers. When SE/BTL is held low, the RLINEIN input
is selected and the BTL gain register values are used to set the gain of the input signal. When SE/BTL is held
high, the RHPIN input is selected and the SE gain register values are used to set the gain. Table 5 shows the
operation of the SE/BTL input pin in selecting different modes of operation.
Table 5. SE/BTL Operation
SE/BTL
INPUT
GAIN REGISTER
OUTPUT
Low
Line
BTL
BTL
High
Headphone
SE
SE
The external SE/BTL pin may also be disabled and its function controlled through the I2C interface. Refer to the
I2C interface section.
17
RHPIN
18
RLINEIN
R
MUX
−
+
9
ROUT+
12
RIN
COUTR
330 µF
−
+
ROUT−
VDD
14
1 kΩ
100 kΩ
SE/BTL
11
100 kΩ
Figure 25. TPA0172 Resistor Divider Network Circuit
22
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APPLICATION INFORMATION
SE/BTL operation (continued)
Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When
closed, the 100-kΩ/1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ resistor is
disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT− amplifier is shut down
causing the speaker to mute (virtually open-circuits the speaker). The OUT+ amplifier then drives through the
output capacitor (CO) into the headphone jack.
PC-BEEP operation
The PC-BEEP input allows a system beep to be sent directly from a computer through the amplifier to the
speakers with few external components. The input is normally activated automatically but may be selected
manually through the I2C interface. Refer to the I2C interface section. When the PC-BEEP input is active, both
of the LINEIN and HPIN inputs are deselected and both the left and right channels are driven in BTL mode with
the signal from PC-BEEP. The gain from the PC-BEEP input to the speakers is fixed at 0.3 V/V and is
independent of the volume setting. When the PC-BEEP input is deselected, the amplifier will return to the
previous operating mode and volume setting. Furthermore, if the amplifier is in shutdown mode, activating
PC-BEEP will take the device out of shutdown and output the PC-BEEP signal, and then return the amplifier
to shutdown mode.
In auto-detect mode, the amplifier will automatically switch to PC-BEEP mode after detecting a valid signal at
the PC-BEEP input. The preferred input signal is a square wave or pulse train with an amplitude of 1 Vpp or
greater. To be accurately detected, the signal must have a minimum of 1-Vpp amplitude, rise and fall times of
less than 0.1 µs, and a minimum of eight rising edges. When the signal is no longer detected, the amplifier will
return to its previous operating mode and volume setting.
When manually selected, the PC-BEEP input is selected, and the LINEIN and HPIN inputs are deactivated
regardless of the input signal.
If it is desired to ac couple the PC-BEEP input, the value of the coupling capacitor should be chosen to satisfy
the following equation:
C PCB w
1
2p f PCB (100 kW)
(14)
The PC-BEEP input can also be dc coupled to avoid using this coupling capacitor. The pin normally sits at midrail
when no signal is present.
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shutdown modes
The TPA0172 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal
should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the
outputs to mute and the amplifier to enter a low-current state (IDD = 15 µA). SHUTDOWN should never be left
unconnected because amplifier operation would be unpredictable.
The external SHUTDOWN pin may also be disabled and its function controlled through the I2C interface. Refer
to the I2C interface section.
I2C interface
The I2C interface is used to access the internal registers of the TPA0172. This two pin interface consists of one
clock line (SCL) and one serial data line (SDA). The basic I2C access cycles are shown in Figure 26.
The basic access cycle consists of the following:
D
D
D
D
A start condition
A slave address cycle
Any number of data cycles
A stop condition
SDA
SCL
Start Condition (S)
Stop Condition (P)
Figure 26. I2C Start and Stop Conditions
The start and stop conditions are shown in Figure 26. The high-to-low transition of SDA while SCL is high,
defines the start condition. The low-to-high transition of SDA while SCL is high, defines the stop condition. Each
cycle, data, or address consists of 8 bits of serial data followed by one acknowledge bit generated by the
receiving device. Thus, each data/address cycle contains nine bits as shown in Figure 27.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
MSB
Stop
Acknowledge
Acknowledge
Slave Address
Data
Figure 27. I2C Access Cycles
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
As indicated in Figure 27, following a start condition, each I2C device decodes the slave address. The TPA0172
responds with an acknowledge by pulling the SDA line low during the ninth clock cycle, if it decodes the address
as its address.
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle
so that the receiving device may drive the SDA signal low. After each byte transfer following the address byte,
the receiving device will pull the SDA line low for one SCL clock cycle. A stop condition will be initiated by the
transmitting device after the last byte is transferred. An example of a write cycle can be found in Figure 28 and
Figure 29.
During a read cycle, the slave receiver will acknowledge the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 30 and Figure 31.
From Receiver
S
Slave Address
W
A
Data
A
Data
A
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
P
From Transmitter
Figure 28. I2C Write Cycle
Acknowledge
(From Receiver)
Start
Condition
A6
SDA
A5
A1
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Acknowledge
(Receiver)
Acknowledge
(Receiver)
D6
D1
D0 ACK
First Data Byte
D7
D6
D1
D0 ACK
Last Data Byte
Other
Data Bytes
Stop
Condition
Figure 29. Multiple Byte Write Transfer
S
Slave Address
R
A
Data
A
Data
A
P
Transmitter
Receiver
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
Figure 30. I2C Read Cycle
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
Start
Condition
Acknowledge
(From
Receiver)
A6
SDA
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Acknowledge
(From
Transmitter)
D0 ACK
First Data
Byte
Not
Acknowledge
(Transmitter)
D7
D6
D1
D0 ACK
Stop
Condition
Other Last Data Byte
Data Bytes
Figure 31. Multiple Byte Read Transfer
timing characteristics for I2C interface
STANDARD
MODE
PARAMETER
MIN
MAX
100
FAST MODE
MIN
MAX
0
400
UNITS
fSCL
tw(H)
Clock frequency, SCL
0
Pulse duration, SCL high
4
0.6
µs
tw(L)
tr
Pulse duration, SCL low
4.7
1.3
µs
Rise time, SCL and SDA
1000
300
ns
tf
tsu(1)
Fall time, SCL and SDA
300
300
ns
th(1)
t(buf)
Hold time, SCL to SDA
Setup time, SDA to SCL
kHz
250
100
0
0
ns
Bus free time between stop and start condition
4.7
1.3
µs
tsu(2)
th(2)
Setup time, SCL to start condition
4.7
0.6
µs
Hold time, start condition to SCL
4
0.6
µs
tsu(3)
Setup time, SCL to stop condition
4
0.6
µs
tw(H)
tw(L)
tr
tf
SCL
tsu(1)
th(1)
SDA
Figure 32. SCL and SDA Timing
SCL
tsu(2)
th(2)
tsu(3)
t(buf)
SDA
Start Condition
Stop Condition
Figure 33. Start and Stop Conditions
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
I2C operation specific to the TPA0172 device
The TPA0172 operates using only a multiple byte transfer protocol as shown in Figures 29 and 31. The six
internal registers and the functionality of each can be found in Table 6. When writing to the device, all 6 bytes
corresponding to all six registers must be sent to the device in a single multiple byte transfer. During a read cycle,
the TPA0172 will send 6 bytes in a single transfer to the master device requesting the information.
Table 6. Internal Registers
REGISTER NAME
POWER-UP/RESET VALUE
(b7b6b5…b0)
BIT ASSIGNMENT
Right Gain Register 1
(BTL Gain Register)
0011 1111
0−5: Gain level
6: Mute
7: Mute
Left Gain Register 1
(BTL Gain Register)
0011 1111
0−5: Gain level
6: Mute
7: Mute
Right Gain Register 2
(SE Gain Register)
0011 1111
0−5: Gain level
6: Mute
7: Mute
Left Gain Register 2
(SE Gain Register)
0011 1111
0−5: Gain level
6: Mute
7: Mute
1111 1111
0: Disable internal SHUTDOWN control
1: Disable internal SE/BTL control
2: Disable internal PC-BEEP control
3−6: Unused
7: Powering-up indicator (read-only)
0000 0000
0: SHUTDOWN
1: HP/LINE
2: Reserved
3: Mute
4: Reserved
5: SE/BTL
6: Gain register select
7: PC-BEEP
Mask Register
Control Register
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
slave address
The slave address for the TPA0172 consists of 7 bits of address information along with 1 bit, the LSB, reserved
for read/write information. There are eight possible addresses (including the read/write bit) for this device that
can be selected with the external A1 and A0 address pins. The most significant 5 bits of the address are fixed.
Table 7 lists the possible addresses for the TPA0172.
Table 7. Valid Slave Addresses
SELECTABLE WITH
ADDRESS PINS
FIXED ADDRESS
READ/WRITE
BIT
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
(A1)
BIT 1
(A0)
BIT 0
(R/W)
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
gain register operation
The gain of the TPA0172 ranges from 20 dB to −60 dB in 64 1.25-dB steps. At power-up, both the right and left
channels are set at −60 dB. The truth table shown in Table 8 gives examples of valid values that may be read
from or written to the four gain setting registers. Note that the amplifier is muted if either bit 7 or bit 6 is set.
Furthermore, to avoid any unwanted clicks or pops, the gain settings should not be changed until the amplifier
has completed the power-up sequence, which can be determined by monitoring bit 7 of the mask register. When
the bit goes to 0, the power-up sequence is complete.
Table 8. Gain Settings Truth Table
28
GAIN (dB)
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
20
0
0
0
0
0
0
0
0
18.75
0
0
0
0
0
0
0
1
17.5
0
0
0
0
0
0
1
0
16.25
0
0
0
0
0
0
1
1
…
…
…
…
…
…
…
…
…
−57.5
0
0
1
1
1
1
0
1
−58.75
0
0
1
1
1
1
1
0
−60
0
0
1
1
1
1
1
1
−85 (mute)
1
1
X
X
X
X
X
X
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLOS327C − AUGUST 2000 − REVISED MAY 2001
APPLICATION INFORMATION
mask register operation
The mask register allows the user to select whether SHUTDOWN, SE/BTL, and PC-BEEP are to be controlled
by the external pins or by the internal control register. Since PC-BEEP does not have an external control pin
available, writing a 1 to this bit will disable all internal register control and place the PC-BEEP input in auto-detect
mode. When a bit is set, the corresponding internal control register bit is masked or ignored and the external
pin controls the operating mode. Conversely, when a bit is set to 0, the corresponding external pin is disabled
and the internal control register bit determines the operating mode. For example, writing XXXXX010 to the
register allows the control register to control the operation of the PC-BEEP input and SHUTDOWN, while
allowing the external pin to control SE/BTL.
The MSB of the mask register is read-only. It is set when the TPA0172 is executing its power-up sequence and
is set to 0 upon completion of the sequence and during normal operation. To avoid any unwanted clicks or pops,
the gain registers should not be changed while this bit is set.
control register operation
Each bit of the control register allows the user to control the operating mode of the TPA0172, as shown in
Table 9.
Table 9. Control Register Bit Assignments
BIT
FUNCTION
VALUE
RESULT
0
SHUTDOWN
0
1
Normal operation
Shutdown mode
1
HP/LINE
0
1
Line inputs selected
Headphone inputs selected
2
Reserved
0
3
Mute
0
1
4
Reserved
1
5
SE/BTL
0
1
BTL mode
SE mode
6
Gain register select
0
1
Use BTL gain registers
Use SE gain registers
7
PC-BEEP enable
0
1
Auto-detect PC-BEEP
PC-BEEP always on
Normal operation
Mute mode
Bit 0 operates in the same manner as the external SHUTDOWN pin, but the logic is active high in the internal
register.
Bit 1 allows the user to select the input source. If bit 1 of the mask register is set, however, the HP/LINE function
is tied to the external SE/BTL pin.
Bit 2 should always be set to 0. Reserved for future functionality.
Bit 3 performs the same mute function as setting either bit 6 or 7 in the gain registers.
Bit 4 should always be set to 1. Reserved for future functionality.
Bit 5 operates in the same manner as the external SE/BTL pin.
Bit 6 allows the user to select which gain registers will determine the gain settings for each channel. For example,
the amplifier may be configured to operate in SE mode, but with the gain settings taken from the BTL registers.
This function is tied to the SE/BTL pin if bit 1 of the mask register is set, which results in the SE gain registers
controlling the gain in SE mode, and the BTL registers controlling the gain in BTL mode.
Bit 7 allows the user to either auto-detect a signal at the PC-BEEP input or manually override that input to always
be on.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA0172PWP
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA0172
TPA0172PWPR
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA0172
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA0172PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA0172PWPR
HTSSOP
PWP
24
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 24
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
4.4 x 7.6, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
SCALE 2.200
PLASTIC SMALL OUTLINE
6.6
TYP
6.2
PIN 1 ID
AREA
A
SEATING PLANE
0.1 C
22X 0.65
24
1
C
2X
7.15
7.9
7.7
NOTE 3
12
B
13
24X
4.5
4.3
0.30
0.19
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
(1)
2.40
1.65
DETAIL A
TYPICAL
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
( 0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
BASED ON
0.125 THICK
STENCIL
SYMM
22X (0.65)
13
12
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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