Texas Instruments | Series Input 16-Bit Monolithic Digital-to-Analog Converter | Datasheet | Texas Instruments Series Input 16-Bit Monolithic Digital-to-Analog Converter Datasheet

Texas Instruments Series Input 16-Bit Monolithic Digital-to-Analog Converter Datasheet
®
PCM56P
PCM56U
DESIGNED FOR AUDIO
Serial Input 16-Bit Monolithic
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● SERIAL INPUT
● –92dB MAX THD: FS Input, K Grade
● –74dB MAX THD: –20dB Input, K Grade
●
●
●
●
●
●
●
●
●
●
96dB DYNAMIC RANGE
NO EXTERNAL COMPONENTS REQUIRED
16-BIT RESOLUTION
15-BIT MONOTONICITY, TYP
0.001% OF FSR TYP DIFFERENTIAL
LINEARITY ERROR
1.5µs SETTLING TIME, TYP: Voltage Out
±3V OR ±1mA AUDIO OUTPUT
EIAJ STC-007-COMPATIBLE
OPERATES ON ±5V TO ±12V SUPPLIES
PINOUT ALLOWS IOUT OPTION
● PLASTIC DIP OR SOIC PACKAGE
This converter is completely self-contained with a
stable, low noise, internal zener voltage reference;
high speed current switches; a resistor ladder network; and a fast settling, low noise output operational
amplifier all on a single monolithic chip. The
converters are operated using two power supplies that
can range from ±5V to ±12V. Power dissipation with
±5V supplies is typically less than 200mW. Also
included is a provision for external adjustment of the
MSB error (differential linearity error at bipolar zero)
to further improve total harmonic distortion (THD)
specifications if desired. Few external components
are necessary for operation, and all critical
specifications are 100% tested. This helps assure the
user of high system reliability and outstanding overall
system performance.
The PCM56 is packaged in a high-quality 16-pin
molded plastic DIP package or SOIC and has passed
operating life tests under simultaneous high-pressure,
high-temperature, and high-humidity conditions.
DESCRIPTION
RF
The PCM56 is a state-of-the-art, fully monotonic,
digital-to-analog converter that is designed and
specified for digital audio applications. This device
employs ultra-stable nichrome (NiCr) thin-film
resistors to provide monotonicity, low distortion, and
low differential linearity error (especially around
bipolar zero) over long periods of time and over the
full operating temperature.
Reference
16-Bit
IOUT DAC
Audio
Output
16-Bit Input Latch
16-Bit Serial-to-Parallel Conversion
Clock LE Data
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
SBAS149
1987 Burr-Brown Corporation
PDS-700D
Printed in U.S.A. August, 1993
SPECIFICATIONS
ELECTRICAL
Typical at +25°C, and nominal power supply voltages ±5V, unless otherwise noted.
PCM56U, PCM56P-J, -K
PARAMETER
MIN
DIGITAL INPUT
Resolution
Digital Inputs(1): VIH
VIL
IIH, VIN = +2.7V
IIL, VIN = +0.4V
Input Clock Frequency
TYP
MAX
UNITS
+VL
+0.8
+1.0
–50
Bits
V
V
µA
µA
MHz
16
+2.4
0
10.0
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
Bipolar Zero Error
Differential Linearity Error
Noise (rms, 20Hz to 20kHz) at Bipolar Zero (VOUT models)
±2.0
±30
±0.001
6
%
mV
% of FSR(2)
µV
TOTAL HARMONIC DISTORTION
VO = ±FS at f = 991Hz: PCM56P-K
PCM56P-J
PCM56P, PCM56U
PCM56P-L
VO = –20dB at f = 991Hz: PCM56P-K
PCM56P-J
PCM56P, PCM56U
PCM56P-L
VO = –60dB at f = 991Hz: PCM56P-K
PCM56P-J
PCM56P, PCM56U
PCM56P-L
–94
–94
–94
–94
–75
–75
–75
–75
–35
–35
–35
–35
MONOTONICITY
15
Bits
DRIFT (0°C to +70°C)
Total Drift(3)
Bipolar Zero Drift
±25
±4
ppm of FSR/°C
ppm of FSR/°C
SETTLING TIME (to ±0.006% of FSR)
Voltage Output: 6V Step
1LSB
Slew Rate
Current Output, 1mA Step: 10Ω to 100Ω Load
1kΩ Load(4)
1.5
1.0
10
350
350
µs
µs
V/µs
ns
ns
WARM-UP TIME
–92
–88
–82
–80
–74
–68
–68
–60
–34
–28
–28
–20
1
OUTPUT
Voltage Output Configuration: Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration:
Bipolar Range (±30%)
Output Impedance (±30%)
±2.0
POWER SUPPLY REQUIREMENTS(5)
Voltage: +VS and +VL
–VS and –VL
Supply Drain (No Load): +V (+VS and +VL = +5V)
–V (–VS and –VL = –5V)
+V (+VS and +VL = +12V)
–V (–VS and –VL = –12V)
Power Dissipation: VS and VL = ±5V
VS and VL = ±12V
+4.75
–4.75
TEMPERATURE RANGE
Specification
Operation
Storage
0
–25
–60
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Min
±3.0
0.10
V
mA
Ω
Indefinite to Common
±1.0
1.2
mA
kΩ
+5.00
–5.00
+10.00
–25.0
+12.0
–27.0
175
468
+13.2
–13.2
+17.0
–35.0
260
+70
+70
+100
V
V
mA
mA
mA
mA
mW
mW
°C
°C
°C
NOTES: (1) Logic input levels are TTL/CMOS-compatible. (2) FSR means full-scale range and is equivalent to 6V (±3V) for PCM56 in the VOUT mode. (3) This is the
combined drift error due to gain, offset, and linearity over temperature. (4) Measured with an active clamp to provide a low impedance for approximately 200ns. (5) All
specifications assume +VS connected to +VL and –VS connected to –VL. If supplies are connected separately, –VL must not be more negative than –VS supply voltage
to assure proper operation. No similar restriction applies to the value of +VL with respect to +VS.
®
PCM56
2
PACKAGE INFORMATION
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages ...................................................................... ±16VDC
Input Logic Voltage ............................................................ –1V to +VS/+VL
Power Dissipation .......................................................................... 850mW
Operating Temperature ..................................................... –25°C to +70°C
Storage Temperature ...................................................... –60°C to +100°C
Lead Temperature (soldering, 10s) ................................................ +300°C
MODEL
PCM56U
PCM56P
PCM56P-J
PCM56P-K
PCM56P-L
PACKAGE
PACKAGE DRAWING
NUMBER(1)
16-Pin SOIC
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Plastic DIP
211
180
180
180
180
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
PIN ASSIGNMENTS
PIN
DESCRIPTION
MNEMONIC
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
Analog Negative Supply
Logic Common
Logic Positive Supply
No Connection
Clock Input
Latch Enable Input
Serial Data Input
Logic Negative Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Common
Current Output
MSB Adjustment Terminal
MSB Trim-pot Terminal
Analog Positive Supply
–VS
LOG COM
+VL
NC
CLK
LE
DATA
–VL
VOUT
RF
SJ
ANA COM
IOUT
MSB ADJ
TRIM
+VS
CONNECTION DIAGRAM
–5V
1µF
–VS
Logic
Common
1
16
1µF
15 Trim(1)
2
+5V
+VL
3
1µF
–5V
16-Bit
IOUT
DAC
16-Bit Serial
to Parallel
Conversion
14 MSB Adjust(1)
NC
4
13
CLK
5
12
LE
6
Data
7
–VL
+5V
–VS
16-Bit
DAC Latch
Control
Logic and
Level
Shifting
Circuit
11
10
IOUT
Analog
Common
SJ
RF
Analog
Output
9
8
VOUT
(±3.0V)
1µF
NOTE: (1) MSB error (Bipolar Zero differential linearity error)
can be adjusted to zero using the external circuit shown in Figure 6.
®
3
PCM56
DISCUSSION OF
SPECIFICATIONS
All Bits On
0111...1111
Gain
Drift
0111...1110
The PCM56 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for D/A converter in audio applications are
Total Harmonic Distortion, Differential Linearity Error,
Bipolar Zero Error, parameter shifts with time and
temperature, and settling time effects on accuracy.
Digital Input
0000...0010
The PCM56 is factory-trimmed and tested for all critical key
specifications.
0000...0001
0000...0000
Offset
Drift
1111...1111
Bipolar
Zero
1111...1110
1000...0001
The accuracy of a D/A converter is described by the transfer
function shown in Figure 1. Digital input to analog output
relationship is shown in Table I. The errors in the D/A
converter are combinations of analog errors due to the linear
circuitry, matching and tracking properties of the ladder and
scaling networks, power supply rejection, and reference
errors. In summary, these errors consist of initial errors
including Gain, Offset, Linearity, Differential Linearity, and
Power Supply Sensitivity. Gain drift over temperature rotates
the line (Figure 1) about the bipolar zero point and Offset
drift shifts the line left or right over the operating temperature
range. Most of the Offset and Gain drift with temperature or
time is due to the drift of the internal reference zener diode.
The converter is designed so that these drifts are in opposite
directions. This way the Bipolar Zero voltage is virtually
unaffected by variations in the reference voltage.
1000...0000
Analog Output
–FSR/2
(+FSR/2) –1LSB
* See Table I for digital code definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar D/A Converter.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy.
The PCM56 power supply sensitivity is shown by Figure 2.
Normally, regulated power supplies with 1% or less ripple
are recommended for use with the DAC. See also Power
Supply Connections paragraph in the Installation and
Operating Instructions section.
DIGITAL INPUT CODES
SETTLING TIME
Settling time is the total time (including slew time) required
for the output to settle within an error band around its final
value after a change in input (see Figure 3).
The PCM56 accepts serial input data (MSB first) in the
Binary Two’s Complement (BTC) form. Refer to Table I
for input/output relationships.
DIGITAL INPUT
Settling times are specified to ±0.006% of FSR: one for a
large output voltage change of 6V and one for a 1LSB
change. The 1LSB change is measured at the major carry
(0000 hex to ffff hex), the point at which the worst-case
settling time occurs.
ANALOG OUTPUT
Binary Two’s
Complement (BTC)
DAC Output
Voltage (V),
VOUT Mode
Current (mA),
IOUT Mode
7FFF Hex
8000 Hex
0000 Hex
FFFF Hex
+ Full Scale
– Full Scale
Bipolar Zero
Zero –1LSB
+2.999908
–3.000000
0.000000
–0.000092
–0.999970
+1.000000
0.000000
+0.030500µA
86
TABLE I. Digital Input to Analog Output Relationship.
Power Supply Rejection (dB)
BIPOLAR ZERO ERROR
Initial Bipolar Zero Error (Bit 1 “on” and all other bits “off”)
is the deviation from 0V out and is factory-trimmed to
typically ±30mV at +25°C.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the deviation from an
ideal 1LSB change from one adjacent output state to the
next. DLE is important in audio applications because
excessive DLE at Bipolar Zero (at the “major carry”) can
result in audible crossover distortion for low level output
signals. Initial DLE on the PCM56 is factory trimmed to
typically ±0.001% of FSR. The MSB DLE is adjustable to
zero using the circuit shown in Figure 6.
74
68
62
Positive Supplies
56
52
46
40
34
28
1
10
100
1k
Frequency (Hz)
FIGURE 2. Power Supply Sensitivity.
®
PCM56
Negative Supplies
80
4
10k
100k
The THD is defined as the ratio of the square root of the sum
of the squares of the values of the harmonics to the value of
the fundamental input frequency and is expressed in percent
or dB. The rms value of the PCM56 error referred to the
input can be shown to be:
Accuracy
Percent Full-Scale Range (%)
1.0
Voltage
Output
Mode
0.3
Current
Output
Mode
0.1
0.03
n
∈ rms =
1/n
0.01
 E (i ) + E (i) 
L
Q
i =1
RL = 200Ω
0.003
0.001
0.01
∑
0.1
1.0
2
(1)
where n is the number of samples in one cycle of any given
sine wave, EL(i) is the linearity error of the PCM56 at each
sampling point, and EQ(i) is the quantization error at each
sampling point. The THD can then be expressed as:
10.0
Settling Time (µs)
THD = ∈ rms / E rms
FIGURE 3. Full Scale Range Settling Time vs Accuracy.
n
STABILITY WITH TIME AND TEMPERATURE
1 /n
The parameters of a D/A converter designed for audio
applications should be stable over a relatively wide
temperature range and over long periods of time to avoid
undesirable periodic readjustment. The most important
parameters are Bipolar Zero Error, Differential Linearity
Error, and Total Harmonic Distortion. Most of the Offset
and Gain drift with temperature or time is due to the drift of
the internal reference zener diode. The PCM56 is designed
so that these drifts are in opposite directions so that the
Bipolar Zero voltage is virtually unaffected by variations in
the reference voltage. Both DLE and THD are dependent
upon the matching and tracking of resistor ratios and upon
VBE and hFE of the current-source transistors. The PCM56
was designed so that any absolute shift in these components
has virtually no effect on DLE or THD. The resistors are
made of identical links of ultra-stable nichrome thin-film.
The current density in these resistors is very low to further
enhance their stability.
∑
i =1
 E (i ) + E (i) 
L
Q
2
(2)
=
X
100%
Erms
where Erms is the rms signal-voltage level.
This expression indicates that, in general, there is a correlation
between the THD and the square root of the sum of the
squares of the linearity errors at each digital word of interest.
However, this expression does not mean that the worst-case
linearity error of the D/A is directly correlated to the THD.
For the PCM56 the test period was chosen to be 22.7µs
(44.1kHz), which is compatible with the EIAJ STC-007
specification for PCM audio. The test frequency is 991Hz
and the amplitude of the input signal is 0dB, –20dB, and
–60dB down from full scale.
Figure 4 shows the typical THD as a function of output
voltage.
Figure 5 shows typical THD as a function of frequency.
DYNAMIC RANGE
The Dynamic Range is a measure of the ratio of the smallest
signals the converter can produce to the full-scale range and
is usually expressed in decibels (dB). The theoretical dynamic
range of a converter is approximately 6 x n, or about 96dB
of a 16-bit converter. The actual, or useful, dynamic range is
limited by noise and linearity errors and is therefore somewhat
less than the theoretical limit. However, this does point out
that a resolution of at least 16 bits is required to obtain a
90dB minimum dynamic range, regardless of the accuracy
of the converter. Another specification that is useful for
audio applications is Total Harmonic Distortion.
Total Harmonic Distortion (%)
10.0
TOTAL HARMONIC DISTORTION
THD is useful in audio applications and is a measure of the
magnitude and distribution of the Linearity Error, Differential
Linearity Error, and Noise, as well as Quantization Error. To
be useful, THD should be specified for both high level and
low level input signals. This error is unadjustable and is the
most meaningful indicator of D/A converter accuracy for
audio applications.
1.0
14 Bits
0.1
0.01
16 Bits
0.001
–60
–50
–40
–30
–20
–10
0
VOUT (dB)
0dB = Full Scale Range (FSR)
FIGURE 4. Total Harmonic Distortion (THD) vs VOUT.
®
5
PCM56
A much simpler method is to dynamically adjust the DLE at
BPZ. Again, refer to Figure 6 for circuitry and component
values. Assuming the device has been installed in a digital
audio application circuit, send the appropriate digital input
to produce a –80dB level sinusoidal output. While measuring
the THD of the audio circuit output, adjust the 100kΩ
potentiometer until a minimum level of distortion is observed.
Total Harmonic Distortion (%)
0.1
(–20dB)
0.01
470kΩ
100kΩ
Trim 15
(Full Scale)
200kΩ
1 –VS
0.001
100
1k
10k 20k
MSB Adjust 14
Frequency (Hz)
FIGURE 6. MSB Adjustment Circuit.
FIGURE 5. Total Harmonic Distortion (THD) vs Frequency.
INPUT TIMING CONSIDERATIONS
Figure 7 and 8 refer to the input timing required to interface
the inputs of PCM56 to a serial input data stream. Serial data
is accepted in Binary Two’s Complement (BTC) with the
MSB being loaded first. Data is clocked in on positive going
clock (CLK) edges and is latched into the DAC input
register on negative going latch enable (LE) edges.
INSTALLATION AND
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown in the
Connection Diagram. These capacitors (1µF tantalum or
electrolytic recommended) should be located close to the
converter.
The latch enable input must be high for at least one clock
cycle before going low, and then must be held low for at
least one clock cycle. The last 16 data bits clocked into the
serial input register are the ones that are transferred to the
DAC input register when latch enable goes low. In other
words, when more than 16 clock cycles occur between a
latch enable, only the data present during the last 16 clocks
will be transferred to the DAC input register.
MSB ERROR ADJUSTMENT PROCEDURE
(OPTIONAL)
The MSB error of the PCM56 can be adjusted to make the
differential linearity error (DLE) at BPZ essentially zero.
This is important when the signal output levels are very low,
because zero crossing noise (DLE at BPZ) becomes very
significant when compared to the small code changes
occurring in the LSB portion of the converter.
One requirement for clocking in all 16 bits is the necessity
for a “17th” clock pulse. This automatically occurs when the
clock is continuous (last bit shifts in on the first bit of the
next data word). If the clock is stopped between input of 16bit data words, the latch enable (LE) must remain low until
after the first clock of the next 16-bit data word stream. This
ensures that the latch is properly set up.
Differential linearity error at bipolar zero and THD are
guaranteed to meet data sheet specifications without any
external adjustment. However, a provision has been made
for an optional adjustment of the MSB linearity point which
makes it possible to eliminate DLE error at BPZ. Two
procedures are given to allow either static or dynamic
adjustment. The dynamic procedure is preferred because of
the difficulty associated with the static method (accurately
measuring 16-bit LSB steps).
Figure 7 refers to the general input format required for the
PCM56. Figure 8 shows the specific relationships between
the various signals and their timing constraints.
INSTALLATION
CONSIDERATIONS
To statically adjust DLE at BPZ, refer to the circuit shown
in Figure 6, or the PCM56 connection diagram.
If the optional external MSB error circuitry is used, a
potentiometer with adequate resolution and a TCR of 100ppm/
°C or less is required. Also, extra care must be taken to
insure that no leakage path (either AC or DC) exists to pin
14. If the circuit is not used, pins 14 and 15 should be left
open.
After allowing ample warm-up time (5-10 minutes) to assure
stable operation of the PCM56, select input code FFFF
hexadecimal (all bits on except the MSB). Measure the
audio output voltage using a 6-1/2 digit voltmeter and record
it. Change the digital input code to 0000 hexadecimal (all
bits off except the MSB). Adjust the 100kΩ potentiometer to
make the audio output read 92µV more than the voltage
reading of the previous code (a 1LSB step = 92µV).
The PCM converter and the wiring to its connectors should
be located to provide the optimum isolation from sources of
RFI and EMI. The important consideration in the elimination
®
PCM56
6
(1)
Clock
LSB
MSB
Data
1
(2)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
MSB
Latch
Enable
(3)
(4)
NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data
word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch
enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going
negative.
FIGURE 7. Input Timing Diagram.
source and drain of the FET switch operate at a virtual
ground when “C” and “B” are connected in the sample
mode, there is no increase in distortion caused by the
modulation effect of RON by the audio signal.
> 40ns
Data
Input
LSB
MSB
Figure 10 shows the deglitcher controls for both left and
right channels which are produced by timing control logic.
A delay of 1.5µs (tω) is provided to allow the output of the
PCM56 to settle within a small error band around its final
value before connecting it to the channel output. Due to the
fast settling time of the PCM56 it is possible to minimize the
delay between the left- and right-channel outputs when
using a single D/A converter for both channels. This is
important because the right- and left-channel data are recorded
in-phase and the use of the slower D/A converter would
result in significant phase error at higher frequencies.
>15ns >15ns
Clock
Input
> 40ns
> 40ns
> 5ns
> 100ns
Latch
Enable
> 15ns
> One Clock Cycle
> One Clock Cycle
The obvious solution to the phase shift problem in a twochannel system would be to use two D/A converters (one per
channel) and time the outputs to change simultaneously.
Figure 11 shows a block diagram of the final test circuitry
used for PCM56. It should be noted that no deglitching
circuitry is required on the DAC output to meet specified
THD performance. This means that when one PCM56 is
used per channel, the need for all the sample/hold and
controls circuitry associated with a single DAC (two-channel)
design is effectively eliminated. The PCM56 is tested to
meet its THD specifications without the need for output
deglitching.
FIGURE 8. Input Timing Relationships.
of RF radiation or pickup is loop area; therefore, signal leads
and their return conductors should be kept close together.
This reduces the external magnetic field along with any
radiation. Also, if a signal lead and its return conductor are
wired close together, they represent a small flux-capture
cross section for any external field. This reduces radiation
pickup in the circuit.
APPLICATIONS
A low-pass filter is required after the PCM56 to remove all
unwanted frequency components caused by the sampling
frequency as well as those resulting from the discrete nature
of the D/A output. This filter must have a flat frequency
response over the entire audio band (0-20kHz) and a very
high attenuation above 20kHz.
Figures 9 and 10 show a circuit and timing diagram for a
single PCM56 used to obtain both left- and right-channel
output in a typical digital audio system. The audio output of
the PCM56 is alternately time-shared between the left and
right channels. The design is greatly simplified because the
PCM56 is a complete D/A converter requiring no external
reference or output op amp.
Most previous digital audio circuits used a higher order (913 pole) analog filter. However, the phase response of an
analog filter with these amplitude characteristics is nonlinear
and can disturb the pulse-shaped characteristic transients
contained in music.
A sample/hold (S/H) amplifier, or “deglitcher” is required at
the output of the D/A for both the left and right channel, as
shown in Figure 9. The S/H amplifier for the left channel is
composed of A1, SW1, and associated circuitry. A1 is used
as an integrator to hold the analog voltage in C1. Since the
®
7
PCM56
SECOND GENERATION SYSTEMS
One method of avoiding the problems associated with a
higher order analog filter would be to use digital filter
oversampling techniques. Oversampling by a factor of two
would move the sampling frequency (88.2kHz) out to a
point where only a simple low-order phase-linear analog
filter is required after the deglitcher output to remove
unwanted intermodulation products. In a digital compact
disc application, various VLSI chips perform the functions
of error detection/correction, digital filtering, and formatting
of the digital information to provide the clock, latch enable,
and serial input to the PCM56. These VLSI chips are
available from several sources (Sony, Yamaha, Signetics,
etc.) and are specifically optimized for digital audio
applications.
Oversampled circuitry requires a very fast D/A converter
since the sampling frequency is multiplied by a factor of two
or more (for each output channel). A single PCM56 can
provide two-channel oversampling at a 4X rate (176.4kHz/
channel) and still remain well within the settling time
requirements for maintaining specified THD performance.
This would reduce the complexities of the analog filter even
further from that used in 2X oversampling circuitry.
R2
2.2kΩ
R1
2.2kΩ
C
C1
680pF
Serial Data
A
Clock
B
SW1
PCM56
A1(1)
Left Channel
Output to LPF
MP7512
(Micro Power)
Latch Enable
R4
2.2kΩ
R3
2.2kΩ
Left Channel
Deglitcher Control
Right Channel
Deglitcher Control
C
A
B
SW2
A "low" signal on the deglitcher control closes switch "A",
while a "high" signal closes switch "B".
C2
680pF
A2(1)
Right Channel
Output to LPF
MP7512
(Micro Power)
NOTE: (1) 1 OPA101AM or 1/4 OPA404KP or 1 OPA606KP or OPA2604.
FIGURE 9. A Sample/Hold Amplifier (Deglitcher) is Required at the Digital-to-Analog Output for Both Left and Right Channels.
44.1kHz
Serial Data
Left Channel
Right Channel
Left Channel
Right Channel
Latch Enable
tω = 1.5µs DAC Settling Time
Right Channel
Deglitcher Control
Left Channel
Deglitcher Control
t DELAY 4.5µs max
The deglitcher control signals by timing control logic. The fast settling time of the PCM56 makes it possible to
minimize the delay between left and right channels to about 4.5µs, which reduces phase error at the higher audio frequencies.
FIGURE 10. Timing Diagram for the Deglitcher Control Signals.
®
PCM56
8
Low-Pass
Filter
(Toko APQ-25
or Equivalent)
Programmable
Gain Amp
0dB to 60dB
Distortion
Analyzer
(Shiba Soku Model
725 or Equivalent)
0
LOW-PASS FILTER
CHARACTERISTIC
–20
Gain (dB)
Use 400Hz High-Pass
Filter and 30kHz
Low-Pass Filter
Meter Settings
–40
–60
–80
–100
Binary
Counter
Digital Code
(EPROM)
Parallel-to-Serial
Conversion
DUT
(PCM58P)
–120
1
1
2
3
4
5
10 10 10 10 10
Frequency (Hz)
Clock
Latch Enable
Timing
Logic
Sampling Rate = 44.1kHz x 4 (176.4kHz)
Output Frequency = 991Hz
FIGURE 11. Block Diagram of Distortion Test Circuit.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
9
PCM56
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCM56U
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PCM56U
PCM56U/1K
ACTIVE
SOIC
DW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PCM56U
PCM56U/1KG4
ACTIVE
SOIC
DW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PCM56U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM56U/1K
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM56U/1K
SOIC
DW
16
1000
367.0
367.0
38.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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