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Texas Instruments Using the Automatic Gain Controller in TLV320ADCx140 Application notes
Application Report
SBAA401 – July 2019
Using the Automatic Gain Controller (AGC) in the
TLV320ADCx140
Diljith Thodi
ABSTRACT
The TLV320ADCx140 family of devices (TLV320ADC3140, TLV320ADC5140, and TLV320ADC6140) are
quad-channel, high-performance, analog-to-digital converters for audio applications. This family of devices
has an extensive set of features that includes the following:
• Programmable channel gain (PGA)
• Digital volume control
• A programmable microphone bias voltage
• A phase-locked loop (PLL)
• A programmable high pass filter (HPF)
• Automatic Gain Control (AGC)
• Dynamic Range Enhancer (DRE) support in the TLV320ADC5140 and TLV320ADC6140
• Linear phase or low-latency filter modes for sample-rates up to 768 kHz
This application note describes how to configure the automatic gain control (AGC) feature in
TLV320ADCx140 devices.
1
2
3
4
Contents
Introduction ................................................................................................................... 2
Automatic Gain Control ..................................................................................................... 2
Examples ..................................................................................................................... 9
References .................................................................................................................. 11
List of Figures
1
AGC Example ................................................................................................................ 2
2
AGC Block Diagram ......................................................................................................... 3
List of Tables
....................................................................
1
DRE or AGC Selection using DSP_CFG1 Register
2
Programmable Coefficient Registers for High Pass Filter .............................................................. 4
3
List of AGC Parameters..................................................................................................... 4
4
AGC Target Level Programmable Settings
5
AGC Maximum Gain Programmable Settings ........................................................................... 5
6
Programmable Coefficient Registers for Noise Threshold
7
Programmable Registers for Release Time Constant .................................................................. 6
8
Programmable Registers for Attack Time Constant
6
9
Programmable Registers for Release Hysteresis
7
10
11
12
..............................................................................
............................................................
....................................................................
......................................................................
Programmable Coefficient Registers for Attack Hysteresis ...........................................................
Programmable Registers for Noise Hysteresis .........................................................................
Programmable Registers for Attack Debounce .........................................................................
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3
5
5
7
7
8
1
Introduction
13
14
1
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.......................................................................
Programmable Registers for Noise Debounce ..........................................................................
Programmable Registers for Release Debounce
8
8
Introduction
Automatic Gain Control (AGC) is an algorithm that dynamically controls the gain of a signal to maintain a
nominally constant output level. A typical example application for AGC occurs while recording speech
signals when the speaker is changing his or her distance from the microphone while speaking. Sound
pressure levels at the microphone vary inversely with distance to the sound source. Therefore,
microphone output levels are weak for the farther sound sources, and loud for the closer sound sources.
Without AGC and just a fixed-gain PGA, output levels vary from soft to loud as the person moves closer to
the microphone. With AGC enabled, the input level variation can be maintained at a constant level. Thus,
AGC automatically responds to changes in the input signal to maintain a fixed level to meet target
application requirements. Figure 1 shows how the AGC responds to a tone whose level falls below the
target level and then rises above it.
Input
Signal
Output
Signal
Target
Level
AGC
Gain
Decay Time
Attack
Time
Figure 1. AGC Example
Automatic Gain Control (AGC) is supported on all ADC channels of the TLV320ADCx140 device family.
This application note describes the operation of the AGC, the tunable parameters, and the device
configurations required to support AGC.
2
Automatic Gain Control
The AGC algorithm is a mixed-signal solution, where the analog programmable gain amplifier (PGA) of a
channel is controlled by a closed-loop control digital algorithm. Figure 2 shows the signal processing chain
for the device.
2
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Figure 2. AGC Block Diagram
To respond to changes in the input signal, the AGC algorithm monitors the digitized signal from the ADC
and adjusts the PGA to maintain a constant target level. If the signal is below the target level, the AGC
increases the PGA gain. If the signal is above the target level, the AGC decreases the PGA gain. Using
the analog circuitry of the PGA to change the input signal provides optimal noise performance, since it
avoids gain adjustments in the digital circuitry that increases the quantization noise. Moreover, the AGC
algorithm uses a small step size during PGA changes to reduce distortions in the input signal.
The TLV320ADCx140 family supports up to four analog external input channels, with all input channels
supporting AGC. The devices support differential or single-ended signals from an analog microphone
source or auxiliary line input. The analog microphone inputs supports electret condensers and
microelectrical-mechanical (MEMS) microphones. Even though the devices also support digital pulse
density modulated (PDM) digital microphones, the AGC does not support digital channels, since the
analog gain of the digital microphone cannot be controlled.
The TLV320ADC5140 and TLV320ADC6140 also support a Dynamic Range Enhancer (DRE) algorithm
on the analog channels to augment the dynamic range. The DRE algorithm controls the PGA to reduce
the noise floor for low-level signals. DRE and AGC algorithms cannot be used simultaneously, since both
the algorithms control the PGA. As shown in Table 1, DRE or AGC selection is done using the
DRE_AGC_SEL bit of DSP_CFG1 register (page = 0x00, address = 0x6C). AGC or DRE can be
independently enabled or disabled for each channel using the CH1_DREEN (P0_R60_D0), CH2_DREEN
(P0_R65_D0), CH3_DREEN (P0_R70_D0), and CH4_DREEN (P0_R75_D0) register bits.
Table 1. DRE or AGC Selection using DSP_CFG1 Register
BIT
3
2.1
FIELD
TYPE
DRE_AGC_SEL
R/W
RESET
DESCRIPTION
0h
DRE or AGC selection when is enabled for any channel.
0d = DRE is selected.
1d = AGC is selected.
High Pass Filter
To remove any DC offset that leads to incorrect input level estimates, the AGC algorithm processes the
input signal through a high-pass filter. This HPF is exclusive to the AGC, and is different from the secondorder HPF filters used by the decimation filters.
The transfer function implemented by the high-pass filter is given by Equation 1.
H(z)
N0 N1u z
1 D1u z
1
1
(1)
The HPF is a first-order filter implemented using three coefficients: AGC_HPF_B0, AGC_HPF_B1, and
AGC_HPF_A1. The transfer function parameters (N0, N1, and D1) are converted to coefficients using
Equation 2, Equation 3, and Equation 4.
AGC _ HPF _ B0
round(231 u N0)
(2)
AGC _ HPF _ B1 round(231 u N1)
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(3)
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AGC _ HPF _ A1 round(231 u D1)
(4)
These coefficients are user-programmable to set a different cutoff frequency from the default cutoff (-3 dB)
of 100 Hz for a 48 kHz sample rate. Increasing the cutoff frequency results in faster settling of signal-level
estimates, while decreasing the cutoff frequency improves the accuracy of the signal-level estimate. The
default filter coefficients provide a good balance between speed and accuracy, and are suitable for most
applications. Table 2 shows the coefficient registers. The coefficients are represented in 2s-complement,
32-bit format.
Table 2. Programmable Coefficient Registers for High Pass Filter
COEFFICIENT
AGC_HPF_B0
AGC_HPF_B1
AGC_HPF_A1
2.2
PAGE
REGISTER
RESET VALUE
0x06
0x78
0x7F
AGC_HPF_B0 Byte[31:24]
DESCRIPTION
0x06
0x79
0x7F
AGC_HPF_B0 Byte[23:16]
0x06
0x7A
0xD2
AGC_HPF_B0 Byte[15:8]
0x06
0x7B
0xB4
AGC_HPF_B0 Byte[7:0]
0x06
0x7C
0x80
AGC_HPF_B1 Byte[31:24]
0x06
0x7D
0x80
AGC_HPF_B1 Byte[23:16]
0x06
0x7E
0x2D
AGC_HPF_B1 Byte[15:8]
0x06
0x7F
0x4C
AGC_HPF_B1 Byte[7:0]
0x07
0x08
0x7E
AGC_HPF_A1 Byte[31:24]
0x07
0x09
0xFF
AGC_HPF_A1 Byte[23:16]
0x07
0x0A
0xA5
AGC_HPF_A1 Byte[15:8]
0x07
0x0B
0x68
AGC_HPF_A1 Byte[7:0]
AGC Parameters
Table 3 shows the parameters of the AGC algorithm. The first two parameters (AGC Target Level and
Maximum Gain) are controlled by writing to the device registers. The other parameters reside in the 32-bit
wide coefficient memory (Book 0, Page 5, Page 6, and Page 7) of the device.
Table 3. List of AGC Parameters
AGC PARAMETER
AGC Target Level (dB)
Function/Description
The AGC target level represents the nominal level at which the AGC attempts to maintain its
output signal.
Maximum Gain (dB)
Upper limit of gain in dB applied by the AGC for signals below target level.
Noise Threshold (dB)
The threshold level the AGC utilizes to distinguish noise from weak signals. Signals lower than
this threshold are classified as noise and not amplified by the AGC.
Release Time Constant (seconds) How fast the AGC circuitry responds with a PGA gain increase when the input signal falls
below the target level.
Attack Time Constant (seconds)
4
How fast the AGC circuitry responds with a PGA gain decrease when input signal rises above
the target level.
Release Hysteresis (dB)
Amount of signal level decrease in dB past the Target Level that forces the AGC to increase
gain and start a release.
Attack Hysteresis (dB)
Amount of signal level increase in dB past the Target Level that forces the AGC to decrease
gain and start an attack.
Noise Hysteresis (dB)
Amount of signal level change past the Noise Threshold that causes the AGC to decide
between noise or signal.
Release Debounce (samples)
The number of consecutive input samples that falls below Target Level after an attack event
before the AGC starts releasing and increasing PGA gain.
Attack Debounce (samples)
The number of consecutive input samples that rises above Target Level after a release event
before the AGC starts attacking and decreasing PGA gain.
Noise Debounce (samples)
The number of consecutive samples for the input to fall below Noise Threshold for the signal to
be considered as noise.
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AGC Target Level: The AGC target level represents the nominal level at which the AGC attempts to
maintain the output signal. The target level is expressed relative to full scale (dBFS) of the ADC output.
Table 4 lists the AGC Target Level configuration settings. The default is -34 dB. Setting a high target level
increases the converted output level. However, large target level settings can lead to clipping the input
signal with a sudden increase in the signal level. Therefore, set the target level with enough margin so as
to prevent clipping when loud sounds occur.
Table 4. AGC Target Level Programmable Settings
P0_R112_D[7:4] : AGC_LVL[3:0]
AGC TARGET LEVEL FOR OUTPUT
0000
The AGC target level is the –6 dB output signal level
0001
The AGC target level is the –8 dB output signal level
0010
The AGC target level is the –10 dB output signal level
…
…
1110 (default)
The AGC target level is the –34 dB output signal level
1111
The AGC target level is the –36 dB output signal level
Maximum Gain: The maximum gain represents the upper limit of gain applied by the AGC for signals
below the target level. Table 5 lists the Maximum Gain configuration settings. The default value is 24 dB. It
can be programmed from 3 dB to 42 dB with steps of 3 dB.
Table 5. AGC Maximum Gain Programmable Settings
P0_R112_D[3:0] :
AGC_MAXGAIN[3:0]
AGC MAXIMUM GAIN ALLOWED
0000
The AGC maximum gain allowed is 3 dB
0001
The AGC maximum gain allowed is 6 dB
0010
The AGC maximum gain allowed is 9 dB
…
…
0111 (default)
The AGC maximum gain allowed is 24 dB
…
…
1110
The AGC maximum gain allowed is 39 dB
1111
The AGC maximum gain allowed is 42 dB
Noise Threshold: The threshold level used by the AGC to distinguish noise from weak signals. Signals
lower than this threshold are classified as noise and not amplified by the AGC. Noise Threshold is set by
writing to the AGC_NOISE coefficient. Equation 5 shows the computation of the AGC_NOISE parameter.
AGC _ NOISE
round(28 u NT)
where
•
NT is the Noise Threshold in dB
(5)
The default value (0xFFFFA600) corresponds to -90 dB. Table 6 shows the registers that control the
AGC_NOISE parameter.
Table 6. Programmable Coefficient Registers for Noise Threshold
COEFFICIENT
AGC_NOISE
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PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x20
0xFF
AGC_NOISE Byte[31:24]
0x06
0x21
0xFF
AGC_NOISE Byte[23:16]
0x06
0x22
0xA6
AGC_NOISE Byte[15:8]
0x06
0x23
0x00
AGC_NOISE Byte[7:0]\
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Release Time Constant: How fast the AGC circuitry responds with a PGA gain increase when the input
signal falls below the target level. The Release Time Constant is controlled by two coefficients:
AGC_REL_ALPHA and AGC_REL_BETA. Equation 6 and Equation 7 show how to compute the
AGC_REL_ALPHA and AGC_REL_BETA parameters from the following time constant:
AGC _ REL _ ALPHA
round(231 u e
AGC _ REL _ BETA
31
2
31
ln(9)/48000uRT
round(2 u e
)
(6)
ln(9)/48000uRT
)
where
•
RT is the Release Time Constant in seconds
(7)
Table 7 shows the registers that control AGC_REL_ALPHA and AGC_REL_BETA parameters. These
parameters are written in 2s-complement representation. The default values for AGC_REL_ALPHA and
AGC_REL_BETA corresponds to a time constant of 20 milliseconds.
Table 7. Programmable Registers for Release Time Constant
COEFFICIENT
AGC_REL_ALPHA
AGC_REL_BETA
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x05
0x7C
0x7F
AGC_REL_ALPHA Byte[31:24]
0x05
0x7D
0xB5
AGC_REL_ALPHA Byte[23:16]
0x05
0x7E
0x16
AGC_REL_ALPHA Byte[15:8]
0x05
0x7F
0x50
AGC_REL_ALPHA Byte[7:0]
0x06
0x08
0x00
AGC_REL_BETA Byte[31:24]
0x06
0x09
0x4A
AGC_REL_BETA Byte[23:16]
0x06
0x0A
0xE9
AGC_REL_BETA Byte[15:8]
0x06
0x0B
0xB0
AGC_REL_BETA Byte[7:0]
Attack Time Constant: How fast the AGC circuitry responds with a PGA gain decrease when the input
signal rises above the target level. Equation 8 and Equation 9 show the computation of the Attack Time
Constant Parameters AGC_ATT_ALPHA and AGC_ATT_BETA.
AGC _ ATT _ ALPHA
AGC _ ATT _BETA
round(231 u e
31
round(2 u e
ln(9)/48000uAT
ln(9)/48000uAT
)
(8)
)
where
•
AT is the Attack Time Constant in seconds
(9)
AGC_ATT_ALPHA and AGC_ATT_BETA parameters are each 32-bit wide, 2s-complement
representations, and are controlled by registers shown in Table 8. The default values for
AGC_ATT_ALPHA and AGC_ATT_BETA corresponds to a time constant of 0.1 milliseconds.
Table 8. Programmable Registers for Attack Time Constant
COEFFICIENT
AGC_ATT_ALPHA
AGC_ATT_BETA
6
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x0C
0x50
AGC_ATT_ALPHA Byte[31:24]
0x06
0x0D
0xFC
AGC_ATT_ALPHA Byte[23:16]
0x06
0x0E
0x64
AGC_ATT_ALPHA Byte[15:8]
0x06
0x0F
0x5C
AGC_ATT_ALPHA Byte[7:0]
0x06
0x10
0x2F
AGC_ATT_BETA Byte[31:24]
0x06
0x11
0x03
AGC_ATT_BETA Byte[23:16]
0x06
0x12
0x9B
AGC_ATT_BETA Byte[15:8]
0x06
0x13
0xA4
AGC_ATT_BETA Byte[7:0]
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Release Hysteresis: Amount of signal level decrease past Target Level that forces the AGC to increase
gain and start a release. Release Hysteresis is specified in dB. Equation 10 shows the computation of the
AGC_REL_HYST parameter.
AGC _ REL _ HIST
round(28 u RH)
where
•
RH (>= 0) is the Release Hysteresis in dB
(10)
The default value of AGC_REL_HYST is 0x00000300, which corresponds to a hysteresis of 3 dB. Table 9
list the registers corresponding to AGC_REL_HYST.
Table 9. Programmable Registers for Release Hysteresis
COEFFICIENT
AGC_REL_HYST
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x34
0x00
AGC_REL_HYST Byte[31:24]
0x06
0x35
0x00
AGC_REL_HYST Byte[23:16]
0x06
0x36
0x03
AGC_REL_HYST Byte[15:8]
0x06
0x37
0x00
AGC_REL_HYST Byte[7:0]
Attack Hysteresis: Amount of signal level increase past Target Level that forces the AGC to decrease the
gina and start an attack. Attack Hysteresis is specified in dB. Equation 11 shows the computation of the
AGC_ATT_HYST parameter.
AGC _ ATT _ HYST
round(28 u AH)
where
•
AH (>= 0) is the Attack Hysteresis in dB
(11)
The default value of Attack Hysteresis is 1 dB. Table 10 shows the registers that control the
AGC_ATT_HYST parameter.
Table 10. Programmable Coefficient Registers for Attack Hysteresis
COEFFICIENT
AGC_ATT_HYST
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x3C
0x00
AGC_ATT_HYST Byte[31:24]
0x06
0x3D
0x00
AGC_ATT_HYST Byte[23:16]
0x06
0x3E
0x01
AGC_ATT_HYST Byte[15:8]
0x06
0x3F
0x00
AGC_ATT_HYST Byte[7:0]
Noise Hysteresis: (AGC_NOISE_HYST): Amount of signal level change around the Noise Threshold that
causes the AGC to decide between noise and signal. A rising signal has to rise above the Noise
Hysteresis level to be amplified to the Target Level. A decreasing signal has to fall below the Noise
Hysteresis level to be considered as noise. Noise Hysteresis is specified in dB. Equation 12 shows the
computation of the AGC_NOISE_HYST parameters.
AGC _ NOISE _ HYST
round(28 u NH)
where
•
NH (>= 0) is the Noise Hysteresis in dB
(12)
The default value of AGC_NOISE_HYST is 0x00000600, which corresponds to a hysteresis of 6 dB.
Table 10 shows the registers controlling the AGC_NOISE_HYST parameter.
Table 11. Programmable Registers for Noise Hysteresis
COEFFICIENT
AGC_NOISE_HYST
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PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x54
0x00
AGC_NOISE_HYST Byte[31:24]
0x06
0x55
0x00
AGC_NOISE_HYST Byte[23:16]
0x06
0x56
0x06
AGC_NOISE_HYST Byte[15:8]
0x06
0x57
0x00
AGC_NOISE_HYST Byte[7:0]
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Attack Debounce: The number of consecutive input samples that rises above the target level after a
release event before the AGC starts attack and decreases the PGA. Equation 13 shows the computation
of the AGC_ATT_CNT parameter.
AGC _ ATT _ CNT
round(28 u 48000 u AD)
where
•
AD (>= 0) is specified in seconds
(13)
Table 12 shows the registers controlling the AGC_ATT_CNT parameter.
Table 12. Programmable Registers for Attack Debounce
COEFFICIENT
AGC_ATT_CNT
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x18
0x00
AGC_ATT_CNT Byte[31:24]
0x06
0x19
0x00
AGC_ATT_CNT Byte[23:16]
0x06
0x1A
0x02
AGC_ATT_CNT Byte[15:8]
0x06
0x1B
0x00
AGC_ATT_CNT Byte[7:0]
Release Debounce: The number of consecutive input samples that falls below Target Level after an
attack event before the AGC starts releasing and increasing the PGA gain. The default value of Release
Debounce is 25 milliseconds at 48 kHz. Equation 14 shows the computation of the AGC_REL_CNT
parameter.
AGC _ REL _ CNT
round(28 u 48000 u RD)
where
•
RD (>= 0) is the Release Debounce specified in seconds
(14)
Table 13 shows the registers controlling the AGC_REL_CNT parameter.
Table 13. Programmable Registers for Release Debounce
COEFFICIENT
AGC_REL_CNT
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x1C
0x00
AGC_REL_CNT Byte[31:24]
0x06
0x1D
0x04
AGC_REL_CNT Byte[23:16]
0x06
0x1E
0xB0
AGC_REL_CNT Byte[15:8]
0x06
0x1F
0x00
AGC_REL_CNT Byte[7:0]
Noise Debounce: The number of consecutive samples for the input to fall below Noise Threshold for the
signal to be considered noise. Equation 15 shows the computation of the AGC_NOISE_CNT parameter.
AGC _NOISE _ CNT
round(28 u 48000 u ND)
where
•
ND (>= 0) is the Noise Debounce time specified in seconds
(15)
The default value of AGC_NOISE_CNT is 0x0004B000, which corresponds to a debounce time of 25
milliseconds at 48 kHz. Table 14 shows the registers controlling the AGC_NOISE_CNT parameter.
Table 14. Programmable Registers for Noise Debounce
COEFFICIENT
AGC_NOISE_CNT
8
PAGE
REGISTER
RESET VALUE
DESCRIPTION
0x06
0x44
0x00
AGC_NOISE_CNT Byte[31:24]
0x06
0x45
0x04
AGC_NOISE_CNT Byte[23:16]
0x06
0x46
0xB0
AGC_NOISE_CNT Byte[15:8]
0x06
0x47
0x00
AGC_NOISE_CNT Byte[7:0]
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Examples
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3
Examples
Two examples are presented below for configuring the AGC for two different target applications. Example
1 is for scenarios when the noise is much lower than the input signal. Example 2 is for scenarios where
the noise is significantly larger than the desired signal.
Example 1: When noise is significantly smaller in amplitude compared to signal, the AGC can easily
distinguish between noise and signal by setting the Noise Threshold higher than the noise floor, but lower
than the weakest possible signal. When such clear demarcations are possible, higher maximum gain can
be used, since there is low possibility of gaining up the noise. The following values can be used for this
application.
• Target Level = -36 dB
• Maximum Gain = 24 dB
• Noise Threshold = -90 dB
• Attack Time = 0.1 ms
• Release Time = 20 ms
• Attack Hold = 0.0417 ms
• Release Hold = 20 ms
• Attack Hysteresis = 1 dB
• Release Hysteresis = 3 dB
• Noise Hysteresis = 4 dB
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#
# ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 4-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/INM4 - Ch4
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
w
w
w
d
98 00 00 # Goto Page 0
98 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
98 02 81 # Exit Sleep mode
10
# Wait for 16 ms
w
w
w
w
w
w
98
98
98
98
98
98
6C
3C
41
74
75
70
48
01
01
01
01
E7
#
#
#
#
#
#
w
w
w
w
w
w
w
98
98
98
98
98
98
98
00
7C
00
08
0C
10
18
05
7F
05
00
50
2F
00
#
B5 16 50 #
#
4A E9 B0 #
FC 64 5C #
03 9B A4 #
00 02 00 #
Enable AGC in
Select AGC on
Select AGC on
Select AGC on
Select AGC on
AGC LVL = -36
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DSP_CFG1
Ch. 1 using CH1_CFG0
Ch. 2 using CH2_CFG0
Ch. 3 using CH3_CFG0
Ch. 4 using CH4_CFG0
dB, AGC GAIN = 24 dB
Goto Page 5
AGC Release Time Alpha
Goto Page 6
AGC Release Time Beta
AGC Attack Time Alpha
AGC Attack Time Beta
AGC Attack Debounce
Using the Automatic Gain Controller (AGC) in the TLV320ADCx140
Copyright © 2019, Texas Instruments Incorporated
9
Examples
www.ti.com
w
w
w
w
w
w
w
w
w
w
98
98
98
98
98
98
98
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98
98
1C
20
44
3C
34
54
78
7C
00
54
00
FF
00
00
00
00
7F
80
06
7E
04
FF
04
00
00
00
7F
80
w
w
w
w
w
98
98
98
98
98
00
07
73
74
75
00
30
f0
f0
e0
#
#
#
#
#
B0
A6
B0
01
03
04
D2
2D
00
00
00
00
00
00
B4
4C
#
#
#
#
#
#
#
#
#
FF A5 68 #
AGC Release Debounce
AGC Noise Threshold : -90 dB
AGC Noise Debounce
AGC Attack Hysteresis
AGC Release Hysteresis
AGC Noise Hysteresis : 4 dB
AGC HPF B0
AGC HPF B1
Goto Page 6
AGC HPF A1
Goto Page 0
TDM Mode with 32 Bits/Channel
Enable Ch.1 - Ch.4
Enable ASI Output channels
Power up ADC
Example 2: When noise is significantly high and not easily distinguishable from a weak signal, it is not
recommended to use a high maximum gain. The Noise Threshold has to be set closer to the expected
noise floor. The following values can be used for this application.
• Target Level = -36 dB
• Maximum Gain = 18 dB
• Noise Threshold = -84 dB
• Attack Time = 0.1 ms
• Release Time = 20 ms
• Attack Hold = 0.0417 ms
• Release Hold = 20 ms
• Attack Hysteresis = 1 dB
• Release Hysteresis = 3 dB
• Noise Hysteresis = 4 dB
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#
# ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 4-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/INM4 - Ch4
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
10
w
w
w
d
98 00 00 # Goto Page 0
98 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
98 02 81 # Exit Sleep mode
10
# Wait for 16 ms
w
w
w
w
w
98
98
98
98
98
6C
3C
41
74
75
48
01
01
01
01
#
#
#
#
#
Enable
Select
Select
Select
Select
AGC
AGC
AGC
AGC
AGC
in
on
on
on
on
DSP_CFG1
Ch. 1 using
Ch. 2 using
Ch. 3 using
Ch. 4 using
CH1_CFG0
CH2_CFG0
CH3_CFG0
CH4_CFG0
Using the Automatic Gain Controller (AGC) in the TLV320ADCx140
Copyright © 2019, Texas Instruments Incorporated
SBAA401 – July 2019
Submit Documentation Feedback
References
www.ti.com
w 98 70 E5 # AGC LVL = -36 dB, AGC GAIN = 18 dB
4
w
w
w
w
w
w
w
w
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w
w
w
98
98
98
98
98
98
98
98
98
98
98
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98
98
98
98
98
00
7C
00
08
0C
10
18
1C
20
44
3C
34
54
78
7C
00
54
05
7F
05
00
50
2F
00
00
FF
00
00
00
00
7F
80
06
7E
#
B5 16 50 #
#
4A E9 B0 #
FC 64 5C #
03 9B A4 #
00 02 00 #
04 B0 00 #
FF AC 00 #
04 B0 00 #
00 01 00 #
00 03 00 #
00 04 00 #
7F D2 B4 #
80 2D 4C #
#
FF A5 68 #
w
w
w
w
w
98
98
98
98
98
00
07
73
74
75
00
30
f0
f0
e0
#
#
#
#
#
Goto Page 5
AGC Release Time Alpha
Goto Page 6
AGC Release Time Beta
AGC Attack Time Alpha
AGC Attack Time Beta
AGC Attack Debounce
AGC Release Debounce
AGC Noise Threshold : -84 dB
AGC Noise Debounce
AGC Attack Hysteresis
AGC Release Hysteresis
AGC Noise Hysteresis : 4 dB
AGC HPF B0
AGC HPF B1
Goto Page 6
AGC HPF A1
Goto Page 0
TDM Mode with 32 Bits/Channel
Enable Ch.1 - Ch.4
Enable ASI Output channels
Power up ADC
References
•
•
Texas Instruments, TLV320ADC5140 Quad-Channel, 768-kHz, Burr-Brown Audio ADC Data Sheet
(SBAS892)
Texas Instruments, TLV320ADC3140 Quad-Channel, 768-kHz, Burr-Brown Audio ADC Data Sheet
(SBAS992)
SBAA401 – July 2019
Submit Documentation Feedback
Using the Automatic Gain Controller (AGC) in the TLV320ADCx140
Copyright © 2019, Texas Instruments Incorporated
11
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