Texas Instruments | Layout lines For TPA300x Series Parts | Application notes | Texas Instruments Layout lines For TPA300x Series Parts Application notes

Texas Instruments Layout lines For TPA300x Series Parts Application notes
Application Report
SLOA103 - July 2003
Layout Guidelines for TPA300x Series Parts
High Performance Linear/Audio Power Amplifiers
ABSTRACT
This article provides a well-reinforced procedure for the PCB layout task as it pertains to the
TPA300x series of class D amplifiers. This information can also be used in the layout of the
TPA200x series, or any other class D audio amplifier.
This task needs a logical sequence. If we simply jump into the layout task, without
understanding how the circuits work, we risk not having an optimal end result. Whether the
design engineer does the layout on his or her own or hands the layout task off to the
appropriate PCB specialist, there needs to be a clear understanding of the fundamentals of
the circuit on the designer’s part. As is true in most any engineering practice, there is no
unique solution to a given problem. In this case, there is no unique solution to a given layout.
However, several unique steps should be followed in order to achieve an optimal solution.
This article has four major parts. The first is the power train analysis and output inductor
specification section. This is the most important section as well as the most involved. Second,
there is a brief section on noise and grounding. Third, there is a detailed section on the
component placement and layout tasks. The fourth section is an EMI mitigation example
performed on the same principles illustrated in this document. From front to back this should
be a two hour read. More importantly before, throughout, and after the process of building
the end product, this application note serves as a reference to the designer.
Contents
1
Power Train Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Specifying the Output Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 Design Example Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1 Trace, Via, and Wire Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
EMC-The Final Word: Did Those Tricks Really Work? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 The Arsenal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 The Mitigation Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1
SLOA103
Appendix A Copper Wire Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
A.1 Current Density Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix B PCB Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
B.1 Board Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Appendix C Bruce Carsten Associates, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C.1 Appnote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of Figures
1 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Power Train Schematic For 1 Channel of TPA300x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Power Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 t2 - Q3 Channel Turned On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Time t3 And t1 - Equivalent Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Time t4 Is The Same as t0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 t5-Freewheel Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 t6-Q2 Is Turned On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
10 Time t7-Similar to t5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
11 Time t8-A Power Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Current Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Initial Layout Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Noise - First Segmentation Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
17 Noise - With Staggered MLCCs Along the Trace Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18 Noise Signature-After Adding a Common Mode Choke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
List of Tables
1 Header Pinout - Output Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1
Power Train Analysis
The first critical step is to map the power current flow through the system. In this case, the
system includes the PCB, Vcc/Return header, and the output connections. The first thing that
needs to be understood for any switchmode circuit is the current flow through the system in each
switch state. Usually there are fixed physical aspects of the board that determine some of this,
namely the board dimensions and the placement of the input, output and Vcc/Return
connections. Once these physical constraints are known, it is important to look at the key
elements in the power train and place them so that they can be optimally routed. The routing of
every current path in this chain is critical to the over all performance of the amplifier. A good
understanding of the operation of the amplifier proves invaluable in the placement task as well
as the PCB layout.
2
Layout Guidelines for TPA300x Series Parts
SLOA103
Energy is switched from the input decoupling capacitors through the TPA300x, to the filter
elements, to the load, through the other filter leg, through OUT - /OUT+, through the ‘300x, and
back to the input decoupling capacitors. This power path is lengthy and complex. The nodes
involved with this switching action are: Out±, Pvcc, Pgnd. When positioning, it is a good idea to
visualize the current flowing through various switching cycles. The switching waveforms and
corresponding switch diagrams may serve to clarify the switching intervals and the current paths
involved during various switching intervals. The state diagrams below illustrate a positive
excursion. For a negative excursion, simply switch the half bridge legs.
VCC
OUT+
GND
VCC
OUT GND
t_cycle
VCC
OUT+
GND
t_cycle (5x MAG)
VCC
OUT GND
t0
t1
t2
t3
t4
t5
t6
t7
t8
Figure 1. Switching Waveforms
Layout Guidelines for TPA300x Series Parts
3
SLOA103
Power Trans Schematic for 1 Channel of TPA300x
P_VCC Pin(s)
Q1
L1
15 µH
+
C_BYPASS
D3
D1
FB1
R1
R_Load
FB2
P_VCC Pin(s)
Q3
L1
15 µH
C10
OUT+_ Pins
Q2
C5
C1
0.47 µF 220 pF
C6
220 pF
C2
0.47 µF
D4
D2
OUT - _ Pins
Q4
1
PGND_ Pin(s)
PGND_ Pin(s)
Figure 2. Power Train Schematic For 1 Channel of TPA300x
Note that the mosfets (Q1 thru Q4) are modeled with ideal switches, in parallel with ideal diodes
(D1 thru D4), for this analysis.
t0
P_VCC Pin(s)
Q3 = OPEN
L1
15 µH
i
FB1
R1
R_Load
FB2
L2
15 µH
+
C_BYPASS
C10
OUT+_ Pins
C1
0.47 µF
C5
220 pF
C6
220 pF
C2
0.47 µF
OUT - _ Pins
Q4 = SHORT
1
Figure 3. Power Cycle
Time t0 is a power cycle. Energy from the decoupling capacitors is switched through the output
inductors and through the load. The inductors are charged in this cycle, while the decoupling
capacitors are discharged slightly. The current path consists of Pvcc, OUTP, the output filters,
output capacitors, the load, OUTN, and Pgnd.
4
Layout Guidelines for TPA300x Series Parts
SLOA103
t1
D3
i
Q1 = SHORT
Q3 = OPEN
L1
15 µH
OUT+_ Pins
FB1
C1
0.47 µF
R1
R_Load
C5
220 pF
FB2
C6
220 pF
L2
15 µH
C2
0.47 µF
Q2 = OPEN
OUT - _ Pins
Q4 = OPEN
1
Figure 4. Dead Time
Time t1 occurs during the dead time between the high side and low side switches in the OUTN
leg of the bridge. At this time, both Q3 and Q4 are open. Since there is no connection to the
decoupling capacitors, this is a freewheel cycle. At this time, both switches are off. The
inductors are no longer being driven from the input decoupling capacitors. The current waveform
changes slope at this instant. The voltage across the inductors changes instantaneously in an
attempt to keep the current flowing. This polarity change forward biases the body diode of Q3.
The channel of Q3 is off, however, the body diode is conducting. The current path consists of
PVcc, OUTP, the output filters, the load, and OUTN.
t2
D3
i
Q1 = SHORT
Q3 = SHORT
L1
15 µH
OUT+_ Pins
FB1
C1
0.47 µF
R1
R_Load
C5
220 pF
FB2
C6
220 pF
L2
15 µH
C2
0.47 µF
Q2 = OPEN
OUT - _ Pins
Q4 = OPEN
1
Figure 5. t2 - Q3 Channel is Turned On
At time t2, the channel of Q3 is turned on. Since current had been flowing through the body
diode, the voltage drop across Q3 is very low (Vf of the body diode) when Q3 is turned on. The
current path consists of PVcc, OUTP, the output filters, the load, and OUTN.
Layout Guidelines for TPA300x Series Parts
5
SLOA103
t3
D3
i
Q1 = SHORT
Q3 = OPEN
L1
15 µH
R1
R_Load
FB1
OUT+_ Pins
C1
0.47 µF
L2
15 µH
FB2
C5
220 pF
C6
220 pF
OUT - _ Pins
C2
0.47 µF
Q2 = OPEN
Q4 = OPEN
1
Figure 6. Time t3 and t1 - Equivalent Paths
Time t3 and t1 are equivalent paths. This is also a transition. The difference lies in the transition
to t4. The transition from t1 to t2 was a soft transition. The output inductors forward biased the
body diode of Q3 before it turned on. In this case, the output inductors source current around
the same loop; only the next transition turns on Q4. This is a hard transition.
t4
Q1 = SHORT
Q3 = OPEN
L1
15 µH
i
R1
R_Load
FB1
FB2
L2
15 µH
+
C_BYPASS
C10
OUT+_ Pins
C1
0.47 µF
C5
220 pF
C6
220 pF
Q1 = OPEN
C2
0.47 µF
OUT - _ Pins
Q4 = SHORT
1
Figure 7. Time t4 Is The Same as t0
t5
Q1 = OPEN
Q3 = OPEN
L1
15 µH
FB1
R1
R_Load
FB2
L2
15 µH
C6
220 pF
C2
0.47 µF
i
OUT - _ Pins
OUT+_ Pins
D2
C1
0.47 µF
C5
220 pF
Q2 = OPEN
1
Figure 8. t5-Freewheel Cycle
6
Layout Guidelines for TPA300x Series Parts
Q4 = SHORT
SLOA103
Time t5 is a freewheel cycle that occurs during the dead time of the OUTP leg of the bridge. At
this time, both switches are off in the OUTP leg and the current through the output inductors
forward biases the body diode of Q2. The current path consists of Pgnd, OUTP, the output
filters, the load, and OUTN.
t6
Q1 = OPEN
Q3 = OPEN
L1
15 µH
FB1
R1
R_Load
FB2
L2
15 µH
C6
220 pF
C2
0.47 µF
i
OUT - _ Pins
OUT+_ Pins
C1
0.47 µF
C5
220 pF
Q4 = SHORT
Q2 = SHORT
1
Figure 9. t6-Q2 Is Turned On
At time t6, Q2 is turned on. Since the body diode of Q2 was conducting, the voltage across Q2 is
minimal when it is turned on (Vf of the body diode). The current path is the same as t4.
t7
Q1 = OPEN
Q3 = OPEN
L1
15 µH
FB1
R1
R_Load
FB2
L2
15 µH
C6
220 pF
C2
0.47 µF
i
OUT - _ Pins
OUT+_ Pins
D2
C1
0.47 µF
C5
220 pF
Q4 = SHORT
Q2 = OPEN
1
Figure 10. Time t7-Similar to t5
Time t7 is similar to t5. The only exception is in the next cycle. Time t4 to time t5 was a soft
transition. Time t6 to t7 is a hard transition. The current path is the same as t5.
Layout Guidelines for TPA300x Series Parts
7
SLOA103
t8
Q3 = OPEN
Q1 = SHORT
L1
15 µH
i
FB1
R1
R_Load
FB2
L2
15 µH
+
C_BYPASS
C10
OUT+_ Pins
C1
0.47 µF
C5
220 pF
C6
220 pF
Q2 = OPEN
C2
0.47 µF
OUT - _ Pins
Q4 = SHORT
1
Figure 11. Time t8-A Power Cycle
Time t8 is the same as t0. This is a power cycle having the same current path as t0.
From the switching diagrams above, the current waveforms through the power transistors are:
i Q1
i Q2
i Q3
i Q4
t0 t1
t2
t3 t4 t5
t6
t7 t8
Figure 12. Current Waveforms
Note that FB1, FB2, C5, and C6 are for high frequency noise filtering and do not effect the
power train operation.
In every switch state above, it is important to understand the role of the filter inductors (L1 and
L2). These parts are excited with a square wave from the half bridge legs. We know that an
inductor wants to look like a current source, that is, it opposes any change in current.
If we look into Ohm’s law for an inductor, we see the equation:
V + * Ldi
dt
(1)
In the case of the switching amplifier, V across the inductor is known with each switch state, L is
a constant value, and dt is the time spent in a particular cycle. There is then a dependant
variable, di. If we approximate dt as ∆t and di as ∆i, we can rearrange the approximation:
8
Layout Guidelines for TPA300x Series Parts
SLOA103
ǒ
Ǔ
Di + * V
L
(2)
Dt
This is the ripple current in the output inductor.
From the diagrams above, it is clear that there are two states for the output inductors. When the
inductors are switched to Vcc on one leg and ground on the other leg, they are charging. This is
a charge cycle. When the output is switched any other way, the inductor begins to discharge, at
this point the slope of the current in the inductor changes. The voltage across the inductor
reverses polarity at this instant to oppose the change in current flow. We also know that an ideal
inductor cannot sustain a dc voltage drop. This means that the volt-time product in the charge
state of the inductor is equal to the volt-time product in the discharge state.
Building on the example above, the duty cycle of OUTP is about 2/3 or 67%. The duty cycle of
OUTN is then (1 - 2/3) or 33%. If the switching frequency is 250 kHz then tcycle = 4 µs. Looking at
each half bridge leg on its own.
OUTP is tied to Vcc for 2.66 µs and then tied to ground for 1.33 µs. OUTN is tied to Vcc for
1.33µs and then tied to ground for 2.66 µs.
Assuming that these duty cycles are steady state, if we look at L1:
•
V × t (charge) = (Vcc - VC1) × 2.66 µs
•
V ×t (discharge) = (VC1) × 1.33 µs
Since these volt-time products are equal, we can combine these two equations to get:
•
VC1 = Vcc × (2.66/4)
To solve this equation for VC1, we get:
•
VC1=Vcc*Doutp
This is the dc transfer function of the OUTP leg of this amplifier. In this example, this is 2 Vcc/3.
We can do the same for L2 to get:
•
VC2 = Vcc × (1.33/4)
•
VC2 = Vcc × (1 - Doutp)
In this example, this is Vcc/3. This is the dc transfer function for the OUTN leg of this amplifier.
So the output voltage across the bridge legs is then:
•
VC1 - VC2 or Vcc/3.
If we apply equation 2), and there is no interaction between the half bridges, the ripple current in
the inductor (L1) is then:
•
∆i=((Vcc - 2/3 × Vcc) × 2/3 × 4 µs)/L1
which can be simplified to:
•
∆i = (2/9) × (Vcc × tcycle/L1)
The same is true for L2. For this discussion, if Vcc = 12 V, ∆i = 711 mA in both L1 and L2.
Layout Guidelines for TPA300x Series Parts
9
SLOA103
Note that the ripple current can not be completely analyzed in this fashion. When the bridge
traverses its various states, the inductors are actually charged in series. Due to our proprietary
modulation scheme, there are two charge cycles for the inductors for each tcycle. Both of these
charge cycles are equivalent as are the discharge cycles. Relative to the output, the frequency is
effectively doubled. The interaction between the two half bridge legs serves to reduce the ripple
current dramatically.
If we work through this, we see that the inductors are charged in series for 0.66 µs. They then
discharge for 1.33 µs. If the output has the same steady state value of Vcc/3, and we apply
equation 2), it becomes clear that the ripple current is:
•
∆i = [(Vcc - Vcc/3) × 0.66µs]/2 × L1
which simplifies to:
•
∆i = (2/9) × (Vcc × t’cycle)/ (2 × L1)
Note: Due to the output frequency doubling, t’cycle = (tcycle)/2
In this example, If Vcc = 12 V, ∆i = 177 mA
By having the bridge legs interleaved, the ripple current dropped by a factor of 4.
While the switch diagrams and equations illustrate the complexity of the power train, the nodes
involved are reasonably simple. The output filters, the load, Pgnd, Pvcc, and the connections to
the input decoupling capacitors. These node voltages and mesh currents need to be visualized
for proper component placement. As we get beyond the placement task into the layout, the
switch diagrams are useful for analyzing mesh currents to use the PCB traces to cancel noise.
1.1
Specifying the Output Inductors
There are a few important parameters that need to be addressed when specifying the output
inductors. These specifications are:
•
•
•
•
•
•
Inductance value
Current carrying capability
Saturation current
Self resonant frequency
DC resistance (DCR)
Max Volt - time product (V*µs)
The current carrying capability is usually specified as two different values: Irms and Isat. Irms is
clearly the RMS current that the part can withstand. Isat varies from manufacturer to
manufacturer. It is usually specified as the dc current value that causes the inductance to drop
10%. Recall, a totally saturated inductor has a permeability of 1.0 µ0, the same as free space,
while the permeability of the core in an unsaturated state is much higher. Since µ is proportional
to inductance, we can conclude that a saturated inductor has minimal inductance. This minimal
inductance can cause excessive ripple currents in the bridge switches and premature failure of
the TPA300x.
The worst case Irms in our output is the root of the sums of the squares of peak output current as
seen by the load and the RMS ripple current in the inductor. We use the peak output current
because the amplifier may have to source this current to the load for several cycles in clipping.
The saturation current indicates the maximum dc stress that the inductor can handle in a dc
circuit.
10
Layout Guidelines for TPA300x Series Parts
SLOA103
I rms(worst case) +
Ǹ
I peak(worst case) +
ȱ
ȧ
Ȳ
ǒ Ǔ ǒ Ǔ ȳȧ
V CC
ǒ Ǔ
V CC
RI
RI
2
) Di
Ǹ3
ǒ
2
ȴ
ǒA rmsǓ
Ǔ
) Di A peak
2
In our example, if the load has a 4-Ω DCR, this is 3.002 A RMS, and 3.11 A peak.
The self resonant frequency (SRF) of the inductor is the paralell resonant frequency of the part.
This exists due to the parasitic capacitance between the windings. At frequencies above the
SRF, the inductor looks like a coupling capacitor. This frequency should be much higher than the
switching frequency of the amplifier.
•
SRF>10 × fsw
The volt-time product indicates how much stress the inductor can handle in the ac domain.
Recall that any given inductor in a circuit has a BH curve. The curve has a linear region and a
saturated region. For the purpose of this discussion, Isat determines the H axis boundary, and
Bsat determines the B axis boundary. B is proportional to the volt-time product seen by the core.
Most inductor manufacturers do not readily specify this data in their data sheets. I strongly
suggest verifying that the inductor you choose is specified to safely handle the volt time product
applied.
•
Volt × time = worst case on time × Vcc [V × µs]
In our example, the core needs to withstand a max volt × time product of 48V × µs.
The DCR should be kept to a minimum to maximize output swing under load.
Summary of specifications:
•
•
•
•
Irms(worst case) = 3.002 A
Ipeak(worst case) = 3.11 A
SRF> 5 MHz
Max V × t = 48 V × µs
For the sake of margin, I recommend an inductor with an Isat rating of greater than 4.5 A, an Irms
rating of 4 A, an SRF above 2.5 MHz, and a max volt - time product handling of 200 V*µs or
greater. (All of the temperature rise in the core, and most of the temperature rise in the windings
can be derived from the ac flux in the core—the volt-time product. It is worthwhile to specify a
much larger value to keep the ac heating to a minimum)
2
Noise
Noise as it pertains to switching circuitry resides in the fast rising edges of the voltage and
current waveforms at various switching cycles. With the bridge switches constantly switching
and the output inductors charging and discharging, we have both electric and magnetic fields to
mitigate as part of our design task. From a near field standpoint, transmitting magnetic noise in a
magnetic field requires a current loop while transmitting noise in an electric field requires surface
area.
Layout Guidelines for TPA300x Series Parts
11
SLOA103
To minimize the noise transmitters in a given circuit, keep the loop areas of the power train as
small as possible. Ideally, this means that the current into a component flows as close to the
current out of the component as possible. This scenario not only minimizes loop area, but the
magnetic fields associated with the opposing currents are cancelled to a large degree. Bruce
Carsten has developed an excellent seminar series on this topic that can be viewed in most any
of the APEC literature from 1997 on. We also need to keep the nodes from capacitively radiating
energy through large copper areas tied to high dv/dt switching nodes. There has to be some
compromise on copper area since we need a given trace width for a given RMS current through
the trace.
The noise receivers are necessary evils. In this example, the noise receivers are the signal
components around the amplifier: the inputs, the oscillator connections, the shutdown pins,
headphone outputs (if on IC), etc. All we can do in this case is try to minimize the loop area and
keep the copper traces short and narrow.
Oddly, the output and input cables can be either noise transmitters or noise receivers. In most
applications of the TPA300X series, the output cable needs to be addressed as a noise
transmitter.
The higher level EMI textbooks, such as Controlling Radiated Emissions by Design by Michel
Mardiguian, and Noise Reduction Techniques in Electronic Systems by Henry Ott get into
modeling and noise sources. For the purposes of this discussion, I truncate most of the
modeling techniques and assume that any noise above 1 MHz is common to the cables and
traces (a common mode source), and that any noise source below 1 MHz is a differential
source. This is a gross truncation that only works due to the simplicity, small area, and low parts
count of this circuit.
2.1
Grounding
At this stage it is paramount that we acknowledge the need for separate grounds. Noise currents
in the output power stage need to be returned to output noise ground and nowhere else. Were
these currents to circulate elsewhere, they may get into the power supply, the signal ground, etc,
worse yet, they may form a loop and radiate noise. Any of these instances results in degraded
amplifier performance. The logical returns for the output noise currents associated with class D
switching are the respective Pgnd pins for each channel. The switch state diagram illustrates
that Pgnd is instrumental in nearly every switch state. This is the perfect point to which the
output noise ground trace should return. Also note that output noise ground is channel specific.
A two channel amplifier has two mutually exclusive channels and consequently must have two
mutually exclusive output noise ground traces. The layout of the IC offers separate Pgnd
connections for each channel and in some cases each side of the bridge. Output noise
ground(s) must tie to system ground at the PowerPAD exclusively. Signal currents for the
inputs, oscillator, etc need to be returned to quiet ground. This ground only ties to the signal
components and the Agnd pin(s). Agnd then ties to the PowerPAD. System ground is the
connection between the power pad and the main decoupling capacitors. These ground
connections should all tie together in a Kelvin or star fashion at the PowerPAD connection.
Ground planes are strongly discouraged due to the noise currents in the ground plane having
the ability to circulate wherever they choose. The main decoupling capacitor may be fed from a
ground plane, but system ground, output noise ground, and quiet ground must not tie to the
ground plane. The PowerPAD requires as much copper connection as possible for heat
dissipation. This copper flood is usually connected to system ground.
12
Layout Guidelines for TPA300x Series Parts
SLOA103
3
Component Placement
Now that we have mapped the current paths, we have a good idea of how current circulates in
the power train. The placement task is greatly simplified. The first elements to be placed are the
power train elements. When placing these elements, it is important to remain focused on the
whole amplifier circuit. Clearly the Vcc decoupling capacitors need to be close to the Pvcc and
Pgnd pins. The output filters need to be close to the OUTP and OUTN pins. The load needs to
be close to the output filters. However, the signal level pins of the IC also need real estate
consideration. The inputs need to be routed away from the power train, yet they need to remain
close to the IC to maintain a small loop area to maximize the amplifier’s noise immunity. So just
when we think we’ve got it figure out, there is a compromise.
3.1
Design Example
3.1.1
Design Example Constraints
Below, I have included an example of the schematic, placement, and layout of a basic amplifier
application. The IC featured is the TPA3004D2. I have explained the major decisions throughout
the process. The constraints for this placement were:
•
4 layer board, 1-oz. copper (1.4 mil thick) on each layer. Inside layers are reserved for +Vcc
and ground flood, nothing else
•
Inputs and outputs combined on a two row Molex Cgrid connector. Pin placement and pin
count is negotiable.
•
Component placement allowed only on top of the PCB
•
Amplifier inputs are single ended
•
Amplifier circuitry must occupy minimal real estate
•
4-Ω speakers
Layout Guidelines for TPA300x Series Parts
13
SLOA103
L4
15 µH
+VCC
FB4
L3
15 µH
C6
0.47 µF,
0805
C22
0.47 µF,
0805
C26
220 pF
C23
0.47 µF,
0805
C25
220 pF
FB3
REFGND
13
14
15
16
17
LOUTP
VOLUME
ROUT+
14
ROUT -
C10
0.01 µF
13
R+TO_PA
BSPR
ROUTP
ROUTP
PGNDR
ROUTN
ROUTN
PGNDR
VARMAX
12
BSNL
R12
22 kΩ
VARDIF
11
LOUTP
10
VREF
PGNDL
R13
22 kΩ
AVDDREF
PGNDL
9
LINN
18
19
20
21
22
23
8
LOUTN
7
IC1
TPA3004D2
LOUTN
1 µF
LINP
C9
0.01 µF
12
11
L+TO_PA
BSPL
6
PVCCL
1 µF
+VCC
C28
0.47 µF,
0805
36
VCLAMPR
MODE_OUT 35
MODE 34
AVCC 33
VAROUTR 32
31
VAROUTL
FADE_z AGND 30
AVDD 29
COSC 28
ROSC 27
AGND 26
VCLAMPL 25
PVCCL
5
PVCCL
C4
C3
V2P5
Audio OUT R+
10
9
C21
1 µF
MODE
8
MODE
7
+VCC
6
5
C29
0.47 µF
4
3
2
1
R11
120 kΩ
C19
220 pF
C20
0.01 µF
J1
1
C18
1 µF
24
4
L+TO_PA
C5
220 pF
PVCCR
BSNR
SHUTDOWN
2
RINN
3 RINP
C1
1 µF
PVCCL
C2
1 µF
R+TO_PA
PVCCR
1
41
40
39
PVCCR
38
PVCCR
37
C8
0.01 µF
48
47
46
45
44
43
42
V2P5
Audio OUT R -
LOUT+
C11
0.01 µF
LOUT +VCC
+VCC
+
C16
0.47 µF, 25 V
C7
0.47 µF, 0805
L2
15 µH
L1
15 µH
C12
0.47 µF, 0805
FB2
Audio OUT L+
C13
0.47 µF, 0805
C14
220 pF
C17
0.47 µF, 0805
C15
220 pF
Audio OUT L -
FB1
Figure 13. Schematic
3.1.2
Placement
In the component placement of the TPA3004D2 circuit, we first place the header. This header
accommodates the outputs and the inputs. Precautions must be taken to avoid crosstalk
between the output and the input sections. I have segmented the header such that the outputs
are on one extreme end and the inputs are on the other extreme end. If we could place Rout+
next to Rout - , we could maximize the cancellation of the noise fields around Rout+ and Rout by minimizing the loop area between Rout+ and Rout - . The same holds true for Lout+ and
Lout - . Additionally, if we could place ground connections between the right and left connections,
this would further reduce the chance of right or left channel noise coupling into the inputs.
So we have some tentative notions on how the output structure should be positioned. The
outputs should be next to each other, each output should be guarded, the inputs should be on
the other end of the header, and the output loop areas should be as small as possible.
On the schematic, if we spend a little time envisioning the output traces, we quickly realize a few
things, namely: if the output traces and output ground are to be routed for a short trace length,
and minimal loop area, one side of the IC is trapped in the output area. This is either pins 25 thru
36, or pins 1 thru 12. Pins 1 thru 12 are the signal inputs, and as such they are far more noise
sensitive than pins 25 thru 36. I have chosen to trap pins 25 thru 36 in the output area and leave
the inputs as far from the output current paths as possible.
The pinout of the output side of the header was an iterative process. It took a couple of iterations
to get the pins to flow without traces having to jump over one another. The header was finally
pinned out as:
14
Layout Guidelines for TPA300x Series Parts
SLOA103
Table 1. Header Pinout-Output Side
PIN NUMBER
NODE
1
Output ground
2
Right out +
3
Right out –
4
Output ground
5
Left out +
6
Left out –
7
Output ground
8
NC
9
Mode
10
Quiet ground
11
Left + input
12
Quiet ground
13
Right + input
14
Quiet ground
Once the schematic looks reasonable, we move on to the placement task. It is worthwhile to
note that the output inductor is a coupling cap for all purposes beyond its self - resonant
frequency. The ferrite beads (FB1 thru FB4) should be located as near to the output leads as
possible in this example. They are used as secondary filters to filter out noise above the self
resonant frequency of the output inductor. The shunt capacitors (C22, C23, C26, C25, C13, C14,
C15, and C17) provide a path for noise energy to output noise ground. This helps with noise
reduction both at the output inductors and at the ferrite beads. The shunt capacitors (C14, C15,
C25, C26) need to be close the both the ferrite beads and the output pins of the ‘3004D2 IC. The
shunt capacitors (C13, C17, C22, and C23) need to be between the output inductor and the
ferrite beads. All shunt capacitors need to be tied to the output noise ground with the shortest,
lowest impedance traces possible.
Wrapping up the placement of the output structure, we still have the bootstrap capacitors (C8,
C9, C10, and C11) and the PVcc capacitors (C6, C7, C12, and C28). These capacitors need to
be placed as close to the IC as possible. Noise currents flow through the bootstrap capacitors as
the high side switches in the output bridge are switched on and off. Similarly noise currents flow
through the PVcc capacitors as the bridge transitions through its switching states. In the
positioning sketch, I compromised a little trace length in the bootstrap capacitors to allow the
best possible placement of the PVcc capacitors. From the switching diagrams above, these
capacitors are a vital part of the power train and need to have as little loop area as possible. The
bootstrap capacitors are also a vital path, but the power currents through the switches have to
flow from the PVcc capacitors. The bootstrap capacitors were given second priority in the
placement.
C16 is the main decoupling capacitor for the whole circuit. The PVcc feeders and the Avcc
feeder should connect to C16 through a Kelvin or ‘star’ connection. This eliminates any noise
currents on PVcc from getting into the signal components tied to AVcc. The ground connection
from C16 is the system ground. This should tie from C16 to the PowerPAD. The pad of C16
may tie to the system ground plane as this is the purest point to reference.
Layout Guidelines for TPA300x Series Parts
15
SLOA103
The trapped components that tie to the trapped pins are C18, C19, C20, C21, C29, and R11.
These components form the relaxation oscillator that determines the switching frequency of the
amplifier, the clamp circuits for the right and left channel, and the decoupling for the 5V output
line. The relaxation oscillator components (C19, R11) and the Avcc decoupling capacitor (C29)
get first priority in placement. These parts need to be located as close to their respective pins as
possible. The ground connection for all trapped components is to be a quiet ground whose only
tie to system ground is at the power pad of the IC. All other trapped components are then placed
as close to their respective pins as possible.
The only components left are the input components (C1 thru C5, R12, and R13). These
components are placed as near to their respective pins as possible. All grounds pertaining to the
input are to be on a quiet ground whose only tie to system ground is at the power pad.
The sketch below illustrates how these steps were followed through the placement task. For
scaling purposes, the header is on a 0.100” grid. The asymptotic box around the entire
positioning is about 2.0” x 2.2”.
Figure 14. PCB Layout
16
Layout Guidelines for TPA300x Series Parts
SLOA103
3.2
3.2.1
PCB Layout
Trace, Via, and Wire Consideration
Similar to the component placement, the first portion of the circuit to be routed is the output
portion. It is easiest to start at one end and work through the other. I chose to start at the output
header and work back through the IC. For maximal field cancellation through all switching
states, the best layout we can have is Out+ next to Out - , with output noise ground flowing under
these traces back to the IC. From the specifications called out above, the board will have 1 oz
copper on all layers. The load impedance is 4 Ω. If the IC can deliver 10 W RMS into a 4-Ω load,
there is approximately 1.6 A RMS flowing through each output trace at the fundamental
frequency. Additionally, in the traces between the TPA300x and the output inductors, the RMS
current is somewhat larger. This is due to the ripple current flowing into the output inductor of
∆I (p - p) where ∆I = (Vin - Vout) × ∆t/L. The RMS contribution of this ripple current is
approximately ∆I√12. While we should not forget about this ripple current, it is negligible.
Per Appendix A, a good safe current density in the output trace is 100 CM/A (circular mils per
amp) or greater. If we look down the 100 CM/A column, our 1.6 A RMS current falls right on the
values corresponding to #28 AWG wire. In 1 oz copper, we can use about 90 mil trace width
(2.3mm). This is only a guideline. It is always safer to use wider traces. The PVcc lines should
be much thicker to minimize voltage ripple. No current density on the PC board should ever fall
below 30 CM/A for any trace length. The current density in the output cable from the header
should be much higher to avoid losses. A good current density for the wire harness is 300CM/A.
From the table this corresponds to a #23 AWG wire. For design purposes, #22 AWG wire is
much more readily available.
3.2.2
Routing
The routing task should start at the output pins. The output filters, inductors, caps etc should be
routed first. This may need to be an iterative process to get the noise currents returned to output
noise ground through as short and wide of a trace as possible. Note that this same trace is used
to shield the output traces, inductors, etc.
The next traces to be considered are the Pvcc traces. Recall from the switch diagrams that Pvcc
is the critical node in the power train. In this example there are 4 different connections to Pvcc
(C6, C7, C12, and C28). We need a very low impedance trace to all 4 of these connection
points. This trace should be considered noisy in that it carries ripple current to the power train.
Consequently it should be routed as far away from the amplifier inputs as possible. It should also
have a ground trace flowing under it.
The next task is to route the trapped pins. These pins have a separate connection to system
ground. While it is difficult to minimize loop area, we can keep the components as close to the IC
as possible, and flood the underside of these components with quiet ground.
The last task is to route the inputs. These pins are the most susceptible to noise. They should be
surrounded by as much quiet ground copper as possible. In this case, I routed guard traces
around and between the inputs, and quiet ground under the inputs. This should keep any
incident noise out of the inputs.
Appendix B contains printouts of each layer of the PCB. These printouts can be photocopied to
transparencies for viewing purposes.
Layout Guidelines for TPA300x Series Parts
17
SLOA103
A good trick that I learned early on in power electronics layout is to hold the final board up to a
light source. You should not see a lot of light coming through the power train areas. If you do,
you probably have excessive loop area and (or) not enough grounded copper. That results in
excessive noise. This is, of course, a loose guideline to be used only after good placement and
routing techniques have been used.
4
EMC-The Final Word: Did Those Tricks Really Work?
4.1
The Arsenal
Before undertaking the mitigation task, we need to put together an arsenal. Most of the time the
EMI test chamber is located somewhere else and very seldom do they have all the comforts of
your home lab. I strongly suggest bringing along a few items to assist in mitigation and
modeling. These items include:
18
•
Bruce Carsten’s EMI probe—Plans for this probe are available at www.bcarsten.com and
included in Appendix C of this article. It allows an ordinary analog oscilloscope to be used to
pinpoint the source of radiated energy.
•
Copper Tape—It is nice because it can quickly be used to create a stick on ground plane.
Note that terminations to the copper tape need to be soldered and the adhesive should not
be assumed to be either a good insulator or a good conductor. 3M is a good source for this
material.
•
Ferrites—I would suggest bringing along a kit consisting of various high current beads,
toroids, surface mount common mode filters, clam shells, etc., in various ferrite materials.
The clamshells are often too expensive for mass production; however, they are a very fast
way to determine a common mode radiator. If you suspect that a cable is radiating, place a
clam shell around it. If the levels drop, your suspicion was correct. You should then begin
looking for the source that is coupling the energy into the cable.
•
Spare parts—as the models grow in complexity, you may wish to try different inductors from
different manufacturers, all having the proper ratings for your circuitry. Perhaps manufacturer
A has a better shielded part than Manufacturer B.
•
Spare boards—you might get into a lengthy modeling/modification that is irreversible. A few
virgin spares are always a good idea.
•
Solder wick—for desoldering and ground strap, trace-thickening agent, etc. Solder wick is a
great low impedance conductor and it remains flexible until it is consumed or in the case of a
wiring mod, tinned.
•
Exacto knife and spare blades—just in case you need to alter a current path on the board
•
Dremel tool and a good selection of bits—just in case you REALLY need to alter a current
path.
•
Soldering Irons—bring a couple. A small one for surface-mount work, a large one for
grounding large copper masses, etc.
•
Solder—it is the glue that holds our world together.
•
Various electronic tools—Cutters, screwdrivers, picks, pliers, etc.
Layout Guidelines for TPA300x Series Parts
SLOA103
The Mitigation Task
The layout included in this article is very similar to the final layout of an internal project that we
recently did. The goal of this project was to pass the EMI limits put forth by CISPR22. Initially the
layout had a ground plane where all connections to ground returned. There was no
segmentation, or attempts to isolate output noise ground, quiet ground and system ground. The
outputs were lengthy, employed little or no field cancellation and had no ground running
underneath them. I have included an initial plot of the radiated noise from this layout:
80
70
60
Level - [dB µ V/m]
4.2
50
40
30
20
10
0
30 M
50 M 70 M 100 M
200 M 300 M
500 M
1G
f - Frequency - Hz
Figure 15. Initial Layout Noise
The first change I made to this layout was to segment the groundplane layer such that all output
noise currents returned to Pgnd and then tied to the power pad. The results of this segmentation
are shown in Figure 16.
Layout Guidelines for TPA300x Series Parts
19
SLOA103
80
70
Level - [dB µ V/m]
60
50
40
30
20
10
0
30 M
50 M 70 M 100 M
200 M 300 M
500 M
1G
f - Frequency - Hz
Figure 16. Noise-First Segmentation Change
From this point, I decided to investigate the broadband noise source around 150 MHz. I did this
with the use of Bruce Carsten’s EMI probe. (Plans for this probe are available at
www.bcarsten.com and included in Appendix C). I regularly use this probe in mitigating EMI
noise. It is easy to build, works best with an oscilloscope, and gets within 1/32” of the offender. I
strongly recommend this probe for finding noise sources on PCB’s. The probe showed that the
thin trace connecting the Pvcc decoupling capacitors was radiating fiercely. I added a few
MLCCs, staggered along the length of the trace, to get the plot shown in Figure 17.
80
70
Level - [dB µ V/m]
60
50
40
30
20
10
0
30 M
50 M 70 M 100 M
200 M 300 M
500 M
1G
f - Frequency - Hz
Figure 17. Noise-With Staggered MLCCs Along the Trace Length
20
Layout Guidelines for TPA300x Series Parts
SLOA103
Note the change in signature. While the MLCC’s did not resolve the problem, they did alter the
signature significantly. This is a strong hint that we are on the right track in assuming that the
Pvcc trace is the offender. I did not have the ability to reroute the offending trace properly;
however, we did add a common mode choke to the outputs on the theory that the noisy Pvcc
trace was combining with noise coming through the output filters. The results of this are shown
in Figure 18.
80
70
Level - [dB µ V/m]
60
50
40
30
20
10
0
30 M
50 M 70 M 100 M
200 M 300 M
500 M
1G
f - Frequency - Hz
Figure 18. Noise Signature-After Adding a Common Mode Choke
Later, when the offending Pvcc trace was thickened and rerouted, we passed the CISPR 22
requirements with 5 dB of margin in the 150 MHz area and much more margin everywhere else.
Clearly there is some method to the madness. Four of the five nuisance peaks were brought
down to passable levels by simply segmenting the ground layer. With some analysis and first
order modeling, we were able to bring the remaining noise peak down to nearly passing. Finally,
by rerouting the Pvcc trace and minimizing its loop area, the problem was resolved.
While the techniques in this article were applied to the TPA300x series of parts, they are useful
in any switchmode amplifier or power converter. Power train analysis is often lengthy, but vital to
the designer’s understanding of how the circuit works and should be performed on any power
converter before the design stage is started. From this point the designer can begin the design
process. The data sheet supports the paper design process and the calculation of values. This
collateral should serve to support the PC board level design and the debugging of the design as
it pertains to EMI. If care is taken in the layout task, and these guidelines are understood and
adhered to, the EMI stage of the design should require minimal change. I strongly recommend
allowing enough time in the product schedule to allow for one full EMI screening and a quick
respin to implement any fixes. As the output power level increases, these techniques become
increasingly important. I have written this based on my own past design experiences and with
customers. All of these techniques are tried and true. The extent to which they are practiced and
enforced determines their success.
Layout Guidelines for TPA300x Series Parts
21
SLOA103
5
References
1. Carsten, Bruce. Professional Advancement courses and seminars at APEC, etc. Appears
in Apec literature from 1995 on.
2. Mardiguian, Michel. Controlling Radiated Emissions By Design, Second Edition. Boston:
Kluwer Academic Publishers, 2001.
3. Ott, Henry. Noise Reduction Techniques in Electronic Systems. New York: Wiley, 1988.
4. Texas Instrument’s TPS3004D2 data sheet (SLOS407).
6
Trademarks
1. PowerPAD is a trademark of Texas Instruments
2. All other trademarks are the property of their respective owners.
22
Layout Guidelines for TPA300x Series Parts
SLOA103
Appendix A
A.1
Copper Wire Current Density
Current Density Table
See the following page for the current density table.
Layout Guidelines for TPA300x Series Parts
23
Paul L. Schimel
rev 3/3/2003
COPPER WIRE
Equivalent
Equivalent
Equivanlent
Equivalent
Cross section Cross Section Cross Section Cross Section
in 1/2 oz copper in 1 oz copper in 2 oz copper in 4 oz Copper
Solid Wire
Cross Section Cross Section Cross section 1/2oz Cu=.7 mil 1oz cu=1.4 mil 2oz cu=2.8 mil 4oz cu=5.6 mil
AWG #
Diameter (mil)
Cir mil
Square mil
Square mm
Width (mil)
Width (mil)
Width (mil)
Width (mil)
40
3.15
9.9
7.78
0.0050
11.11
5.55
2.78
1.39
39
3.54
12.5
9.82
0.0063
14.02
7.01
3.51
1.75
38
3.96
15.7
12.33
0.0080
17.62
8.81
4.40
2.20
37
4.45
19.8
15.55
0.0100
22.22
11.11
5.55
2.78
36
5.00
25.0
19.63
0.0127
28.05
14.02
7.01
3.51
35
5.61
31.5
24.74
0.0160
35.34
17.67
8.84
4.42
34
6.31
39.8
31.26
0.0202
44.66
22.33
11.16
5.58
33
7.08
50.1
39.35
0.0254
56.21
28.11
14.05
7.03
32
7.95
63.2
49.64
0.0320
70.91
35.46
17.73
8.86
31
8.93
79.7
62.60
0.0404
89.42
44.71
22.36
11.18
30.00
10.05
101
79.33
0.0512
113.32
56.66
28.33
14.17
29
11.27
127
99.75
0.0644
142.49
71.25
35.62
17.81
28
12.65
160
125.66
0.0811
179.52
89.76
44.88
22.44
27
14.21
202
158.65
0.1024
226.64
113.32
56.66
28.33
26
15.94
254
199.49
0.1287
284.99
142.49
71.25
35.62
25
17.89
320
251.33
0.1621
359.04
179.52
89.76
44.88
24
20.10
404
317.30
0.2047
453.29
226.64
113.32
56.66
23
22.56
509
399.77
0.2579
571.10
285.55
142.77
71.39
22
25.34
642
504.23
0.3253
720.32
360.16
180.08
90.04
21
28.46
810
636.17
0.4104
908.82
454.41
227.20
113.60
20
31.94
1020
801.11
0.5168
1144.44
572.22
286.11
143.05
19
35.92
1290
1013.16
0.6537
1447.38
723.69
361.84
180.92
18
40.25
1620
1272.34
0.8209
1817.63
908.82
454.41
227.20
17
45.28
2050
1610.06
1.0387
2300.09
1150.05
575.02
287.51
16
50.79
2580
2026.33
1.3073
2894.75
1447.38
723.69
361.84
15
57.10
3260
2560.40
1.6519
3657.71
1828.85
914.43
457.21
14
64.11
4110
3227.98
2.0826
4611.41
2305.70
1152.85
576.43
13
71.97
5180
4068.36
2.6247
5811.94
2905.97
1452.99
726.49
12
80.81
6530
5128.65
3.3088
7326.64
3663.32
1831.66
915.83
11
90.72
8230
6463.82
4.1702
9234.03
4617.02
2308.51
1154.25
10
101.98
10400
8168.13
5.2698
11668.76
5834.38
2917.19
1458.60
9
114.46
13100
10288.71
6.6379
14698.15
7349.08
3674.54
1837.27
8
128.45
16500
12959.06
8.3607
18512.94
9256.47
4628.24
2314.12
7
144.22
20800
16336.27
10.5395
23337.53
11668.76
5834.38
2917.19
6
162.17
26300
20655.95
13.3264
29508.51
14754.25
7377.13
3688.56
5
181.93
33100
25996.66
16.7720
37138.08
18569.04
9284.52
4642.26
4
204.21
41700
32751.08
21.1297
46787.25
23393.63
11696.81
5848.41
3
229.35
52600
41311.91
26.6528
59017.01
29508.51
14754.25
7377.13
2
257.68
66400
52150.39
33.6453
74500.56
37250.28
18625.14
9312.57
1
289.31
83700
65737.77
42.4114
93911.10
46955.55
23477.78
11738.89
106000
83252.14
53.7109
118931.62
59465.81
29732.91
14866.45
ought (0)
325.58
2ought (00)
364.69
133000
104457.87
67.3920
149225.53
74612.76
37306.38
18653.19
3ought (000)
409.88
168000
131946.78
85.1268
188495.40
94247.70
47123.85
23561.93
4ought (0000)
460.43
212000
166504.27
107.4219
237863.24
118931.62
59465.81
29732.91
Equivalent
Cross Section
in 6 oz copper
6oz cu=8.4 mil
Width (mil)
0.93
1.17
1.47
1.85
2.34
2.95
3.72
4.68
5.91
7.45
9.44
11.87
14.96
18.89
23.75
29.92
37.77
47.59
60.03
75.73
95.37
120.61
151.47
191.67
241.23
304.81
384.28
484.33
610.55
769.50
972.40
1224.85
1542.75
1944.79
2459.04
3094.84
3898.94
4918.08
6208.38
7825.93
9910.97
12435.46
15707.95
19821.94
30 cir mil/A
Current
0.33
0.42
0.52
0.66
0.83
1.05
1.33
1.67
2.11
2.66
3.37
4.23
5.33
6.73
8.47
10.67
13.47
16.97
21.40
27.00
34.00
43.00
54.00
68.33
86.00
108.67
137.00
172.67
217.67
274.33
346.67
436.67
550.00
693.33
876.67
1103.33
1390.00
1753.33
2213.33
2790.00
3533.33
4433.33
5600.00
7066.67
1.) FOR THE SAME RUN IN ALUMINUM WIRE, TO GET THE SAME CONDUCTOR RESISTANCE REQUIRES 160% OF THE CROSS SECTION OF COPPER. (Al=(CuAWG-2))
2.) THE TEMCO FOR Al AND Cu ARE VERY SIMILAR, SO THIS APPLIES OVER ALL TEMP.
Temperature Classifacation
(per UL1446)
Additional Notes:
Designator
Hot spot temp
Resistivity of Cu:
B
130
(deg C)
S(T)=(1.7241*10^--6)*(1+.0039*(T-20))
F
155
T is temp in deg C
H
180
S is Resistivity in OHM*centimeters (cm)
N
200
Resistance= [S(Tx)*Length(cm)]/Cross Section(cm^2)
R
220
S
240
Current Density:
1000 cir mil per amp is reserved for absolute worst case conditions. IE: high ambient temp, no air circulation around conductors, minimal self heating
500 cir mil per amp is a good starting point. With a little airflow, reasonable max ambient temp (say 85 deg C), and conductor thickness thinner than the
depth of penetration for the ac frequencies through the conductor, this is a reasonable starting point.
300 cir mil per amp: with good airflow, and paying close attention to the skin effect issues, this current density should keep the temp rise in a conductor less than
20 degrees or so. #10 AWG wire is known good for 30 A of current in conduit pipe, in a residence, with a max ambient of 65 deg C. This works out to about 300 cir mil/A.
100 cir mil per amp is a worst case guideline for high reliability PWB traces. Bottleneck may be thinner, however the surrounding connected trace must be heavy enough
to pull the heat out of the bottlenecked area. Bottleneck current densities should not be less than 30 cir mil/amp under any circumstance.
100 cir mil/A
Current
0.10
0.13
0.16
0.20
0.25
0.32
0.40
0.50
0.63
0.80
1.01
1.27
1.60
2.02
2.54
3.20
4.04
5.09
6.42
8.10
10.20
12.90
16.20
20.50
25.80
32.60
41.10
51.80
65.30
82.30
104.00
131.00
165.00
208.00
263.00
331.00
417.00
526.00
664.00
837.00
1060.00
1330.00
1680.00
2120.00
300 cir mil/A
Current
0.03
0.04
0.05
0.07
0.08
0.11
0.13
0.17
0.21
0.27
0.34
0.42
0.53
0.67
0.85
1.07
1.35
1.70
2.14
2.70
3.40
4.30
5.40
6.83
8.60
10.87
13.70
17.27
21.77
27.43
34.67
43.67
55.00
69.33
87.67
110.33
139.00
175.33
221.33
279.00
353.33
443.33
560.00
706.67
500 cir mil/A 1000 cir mil/A
Current
Current
0.02
0.01
0.03
0.01
0.03
0.02
0.04
0.02
0.05
0.03
0.06
0.03
0.08
0.04
0.10
0.05
0.13
0.06
0.16
0.08
0.20
0.10
0.25
0.13
0.32
0.16
0.40
0.20
0.51
0.25
0.64
0.32
0.81
0.40
1.02
0.51
1.28
0.64
1.62
0.81
2.04
1.02
2.58
1.29
3.24
1.62
4.10
2.05
5.16
2.58
6.52
3.26
8.22
4.11
10.36
5.18
13.06
6.53
16.46
8.23
20.80
10.40
26.20
13.10
33.00
16.50
41.60
20.80
52.60
26.30
66.20
33.10
83.40
41.70
105.20
52.60
132.80
66.40
167.40
83.70
212.00
106.00
266.00
133.00
336.00
168.00
424.00
212.00
ohm/foot
25 deg c
1.0679787990
0.8458392088
0.6734388605
0.5339893995
0.4229196044
0.3356504797
0.2656530178
0.2110377267
0.1672941473
0.1326598508
0.1046830704
0.0832518906
0.0660811882
0.0523415352
0.0416259453
0.0330405941
0.0261707676
0.0207720827
0.0164688319
0.0130530742
0.0103656766
0.0081961164
0.0065265371
0.0051575562
0.0040980582
0.0032432485
0.0025725037
0.0020411178
0.0016191409
0.0012846890
0.0010166337
0.0008070985
0.0006407873
0.0005083168
0.0004020148
0.0003194257
0.0002535489
0.0002010074
0.0001592318
0.0001263201
0.0000997452
0.0000794962
0.0000629345
0.0000498726
Via Cross Section Table
(Cir Mil)
Via I.D. (mil)
1/2 oz Cu
1 oz Cu
5
15.96
35.84
10
29.96
63.84
15
43.96
91.84
20
57.96
119.84
25
71.96
147.84
30
85.96
175.84
35
99.96
203.84
40
113.96
231.84
45
127.96
259.84
50
141.96
287.84
via table assumes via wall thickness is the same as
ohm/foot
105 deg c
1.3947772249
1.1046635621
0.8795092055
0.6973886124
0.5523317810
0.4383585564
0.3469420735
0.2756146612
0.2184856729
0.1732533818
0.1367157874
0.1087267286
0.0863018408
0.0683578937
0.0543633643
0.0431509204
0.0341789468
0.0271282800
0.0215082469
0.0170472772
0.0135375437
0.0107041043
0.0085236386
0.0067357534
0.0053520521
0.0042356732
0.0033596824
0.0026656939
0.0021145933
0.0016778001
0.0013277206
0.0010540683
0.0008368663
0.0006638603
0.0005250302
0.0004171690
0.0003311342
0.0002625151
0.0002079562
0.0001649737
0.0001302669
0.0001038218
0.0000821922
0.0000651335
2 oz Cu
4oz Cu
87.36
237.44
143.36
349.44
199.36
461.44
255.36
573.44
311.36
685.44
367.36
797.44
423.36
909.44
479.36
1021.44
535.36
1133.44
591.36
1245.44
Cu thickness on PWB
SLOA103
Appendix B
B.1
PCB Layers
Board Layers
See the following pages for the PCB layers.
25
SLOA103
Appendix C
C.1
Bruce Carsten Associates, Inc.
Appnote
See the following pages for Bruce Carsten Associates, Inc. Appnote
31
- Appnote
Page 1 of 6
Introduction || Seminars || Services || EMI SnifferTM Probe || Other Products || Resources || Order
Introduction
Seminars
Services
EMI SnifferTM Probe
Other Products
Resources
Order
APPNOTE
EMI SNIFFER TM PROBE - APPLICATION NOTE
CONTACT US
Tel: (541) 745-3935
Fax: (541) 745-3923
The EMI SnifferTM Probe is used with an oscilloscope to locate and identify magnetic field
sources of electromagnetic interference (EMI) in electronic equipment. The probe consists
of a miniature 10 turn pickup coil located in the end of a small shield tube, with a BNC
connector provided for connection to a coaxial cable.
6410 NW Sisters Pl.
Corvallis, OR 97330
The EMI SnifferTM Probe output voltage is essentially proportional to the rate of change of
the ambient magnetic field, and thus to the rate of change of nearby currents.
info@bcarsten.com
The principal advantages of the EMI SnifferTM Probe over simple pickup loops are:
1.
2.
3.
4.
Spatial resolution of about a millimeter;
Relatively high sensitivity for a small coil;
A 50 ohm source termination to minimize cable reflections with unterminated scope
inputs;
Faraday shielding to minimize sensitivity to electric fields.
The EMI SnifferTM Probe was developed to diagnose sources of EMI in switchmode power
converters, but it can also be used in high speed logic systems and other electronic
equipment.
SOURCES OF EMI
Rapidly changing voltages and currents in electrical and electronic equipment can easily
result in radiated and conducted noise. Most EMI in switchmode power converters is thus
generated during switching transients, when power transistors are turned on or off.
Conventional scope probes can readily be used to see dynamic voltages, which are the
principal sources of common mode conducted EMI. (High dV/dt can also feed through
poorly designed filters as normal mode voltage spikes, and may radiate fields from a circuit
without a conductive enclosure.)
Dynamic currents produce rapidly changing magnetic fields which radiate far more easily
than electric fields, as they are more difficult to shield. These changing magnetic fields can
also induce low impedance voltage transients in other circuits, resulting in unexpected
normal and common mode conducted EMI.
These high dI/dt currents and resultant fields can not be directly sensed by voltage probes,
but are readily detected and located with the EMI SnifferTM Probe. While current probes can
sense currents in discrete conductors and wires, they are of little use with printed circuit
traces, or in detecting dynamic magnetic fields.
PROBE RESPONSE CHARACTERISTICS
The EMI SnifferTM Probe is sensitive to magnetic fields only along the probe axis. This
directionality is useful in locating the paths and sources of high dI/dt currents. The
resolution is usually sufficient to locate which trace on a printed circuit board, or which lead
on a component package, is conducting the EMI generating current.
For "isolated" single conductors or PC traces, the Probe response is greatest just to either
http://www.bcarsten.com/?page=appnote
5/15/2003
- Appnote
Page 2 of 6
side of the
conductor where the magnetic flux is along the probe axis. (Probe response may be a little
greater with
the axis tilted
towards the
center of the
conductor.) As
shown in
Figure 1, there
is a sharp
response null
in the middle
of the
conductor, with
a 180 degree
phase shift to
either side and
a decreasing
response with
distance. The
response will
increase on
the inside of a
bend where
the flux lines
are crowded together, and is reduced on the outside of a bend where the flux lines spread
apart.
When the return current is in an adjacent parallel conductor, the Probe response is greatest
between the
two conductors
as shown in
Figure 2.
There will be a
sharp null and
phase shift
over each
conductor, with
a lower peak
response
outside the
conductor pair,
again
decreasing
with distance.
The response
to a trace with
a return
current on the
opposite side
of the board is
similar to that
of a single isolated trace, except that the probe response may be greater with the Probe
axis tilted away from the trace. A "ground plane" below a trace will have a similar effect, as
there will be a counter-flowing "image" current in the ground plane.
http://www.bcarsten.com/?page=appnote
5/15/2003
- Appnote
Page 3 of 6
The Probe frequency response to a uniform magnetic field is shown in Figure 3. Due to
large variations in field strength around a conductor, the Probe should be considered as a
qualitative indicator only, with no attempt made to "calibrate" it. The response rolloff near
300 MHz is due to the pickup coil inductance of 75nH driving the total terminated
impedance of 100 ohms, and the mild resonant peaks (with a 1 M ohm scope termination)
at multiples of 80 MHz are due to transmission line reflections.
PRINCIPLES OF PROBE USE
The EMI SnifferTM Probe is used with at least a two channel scope. One channel is used to
view the noise whose source is to be located (which may also provide the scope trigger),
and the other channel is used for the EMI SnifferTM Probe. The probe response nulls make
it inadvisable to use this scope channel for triggering.
A third scope trigger channel can be very useful, particularly if it is difficult to trigger on the
noise. Transistor drive waveforms (or their predecessors in the upstream logic) are ideal for
triggering; they are usually stable, and allow immediate precursors of the noise to be
viewed.
Start with the Probe at some distance from the circuit with the Probe channel at maximum
sensitivity. Move the probe around the circuit, looking for "something happening" in the
circuit's magnetic fields at the same time as the noise problem. A precise "time domain"
correlation between EMI noise transients and internal circuit fields is fundamental to the
http://www.bcarsten.com/?page=appnote
5/15/2003
- Appnote
Page 4 of 6
diagnostic approach.
As a candidate noise source is located, the Probe is moved closer while the scope
sensitivity is decreased to keep the Probe waveform on-screen. It should be possible to
quickly bring the probe down to the PC board trace (or wiring) where the Probe signal
seems to be a maximum. This may not be near the point of EMI generation, but it should be
near a PC trace or other conductor carrying the current from the EMI source. This can be
verified by moving the Probe back and forth in several directions; when the appropriate PC
trace is crossed at roughly right angles, the probe output will go through a sharp null over
the trace, with an evident phase reversal in probe voltage on each side of the trace (as
noted above).
This EMI "hot" trace can be followed (like a bloodhound on the scent trail) to find all or
much of the EMI generating current loop. If the trace is hidden on the back side (or inside)
of the board, mark it's path with a felt pen and locate the trace on disassembly, on another
board, or on the artwork. From the current path and the timing of the noise transient, the
source of the problem usually becomes almost self-evident.
Some of the more common EMI problems are discussed in this short form ap-note to
illustrate typical probe uses.
TYPICAL dI/dt EMI PROBLEMS
Rectifier Reverse Recovery
Reverse recovery of rectifiers is the most common source of dI/dt related EMI in power
converters; the charge stored in P-N junction diodes during conduction causes a
momentary
reverse current
flow when the
voltage reverses.
This reverse
current may stop
very quickly (<1
ns) in diodes with
a "snap" recovery
(more likely in
devices with a PIV
rating of less than
200V), or the
reverse current
may decay more
gradually with a
"soft" recovery.
Typical EMI
SnifferTM Probe
waveforms for
each type of
recovery are shown in Fig. 4.
The sudden change in current creates a rapidly changing magnetic field, which will both
radiate external fields and induce low impedance voltage spikes in other circuits. This
reverse recovery may "shock" parasitic L-C circuits into ringing, which will result in
oscillatory waveforms with varying degrees of damping when the diode recovers. A series
R-C damper circuit in parallel with the diode is the usual solution.
Output rectifiers generally carry the highest currents, and are thus the most prone to this
problem, but this is often recognized and they may be well snubbed. It is not uncommon for
unsnubbed catch or clamp diodes to be more of an EMI problem. (The fact that a diode in
an R-C-D snubber may need its own R-C snubber is not always self evident, for example).
The problem can usually be identified by placing the EMI SnifferTM Probe near a rectifier
lead. The signal will be strongest on the inside of a lead bend in an axial package, or
between the anode and cathode leads in a TO-220, TO-247 or similar type of package, as
shown in Fig. 4.
Using "softer" recovery diodes is a possible solution, and Schottky diodes are ideal in low
voltage applications. However, it must be recognized that a P-N diode with soft recovery is
also inherently lossy (while a "snap" recovery is not), as the diode simultaneously develops
http://www.bcarsten.com/?page=appnote
5/15/2003
- Appnote
Page 5 of 6
a reverse voltage while still conducting current. The fastest possible diode (lowest
recovered charge) with a moderately soft recovery is usually the best choice. Sometimes a
faster, slightly "snappy" diode with a tightly coupled R-C snubber works as well or better
than a soft but excessively slow recovery diode.
If significant ringing occurs, a "quick-and-dirty" R-C snubber design approach works fairly
well: increasingly large damper capacitors are placed across the diode until the ringing
frequency is halved. We know that the total ringing capacity is now quadrupled, or that the
original ringing capacity is 1/3 of the added capacity. The damper resistance required is
about equal to the capacitive reactance of the original ringing capacity at the original ringing
frequency. The "frequency halving" capacity is then connected in series with the damping
resistance and placed across the diode, as tightly coupled as possible.
Leakage Inductance Fields
Transformer leakage inductance fields emanate from between primary and secondary
windings. With a
single primary and
secondary, a
significant dipole
field is created,
which may be seen
by placing the EMI
SnifferTM Probe
near the winding
ends as shown in
Fig. 5a. If this field
is generating EMI
problems, there are
two principal fixes
available:
1.
2.
Split the
Primary or
Secondary
in two, to
"sandwich"
the other winding, and/or:
Place a shorted copper strap "electromagnetic shield" around the complete core
and winding assembly. Eddy currents in the shorted strap largely cancel the
external magnetic far field.
The first approach creates a "quadrapole" instead of a dipole leakage field, which
significantly reduces the distant field intensity. It also reduces the eddy current losses in
any shorted strap electromagnetic shield used, which may or may not be an important
consideration.
External Air Gap Fields
External air gaps in an inductor, such those in open "bobbin core" inductors or with "E"
cores spaced apart (Fig. 5b), can be a major source of external magnetic fields when
significant ripple or AC currents are present. These fields can also be easily located with
the EMI SnifferTM probe; response will be a maximum near an air gap, or near the end of an
open inductor winding.
"Open" inductor fields are not readily shielded, and if they present an EMI problem the
inductor must usually be redesigned to reduce external fields. The external filed around
spaced E cores can be virtually eliminated by placing all of the air gap in the center leg.
Fields due to a (possibly intentional) residual or minor outside air gap can be minimized
with the shorted strap electromagnetic shield of Fig. 11, if eddy current losses prove not to
be too high.
A less obvious problem may occur when inductors with "open" cores are used as second
stage filter chokes. The minimal ripple current may not create a significant field, but such an
inductor can "pick up" external magnetic fields and convert them to noise voltages, or be an
EMI susceptibility problem.
Poorly Bypassed High Speed Logic
http://www.bcarsten.com/?page=appnote
5/15/2003
- Appnote
Page 6 of 6
Ideally, all high speed logic should have a tightly coupled bypass capacitor for each IC,
and/or have power and ground distribution planes in a multi-layer PCB.
At the other extreme, I have seen one bypass capacitor used at the power entrance to a
logic board, with power and ground led to the ICs from opposite sides of the board. This
created large spikes on the logic supply voltage, and produced significant electromagnetic
fields around the board.
With an EMI SnifferTM Probe I was able to show which pins of which ICs had the larger
current transients in synchronism with the supply voltage transients. (The logic design
engineers were accusing the power supply vendor of creating the noise. I found that the
supplies were fairly quiet; it was the poorly designed logic power distribution system that
was was the problem.)
SPURIOUS CAPACITIVE RESPONSE
The electrostatic Faraday shielding of the EMI SnifferTM Probe is excellent, despite the
open end of the Probe. (This end of the pickup coil is grounded to enhance shielding.) The
spurious capacitive pickup is only about 4 fF (0.004 pF), based on the measured capacitive
feedthrough. The effect is so slight that it can be ignored in virtually all applications; it is
actually very difficult to measure, requiring a special test jig to minimize pickup of
associated capacitive "displacement" currents in the vicinity, while maximizing the "true"
capacitive coupling.
Due to the 75 nH inductive "loading" of the pickup coil the capacitive response is not
proportional to the derivative of the voltage (dV/dt) but to the second derivative of the
voltage up to about 200 MHz.
NOTES ON SIGNAL INJECTION
Some EMI sensing probes have also been used to test for EMI susceptibility by injecting a
current into the probe and placing it near potentially sensitive circuits. This miniature probe
is not particularly suitable for this application, due to its small coil and limitation to low drive
levels; more than 1/8W input can cause damage.
EMI Diagnostic Test Equipment, Design Seminars, Consulting, and Technology Development Services
All content within this site is copyright © Bruce Carsten Associates, Inc. unless otherwise noted.
Last updated Saturday, November 9, 2002. Website design and development by Josie Nutter.
Project management and additional development by Loren DeLaOsa.
http://www.bcarsten.com/?page=appnote
5/15/2003
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising