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Texas Instruments TAS5028-5122C6EVM User guides
TAS5028-5122C6EVM User's Guide
PurePath Digital™ 5.1 Channel Evaluation Module for the
TAS5028A Digital Audio PWM processor and
TAS5122DCA Digital Amplifier Power Output Stage in
Both Bridge-Tied-Load and Single-Ended Configuration
User's Guide
January 2005
Digital Audio and Video Products
SLEU060
TAS5028-5122C6EVM User's Guide
PurePath Digital™ 5.1 Channel Evaluation Module for the
TAS5028A Digital Audio PWM processor and
TAS5122DCA Digital Amplifier Power Output Stage in
Both Bridge-Tied-Load and Single-Ended Configuration
User's Guide
Literature Number: SLEU060
January 2005
Contents
Preface ............................................................................................................................... 4
1
1.1
1.2
1.3
2
3
................................................................................................................... 7
Overview ............................................................................................................. 8
TAS5028-5122C6EVM Features ................................................................................. 8
PCB Key Map ....................................................................................................... 9
Overview
System Interfaces
..................................................................................................... 11
2.1
PSU Interface ...................................................................................................... 12
2.2
PSU Connector (J70) ............................................................................................. 12
2.3
Loudspeaker Connectors (J100 … J600) ...................................................................... 13
2.4
Optional Header for Line Out and Headphone (J10) ......................................................... 13
2.5
Digital Audio Interface (J40) ..................................................................................... 14
2.6
Control Interface (J30) ............................................................................................ 14
................................................................................................................ 17
Short Circuit Protection & Fault Reporting Circuitry .......................................................... 18
Device Fault Reporting ........................................................................................... 18
Protection
3.1
3.2
Important Notices ............................................................................................................... 19
List of Figures
1-1
1-2
2-1
2-2
2-3
Complete PurePath Digital™ System ..................................................................................... 8
Physical Structure for the TAS5028-5122C6EVM (rough outline) .................................................... 9
Recommended Power Up Sequence .................................................................................... 12
J70 Pin Numbers (PCB connector top view) ........................................................................... 12
J100 … J600 Pin Numbers (PCB connector top view) ................................................................ 13
List of Tables
1
2-1
2-2
2-3
2-4
2-5
2-6
3-1
Related documentation from Texas Instruments ........................................................................ 5
Recommended Power Supplies .......................................................................................... 12
J70 Pin Description ........................................................................................................ 13
J100 - J600 Pin Description............................................................................................... 13
J10 Pin Description ........................................................................................................ 13
J40 Pin Description ........................................................................................................ 14
J40 Pin Description ........................................................................................................ 14
TAS5122 Error Signal Decoding ......................................................................................... 18
SLEU060 – January 2005
Contents
3
Preface
SLEU060 – January 2005
Read Me First
About This Manual
This manual describes the operation of the TAS5028-5122C6EVM evaluation module from Texas
Instruments.
How to Use this Manual
This document contains the following chapters:
Chapter 1 - Overview
Chapter 2 - System Interfaces
Chapter 3 - Protection
Information about Cautions and Warnings
This manual may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your
software or equipment.
WARNING
This is an example of a warning statement.
A warning statement describes a situation that could potentially cause harm to
you.
The information in a caution or a warning is provided for your protection. Please read each caution and
warning carefully.
4
Read Me First
SLEU060 – January 2005
www.ti.com
Related Documentation from Texas Instruments
Related Documentation from Texas Instruments
The following table contains a list of data manuals that have detailed descriptions of the integrated circuits
used in the design of the TAS5028-5122C6EVM. The data manuals can be obtained at the URL
http://www.ti.com.
Table 1. Related documentation from Texas Instruments
PART NUMBER
LITERATURE NUMBER
TAS5028A
SLES120
TAS5122
SLES088D
SN74LVC1G08
SCES217O
SN74LVC1G126
SCES224J
LMV331I
SLCS136K
TPS76433
SLVS180B
Additional Documentation
1. TAS5028-5122C6EVM Applications Report (SLEA042)
2. PC Configuration Tool for TAS5028 (TAS5028 GUI ver. 2.1 or later)
3. General Application Notes
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required
to take whatever measures may be required to correct this interference.
Trademarks
PurePath Digital, Equibit are trademarks of Texas Instruments.
SLEU060 – January 2005
Read Me First
5
www.ti.com
Additional Documentation
6
Read Me First
SLEU060 – January 2005
Chapter 1
SLEU060 – January 2005
Overview
Topic
1.1
1.2
1.3
SLEU060 – January 2005
..................................................................................................
Page
Overview ................................................................................... 8
TAS5028-5122C6EVM Features ..................................................... 8
PCB Key Map ............................................................................. 9
Overview
7
www.ti.com
Overview
1.1
Overview
The TAS5028-5122C6EVM PurePath Digital™ customer evaluation module demonstrates two integrated
circuits TAS5028A and TAS5122DCA from Texas Instruments (TI).
TAS5028APAG is a high performance 32 bit (24 bit input) multichannel PurePath Digital™ Pulse Width
Modulator (PWM) based on Equibit™ technology with new fully symmetrical AD modulation scheme. The
device also has Digital Audio Processing (DAP) that provides 48-bit signal processing, advanced
performance and a high level of system integration. The device has interfaces for headphone output and
Power Supply Volume Control (PSVC).
TAS5122DCA is a high performance digital amplifier power stage designed to drive two 8-Ω loudspeakers
up to 40 W (10%THD+N) in BTL configuration or four 4-Ω loudspeakers up to 20 W (10%THD+N) in
Single Ended configuration. It contains integrated gate-drivers, eight matched and electrically isolated
enhancement-mode N-channel power DMOS transistors and protection/fault-reporting circuitry.
This EVM is configured with five SE channels for the satellites and one BTL channel for the subwoofer.
The TAS5028-5122C6EVM, together with a TI input board, is a complete 6-channel digital audio amplifier
system which includes digital input (S/PDIF), analog inputs, interface to PC and DAP features like digital
volume control, input and output mixers, automute, equalization, tone controls, loudness, dynamic range
compression and PSVC output. There are configuration options for stereo line level output, stereo
headphone output and power stage failure protection.
The system was design for home theater applications such as DVD minicomponent systems, home
theater in a box (HTIB), DVD receivers or Plasma Display Panels (PDP).
TAS5028−5122C6EVM
Figure 1-1. Complete PurePath Digital™ System
1.2
TAS5028-5122C6EVM Features
•
•
•
•
8
6-channel PurePath Digital™ evaluation module design
Self-contained protection system (short circuit & thermal)
Standard I2S and I2C / Control connector for TI Input board
Double-sided plated-through PCB layout
Overview
SLEU060 – January 2005
www.ti.com
PCB Key Map
1.3
PCB Key Map
Physical structure for the TAS5028-5122C6EVM is illustrated in the following figure.
TAS5028A
Figure 1-2. Physical Structure for the TAS5028-5122C6EVM (rough outline)
SLEU060 – January 2005
Overview
9
www.ti.com
PCB Key Map
10
Overview
SLEU060 – January 2005
Chapter 2
SLEU060 – January 2005
System Interfaces
This chapter describes the TAS5028-5122C6EVM board in regards to power supply
(PSU) and system interfaces.
Topic
2.1
2.2
2.3
2.4
2.5
2.6
SLEU060 – January 2005
..................................................................................................
PSU Interface............................................................................
PSU Connector (J70) .................................................................
Loudspeaker Connectors (J100 … J600) ......................................
Optional Header for Line Out and Headphone (J10) ......................
Digital Audio Interface (J40) .......................................................
Control Interface (J30) ...............................................................
Page
12
12
13
13
14
14
System Interfaces
11
www.ti.com
PSU Interface
2.1
PSU Interface
The TAS5028-5122C6EVM module must be powered from one or two external regulated power supplies.
High audio performance requires a stabilized output stage power supply with low ripple voltage and low
output impedance.
Note:
The length of power supply cable must be minimized. Increasing length of PSU cable is
equal to increasing the distortion for the amplifier at high output levels and low
frequencies.
Maximum output stage supply voltage depends of the speaker load resistance. Please check the
recommended maximum supply voltage in the TAS5122 datasheet.
Table 2-1. Recommended Power Supplies
DESCRIPTION
System power supply
Output power stage supply
(1)
VOLTAGE LIMITATIONS(4-8 Ω
LOAD)
CURRENT RECOMMENDATIONS
15 V – 25 V
0.25 A
0 – 25 V
2.7 A (1)
The rated current correspond to two channels (Ch 1-5) full scale (15W/4ohm each) + one channel (CH 6) full scale (30W/8ohm),
which most likely is adequate for a standard 6 channel amplifier design.
The recommended TAS5122 power-up sequence is shown in the following figure. For proper TAS5122
operation the RESET signal should be kept low during power-up. RESET is pulled low during power-up for
200 ms by the onboard reset generator (U80).
Figure 2-1. Recommended Power Up Sequence
2.2
PSU Connector (J70)
Figure 2-2. J70 Pin Numbers (PCB connector top view)
12
System Interfaces
SLEU060 – January 2005
www.ti.com
Loudspeaker Connectors (J100 … J600)
Table 2-2. J70 Pin Description
PIN NUMBER
2.3
NET-NAME AT SCHEMATICS
DESCRIPTION
1
VDD
Output stage power supply
2
-
System power supply
3
GND
Ground
4
GND
Ground
Loudspeaker Connectors (J100 … J600)
CAUTION
Both positive and negative speaker outputs are floating and may not be
connected to ground (e.g. through an oscilloscope).
Figure 2-3. J100 … J600 Pin Numbers (PCB connector top view)
Table 2-3. J100 - J600 Pin Description
PIN NUMBER
2.4
NET-NAME AT SCHEMATICS
DESCRIPTION
1
OUT_A
Speaker negative output
2
OUT_B
Speaker positive output
Optional Header for Line Out and Headphone (J10)
This is a optional interface for line out and headphone connections.
Table 2-4. J10 Pin Description
PIN NUMBER
DESCRIPTION
1
Left line out channel PWM (M)
2
Left line out channel PWM (P)
3
/Valid for line out channels
4
Right line out channel PWM (M)
5
Right line out channel PWM (P)
6
Ground
7
Left headphone channel (M)
8
Left headphone channel (P)
9
Right headphone channel (M)
10
Right headphone channel (P)
11
Headphone select – Active when low and inactive when high
12
Ground
SLEU060 – January 2005
System Interfaces
13
www.ti.com
Digital Audio Interface (J40)
2.5
Digital Audio Interface (J40)
The digital audio interface contains digital audio signal data (I2S), clocks etc. Please see TAS5028A data
manual for signal timing and details not explained in this document.
Table 2-5. J40 Pin Description
PIN NUMBER
2.6
NET-NAME AT SCHEMATICS
DESCRIPTION
1
GND
Ground
2
MCLK
Master Clock input. Low jitter system clock for
PWM generation and reclocking. Ground connection from source to TAS5028A must be a low
impedance connection.
3
GND
Ground
4
SDIN1
I2S Data 1, Channel 1 and 2
5
SDIN2
I2S Data 2, Channel 3 and 4
6
SDIN3
I2S Data 3, Channel 5 and 6
7
SDIN4
I2S Data 4, Channel 7 and 8
8
-
Reserved
9
-
Reserved
10
GND
Ground
11
SCLK
I2S bit clock.
12
GND
Ground
13
LRCLK
I2S left-right clock
14
GND
Ground
15
-
Reserved
16
GND
Ground
Control Interface (J30)
This interface connects the TAS5028-5122C6EVM board to a TI input board.
Table 2-6. J40 Pin Description
PIN NUMBER
14
NET-NAME AT SCHEMATICS
DESCRIPTION
1
GND
Ground
2
-
Reserved
3
GND
Ground
4
/RESET
System reset (bi-directional). Activate MUTE before
RESET for quiet reset
5
/BKND_ERR
Backend error (or soft reset) provides reduced click
and pop reset, without resetting I2C volume register settings
6
/MUTE
Ramp volume from any setting to noiseless soft
mute. Mute can also be activated by I2C
7
/PDN
Power down. TAS5028A will go to power down
state when activated
8
-
Reserved
9
-
Reserved
10
SDA
I2C data clock
System Interfaces
SLEU060 – January 2005
www.ti.com
Control Interface (J30)
Table 2-6. J40 Pin Description (continued)
PIN NUMBER
NET-NAME AT SCHEMATICS
DESCRIPTION
11
GND
Ground
12
SCL
I2C bit clock
13
-
Reserved
14
-
Reserved
15
-
Reserved
16
-
Reserved
17
GND
Ground
18
-
Reserved
19
-
Reserved
20
/SD
Shutdown error reporting for all channels. Activated
if TAS5122 has high current or high temperature
for ~100 mS. See chaptor 3: Protection
21
-
Reserved
22
/OTW
Temperature warning. Activated with low signal if
one or more TAS5122 has reached temperature
warning level
23
-
Reserved
24
/HP_SEL
Headphone select. Headphone active when low
and inactive when high. Default setting is high.
25
GND
Ground
26
GND
Ground
27
-
Reserved
28
-
Reserved
29
-
Reserved
30
-
Reserved
31
GND
Ground
32
GND
Ground
33
+5V
+5Vdc power supply (output)
34
+5V
+5Vdc power supply (output)
SLEU060 – January 2005
System Interfaces
15
www.ti.com
Control Interface (J30)
16
System Interfaces
SLEU060 – January 2005
Chapter 3
SLEU060 – January 2005
Protection
Topic
3.1
3.2
SLEU060 – January 2005
..................................................................................................
Page
Short Circuit Protection & Fault Reporting Circuitry ...................... 18
Device Fault Reporting .............................................................. 18
Protection
17
www.ti.com
Short Circuit Protection & Fault Reporting Circuitry
3.1
Short Circuit Protection & Fault Reporting Circuitry
TAS5122 is a self-protecting device that provides device fault reporting (including high-temperature
protection and short circuit protection). TAS5122 is configured in back-end auto-recovery mode and
therefore resets automatically after all errors (M1 and M2 is set low). This mean that the device will
re-start it self after a error occasion and report shortly through the SD error signal.
3.2
Device Fault Reporting
The OTW, SD_AB, and SD_CD outputs from TAS5122 indicate fault conditions. Please refer to the
TAS5122 data manual for a description of these pins.
Table 3-1. TAS5122 Error Signal Decoding
OTW
SD_XX
0
0
DESCRIPTION
High temperature error and/or high current error
0
1
High temperature warning
1
0
Under voltage lockout or high current error
1
1
Normal operation, no errors/warnings
The temperature warning (OTW) signals at the TAS5028-5122C6EVM board are wired-or to one
temperature warning signal (TEMP_WARNING– pin 22 in control interface connector). Shutdown signals
(SD_AB and SD_CD) are wired-or to one shutdown signal (SHUTDOWN– pin 20 in control interface
connector). The shutdown signals will together with the temperature warning signal give information on the
chip state information as described in the table above. Device fault reporting outputs are open-drain
outputs.
18
Protection
SLEU060 – January 2005
FCC Warnings
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency
energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules,
which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which case the user at his own expense will be required to
take whatever measures may be required to correct this interference.
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY
and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of
required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically
found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User's Guide, the kit may be returned within 30 days
from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER
TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all
claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant
or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user's responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE Liable to the other FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of
patents or services described herein.
Please read the EVM User's Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User's Guide prior to
handling the product. This notice contains important safety information about temperatures and voltages. For further safety
concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
www.ti.com
Device Fault Reporting
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 15 V to 25 V and the output voltage range of 0 V to 25 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 75° C. The EVM is designed to
operate properly with certain components above 75° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2004, Texas Instruments Incorporated
20
Protection
SLEU060 – January 2005
IMPORTANT NOTICE
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