Texas Instruments | DLP5534-Q1 0.55-Inch 1.3-Megapixel 405-nm DMD for Automotive Display (Rev. A) | Datasheet | Texas Instruments DLP5534-Q1 0.55-Inch 1.3-Megapixel 405-nm DMD for Automotive Display (Rev. A) Datasheet

Texas Instruments DLP5534-Q1 0.55-Inch 1.3-Megapixel 405-nm DMD for Automotive Display (Rev. A) Datasheet
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DLP5534-Q1
DLPS177A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
DLP5534-Q1 0.55-Inch 1.3-Megapixel 405-nm DMD for Automotive Display
1 Features
3 Description
•
The DLP5534-Q1 automotive DMD, combined with
the DLPC230-Q1 DMD controller and TPS99000-Q1
system management and illumination controller,
provides the capability to achieve a high performance
transparent window display projector. The chipset can
be coupled with 405-nm illumination sources (e.g.
LEDs or lasers) in an optical projection system to
project onto windows embedded with emissive
phosphor films. When these transparent emissive
films are excited with 405-nm light from a DLP5534Q1 projector, the window becomes a display emitting
light in the visible spectrum. The DLP5534-Q1 has
more than 3 times the optical throughput of the
preceding DLP3034-Q1 automotive DMD enabling
brighter and larger displays. In addition, this chipset
enables high power optical systems with a wide
dynamic range and fast switching speeds that do not
vary with temperature.
1
•
•
•
•
•
•
Qualified for automotive applications
– –40°C to 105°C operating temperature range
for DMD array
Supports 405-nm illumination sources
The DLP5534-Q1 automotive chipset includes:
– DLP5534-Q1 DMD
– DLPC230-Q1 DMD controller
– TPS99000-Q1 system management and
illumination controller
0.55-inch diagonal micromirror array
– 7.6-μm micromirror pitch
– ±12° micromirror tilt angle (relative to flat state)
– Bottom illumination for optimal efficiency and
optical engine size
– Supports 1152 × 576 input resolution
– Compatible with LED or laser illumination
600-MHz sub-LVDS DMD interface for low power
and emission
10-kHz DMD refresh rate over temperature
extremes
Built-in self test of DMD memory cells
Device Information(1)(2)
PART NUMBER
DLP5534-Q1
FYK (149)
BODY SIZE (NOM)
22.30 mm × 32.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This data sheet pertains to the specifications and application
of this DMD in the transparent window display application
utilizing 405-nm light. Please see the other DLP553X-Q1 data
sheets for alternative end equipment specifications and
relevant application information.
2 Applications
•
PACKAGE
Transparent window display for front, side, and
rear vehicle windows
DLP5534-Q1 DLP® Chipset System Block Diagram
VBATT
Power
Regulation
Control &
Monitor
TPS99000-Q1
PROJ_ON
1.1V
1.8V
3.3V
6.5V
Power sequencing
and monitoring
Reset &
Power Good
External
Monitor
SPI
System Diagnostics:
external watchdogs
and other monitors
DLPC230-Q1
2
IC
Host
SPI
HOST
IRQ
OpenLDI
Flash
24-bit RGB
& Syncs
Flash
SPI
MPU
Illumination
Control
& feedback
Dimming LED
Controller, TIA,
12bit ADC DAC, FET
Drive, ...
1
LED drive
FETs
DMD
Power
GPIO
(configurable)
Frame
Buffer
FET
Drive
DMD Power
Regulation
SPI
Internal
Control
Image Scaling &
Bezel
adjustment
VBATT
LED
Control
Window with
Embedded
Phosphor Film(s)
Sub-LVDS
DLP5534-Q1
I2C
TMP411
Projection
Optics
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP5534-Q1
DLPS177A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
8
Absolute Maximum Ratings ...................................... 8
Storage Conditions.................................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 9
Thermal Information ................................................ 11
Electrical Characteristics......................................... 11
Timing Requirements .............................................. 12
Switching Characteristics ....................................... 16
System Mounting Interface Loads .......................... 17
Physical Characteristics of the Micromirror Array. 18
Micromirror Array Optical Characteristics ............. 20
Window Characteristics......................................... 20
Chipset Component Usage Specification ............. 21
Detailed Description ............................................ 22
7.1 Overview ................................................................. 22
7.2 Functional Block Diagram ....................................... 23
7.3
7.4
7.5
7.6
8
Feature Description.................................................
System Optical Considerations...............................
Micromirror Array Temperature Calculation............
Micromirror Landed-On/Landed-Off Duty Cycle .....
24
26
27
29
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Application .................................................. 30
9
Power Supply Recommendations...................... 33
9.1 Power Supply Power-Up Procedure ....................... 33
9.2 Power Supply Power-Down Procedure................... 33
9.3 Power Supply Sequencing Requirements .............. 34
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
DMD Handling.......................................................
Glossary ................................................................
36
37
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Original (September 2019) to Revision A
Page
•
Changed device status from Advance Information to Production Data.................................................................................. 1
•
Added reference to the illumination validation testing application report ............................................................................ 32
2
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DLPS177A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
5 Pin Configuration and Functions
FYK Package
149-Pin CPGA
Bottom View
Pin Functions – Connector Pins
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
DESCRIPTION
DATA INPUTS
D_AN(0)
L2
I
SubLVDS
Double
Data, Negative
D_AN(1)
K2
I
SubLVDS
Double
Data, Negative
D_AN(2)
J2
I
SubLVDS
Double
Data, Negative
D_AN(3)
H2
I
SubLVDS
Double
Data, Negative
D_AN(4)
F2
I
SubLVDS
Double
Data, Negative
D_AN(5)
E2
I
SubLVDS
Double
Data, Negative
D_AN(6)
D2
I
SubLVDS
Double
Data, Negative
D_AN(7)
C2
I
SubLVDS
Double
Data, Negative
D_AP(0)
L1
I
SubLVDS
Double
Data, Positive
D_AP(1)
K1
I
SubLVDS
Double
Data, Positive
D_AP(2)
J1
I
SubLVDS
Double
Data, Positive
D_AP(3)
H1
I
SubLVDS
Double
Data, Positive
D_AP(4)
F1
I
SubLVDS
Double
Data, Positive
D_AP(5)
E1
I
SubLVDS
Double
Data, Positive
D_AP(6)
D1
I
SubLVDS
Double
Data, Positive
D_AP(7)
C1
I
SubLVDS
Double
Data, Positive
D_BN(0)
K19
I
SubLVDS
Double
Data, Negative
D_BN(1)
J19
I
SubLVDS
Double
Data, Negative
D_BN(2)
H19
I
SubLVDS
Double
Data, Negative
D_BN(3)
G19
I
SubLVDS
Double
Data, Negative
D_BN(4)
E19
I
SubLVDS
Double
Data, Negative
D_BN(5)
D19
I
SubLVDS
Double
Data, Negative
D_BN(6)
C19
I
SubLVDS
Double
Data, Negative
D_BN(7)
B19
I
SubLVDS
Double
Data, Negative
D_BP(0)
K20
I
SubLVDS
Double
Data, Positive
D_BP(1)
J20
I
SubLVDS
Double
Data, Positive
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Pin Functions – Connector Pins (continued)
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
DESCRIPTION
D_BP(2)
H20
I
SubLVDS
Double
Data, Positive
D_BP(3)
G20
I
SubLVDS
Double
Data, Positive
D_BP(4)
E20
I
SubLVDS
Double
Data, Positive
D_BP(5)
D20
I
SubLVDS
Double
Data, Positive
D_BP(6)
C20
I
SubLVDS
Double
Data, Positive
D_BP(7)
B20
I
SubLVDS
Double
Data, Positive
DCLK_AN
G2
I
SubLVDS
Double
Clock, Negative
DCLK_AP
G1
I
SubLVDS
Double
Clock, Positive
DCLK_BN
F19
I
SubLVDS
Double
Clock, Negative
DCLK_BP
F20
I
SubLVDS
Double
Clock, Positive
LS_CLKN
R3
I
SubLVDS
Single
Clock for Low Speed Interface, Negative
LS_CLKP
T3
I
SubLVDS
Single
Clock for Low Speed Interface, Positive
LS_WDATAN
R2
I
SubLVDS
Single
Write Data for Low Speed Interface, Negative
LS_WDATAP
T2
I
SubLVDS
Single
Write Data for Low Speed Interface, Positive
DMD_DEN_ARSTZ
T10
I
LPSDR
LS_RDATA_A
T5
O
LPSDR
Single
Read Data for Low Speed Interface
LS_RDATA_B
T6
O
LPSDR
Single
Read Data for Low Speed Interface
CONTROL INPUTS
Asynchronous Reset Active Low. Logic High
Enables DMD.
TEMPERATURE SENSE DIODE
TEMP_N
P1
O
TEMP_P
N1
I
VCCH
A8
Ground
VCCH
A9
Ground
VCCH
A10
Ground
VCCH
B8
Ground
VCCH
B9
Ground
VCCH
B10
Ground
VSSH
A11
Ground
VSSH
A12
Ground
VSSH
A13
Ground
VSSH
B11
Ground
VSSH
B12
Ground
VSSH
B13
Ground
Calibrated temperature diode used to assist
accurate temperature measurements of DMD
die.
RESERVED PINS
4
Reserved Pin. Connect to Ground.
Reserved Pin. Connect to Ground.
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Pin Functions – Connector Pins (continued)
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
DESCRIPTION
POWER
VBIAS
T7
Power
VBIAS
T15
Power
VOFFSET
T9
Power
VOFFSET
T13
Power
VOFFSET
A5
Power
VOFFSET
B5
Power
VOFFSET
A16
Power
VOFFSET
B16
Power
VRESET
T8
Power
VRESET
T14
Power
VDD
R4
Power
VDD
R10
Power
VDD
R11
Power
VDD
R20
Power
VDD
N2
Power
VDD
M20
Power
VDD
L3
Power
VDD
K18
Power
VDD
H3
Power
VDD
G18
Power
VDD
E3
Power
VDD
D18
Power
VDD
C3
Power
VDD
A6
Power
VDD
A18
Power
VDDI
T4
Power
VDDI
R1
Power
VDDI
M3
Power
VDDI
L18
Power
VDDI
J3
Power
VDDI
H18
Power
VDDI
F3
Power
VDDI
E18
Power
VDDI
B3
Power
VDDI
B18
Power
Supply voltage for positive bias level at
micromirrors.
Supply voltage for High Voltage CMOS core
logic. Supply voltage for offset level at
micromirrors.
Supply voltage for negative reset level at
micromirrors.
Supply voltage for Low Voltage CMOS core
logic; for LPSDR inputs; for normal high level at
micromirror address electrodes.
Supply voltage for SubLVDS receivers.
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Pin Functions – Connector Pins (continued)
PIN
NAME
TYPE
NO.
VSS
T1
Ground
VSS
T16
Ground
VSS
T19
Ground
VSS
T20
Ground
VSS
R5
Ground
VSS
R6
Ground
VSS
R7
Ground
VSS
R8
Ground
VSS
R9
Ground
VSS
R13
Ground
VSS
R14
Ground
VSS
R15
Ground
VSS
P2
Ground
VSS
P3
Ground
VSS
P20
Ground
VSS
N19
Ground
VSS
N20
Ground
VSS
M1
Ground
VSS
M2
Ground
VSS
L19
Ground
VSS
L20
Ground
VSS
K3
Ground
VSS
J18
Ground
VSS
G3
Ground
VSS
F18
Ground
VSS
D3
Ground
VSS
C18
Ground
VSS
B2
Ground
VSS
B4
Ground
VSS
B15
Ground
VSS
B17
Ground
VSS
A3
Ground
VSS
A4
Ground
VSS
A7
Ground
VSS
A15
Ground
VSS
A17
Ground
VSS
A19
Ground
VSS
A20
Ground
6
SIGNAL
DATA RATE
DESCRIPTION
Common return. Ground for all power.
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Pin Functions – Test Pads
NUMBER
SYSTEM BOARD
T11
Do not connect
T12
Do not connect
T17
Do not connect
T18
Do not connect
R12
Do not connect
R16
Do not connect
R17
Do not connect
R18
Do not connect
R19
Do not connect
P18
Do not connect
P19
Do not connect
N3
Do not connect
N18
Do not connect
M18
Do not connect
M19
Do not connect
B6
Do not connect
B7
Do not connect
B14
Do not connect
A14
Do not connect
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
MIN
MAX
UNIT
–0.5
2.3
V
–0.5
2.3
V
SUPPLY VOLTAGE
VDD
Supply voltage for LVCMOS core logic (2)
Supply voltage for LPSDR low speed interface
VDDI
Supply voltage for SubLVDS receivers (2)
(2) (3)
VOFFSET
Supply voltage for HVCMOS and micromirror electrode
–0.5
8.75
V
VBIAS
Supply voltage for micromirror electrode (2)
–0.5
17
V
VRESET
Supply voltage for micromirror electrode (2)
–11
0.5
V
(4)
| VDDI–VDD |
Supply voltage delta (absolute value)
0.3
V
| VBIAS–VOFFSET |
Supply voltage delta (absolute value) (5)
8.75
V
| VBIAS–VRESET |
Supply voltage delta (absolute value) (6)
28
V
INPUT VOLTAGE
Input voltage for other inputs LPSDR (2)
–0.5
VDD + 0.5
V
Input voltage for other inputs SubLVDS (2) (7)
–0.5
VDDI + 0.5
V
INPUT PINS
| VID |
SubLVDS input differential voltage (absolute value) (7)
810
mV
IID
SubLVDS input differential current
10
mA
ƒclock
Clock frequency for low speed interface LS_CLK
130
MHz
ƒclock
Clock frequency for high speed interface DCLK
620
MHz
105
°C
CLOCK FREQUENCY
ENVIRONMENTAL
TARRAY
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Operating DMD array temperature
(8)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device
reliability.
All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage to the internal termination resistors may result.
See Micromirror Array Temperature Calculation section.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system
TDMD
DMD storage temperature
MIN
MAX
UNIT
–40
125
°C
6.3 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic
discharge
Charged-device model (CDM), Corner Pins, per JESD22-C101 (2)
Charged-device model (CDM), All Other Pins, per JESD22-C101
(1)
(2)
8
UNIT
±2000
(2)
±750
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1) (2)
SUPPLY VOLTAGE RANGE
MIN
NOM
MAX
UNIT
1.7
1.8
1.95
V
1.7
1.8
1.95
V
(3)
VDD
Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface
VDDI
Supply voltage for SubLVDS receivers
(4)
VOFFSET
Supply voltage for HVCMOS and micromirror electrode
8.25
8.5
8.75
V
VBIAS
Supply voltage for mirror electrode
15.5
16
16.5
V
VRESET
Supply voltage for micromirror electrode
–9.5
–10
–10.5
V
| VDDI–VDD |
Supply voltage delta (absolute value)
(5)
0.3
V
| VBIAS–VOFFSET |
Supply voltage delta (absolute value) (6)
8.75
V
120
MHz
600
MHz
CLOCK FREQUENCY
ƒclock
ƒclock
Clock frequency for low speed interface LS_CLK
Clock frequency for high speed interface DCLK
(7)
Duty cycle distortion DCLK
44%
56%
SUBLVDS INTERFACE (7)
| VID |
SubLVDS input differential voltage (absolute value;
see Figure 6, Figure 7)
150
250
350
mV
VCM
Common mode voltage (see Figure 6, Figure 7)
700
900
1100
mV
VSUBLVDS
SubLVDS voltage (see Figure 6, Figure 7)
575
1225
mV
ZLINE
Line differential impedance (PWB/trace)
90
100
110
Ω
ZIN
Internal differential termination resistance (see Figure 8)
80
100
120
Ω
120
µA
105
°C
TEMPERATURE DIODE
ITEMP_DIODE
Max current source into Temperature Diode (8)
ENVIRONMENTAL
TARRAY
Operating DMD array temperature (9)
ILLsub-385nm
Illumination, wavelength < 385 nm
ILL385-to-395nm
Illumination, 385 nm < wavelength < 395 nm
250 mW/cm2
ILL395-to-400nm
Illumination, 395 nm < wavelength < 400 nm
800 mW/cm2
ILL400-to-420nm
Illumination, 400 nm < wavelength < 420 nm
8
W/cm2
Illumination, 420 nm < wavelength < 800 nm
(10)
W/cm2
ILLVIS
ILLOVERFILL
–40
2 mW/cm2
Thermally limited
Illumination overfill maximum heat load in areas
shown in Figure 1 (11)
TARRAY ≤ 75°C
Illumination overfill maximum heat load in areas
shown in Figure 1 (11)
TARRAY > 75°C
40
mW/mm2
29
(1)
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections
are also required.
(2) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(7) Refer to the SubLVDS timing requirements in Timing Requirements.
(8) Temperature Diode is to allow accurate measurement of the DMD array temperature during operation.
(9) DMD active array temperature can be calculated as shown in Micromirror Array Temperature Calculation section. Additionally, the DMD
array temperature is monitored in the system using the TMP411-Q1 and DLPC230-Q1 as shown in the system block diagram.
(10) Limited by the resulting micromirror array temperature. Refer to the calculation example in Micromirror Array Temperature Calculation
section.
(11) The active area of the DLP5534-Q1 device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light
illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the
DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the
particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause
system performance degradation.
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Limited illumination area
on window aperture
Window
Window
Aperture
Array
Window
0.5 mm
Window Aperture
0.5 mm
Figure 1. Illumination Overfill Diagram
10
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6.5 Thermal Information
DLP5534-Q1
THERMAL METRIC (1)
FYK (CPGA)
UNIT
149 PINS
Thermal resistance
(1)
Active area-to-test point 1 (TP1) (1)
1.1
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the
DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the
window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling
outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted) (1)
TEST CONDITIONS (2)
PARAMETER
MIN
TYP (3)
MAX
UNIT
CURRENT
IDD
Supply current: VDD (4) (5)
IDDI
Supply current: VDDI (4) (5)
IOFFSET
Supply current: VOFFSET (6)
IBIAS
Supply current: VBIAS (6)
IRESET
Supply current: VRESET
VDD = 1.95 V
369
VDD = 1.8 V
VDDI = 1.95 V
62
VDD = 1.8 V
VOFFSET = 8.75 V
16.1
VOFFSET = 8.5 V
VBIAS = 16.5 V
1.3
VBIAS = 16 V
VRESET = –10.5 V
–10.2
VRESET = –10 V
mA
mA
mA
mA
mA
POWER (7)
VDD = 1.95 V
PDD
Supply power dissipation: VDD (4) (5)
PDDI
Supply power dissipation: VDDI (4) (5)
POFFSET
Supply power dissipation: VOFFSET (6)
PBIAS
Supply power dissipation: VBIAS (6)
PRESET
Supply power dissipation: VRESET
PTOTAL
Supply power dissipation: Total
(1)
(2)
(3)
(4)
(5)
(6)
(7)
720
VDD = 1.8 V
VDDI = 1.95 V
121
VDD = 1.8 V
VOFFSET = 8.75 V
141
VOFFSET = 8.5 V
VBIAS = 16.5 V
22
VBIAS = 16 V
VRESET = –10.5 V
108
VRESET = –10 V
1110
mW
mW
mW
mW
mW
mW
Device electrical characteristics are over Recommended Operating Conditions, unless otherwise noted.
All voltage values are with respect to the ground pins (VSS).
Typical current consumption is application and video content dependent. Please see a TI applications engineer for additional
information.
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
Supply power dissipation based on non–compressed commands and data.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are
also required.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
TEST CONDITIONS (2)
PARAMETER
LPSDR INPUT
(8)
VIH(DC)
DC input high voltage (9)
VIL(DC)
DC input low voltage (9)
(9)
VIH(AC)
AC input high voltage
VIL(AC)
AC input low voltage
∆VT
Hysteresis (VT+ – VT–)
See Figure 9
IIL
Low–level input current
VDD = 1.95 V; VI = 0 V
IIH
High–level input current
VDD = 1.95 V; VI = 1.95 V
MIN
TYP (3)
MAX
UNIT
0.7 × VDD
VDD + 0.3
V
–0.3
0.3 × VDD
V
0.8 × VDD
VDD + 0.3
V
–0.3
0.2 × VDD
V
0.1 × VDD
0.4 × VDD
–100
V
nA
300
nA
LPSDR OUTPUT (10)
VOH
DC output high voltage
IOH = –2 mA
0.8 × VDD
V
VOL
DC output low voltage
IOL = 2 mA
0.2 × VDD
Input capacitance LPSDR
ƒ = 1 MHz
10
Input capacitance SubLVDS
ƒ = 1 MHz
20
Output capacitance
ƒ = 1 MHz
10
pF
CRESET
Reset group capacitance
ƒ = 1 MHz; (1152 × 144)
micromirrors
450
pF
CTEMP
Temperature sense diode capacitance
ƒ = 1 MHz
20
pF
V
CAPACITANCE
CIN
COUT
350
400
pF
(8)
(9)
LPSDR input specifications are for pin DMD_DEN_ARSTZ.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.
6.7 Timing Requirements
Device electrical characteristics are over Recommended Operating Conditions (unless otherwise noted)
MIN
NOM
MAX
UNIT
LPSDR
tr
Rise slew rate (1)
(20% to 80%) × VDD, see Figure 2
0.25
V/ns
tƒ
Fall slew rate (1)
(80% to 20%) × VDD, see Figure 2
0.25
V/ns
tW(H)
Pulse duration LS_CLK high
50% to 50% reference points, see Figure 4
0.75
ns
tW(L)
Pulse duration LS_CLK low
50% to 50% reference points, see Figure 4
0.75
ns
tsu
Setup time
LS_WDATA valid before LS_CLK ↑ or LS_CLK ↓,
see Figure 4
1.5
ns
th
Hold time
LS_WDATA valid after LS_CLK ↑ or LS_CLK ↓,
see Figure 4
1.5
ns
tr
Rise slew rate
20% to 80% reference points, see Figure 3
0.7
tƒ
Fall slew rate
80% to 20% reference points, see Figure 3
tc
Cycle time DCLK
See Figure 4
tW(H)
Pulse duration DCLK high
50% to 50% reference points, see Figure 4
0.75
ns
tW(L)
Pulse duration DCLK low
50% to 50% reference points, see Figure 4
0.75
ns
tWINDOW
Window time
Setup time + Hold time; see Figure 4, Figure 5
0.3
ns
tLVDS-
Power-up receiver (2)
SubLVDS
1
V/ns
0.7
1
V/ns
1.61
1.67
ns
2000
ns
ENABLE+REFGEN
(1)
(2)
12
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 2.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
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DMD_DEN_ARSTZ
1.0 * VDD
0.8 * VDD
0.2 * VDD
0.0 * VDD
tr
tf
Figure 2. LPSDR Input Rise and Fall Slew Rate
VLS_CLK_P , VLS_CLK_N , VLS_WDATA_P , VLS_WDATA_N
VDCLK_AP , VDCLK_BP , VDCLK_AN , VDCLK_BN
VD_AP(7:0) , VD_BP(7:0) , VD_AN(7:0) , VD_BN(7:0)
1.0 * VID
0.8 * VID
VCM
0.2 * VID
0.0 * VID
tr
tf
Figure 3. SubLVDS Input Rise and Fall Slew Rate
tc
tw(L)
tw(H)
DCLK_AP , DCLK_BP , LS_CLK_P
50%
50%
50%
DCLK_AN , DCLK_BN , LS_CLK_N
th
tsu
D_AP(7:0) , D_BP(7:0) , LS_WDATA_P
50%
50%
D_AN(7:0) , D_BN(7:0) , LS_WDATA_N
twindow
Figure 4. SubLVDS Switching Parameters
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High Speed Training Scan Window
tc
DCLK_AP, DCLK_BP
DCLK_AN, DCLK_BN
¼ tc
¼ tc
D_AP(7:0), D_BP(7:0)
D_AN(7:0), D_BN(7:0)
Figure 5. High-Speed Training Scan Window
DCLK_AP , D_AP(7:0) ,
DCLK_BP , D_BP(7:0) ,
LS_CLK_P , LS_WDATA_P
VID
VCM = (VIP + VIN) / 2
DCLK_AN , D_AN(7:0) ,
DCLK_BN , D_BN(7:0) ,
LS_CLK_N , LS_WDATA_N
VIP
SubLVDS
Receiver
VIN
Figure 6. SubLVDS Voltage Parameters
1.225V
VSubLVDS max = VCM max + | 1/2 * VID max |
VCM
VID
VSubLVDS min = VCM min ± | 1/2 * VID max |
0.575V
Figure 7. SubLVDS Waveform Parameters
DCLK_AP
DCLK_BP
D_AP(7:0)
D_BP(7:0)
ESD
Internal
Termination
(ZIN)
SubLVDS
Receiver
DCLK_AN
DCLK_BN
D_AN(7:0)
D_BN(7:0)
ESD
Figure 8. SubLVDS Equivalent Input Circuit
14
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VIH
VT+
û VT
VT-
VIL
DMD_DEN_ARSTZ
Figure 9. LPSDR Input Hysteresis
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6.8 Switching Characteristics (1)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
tPD
TEST CONDITIONS
Output propagation, clock to Q, rising edge of LS_CLK
(differential clock signal) input to LS_RDATA output.
See Figure 10, Figure 11
MIN
MAX
CL = 45 pF
15
Slew rate, LS_RDATA
0.5
Output duty cycle distortion, LS_RDATA_A and
LS_RDATA_B
(1)
TYP
UNIT
ns
V/ns
40%
60%
Device electrical characteristics are over Recommended Operating Conditions, unless otherwise noted.
LS_CLK_P
1
0
1
0
1
0
1
0
1
0
LS_CLK_N
LS_WDATA_P
Stop(1)
Start(0)
LS_WDATA_N
tPD
LS_RDATA
Acknowledge
Figure 10. LPSDR Read Out
Data Sheet Timing Reference Point
Device Pin
Output Under Test
Tester Channel
CL
See Sub-LVDS Data Interface section for more information.
Figure 11. Test Load Circuit for Output Propagation Measurement
16
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6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Condition 1: Maximum load evenly distributed within each area (1)
Thermal Interface Area
110.8
Electrical Interface Area
111.3
N
Condition 2: Maximum load evenly distributed within each area (1)
Thermal Interface Area
0
Electrical Interface Area
(1)
222.1
N
See Figure 12.
Figure 12. System Interface Loads
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6.10 Physical Characteristics of the Micromirror Array
VALUE
UNIT
M
Number of active columns
PARAMETER
See Figure 13
1152
micromirrors
N
Number of active rows
See Figure 13
1152
micromirrors
ε
Micromirror (pixel) pitch - diagonal
See Figure 14
7.6
µm
P
Micromirror (pixel) pitch - horizontal and vertical
See Figure 14
10.8
µm
Micromirror active array width
P × M + P / 2; see Figure 13
12.447
mm
Micromirror active array height
(P × N) / 2 + P / 2; see Figure 13
6.226
mm
10
micromirrors/side
Micromirror active border
(1)
18
Pond of micromirrors (POM)
(1)
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
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(0,0)
Col 1151
Col 1150
Pond of Micromirrors (POM) are Omitted for Clarity
Col 1149
Col 1148
Col 3
Col 2
Col 1
Col 0
Illumination
Row 1151
Row 1150
Row 1149
Row 1148
Row 1147
Row 1146
Row 1145
Row 1144
Off-State
Tilt Direction
Height
On-State
Tilt Direction
DMD Active Mirror Array
Row 7
Row 6
Row 5
Row 4
Row 3
Row 2
Row 1
Row 0
Width
DMD Periphery
Illumination
Copyright © 2018, Texas Instruments Incorporated
Figure 13. Micromirror Array Physical Characteristics
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P (um)
0
m
(u
)
P (um)
Figure 14. Mirror (Pixel) Pitch
6.11 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle tolerance
(4)
MAX
UNIT
°
–1
400 nm - 700 nm
Number of non-operational micromirrors (4)
(3)
NOM
12
(2)
DMD efficiency (3)
(1)
(2)
MIN
DMD landed state (1)
Micromirror tilt angle
1
°
66%
Adjacent micromirrors
0
Non-adjacent micromirrors
10
micromirrors
Measured relative to the plane formed by the overall micromirror array at 25°C.
For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some
optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result in
colorimetry variations, system efficiency variations, or system contrast variations.
DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection
apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the efficiency
numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or overfill loss.
This number is measured under conditions described above and deviations from these specified conditions could result in a different
efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application include:
light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as LEDs or
lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well as the
DMD efficiency factors that are not system dependent are described in detail in the DMD Optical Efficiency Application Note.
A non-operational micromirror is defined as a micromirror that is unable to transition between the on-state and off-state positions.
6.12 Window Characteristics
PARAMETER
MIN
Window material designation
Window refractive index
NOM
at wavelength 546.1 nm
20
UNIT
1.5119
Window aperture (1)
(1)
MAX
Corning Eagle XG
See
(1)
See the mechanical package ICD for details regarding the size and location of the window aperture.
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6.13 Chipset Component Usage Specification
The DLP5534-Q1 is a component of a chipset. Reliable function and operation of the DLP5534-Q1 requires that
it be used in conjunction with the TPS99000-Q1 and DLPC230-Q1, and includes components that contain or
implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices
used for operating or controlling a DLP DMD.
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
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7 Detailed Description
7.1 Overview
The DLP5534-Q1 Automotive DMD consists of 1,327,104 highly reflective, digitally switchable, micrometer-sized
mirrors organized in a two-dimensional array. As shown in Figure 15, the micromirror array consists of 1152
micromirror columns × 1152 micromirror rows in a diamond pixel configuration with a 2:1 aspect ratio.
Around the perimeter of the 1152 × 1152 array of micromirrors is a uniform band of border micromirrors called
the Pond of Micromirrors (POM). The border micromirrors are not user-addressable. The border micromirrors
land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each
side of the 1152 × 1152 active array.
Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns
of the even row. Each mirror is switchable between two discrete angular positions: –12° and +12°. The mirrors
are illuminated from the bottom which allows for compact and efficient system optical design.
Col 1151
Col 1150
Pond of Micromirrors (POM) are Omitted for Clarity
Col 1149
Col 1148
Col 3
Col 2
Col 1
Col 0
Although the native resolution of the DLP5534-Q1 is 1152 × 1152, when paired with the DLPC230-Q1 controller,
the DLP5534-Q1 can be driven with different resolutions to utilize the 2:1 aspect ratio. For example, display
applications typically use a resolution of 1152 × 576. Please see the DLPC230-Q1 automotive DMD controller
data sheet (DLPS054) for a list of supported resolutions. Diamond pixel arrays also have the capability to
increase display resolution beyond native resolution. Future controllers or video formatters may take advantage
of this enhanced resolution.
Row 1151
Row 1150
Row 1149
Row 1148
Row 1147
Row 1146
Row 1145
Row 1144
Off-State
Tilt Direction
Height
On-State
Tilt Direction
DMD Active Mirror Array
Row 7
Row 6
Row 5
Row 4
Row 3
Row 2
Row 1
Row 0
Width
Illumination
Figure 15. 0.55-in 1.3-MP Micromirror Array
22
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High Speed Data Path &
Training: Bus A
DCLK_BN
DCLK_BP
D_BN(7:0)
D_BP(7:0)
VSS
VDDI
DCLK_AN
DCLK_AP
D_AN(7:0)
D_AP(7:0)
7.2 Functional Block Diagram
High Speed Data Path &
Training: Bus B
(1151, 1151)
TEMP_P
1.3 Mega Pixel 2:1 Aspect ratio
SRAM & Micromirror Array
TEMP_N
(0,0)
DMD Mirror & SRAM Voltage Control
LS_RDATA_B
LS_RDATA_A
LS_WDATA_N
LS_WDATA_P
LS_CLK_N
LS_CLK_P
DMD_DEN_ARSTZ
VSS
VDD
VSS
VDD
VOFFSET
VBIAS
VRESET
Low Speed Bus Interface & DMD Mirror
Voltage control
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7.3 Feature Description
The DLP5534-Q1 consists of a two-dimensional array of 1-bit CMOS memory cells driven by a sub-LVDS bus
from the DLPC230-Q1 and powered by the TPS99000-Q1. The temperature sensing diode is used to
continuously monitor the DMD array temperature.
To ensure reliable operation the DLP5534-Q1 must be used with the DLPC230-Q1 DMD display controller and
the TPS99000-Q1 system management and illumination controller.
7.3.1 Sub-LVDS Data Interface
The Sub-LVDS signaling protocol was designed to enable very fast DMD data refresh rates while simultaneously
maintaining low power and low emission.
Data is loaded into the SRAM under each micromirror using the sub-LVDS interface from the DLPC230-Q1. This
interface consists of 16 pairs of differential data signals plus two clock pairs into two separate buses A and B
loading the left and right half of the SRAM array. The data is latched on both transitions creating a double data
rate (DDR) interface. The sub-LVDS interface also implements a continuous training algorithm to optimize the
data and clock timing to allow for a more robust interface.
The entire DMD array of 1.3 million pixels can be updated at a rate of less than 100 µs as a result of the high
speed sub-LVDS interface.
7.3.2 Low Speed Interface for Control
The purpose of the low speed interface is to configure the DMD at power up and power down and to control the
micromirror reset voltage levels that are synchronized with the data loading. The micromirror reset voltage
controls the time when the mirrors are mechanically switched. The low speed differential interface includes 2
pairs of signals for write data and clock, and 2 single-ended signals for output (A and B).
7.3.3 DMD Voltage Supplies
The micromirrors require unique voltage levels to control the mechanical switching from –12° to +12°. These
voltage levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET), and are generated by the
TPS99000-Q1.
7.3.4 Asynchronous Reset
Reset of the DMD is required and controlled by the DLPC230-Q1 via the signal DMD_DEN_ARSTZ.
7.3.5 Temperature Sensing Diode
The DMD includes a temperature sensing diode designed to be used with the TMP411 temperature monitoring
device. The DLPC230-Q1 monitors the DMD array temperature via the TMP411 and temperature sense diode.
The DLPC230-Q1 operation of the DMD timing is based in part on the DMD array temperature, therefore this
connection is essential to ensure reliable operation of the DMD.
Figure 16 shows the typical connection between the DLPC230-Q1, TMP411, and the DMD.
24
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Feature Description (continued)
DLPC230-Q1
DLP5534-Q1
TEMP_N
TEMP_P
56 Ÿ
SCL
D+
SCA
100 pF
THERM1
56 Ÿ
Dt
THERM2
TMP411 ± Q1
Copyright © 2017, Texas Instruments Incorporated
Figure 16. Temperature Sense Diode Typical Circuit Configuration
7.3.5.1 Temperature Sense Diode Theory
A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.
The diode is formed by connecting the transistor base to the collector. Three different known currents flow
through the diode and the resulting diode voltage is measured in each case. The difference in their base–emitter
voltages is proportional to the absolute temperature of the transistor.
Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.
Figure 17 and Figure 18 illustrate the relationships between the current and voltage through the diode.
IE1
IE2
TEMP_N
+
VBE 1,2
-
TEMP_P
Figure 17. Temperature Measurement Theory
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û VBE (mV)
VBE (mV)
Feature Description (continued)
100uA
10uA
1uA
Temperature (°C)
Temperature (°C)
Figure 18. Example of Delta VBE Versus Temperature
7.4 System Optical Considerations
Optimizing system optical performance and image performance strongly relates to optical system design
parameter trades. Although it is not possible to anticipate every conceivable application, projector image and
optical performance is contingent on compliance to the optical system operating conditions described in the
following sections.
7.4.1 Numerical Aperture and Stray Light Control
The numerical aperture of the illumination and projection optics at the DMD optical area should be the same.
This cone angle defined by the numerical aperture should not exceed the nominal device mirror tilt angle unless
appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light
from the projection lens. The mirror tilt angle defines the DMD's capability to separate the "On" optical path from
any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces.
7.4.2 Pupil Match
TI’s optical and image performance specifications assume that the exit pupil of the illumination optics is nominally
centered and located at the entrance pupil position of the projection optics. Misalignment of pupils between the
illumination and projection optics can degrade screen image uniformity and cause objectionable artifacts in the
display’s border and/or active area. These artifacts may require additional system apertures to control, especially
if the numerical aperture of the system exceeds the pixel tilt angle.
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System Optical Considerations (continued)
7.4.3 Illumination Overfill
Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and
other surfaces that surround the active array. These artifacts may be visible in the projected image. The
illumination optical system should be designed to minimize light flux incident outside the active array and on the
window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this amount
of overfill light on the area outside of the active array may still cause artifacts to be visible.
Illumination light and overfill can also induce undesirable thermal conditions on the DMD, especially if illumination
light impinges directly on the DMD window aperture or near the edge of the DMD window. Heat load on the
aperture in the areas shown in Figure 1 should not exceed the values listed in Recommended Operating
Conditions. This area is a 0.5-mm wide area the length of the aperture opening. The values listed in
Recommended Operating Conditions assume a uniform distribution. For a non-uniform distribution please contact
TI for additional information.
NOTE
TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD
FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING
LIMITS DESCRIBED PREVIOUSLY.
7.5 Micromirror Array Temperature Calculation
Figure 19. DMD Thermal Test Points
The active array temperature can be computed analytically from measurement points on the outside of the
package, the package thermal resistance, the electrical power, and the illumination heat load.
Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in
Figure 19) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC)
QARRAY = QELECTRICAL + (QINCIDENT × DMD Absorption Constant)
(1)
where
•
•
•
•
•
•
•
TARRAY = computed DMD array temperature (°C)
TCERAMIC = measured ceramic temperature, TP1 location in Figure 19 (°C)
RARRAY–TO–CERAMIC = DMD package thermal resistance from array to thermal test point TP1 (°C/W), see
Thermal Information
QARRAY = total power, electrical plus absorbed, on the DMD array (W)
QELECTRICAL = nominal electrical power dissipation by the DMD (W)
QINCIDENT = incident optical power to DMD (W)
DMD Absorption Constant = 0.42
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Micromirror Array Temperature Calculation (continued)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies.
Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and
the intensity of the light source.
Equations shown above are valid for a 1-chip DMD system with illumination distribution of 83.7% on the active
array and 16.3% on the array border.
The following is a sample calculation for a typical projection application:
1. QELECTRICAL = 0.4 W
2. TCERAMIC = 55°C
3. QINCIDENT = 3 W
4. QARRAY = 0.4 W + (3 W × 0.42) = 1.66 W
5. TARRAY = 55°C + (1.66 W × 1.1°C/W) = 56.8°C
28
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7.6 Micromirror Landed-On/Landed-Off Duty Cycle
7.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 90/10 indicates that the referenced pixel is in the ON state 90% of the
time (and in the OFF state 10% of the time), whereas 10/90 would indicate that the pixel is in the OFF state 90%
of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DLP5534-Q1 chipset is designed to support projection-based automotive applications such as transparent
window display systems.
8.2 Typical Application
The chipset consists of three components—the DLP5534-Q1 automotive DMD, the DLPC230-Q1, and the
TPS99000-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project images.
The DLPC230-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the DMD
illumination sources and the DMD in order to display the incoming video. The TPS99000-Q1 is a controller for
the illumination sources (e.g. LEDs or lasers) and a management IC for the entire chipset. In conjunction, the
DLPC230-Q1 and the TPS99000-Q1 can also be used for system-level monitoring, diagnostics, and failure
detection features. Figure 20 is a system level block diagram with these devices in the DLP head-uptransparent
window display configuration and shows the primary features and functions of each device.
topology and capacity
tailored to specific
system application
VLED
6.5 V
SHUTDOWN.
VBATT.
Preregulator
(optional)
6.5 V
3.3 V
LDO
PROJ_ON.
High-side
current limiting
Flash
SPI (4).
PMIC diagnostics
port
External ADC inputs
for general usage
SPI_1
AC3
ADC_CTRL (2).
SPI_2
SPI (4).
MPU
HOST_IRQ.
WD (2).
LED_SEL (4).
ECC
SEQ_START.
OpenLDI.
24.
DATA
12 bit
ADC
LED drive
with up to 64 HW timed
samples per frame
F
E
T
s
LED dimming
controller
LM3409
shunt(2)
LED1
LED2
LED3
S_EN.
DLPC230-Q1
CTRL
4.
1.1 V
1.8 V
3.3 V
External
regulators
Power sequencing
and monitoring
D_EN.
COMPOUT.
Parallel
28.
SEQ_CLK.
eSRAM
frame buffer
I2C (2).
I2C_0
SPI (4).
SPI_0
TPS99000-Q1
illumination
optics
Low-side current
measurement
PARKZ.
RESETZ.
INTZ.
GPIOx
Spare
GPIO
External watchdogs /
and other monitors
(optional)
Sys clock
monitor
DMD bias
regulator
Window with Embedded
Phosphor Film(s)
BIAS, RST, OFS
(3).
EEPROM
3.3 V
VCC_FLASH
VCC_INTF
1.8 V
VIO
1.1 V
VCORE
I2C_1
TMP411
(2).
DMD die temperature
DMD
Sub-LVDS
Interface
sub-LVDS DATA.
DLP5534-Q1
Control.
illumination
optics
Figure 20. Transparent Window Display System Block Diagram
30
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Typical Application (continued)
8.2.1 Application Overview
Figure 20 shows the system block diagram for a DLP projector in a 405-nm based transparent window display
system. The system uses the DLPC230-Q1, TPS99000-Q1, and the DLP5534-Q1 automotive DMD to enable a
transparent window display with high brightness, high efficiency, and high resolution. The combination of the
DLPC230-Q1 and TPS99000-Q1 removes the need for external SDRAM and a dedicated microprocessor. The
chipset manages the illumination control of LED sources, power sequencing functions, and system management
functions. Additionally, the chipset supports numerous system diagnostic and built-in self test (BIST) features.
The following paragraphs describe the functionality of the chipset used for a 405-nm projection system in more
detail.
The DLPC230-Q1 is a controller for the DMD and the light sources in the DLP projector module. It receives input
video from the host and synchronizes DMD and light source timing in order to achieve the desired video. The
DLPC230-Q1 formats input video data that is displayed on the DMD. It synchronizes these video segments with
light source timing in order to create a video with grayscale shading and multiple colors, if applicable.
The DLPC230-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input
video data. Host commands can be sent using either the I2C bus or SPI bus. The bus that is not being used for
host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an
OpenLDI bus or a parallel 24-bit bus. The 24-bit bus can be limited to only 8-bits or 16-bits of data for single light
source or dual light source systems depending on the system design. The SPI flash memory provides the
embedded software for the DLPC230-Q1’s ARM core and default settings. The TPS99000-Q1 provides
diagnostic and monitoring information to the DLPC230-Q1 using an SPI bus and several other control signals
such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing. The TMP411 uses an
I2C interface to provide the DMD array temperature to the DLPC230-Q1.
The outputs of the DLPC230-Q1 are configuration and monitoring commands to the TPS99000-Q1, timing
controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics
information to the host processor. The DLPC230-Q1 communicates with the TPS99000-Q1 over an SPI bus. It
uses this to configure the TPS99000-Q1 and to read monitoring and diagnostics information from the TPS99000Q1. The DLPC230-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD
mirror timing. The control signals to the DMD are sent using a sub-LVDS interface.
The TPS99000-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and
diagnostics information for the DLP projector module. The power sequencing and monitoring blocks of the
TPS99000-Q1 properly power up the DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V), and
then monitor the system’s power rails during operation. The integration of these functions into one IC significantly
reduces design time and complexity. The TPS99000-Q1 also has several output signals that can be used to
control a variety of LED or laser driver topologies. The TPS99000-Q1 has several general-purpose ADCs that
designers can use for system level monitoring, such as over-brightness detection.
The TPS99000-Q1 receives inputs from the DLPC230-Q1, the power rails it monitors, the host processor, and
potentially several other ADC ports. The DLPC230-Q1 sends configuration and control commands to the
TPS99000-Q1 over an SPI bus and several other control signals. The DLPC230-Q1’s clocks are also monitored
by the watchdogs in the TPS99000-Q1 to detect any errors. The power rails are monitored by the TPS99000-Q1
in order to detect power failures or glitches and request a proper power down of the DMD in case of an error.
The host processor can read diagnostics information from the TPS99000-Q1 using a dedicated SPI bus, which
enables independent monitoring. Additionally the host can request the image to be turned on or off using a
PROJ_ON signal. Lastly, the TPS99000-Q1 has several general-purpose ADCs that can be used to implement
system level monitoring functions.
The outputs of the TPS99000-Q1 are diagnostic information and error alerts to the DLPC230-Q1, and control
signals to the LED or laser driver. The TPS99000-Q1 can output diagnostic information to the host and the
DLPC230-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the
DLPC230-Q1 that trigger power down or reset sequences. It also has output signals that can be used to
implement various LED or laser driver topologies.
The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video
data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS
interface with the DLPC230-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD
array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.
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Typical Application (continued)
8.2.2 Reference Design
For information about connecting together the DLP5534-Q1 DMD, DLPC230-Q1 controller, and TPS99000-Q1,
please contact the TI Application Team for additional information about the DLP5534-Q1 evaluation module
(EVM). TI has optical-mechanical reference designs available, see the TI Application team for more information.
8.2.3 Application Mission Profile Consideration
Each application is anticipated to have different mission profiles, or number of operating hours at different
temperatures. To assist in evaluation, the automotive DMD reliability lifetime estimates Application Report may
be provided. Please contact the TI Applications team for more information.
8.2.4
Illumination Mission Profile Considerations
TI has performed evaluations at 405-nm illumination wavelengths under certain conditions. The details of these
test conditions can be found in the Application Report Illumination Validation Testing Performed by Texas
Instruments. These conditions should be considered when evaluating the final application's implementation.
Please contact the TI Applications team for details about this testing.
32
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET.
All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the
TPS99000-Q1 devices.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power-up and
power-down procedures may affect device reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated
during power-up and power-down operations. Failure to meet any of the below
requirements will result in a significant reduction in the DMD’s reliability and lifetime.
VSS must also be connected.
9.1 Power Supply Power-Up Procedure
•
•
•
•
During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in the Recommended Operating Conditions.
During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled
at operating voltage.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow
the requirements listed previously and in Figure 21.
9.2 Power Supply Power-Down Procedure
•
•
•
•
•
The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement
that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended
Operating Conditions (refer to Note 2 in Figure 21).
During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in the
Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in Figure 21.
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9.3 Power Supply Sequencing Requirements
TPS99000 initiates DMD power-down
sequence. DLPC230 executes critical
commands.
Note 5
Drawing Not To Scale.
Details Omitted For Clarity.
DLPC230 and TPS99000
control start of DMD operation
Mirror Park Sequence
DLPC230 and TPS99000
disables VBIAS, VOFFSET,
and VRESET
Note 4
Power Off
VDD / VDDI
VDD / VDDI
VDD / VDDI VSS
VSS
VBIAS
VBIAS
VBIAS
VBIAS < 4 V
VSS
ûV < Specification
ûV < Specification
Note 1
Note 2
Note 3
VOFFSET
VSS
ûV < Specification
Note 2
VOFFSET
VOFFSET
VOFFSET < 4 V
VSS
VSS
VRESET < 0.5 V
VSS
VSS
VRESET > - 4 V
VRESET
VRESET
VDD
VRESET
VDD
DMD_DEN_ARSTZ VSS
VSS
Initialization
LS_CLK_P
LS_CLK_N
LS_WDATA_P
LS_WDATA_N
VSS
VSS
Waveforms Not To Scale.
D_AP(7:0) , D_AN(7:0)
D_BP(7:0) , D_BN(7:0) VSS
DCLK_AP , DCLK_AN
DCLK_BP , DCLK_BN
VSS
5HIHU WR WKH VHFWLRQV ³$EVROXWH 0D[LPXP 5DWLQJV´ DQG ³5HFRPPHQGHG 2SHUDWLQJ &RQGLWLRQV´.
(1)
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in the
Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET
prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Also, TPS99000-Q1 is
capable of managing the timing between VBIAS and VOFFSET.
(2)
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified than the limit
shown in the Recommended Operating Conditions.
(3)
When system power is interrupted, the TPS9000 initiates hardware power-down that disables VBIAS, VRESET and
VOFFSET after the Micromirror Park Sequence.
(4)
Drawing is not to scale and details are omitted for clarity.
Figure 21. Power Supply Sequencing Requirements (Power Up and Power Down)
34
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10 Layout
10.1 Layout Guidelines
Please refer to the DLPC230-Q1 and TPS99000-Q1 data sheets for specific PCB layout and routing guidelines.
For specific DMD PCB guidelines, use the following:
• Match lengths for the LS_WDATA and LS_CLK signals.
• Minimize vias, layer changes, and turns for the HS bus signals.
• Minimum of two 220-nF decoupling capacitors close to VBIAS.
• Minimum of two 220-nF decoupling capacitors close to VRESET.
• Minimum of two 220-nF decoupling capacitors close to VOFFSET.
• Minimum of four 100-nF decoupling capacitors close to VDDI and VDD.
• Temperature diode pins
The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411
temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to
noise. Please see the TMP411 data sheet for specific routing recommendations.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DLP5534 A FYK Q1
Automotive
Package Type
Temperature Rating (-40°C to 105°C)
Device Descriptor
Figure 22. Part Number Description
11.1.2 Device Markings
The device marking includes the legible character string GHJJJJK DLP5534AFYKQ1. GHJJJJK is the lot trace
code. DLP5534AFYKQ1 is the part number.
DLP5534AFYKQ1
GHXXXXX LLLLLLM
Part 2 of Serial Number
(7 characters)
Part 1 of Serial Number
(7 characters)
DMD Part Number
2-Dimension Matrix Code
(Part Number and Serial Number)
Figure 23. DMD Marking
36
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11.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 DMD Handling
The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see
the application note DLPA019 DMD Handling for instructions on how to properly handle the DMD.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
DLP5534AFYKQ1
ACTIVE
CPGA
FYK
149
XDLP5534AFYKQ1
ACTIVE
CPGA
FYK
149
33
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
RoHS & Green
NI-PD-AU
N / A for Pkg Type
-40 to 105
TBD
Call TI
Call TI
-40 to 105
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
8
5
6
7
3
4
C
NOTES UNLESS OTHERWISE SPECIFIED:
DWG NO.
COPYRIGHT 2015 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED. REV
A
B
C
1 SUBSTRATE EDGE PERPENDICULARITY TOLERANCE APPLIES TO ENTIRE SURFACE.
2 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
2514853
SH
1
1
REVISIONS
DESCRIPTION
ECO 2155049: INITIAL RELEASE
ECO 2165903: UPDATE SUBSTRATE BACK MARKING, SH. 4
ECO 2170159: RELAX DIE HEIGHT TOL., WAS +/-0.08
DATE
12/7/2015
4/25/2017
11/9/2017
BY
BMH
BMH
BMH
3 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM VALUE OF 0.8 DEGREES.
D
4 SUBSTRATE SYMBOLIZATION PAD AND PLATING AT BOTTOM OF DATUMS B AND C
HOLES TO BE ELECTRICALLY CONNECTED TO VSS PLANE WITHIN THE SUBSTRATE.
D
5 BOUNDARY MIRRORS SURROUNDING THE ACTIVE ARRAY.
6 MAXIMUM ENCAPSULANT PROFILE SHOWN.
7 ENCAPSULANT ALLOWED ON THE SURFACE OF THE CERAMIC IN THE AREA SHOWN
IN VIEW B (SHEET 2). ENCAPSULATION SHALL NOT EXCEED 0.2 THICKNESS MAXIMUM.
A
8 INDICATED CERAMIC SUBSTRATE FEATURES TO BE PLATED WITH 0.3 MICROMETERS
MINIMUM ELECTROLYTIC GOLD OVER 0.1 MICROMETER MINIMUM PALLADIUM OVER
1.27-8.89 MICROMETERS ELECTROLYTIC NICKEL PER ASTM B488-01, ASTM
B679-95(2009), AND AMS-QQ-N-290, RESPECTIVELY.
1
9 NOTE THAT THE ACTIVE ARRAY CENTER IS IN A DIFFERENT LOCATION FROM ALL
PRIOR SERIES 450 DMD'S.
A
(Ø2)
 0.2 E
SEE VIEW E (SHEET 3)
FOR WINDOW AND ACTIVE
ARRAY DIMENSIONS
3 0.5
B
E
1.064 0.15
3 0.5
C
C
A
A
22.3 0.22
12.687 0.15
C
(1.5)
2.335 0.15
23.33 0.15
B
B
32.2 0.32
SUBSTRATE
A
6 ENCAPSULANT
(0.56)
3 PLACES
INDICATED
(SHEET 2)
0.8 MAX
WINDOW
1.05 0.1
2.925 0.24
G
WINDOW APERTURE
1.1 0.05
(0.51)
(0.75)
INCIDENT
LIGHT
1.61 0.077

0.0254 A
0.02 G
2
ACTIVE ARRAY
149X 1.4 0.1
A
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
SECTION A-A
(Ø0.305)
SCALE 20 : 1
THIRD ANGLE
PROJECTION
NONE
0314DA
NEXT ASSY
USED ON
8
7
6
5
4
12/7/2015
ENGINEER
12/7/2015
B. HASKETT
2 PLACE DECIMALS 0.25
QA/CE
1 PLACE DECIMALS 0.50
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
P. KONRAD
CM
Dallas Texas
TITLE
12/8/2015
12/8/2015
M. DORAK
12/8/2015
SIZE
APPROVED
12/8/2015
SCALE
2
A
TEXAS
INSTRUMENTS
S. SUSI
B. RAY
3
DATE
B. HASKETT
ANGLES 1
APPLICATION
INV2013-DLPa
DRAWN
ICD, MECHANICAL, DMD
.55 2:1 1.3MP SERIES 450 -A1
(FYK PACKAGE)
REV
DWG NO
D
C
2514853
4:1
SHEET
1
1
OF
4
8
5
6
7
3
4
DWG NO.
2514853
SH
1
2
D
D
0.5 MIN
A
1.84 0.13
28 0.28
(DATUM B TO CENTER OF DATUM C SLOT)
F
A
25.85 MAX
2.1 0.15
2±0.05
D
B
(Ø2)
2 MIN
ENCAPSULANT ALLOWED
ON CERAMIC AREA
B
A2
7
E
SECTION C-C
DATUM B
SCALE 16 : 1
5.15 0.15
C
C
2.9
C
C
6
23.2° 1°
12 0.12
14.9
0.5 MIN
A1
C
(1.5)
3X 4
D
1.84 0.13
B
B
C
D
1.5 0.05
0.75 0.025
1 0.1
WINDOW
SECTION D-D
DATUM C
0.5 0.05
A3
2X 28
(DATUM B TO A2 AND A3)
(VIEW ROTATED FOR CLARITY)
SCALE 16 : 1
VIEW B
DATUMS AND ENCAPSULANT ALLOWABLE AREA
A
A
SCALE 10 : 1
TEXAS
INSTRUMENTS
Dallas Texas
INV2013-DLPa
8
7
6
5
4
3
DRAWN
B. HASKETT
DATE
12/7/2015
SIZE
D
SCALE
2
DWG NO
REV
2514853
SHEET
1
2
OF
C
4
8
5
6
7
4
3
DWG NO.
2514853
SH
1
3
D
D
3 9
(2.1)
(Ø2)
(12.447)
ACTIVE ARRAY
7.776 0.076
5
B
4X (0.108)
(5.15)
1.073±0.0885
3 9
C
C
2.887 0.076

2.075 0.05
(8.033)
WINDOW
APERTURE
2
(6.2262)
ACTIVE ARRAY
6.96±0.0885
(10)
WINDOW
7.925±0.05
C
B
B
(1.5)
0.356±0.0885
12.802±0.0885
(13.158)
WINDOW APERTURE
2.6844 0.05
15.1314 0.05
(17.8158)
WINDOW
A
A
VIEW E
ACTIVE ARRAY AND WINDOW
SCALE 12 : 1
TEXAS
INSTRUMENTS
Dallas Texas
INV2013-DLPa
8
7
6
5
4
3
DRAWN
B. HASKETT
DATE
12/7/2015
SIZE
D
SCALE
2
DWG NO
REV
2514853
SHEET
1
3
OF
C
4
8
5
6
7
3
4
DWG NO.
2514853
SH
1
4
D
D
F
19.145
9 X 1.27 = 11.43
1.625
1.625
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
(A1, A2, & B1 OMITTED)
D
20
A
9 X 1.27 = 11.43
E
A
3.895 0.25
B
C
D
E
C
C
F
G
H
14.51 0.25
J
15 X 1.27 = 19.05
K
L
M
N
P
R
G
T
8
+0.05
149X 0.305 PINS
0.025
0.5 D E F

0.25 D
B
SYMBOLIZATION
PAD
4 8
8.5 0.25
11.85 0.25
B
8
VIEW F
PINS AND SYMBOLIZATION PAD
SCALE 8 : 1
0.28 MAX
(BRAZE AREA)
Ø0.85 MAX
(BRAZE AREA)
(R0.05)
(Ø0.305)
(1.4)
A
A
DETAIL G
PIN AND BRAZE DIMENSIONS
149 PLACES
SCALE 40 : 1
TEXAS
INSTRUMENTS
Dallas Texas
INV2013-DLPa
8
7
6
5
4
3
DRAWN
B. HASKETT
DATE
12/7/2015
SIZE
D
SCALE
2
DWG NO
REV
2514853
SHEET
1
4
OF
C
4
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