Texas Instruments | DLP230KP 0.23 HD DMD (Rev. A) | Datasheet | Texas Instruments DLP230KP 0.23 HD DMD (Rev. A) Datasheet

Texas Instruments DLP230KP 0.23 HD DMD (Rev. A) Datasheet
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DLP230KP
DLPS138A – JULY 2018 – REVISED SEPTEMBER 2018
DLP230KP 0.23 HD DMD
1 Features
3 Description
•
The DLP230KP digital micromirror device (DMD) is a
digitally
controlled
micro-opto-electromechanical
system (MOEMS) spatial light modulator (SLM).
When coupled to an appropriate optical system, the
device DMD displays a crisp and high quality HD
image or video. DLP230KP is part of the chipset
comprising the DLP230KP DMD and DLPC3434
controller. The DLPA2000, DLP2005, and DLP3000
PMIC/LED drivers also support this chipset. The
compact physical size of the device applies to
portable equipment where high image quality, small
form factor, and low power are important.
1
•
•
•
Ultra Compact 0.23-Inch (5.95-mm) Diagonal
Micromirror Array
– Displays HD 1280 × 720 Pixels On the Screen
– 5.4 µm Micromirror Pitch
– 17° Micromirror Tilt (Relative to Flat Surface)
– Side Illumination for Optimal Efficiency and
Optical Engine Size
– Polarization Independent Aluminum
Micromirror Surface
8-Bit SubLVDS Input Data Bus
Dedicated DLPC3434 Controller for Display
Applications
Dedicated DLPA2000, DLPA2005, or DLPA3000
PMIC/LED Driver for Reliable Operation
2 Display Applications
•
•
•
•
Ultra Mobile, Ultra Low Power Pico Projectors
Phone, Tablet and Laptop
Smart Speaker
Smart Home
Visit the Getting Started with TI DLP® PicoTM Display
Technology page to learn more about DMD
technology.
The DLP230KP includes established resources to
help the user accelerate the design cycle, which
include production ready optical modules, optical
modules manufacturers, and design houses.
Device Information(1)
PART NUMBER
DLP230KP
PACKAGE
FQP (54)
BODY SIZE (NOM)
16.8 mm × 5.92 mm × 3.58 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
DLPC3434
Display
Controller
D_P(0)
D_N(0)
VOFFSET
D_P(1)
D_N(1)
VBIAS
600 MHz
SubLVDS
DDR
Interface
D_P(6)
D_N(6)
D_P(7)
D_N(7)
DLPA2000
DLPA2005
DLPA3000
Power
Management
VRESET
DLP230KP DMD
Digital
Micromirror
Device
VDDI
DCLK_P
DCLK_N
VDD
120 MHz
SDR
Interface
LS_WDATA
LS_CLK
LS_RDATA
VSS
DMD_DEN_ARSTZ
(System signal routing omitted for clarity)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP230KP
DLPS138A – JULY 2018 – REVISED SEPTEMBER 2018
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Display Applications..............................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
6
Absolute Maximum Ratings ..................................... 6
Storage Conditions.................................................... 6
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information ................................................ 10
Electrical Characteristics......................................... 10
Timing Requirements .............................................. 11
Switching Characteristics ....................................... 15
System Mounting Interface Loads .......................... 16
Micromirror Array Physical Characteristics ........... 17
Micromirror Array Optical Characteristics ............. 18
Window Characteristics......................................... 19
Chipset Component Usage Specification ............. 19
Detailed Description ............................................ 20
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
21
22
22
7.5 Optical Interface and System Image Quality
Considerations ......................................................... 22
7.6 Micromirror Array Temperature Calculation............ 23
7.7 Micromirror Landed-On/Landed-Off Duty Cycle .... 24
8
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application .................................................. 29
9
Power Supply Recommendations...................... 31
9.1 Power Supply Power-Up Procedure ...................... 31
9.2 Power Supply Power-Down Procedure .................. 31
9.3 Power Supply Sequencing Requirements .............. 32
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
12.1 Package Option Addendum .................................. 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2018) to Revision A
Page
•
Updated Simplified Application .............................................................................................................................................. 1
•
Changed data sheet status from Advance Information to Production Data .......................................................................... 1
2
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DLPS138A – JULY 2018 – REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
FQP Package
54-Pin CLGA
Bottom View
1
3
2
5
7
6
4
9
8
11
10
13
12
15
14
A
B
C
D
E
F
Pin Functions – Connector Pins (1)
PIN
NAME
NO.
TYPE
SIGNAL
DATA RATE
DESCRIPTION
PACKAGE NET
LENGTH (2) (mm)
DATA INPUTS
D_N(0)
A2
I
SubLVDS
Double
Data, negative
1.96
D_N(1)
A1
I
SubLVDS
Double
Data, negative
1.42
D_N(2)
C1
I
SubLVDS
Double
Data, negative
1.35
D_N(3)
B4
I
SubLVDS
Double
Data, negative
3.36
D_N(4)
F5
I
SubLVDS
Double
Data, negative
4.29
D_N(5)
D4
I
SubLVDS
Double
Data, negative
3.20
D_N(6)
E1
I
SubLVDS
Double
Data, negative
1.76
D_N(7)
F3
I
SubLVDS
Double
Data, negative
2.66
D_P(0)
A3
I
SubLVDS
Double
Data, positive
1.97
D_P(1)
B1
I
SubLVDS
Double
Data, positive
1.49
D_P(2)
C2
I
SubLVDS
Double
Data, positive
1.44
D_P(3)
A4
I
SubLVDS
Double
Data, positive
3.45
D_P(4)
E5
I
SubLVDS
Double
Data, positive
4.32
D_P(5)
D5
I
SubLVDS
Double
Data, positive
3.27
D_P(6)
E2
I
SubLVDS
Double
Data, positive
1.85
D_P(7)
F2
I
SubLVDS
Double
Data, positive
2.75
DCLK_N
C3
I
SubLVDS
Double
Clock, negative
1.94
DCLK_P
D3
I
SubLVDS
Double
Clock, positive
2.02
A12
I
LPSDR (1)
Single
Write data for low speed interface.
2.16
CONTROL INPUTS
LS_WDATA
(1)
(2)
Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
Net trace lengths inside the package:
Relative dielectric constant for the FQP ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm.
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Pin Functions – Connector Pins(1) (continued)
PIN
TYPE
SIGNAL
DATA RATE
DESCRIPTION
PACKAGE NET
LENGTH (2) (mm)
NAME
NO.
LS_CLK
B12
I
LPSDR
Single
Clock for low-speed interface.
3.38
DMD_DEN_ARSTZ
B14
I
LPSDR
Single
0.67
DMD_DEN_ARSTZ
F1
I
LPSDR
Single
Asynchronous reset DMD signal. A
low signal places the DMD in reset. A
high signal releases the DMD from
reset and places it in active mode.
C13
O
LPSDR
Single
VBIAS (3)
A15
Power
VBIAS (3)
A5
Power
VOFFSET (3)
F13
Power
VOFFSET (3)
F4
Power
VRESET
B15
Power
VRESET
B5
Power
VDD (3)
C15
Power
VDD
C5
Power
VDD
D14
Power
VDD
D15
Power
VDD
E14
Power
VDD
E15
Power
VDD
F14
Power
VDD
F15
Power
VDDI
C14
Power
VDDI
C4
Power
VDDI
D13
Power
VDDI
E13
Power
VSS
A13
Ground
VSS
A14
Ground
VSS
B13
Ground
VSS
B2
Ground
VSS
B3
Ground
VSS
C12
Ground
VSS
D1
Ground
VSS
D12
Ground
VSS
D2
Ground
VSS
E12
Ground
VSS
E3
Ground
VSS
E4
Ground
VSS
F12
Ground
LS_RDATA
Read data for low-speed interface.
14.90
2.44
POWER
(3)
4
Supply voltage for positive bias level
at micromirrors.
Supply voltage for HVCMOS core
logic. Supply voltage for stepped high
level at micromirror address
electrodes.
Supply voltage for offset level at
micromirrors.
Supply voltage for negative reset level
at micromirrors.
Supply voltage for LVCMOS core
logic. Supply voltage for LPSDR
inputs.
Supply voltage for normal high level at
micromirror address electrodes.
Supply voltage for SubLVDS
receivers.
Common return.
Ground for all power.
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also
required.
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Pin Functions – Test Pads
NUMBER
SYSTEM BOARD
A6
Do not connect
A7
Do not connect
A8
Do not connect
A9
Do not connect
A10
Do not connect
A11
Do not connect
F6
Do not connect
F7
Do not connect
F8
Do not connect
F9
Do not connect
F10
Do not connect
F11
Do not connect
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6 Specifications
6.1 Absolute Maximum Ratings
see
(1)
VDD
Clock
frequency
(3)
(4)
(5)
(6)
(7)
(8)
(9)
–0.5
2.3
V
–0.5
2.3
V
VOFFSET
–0.5
11
V
Supply voltage for micromirror electrode (2)
–0.5
19
V
VRESET
Supply voltage for micromirror electrode (2)
–15
0.5
V
|VDDI–VDD|
Supply voltage delta (absolute value) (4)
0.3
V
|VBIAS–VOFFSET|
Supply voltage delta (absolute value)
(5)
11
V
|VBIAS–VRESET|
Supply voltage delta (absolute value) (6)
34
V
–0.5
VDD + 0.5
V
–0.5
(2) (7)
VDDI + 0.5
V
|VID|
SubLVDS input differential voltage (absolute value) (7)
810
mV
IID
SubLVDS input differential current
10
mA
ƒclock
Clock frequency for low speed interface LS_CLK
130
MHz
ƒclock
Clock frequency for high speed interface DCLK
620
MHz
–20
90
°C
–40
90
°C
TARRAY and TWINDOW
Environmental
UNIT
Supply voltage for HVCMOS and micromirror
electrode (2) (3)
Input voltage for other inputs SubLVDS
Input pins
MAX
Supply voltage for SubLVDS receivers
Input voltage for other inputs LPSDR (2)
Input voltage
(2)
(2)
MIN
VDDI
Supply voltage VBIAS
(1)
Supply voltage for LVCMOS core logic (2)
Supply voltage for LPSDR low speed interface
Temperature – operational
(8)
Temperature – non-operational (8)
|TDELTA|
Absolute temperature delta between any point on the
window edge and the ceramic test point TP1 (9)
30
°C
TDP
Dew Point - operating and non-operating
81
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device
reliability.
All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VDD,
VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation) or of any point along the
window edge is defined in Figure 18. The location of thermal test point TP2 in Figure 18 is intended to measure the highest window
edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should
be used.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 18. The window test point TP2 shown in Figure 18 is intended to result in the worst case delta. If a particular application causes
another point on the window edge to result in a larger delta temperature, that point should be used.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
TDMD
DMD storage temperature
TDP
Average dew point temperature (non-condensing)
Elevated dew point temperature range (non-condensing)
CTELR
Cumulative time in elevated dew point temperature range
6
MAX
UNIT
–40
85
°C
24
°C
(1)
TDP-ELR
(1)
(2)
MIN
(2)
28
36
°C
6
months
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative
time of CTELR.
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6.3 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE (3)
VDD
Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface
1.65
1.8
1.95
V
VDDI
Supply voltage for SubLVDS receivers
1.65
1.8
1.95
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode (4)
9.5
10
10.5
V
VBIAS
Supply voltage for mirror electrode
17.5
18
18.5
V
VRESET
Supply voltage for micromirror electrode
–14.5
–14
–13.5
V
|VDDI–VDD|
Supply voltage delta (absolute value) (5)
0.3
V
|VBIAS–VOFFSET|
Supply voltage delta (absolute value) (6)
10.5
V
(7)
33
V
120
MHz
300
540
MHz
44%
56%
|VBIAS–VRESET|
Supply voltage delta (absolute value)
CLOCK FREQUENCY
ƒclock
ƒclock
Clock frequency for low speed interface LS_CLK (8)
Clock frequency for high speed interface DCLK
(9)
Duty cycle distortion DCLK
108
SUBLVDS INTERFACE (9)
|VID|
SubLVDS input differential voltage (absolute value). See
Figure 8, Figure 9
150
250
350
mV
VCM
Common mode voltage. See Figure 8, Figure 9
700
900
1100
mV
VSUBLVDS
SubLVDS voltage. See Figure 8, Figure 9
575
1225
mV
ZLINE
Line differential impedance (PWB/trace)
90
100
110
Ω
ZIN
Internal differential termination resistance. See Figure 10
80
100
120
100-Ω differential PCB trace
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6.35
152.4
Ω
mm
The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also
required.
All voltage values are with respect to the ground pins (VSS).
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
Refer to the SubLVDS timing requirements in Timing Requirements.
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Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
NOM
MAX
UNIT
ENVIRONMENTAL
Array temperature – long-term operational (10)
TARRAY
(11) (12) (13)
0
40 to 70 (12)
°C
–20
–10
°C
Array temperature – short-term operational, 500 hr
max (11) (14)
–10
0
°C
Array temperature – short-term operational, 500 hr
max (11) (14)
70
75
°C
90
°C
25
°C
24
°C
36
°C
Array temperature – short-term operational, 25 hr max
(11)
(14)
TWINDOW
Window temperature – operational (15)
|TDELTA|
Absolute temperature delta between any point on the
window edge and the ceramic test point TP1 (17)
TDP-AVG
Average dew point temperature (non-condensing)
TDP-ELR
Elevated dew point temperature range (non-condensing)
CTELR
Cumulative time in elevated dew point temperature range
ILLUV
Illumination wavelengths < 420 nm
ILLVIS
Illumination wavelengths between 420 nm and 700 nm
ILLIR
Illumination wavelengths > 700 nm
ILLθ
(16)
(18)
(19)
Illumination marginal ray angle
(10)
(15)
28
6
months
0.68
mW/cm2
Thermally
limited
10
mW/cm2
55
degrees
(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 18 and the package thermal resistance using Micromirror Array Temperature Calculation.
(12) Per Figure 1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty
cycle.
(13) Long-term is defined as the usable life of the device.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including at the pond of
micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not
necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance
has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including
POM) will contribute to thermal limitations described in this document and may negatively affect lifetime.
(16) Window temperature is the highest temperature on the window edge shown in Figure 18. The location of thermal test point TP2 in
Figure 18 is intended to measure the highest window edge temperature. If a particular application causes another point on the window
edge to be at a higher temperature, that point should be used.
(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in
Figure 18. The window test point TP2 shown in Figure 18 is intended to result in the worst case delta temperature. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative
time of CTELR.
8
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Max Recommended Array Temperature –
Operational (°C)
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80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
Micromirror Landed Duty Cycle
60/40
55/45
D001
Figure 1. Maximum Recommended Array Temperature – Derating Curve
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6.5 Thermal Information
DLP230KP
THERMAL METRIC (1)
FQP (CLGA)
UNIT
54 PINS
Thermal resistance
(1)
Active area to test point 1 (TP1) (1)
9.0
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the
DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the
window aperture and electrical power dissipated by the array. Optical systems should be designed to minimize the light energy falling
outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted) (1)
TEST CONDITIONS (2)
PARAMETER
MIN
TYP
MAX
UNIT
CURRENT
IDD
Supply current: VDD (3)
(4)
IDDI
Supply current: VDDI (3)
(4)
IOFFSET
Supply current: VOFFSET (5)
IBIAS
Supply current: VBIAS (5)
IRESET
Supply current: VRESET (6)
VDD = 1.95 V
65
VDD = 1.8 V
53
VDDI = 1.95 V
12
VDD = 1.8 V
11
VOFFSET = 10.5 V
(6)
1.5
VOFFSET = 10 V
1.4
VBIAS = 18.5 V
(6)
0.3
VBIAS = 18 V
0.29
VRESET = –14.5 V
–1.3
VRESET = –14 V
–1.2
mA
mA
mA
mA
mA
POWER (7)
PDD
Supply power dissipation: VDD (3)
(4)
PDDI
Supply power dissipation: VDDI (3)
(4)
POFFSET
VDD = 1.95 V
126.75
VDD = 1.8 V
95.4
VDDI = 1.95 V
23.4
VDD = 1.8 V
Supply power dissipation: VOFFSET (5)
(6)
19.8
VOFFSET = 10.5 V
15.75
VOFFSET = 10 V
PBIAS
Supply power dissipation: VBIAS (5)
(6)
PRESET
Supply power dissipation: VRESET (6)
PTOTAL
Supply power dissipation: Total
14
VBIAS = 18.5 V
5.55
VBIAS = 18 V
5.22
VRESET = –14.5 V
18.85
VRESET = –14 V
16.80
151.22
190.3
mW
mW
mW
mW
mW
mW
LPSDR INPUT (8)
VIH(DC)
DC input high voltage (9)
VIL(DC)
DC input low voltage (9)
VIH(AC)
AC input high voltage (9)
(9)
VIL(AC)
AC input low voltage
∆VT
Hysteresis ( VT+ – VT– )
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
10
Figure 10
0.7 × VDD
VDD + 0.3
V
–0.3
0.3 × VDD
V
0.8 × VDD
VDD + 0.3
V
–0.3
0.2 × VDD
V
0.1 × VDD
0.4 × VDD
V
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
Supply power dissipation based on non–compressed commands and data.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also
required.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
TEST CONDITIONS (2)
PARAMETER
IIL
Low–level input current
VDD = 1.95 V; VI = 0 V
IIH
High–level input current
VDD = 1.95 V; VI = 1.95 V
MIN
TYP
MAX
–100
UNIT
nA
100
nA
LPSDR OUTPUT (10)
VOH
DC output high voltage
IOH = –2 mA
VOL
DC output low voltage
IOL = 2 mA
0.8 × VDD
0.2 × VDD
V
V
Input capacitance LPSDR
ƒ = 1 MHz
10
pF
CAPACITANCE
CIN
Input capacitance SubLVDS
ƒ = 1 MHz
20
pF
COUT
Output capacitance
ƒ = 1 MHz
10
pF
CRESET
Reset group capacitance
ƒ = 1 MHz; (540 × 120) micromirrors
150
pF
MAX
UNIT
90
(10) LPSDR specification is for pin LS_RDATA.
6.7 Timing Requirements
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MIN
NOM
LPSDR
tr
Rise slew rate (1)
(30% to 80%) × VDD, Figure 3
1
3
V/ns
tƒ
Fall slew rate (1)
(70% to 20%) × VDD, Figure 3
1
3
V/ns
tr
Rise slew rate (2)
(20% to 80%) × VDD, Figure 3
0.25
(80% to 20%) × VDD, Figure 3
0.25
(2)
tƒ
Fall slew rate
tc
Cycle time LS_CLK
tW(H)
Pulse duration LS_CLK
high
tW(L)
Pulse duration LS_CLK low 50% to 50% reference points, Figure 2
tsu
Setup time
LS_WDATA valid before LS_CLK ↑, Figure 2
th
Hold time
LS_WDATA valid after LS_CLK ↑, Figure 2
tWINDOW
tDERATING
Window time
Figure 2
(1) (3)
Window time derating
50% to 50% reference points, Figure 2
Setup time + hold time, Figure 2
(1) (3)
7.7
V/ns
V/ns
8.3
ns
3.1
ns
3.1
ns
1.5
ns
1.5
ns
3
For each 0.25 V/ns reduction in slew rate
below 1 V/ns, Figure 5
ns
0.35
ns
SubLVDS
tr
Rise slew rate
20% to 80% reference points, Figure 4
0.7
1
V/ns
tƒ
Fall slew rate
80% to 20% reference points, Figure 4
0.7
1
V/ns
tc
Cycle time DCLK
Figure 6
1.79
1.85
tW(H)
Pulse duration DCLK high
50% to 50% reference points, Figure 6
0.79
ns
tW(L)
Pulse duration DCLK low
50% to 50% reference points, Figure 6
0.79
ns
tsu
Setup time
D(0:7) valid before
DCLK ↑ or DCLK ↓, Figure 6
th
Hold time
D(0:7) valid after
DCLK ↑ or DCLK ↓, Figure 6
tWINDOW
Window time
Setup time + hold time, Figure 6, Figure 7
tLVDS-
Power-up receiver (4)
ns
0.3
ns
2000
ns
ENABLE+REFGEN
(1)
(2)
(3)
(4)
Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3.
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3.
Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
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tc
tw(H)
LS_CLK
50%
tw(L)
50%
50%
th
tsu
LS_ WDATA
50%
50%
twindow
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in
JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Figure 2. LPSDR Switching Parameters
LS_CLK, LS_WDATA
DMD_DEN_ARSTZ
1.0 * VDD
1.0 * VDD
0.8 * VDD
0.7 * VDD
VIH(AC)
VIH(DC)
0.3 * VDD
0.2 * VDD
VIL(DC)
VIL(AC)
0.8 * VDD
0.2 * VDD
0.0 * VDD
0.0 * VDD
tr
tf
tr
tf
Figure 3. LPSDR Input Rise and Fall Slew Rate
Figure 4. SubLVDS Input Rise and Fall Slew Rate
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VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tSU
tH
VIH MIN
Midpoint
LS_WDATA
VIL MAX
tWINDOW
Figure 5. Window Time Derating Concept
Figure 6. SubLVDS Switching Parameters
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Note: Refer to High-Speed Interface for details.
Figure 7. High-Speed Training Scan Window
Figure 8. SubLVDS Voltage Parameters
1.225V
V SubLVDS max = V CM max + | 1/2 * V ID max |
VCM
VID
VSubLVDS min = VCM min – | 1/2 * VID max |
0.575V
Figure 9. SubLVDS Waveform Parameters
Figure 10. SubLVDS Equivalent Input Circuit
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Not to Scale
VIH
VT+
Δ VT
VT-
VIL
LS_CLK
LS_WDATA
Figure 11. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop Start
tPD
LS_RDATA
Acknowledge
Figure 12. LPSDR Read Out
Data Sheet Timing Reference Point
Device Pin
Output Under Test
Tester Channel
CL
See Timing for more information.
Figure 13. Test Load Circuit for Output Propagation Measurement
6.8 Switching Characteristics (1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
tPD
Output propagation, clock to Q, rising
edge of LS_CLK input to LS_RDATA
output. See Figure 12.
MAX
UNIT
CL = 5 pF
TEST CONDITIONS
11.1
ns
CL = 10 pF
11.3
ns
CL = 85 pF
15
Slew rate, LS_RDATA
TYP
0.5
Output duty cycle distortion, LS_RDATA
(1)
MIN
40%
ns
V/ns
60%
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
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6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Maximum system mounting interface load to be applied to the:
•
•
(1)
Thermal interface area
(1)
Clamping and electrical interface area
(1)
45
N
100
N
Uniformly distributed within area shown in Figure 14.
Datum 'A' Area
(3 places)
Datum 'E' Area
(1 place)
Thermal Interface Area
Electrical Interface Area
Figure 14. System Interface Loads
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6.10 Micromirror Array Physical Characteristics
PARAMETER
ε
(2)
UNIT
See Figure 15
960
Number of active rows (1)
See Figure 15
540
micromirrors
Micromirror (pixel) pitch
See Figure 16
5.4
µm
Micromirror active array
width
Micromirror pitch × number of active columns; see Figure 15
5.184
mm
Micromirror active array
height
Micromirror pitch × number of active rows; see Figure 15
2.916
mm
(2)
20
micromirrors/side
Micromirror active border
(1)
VALUE
Number of active
columns (1)
Pond of micromirror (POM)
micromirrors
The fast switching speed of the DMD micromirrors combined with advanced DLP image processing algorithms enables each micromirror
to display two distinct pixels on the screen during every frame, resulting in a full 1280 x 720 pixel image being displayed.
The structure and qualities of the border around the active array include a band of partially functional micromirrors called the POM.
These micromirrors are structurally or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to
tilt toward OFF.
Figure 15. Micromirror Array Physical Characteristics
ε
ε
ε
ε
Figure 16. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
Micromirror tilt angle tolerance (2)
Micromirror tilt direction (6)
MIN
DMD landed state (1)
Micromirror tilt angle
(3) (4) (5)
(7)
NOM
–1.4
180
Landed OFF state
270
Typical performance
Micromirror switching time (9)
Typical performance
Number of out-of-specification
micromirrors (10)
Adjacent micromirrors
1
degree
degree
3
10
0
Non-adjacent micromirrors
UNIT
degree
1.4
Landed ON state
Micromirror crossover time (8)
MAX
17
10
µs
micromirrors
(1)
(2)
(3)
(4)
Measured relative to the plane formed by the overall micromirror array.
Additional variation exists between the micromirror array and the package datums.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations, system efficiency variations, or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state
direction. A binary value of 0 results in a micromirror landing in the OFF state direction.
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(9) The minimum time between successive transitions of a micromirror.
(10) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the
specified micromirror switching time.
Figure 17. Landed Pixel Orientation and Tilt
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6.12 Window Characteristics
PARAMETER (1)
MIN
Window material designation
Window refractive index
Window aperture
MAX
UNIT
1.5119
(3)
Window transmittance, single-pass
through both surfaces and glass
(1)
(2)
(3)
At wavelength 546.1 nm
(2)
Illumination overfill
NOM
Corning Eagle XG
Minimum within the wavelength range
420 to 680 nm. Applies to all angles 0°
to 30° AOI.
97%
Average over the wavelength range 420
to 680 nm. Applies to all angles 30° to
45° AOI.
97%
See
(2)
See
(3)
See Optical Interface and System Image Quality Considerations for more information.
See the package mechanical characteristics for details regarding the size and location of the window aperture.
The active area of the DLP230KP device is surrounded by an aperture on the inside of the DMD window surface that masks structures
of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating
the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The
illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux
level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on
the outside of the active array may cause system performance degradation.
6.13 Chipset Component Usage Specification
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
The DLP230KP is a component of one or more DLP® chipsets. Reliable function and operation of the DLP230KP
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI
technology and devices used for operating or controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
The DLP230KP is a 0.23-inch diagonal spatial light modulator of aluminum micromirrors. Micromirror array size is
960 columns by 540 rows in a square micromirror arrangement. The fast switching speed of the DMD
micromirrors combined with advanced DLP image processing algorithms enables each micromirror to display two
distinct pixels on the screen during every frame, resulting in a full 1280 x 720 pixel image being displayed. The
electrical interface is sub low voltage differential signaling (SubLVDS) data.
The DLP230KP is part of the chipset comprised of the DLP230KP DMD, the DLPC3434ZVB display controller,
and the DLPA2000/2005/3000 PMIC/LED driver. To ensure reliable operation, the DLP230KP DMD must always
be used with the DLPC3434ZVB display controller and the DLPA2000/2005/3000 PMIC/LED drivers.
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7.2 Functional Block Diagram
(1)
Details omitted for clarity.
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7.3 Feature Description
7.3.1 Power Interface
The power management IC DLPA2000/2005/3000 contains three regulated DC supplies for the DMD reset
circuitry: VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3434ZVB controller.
7.3.2 Low-Speed Interface
The low speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the
low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs with a dedicated clock.
7.3.4 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 13 shows an equivalent test load circuit for the
output under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance value
stated is only for characterization and measurement of AC timing signals. This load capacitance value does not
indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC3434ZVB controller. See the DLPC3434ZVB controller data
sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light
path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display’s border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
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Optical Interface and System Image Quality Considerations (continued)
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
Array
2.96
Illumination
Direction
TP2
Off-state
Window Edge
TP2
(4 surfaces)
TP1
TP1
8.00
1.10
Figure 18. DMD Thermal Test Points
Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and the
illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test point TP1 in Figure 18) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC)
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
where
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Micromirror Array Temperature Calculation (continued)
•
•
•
•
•
•
•
TARRAY = Computed DMD array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 18
RARRAY–TO–CERAMIC = Thermal resistance from array to TP1 on ceramic (°C/W) specified in Thermal Information
QARRAY = Total (electrical + absorbed) DMD power on array (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W)
CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
SL = Measured ANSI screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. Nominal electrical power dissipation to use when calculating array temperature is 0.17 W. Absorbed
optical power from the illumination source is variable and depends on the operating state of the micromirrors and
the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with total projection
efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and
16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266
W/lm.
Sample calculations for typical projection application:
TCERAMIC = 55°C (measured)
SL = 200 lm (measured)
QELECTRICAL = 0.17 W
CL2W = 0.00266 W/lm
QARRAY = 0.17 W + (0.00266 W/lm × 200 lm) = 0.702 W
TARRAY = 55°C + (0.702 W × 9°C/W) = 61.32°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the
time and in the OFF state 25% of the time, whereas 25/75 would indicate that the pixel is in the ON state 25% of
the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
nominally add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array to an asymmetric landed duty cycle for a prolonged
period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
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Micromirror Landed-On/Landed-Off Duty Cycle (continued)
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the DMD’s usable life. This is quantified in
the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a given long-term average landed duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the nominal landed duty cycle of a given pixel is determined by the image content
being displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience very close to a 100/0 landed duty cycle during that time period. Likewise, when displaying pureblack, the pixel will experience very close to a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 1.
Table 1. Grayscale Value and
Landed Duty Cycle
Grayscale
Value
Nominal Landed
Duty Cycle
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color scale value
(from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the
color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a
given primary must be displayed in order to achieve the desired white point.
During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_%×Blue_Scale_Value)
where
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that red, green, and
blue are displayed (respectively) to achieve the desired white point.
(1)
For example, assuming that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the nominal landed duty cycle for various combinations of red,
green, blue color intensities would be as shown in Table 2.
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Table 2. Example Landed Duty Cycle for Full-Color
Pixels
Red Cycle
Percentage
Green Cycle
Percentage
Blue Cycle
Percentage
50%
20%
30%
Red Scale
Value
Green Scale
Value
Blue Scale
Value
Nominal
Landed Duty
Cycle
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the DLP
controller DLPC3434ZVB, the three functions which influence the actual landed duty cycle are gamma,
IntelliBright™, and bitplane sequencing rules.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC3434ZVB controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical
gamma factor is 2.2, which transforms the incoming data as shown in Figure 19.
100
90
Output Level (%)
80
Gamma = 2.2
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Input Level (%)
70
80
90
100
D002
Figure 19. Example of Gamma = 2.2
26
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For example, from Figure 19, if the gray scale value of a given input pixel is 40% (before gamma is applied), then
the gray scale value will be 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct
impact displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
The IntelliBright algorithm's content adaptive illumination control (CAIC) and local area brightness boost (LABB)
also apply transform functions on the gray scale level of each pixel.
But while the amount of gamma applied to every pixel of every frame is constant (the exponent, gamma, is
constant), CAIC and LABB are both adaptive functions that can apply different amounts of either boost or
compression to every pixel of every frame.
Consideration must also be given to any image processing which occurs before the DLPC3434ZVB controller.
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8 Application and Implementation
NOTE
Information in the following application sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC3434
controller. The new high tilt pixel in the side-illuminated DMD increases brightness performance and enables a
smaller system footprint for thickness-constrained applications. Applications of interest include projection
technology embedded in display devices like ultra low-power battery operated mobile accessory projectors,
phones, tablets, ultra mobile low end Smart TVs, and virtual assistants.
DMD power-up and power-down sequencing is strictly controlled by the DLPA2000/2005/3000. Refer to Power
Supply Recommendations for power-up and power-down specifications. To ensure reliable operation, the
DLP230KP DMD must always be used with the DLPC3434 display controller and a DLPA2000/2005/3000
PMIC/LED driver.
28
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8.2 Typical Application
A common application when using a DLP230KP DMD and a DLPC3434 is for creating a pico projector that can
be used as an accessory to a smartphone, tablet, or a laptop. The DLPC3434 in the pico projector receives
images from a multimedia front end within the product as shown in Figure 20.
Figure 20. Typical Application Diagram
8.2.1 Design Requirements
A pico projector is created by using a DLP chipset comprised of a DLP230KP DMD, a DLPC3434 controller, and
a DLPA2000/2005/3000 PMIC/LED driver. The DLPC3434 controller performs the digital image processing, the
DLPA2000/2005/3000 provides the needed analog functions for the projector, and the DLP230KP DMD is the
display device for producing the projected image.
In addition to the three DLP chips in the chipset, other chips are needed. At a minimum a flash part is needed to
store the DLPC3434 controller software.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico projector.
The DLPC3434 controller receives image data from the multimedia front end over a 24-bit parallel interface. An
I2C interface should be connected from the multimedia front end for sending commands to the DLPC3434
controller for configuring the chipset for different features.
8.2.2 Detailed Design Procedure
For connecting together the DLPC3434 controller, the DLPA2000/2005/3000, and the DLP230KP DMD, see the
reference design schematic. When a circuit board layout is created from this schematic a very small circuit board
is possible. An example small board layout is included in the reference design data base. Layout guidelines
should be followed to achieve a reliable projector.
The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
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Typical Application (continued)
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is as shown in Figure 21. For the LED currents shown, it is assumed
that the same current amplitude is applied to the red, green, and blue LEDs.
1
0.9
0.8
Luminance
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
500
1000
1500
Current (mA)
2000
2500
3000
D001
Figure 21. Luminance vs Current
30
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS
connections are also required. DMD power-up and power-down sequencing is strictly controlled by the
DLPA2000/2005/3000 devices.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power-up and
power-down procedures may affect device reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during
power-up and power-down operations. Failure to meet any of the below requirements
will result in a significant reduction in the DMD’s reliability and lifetime. Refer to
Figure 23. VSS must also be connected.
9.1 Power Supply Power-Up Procedure
•
•
•
•
During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are
applied to the DMD.
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. Refer to Figure 23 for power-up delay
requirements.
During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled
at operating voltage.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements listed previously and in Figure 22.
9.2 Power Supply Power-Down Procedure
•
•
•
•
•
The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that
the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating
Conditions (Refer to Note 2 for Figure 22).
During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in
Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in Figure 22.
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9.3 Power Supply Sequencing Requirements
(1)
Refer to Table 3 and Figure 23 for critical power-up sequence delay requirements.
(2)
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended
Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS
during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 3 and Figure 23 for powerup delay requirements.
(3)
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit shown in
Recommended Operating Conditions.
(4)
When system power is interrupted, the DLPA2000/2005/3000 initiates hardware power-down that disables VBIAS,
VRESET and VOFFSET after the micromirror park sequence.
(5)
Drawing is not to scale and details are omitted for clarity.
Figure 22. Power Supply Sequencing Requirements (Power Up and Power Down)
32
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Power Supply Sequencing Requirements (continued)
Table 3. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX
2
UNIT
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
VOFFSET
Supply voltage level at beginning of power–up sequence delay (see Figure 23)
6
ms
V
VBIAS
Supply voltage level at end of power–up sequence delay (see Figure 23)
6
V
12 V
VOFFSET
8V
VDD ≤ VOFFSET < 6 V
4V
VSS
tDELAY
0V
VBIAS
20 V
16 V
12 V
8V
VDD ≤ VBIAS < 6 V
4V
VSS
0V
Refer to Table 3 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 23. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
The DLP230KP DMD is connected to a PCB or a flex circuit using an interposer. For additional layout guidelines
regarding length matching, impedance, etc. see the DLPC3434 controller datasheet. For a detailed layout
example refer to the layout design files. Some layout guidelines for routing to the DLP230KP DMD are:
•
•
•
•
•
•
Match lengths for the LS_WDATA and LS_CLK signals.
Minimize vias, layer changes, and turns for the HS bus signals. Refer to Figure 24.
Minimum of two 100-nF (25 V) capacitors - one close to VBIAS pin. Capacitors C4 and C8 in Figure 24.
Minimum of two 100-nF (25 V) capacitors - one close to each VRST pin. Capacitors C3 and C7 in Figure 24.
Minimum of two 220-nF (25 V) capacitors - one close to each VOFS pin. Capacitors C5 and C6 in Figure 24.
Minimum of four 100-nF (6.3 V) capacitors - two close to each side of the DMD. Capacitors C1, C2, C9 and
C10 in Figure 24.
10.2 Layout Example
Figure 24. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Figure 25. Part Number Description
11.1.2 Device Markings
The device marking includes the legible character string GHJJJJK DLP230KPAFQP. GHJJJJK is the lot trace
code. DLP230KPAFQP is the device marking.
Lot Trace Code
GHJJJJK
DLP230KPAFQP
Part Marking
Figure 26. DMD Marking
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DLP230KP
TBD
TBD
TBD
TBD
TBD
DLPC3434
TBD
TBD
TBD
TBD
TBD
DLPA3000
Click here
Click here
Click here
Click here
Click here
DLPA2000
Click here
Click here
Click here
Click here
Click here
DLPA2005
Click here
Click here
Click here
Click here
Click here
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11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
IntelliBright, E2E are trademarks of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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12.1 Package Option Addendum
12.1.1 Packaging Information
Orderable Device
DLP230KPAFQP
(1)
(2)
(3)
(4)
(5)
Status
(1)
ACTIVE
Package
Type
Package
Drawing
Pins
Package
Qty
CLGA
FQP
54
100
Eco Plan
(2)
RoHS & Green
Lead/Ball Finish
Call TI
MSL Peak Temp
Level-1-NC-NC
(3)
Op Temp (°C)
Device Marking (4) (5)
–40°C to 90°C
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLP230KPAFQP
ACTIVE
Package Type Package Pins Package
Drawing
Qty
CLGA
FQP
54
100
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
RoHS & Green
Call TI
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
8
5
6
7
3
4
C
NOTES UNLESS OTHERWISE SPECIFIED:
DWG NO.
1
1
DESCRIPTION
ECO 2168534: INITIAL RELEASE
ECO 2168970: CORRECT SUBSTRATE THICKNESS TOL;
ENLARGE APERTURE SLIGHTLY
A
B
2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
SH
REVISIONS
COPYRIGHT 2017 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED. REV
1 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
2515699
DATE
9/5/2017
BY
BMH
9/15/17
BMH
3 BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
D
4 NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
D
5 ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
6 ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
7 DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
8 WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
4
1.176 0.05
4
C
(ILLUMINATION
DIRECTION)
+0.2
1.71 0.1
C
+0.2
2.96 - 0.1
4
1.25
4
4
90° 1°
4
2.5 0.075
4X R0.4 0.1
4
4
A
2.5
C
+0.3
5.92 0.1
7
B
A
4
4
4X (R0.2)
+0.2
0.8 0.1 4
15 0.08
+0.3
16.8 0.1
FRONT SIDE INDEX MARK
(OFF-STATE
DIRECTION)
5 6
B
D
1.403 0.077
1 8
(2.5)

1.1 0.05
(2.183)
0.038 A
0.02 D
4
ACTIVE ARRAY
A
0.78 0.063
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
8
1.4 0.1
H
(SHEET 3)
(1.4)
B
2X ENCAPSULANT
SEE VIEWS C AND D (SHEET 2)
FOR DIMENSIONS
H
(SHEET 3)
0.4 MIN TYP
0 MIN TYP
A
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
SECTION A-A
(ROTATED 90°)
SCALE 20 : 1
0314DA
THIRD ANGLE
PROJECTION
NEXT ASSY
USED ON
8
7
6
5
4
9/5/2017
ENGINEER
9/5/2017
B. HASKETT
2 PLACE DECIMALS 0.25
QA/CE
1 PLACE DECIMALS 0.50
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
P. KONRAD
CM
Dallas Texas
TITLE
9/10/2017
9/6/2017
M. DORAK
9/5/2017
SIZE
APPROVED
9/11/2017
SCALE
2
A
TEXAS
INSTRUMENTS
J. GRIMMETT
R. LONG
3
DATE
B. HASKETT
ANGLES 1
APPLICATION
INV11-2006a
DRAWN
ICD, MECHANICAL, DMD,
.23 TRP SERIES 246
(FQP PACKAGE)
REV
DWG NO
D
B
2515699
20:1
SHEET
1
1
OF
3
8
7
5
6
3
4
2X (1)
DWG NO.
2515699
2X 15
SH
1
2
2X 1.176
2X (0.8)
A3
D
C
A2
D
4X 1.46
1.25
2.5
B
7
4X (1.5)
8
E1
A1
VIEW B
DATUMS A, B, C, AND E
C
(1.1)
7
C
(FROM SHEET 1)
15
1.176
3.06
C
1.25
6.12
2.5
B
B
B
5
VIEW C
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
2X 0 MIN
(FROM SHEET 1)
6
A
A
VIEW D
ENCAPSULANT MAXIMUM HEIGHT
INV11-2006a
8
7
6
TEXAS
INSTRUMENTS
Dallas Texas
5
4
3
DRAWN
B. HASKETT
DATE
9/5/2017
SIZE
D
SCALE
2
DWG NO
REV
2515699
SHEET
1
2
OF
B
3
8
5
6
7
3
4X (0.108)
3
4
(5.184)
ACTIVE ARRAY
DWG NO.
2515699
SH
1
3
5.441 0.075
0.983 0.05
D
D
0.203 0.0635
C
(ILLUMINATION
DIRECTION)
2
1.458 0.075
1.25
(3.556)
APERTURE
(5.16)
WINDOW
F
3.353 0.0635
G
B
4.177 0.05
0.448 0.0635
5.535 0.0635

C
(2.916)
ACTIVE ARRAY
2.5
(5.983)
APERTURE
2.989 0.05
(OFF-STATE
DIRECTION)

C
7.087 0.05
(10.076) WINDOW
VIEW E
WINDOW AND ACTIVE ARRAY
(FROM SHEET 1)
3.49
4 X 0.7424
= 2.9696
B
1
BACK SIDE
INDEX MARK
(42°)
TYP.
(0.15) TYP.
(42°)
TYP.
2
3
4
5
9 X 0.7424 = 6.6816
6
7
2.106
12X CIRCULAR TEST PADS
(Ø0.52)
8
9
10
11
12
13
14
15
B
A
(0.075) TYP.
B
1.856
C
5 X 0.7424
= 3.712
C
1.25
D
2.5
E
(0.068) TYP.
(0.068) TYP.

(42°)
TYP.
F

DETAIL G
APERTURE RIGHT EDGE
DETAIL F
APERTURE LEFT EDGE
VIEW H-H
BACK SIDE METALLIZATION
54X SQUARE LGA PADS
0.52±0.05 X 0.52±0.05
SCALE 60 : 1
SCALE 60 : 1
A
B

0.2 A B C
0.1 A
TEXAS
INSTRUMENTS
Dallas Texas
INV11-2006a
8
7
6
5
A
(FROM SHEET 1)
4
3
DRAWN
B. HASKETT
DATE
9/5/2017
SIZE
D
SCALE
2
DWG NO
REV
2515699
SHEET
1
3
OF
B
3
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