Texas Instruments | DLP650NE 0.65 1080p S600 DMD | Datasheet | Texas Instruments DLP650NE 0.65 1080p S600 DMD Datasheet

Texas Instruments DLP650NE 0.65 1080p S600 DMD Datasheet
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DLP650NE
DLPS097 – AUGUST 2017
DLP650NE 0.65 1080p S600 DMD
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
0.65-Inch Micromirror Array Diagonal
– 1080p (1920 x 1080)
– 7.56 Micron Micromirror Pitch
– ± 12° Micromirror Tilt Angle (Relative to Flat
State)
– Corner Illumination
2x LVDS Input Data Bus
Dedicated DLPC4422 Display Controller,
DLPA100 Power Management IC and Motor
Driver for reliable operation
Full HD (1080p) Display
Laser TV
Mobile Smart TV
Digital Signage
Gaming
Home Cinema
3 Description
The TI DLP650NE digital micromirror device (DMD) is
a digitally controlled micro-opto-electromechanical
system (MEMS) spatial light light modulator (SLM)
that enables bright, affordable DLP® 0.65 1080p
display solutions. The DLP650NE DMD, together with
the DLPC4422 display controller and DLPA100 power
and motor driver, comprise the DLP 0.65 1080p
chipset. The solution is a great fit for display systems
that require high resolution, high brightness and
system simplicity.
.
Device Information(1)
PART NUMBER
DLP650NE
PACKAGE
FYE (350)
BODY SIZE (NOM)
35.0 mm × 32.2 mm × 5.1 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
.
DLP650NE 0.65 1080P DMD
Control Signals
ASIC Power
DLPA100
Colorwheel Motor Control
DAD control
DLPC4422
ASIC
SCP control
DMD RSTZ
DLP650NE
DMD
VBIAS
3.3 V
TPS65145
Voltage Regulator
VOFFSET
VRESET
EN_OFFSET
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP650NE
DLPS097 – AUGUST 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
8
8.3 Feature Description................................................. 24
8.4 Device Functional Modes........................................ 32
1
1
1
2
3
9
9
Application and Implementation ........................ 33
9.1 Application Information............................................ 33
9.2 Typical Application ................................................. 33
10 Power Supply Requirements ............................. 34
10.1 DMD Power Supply Requirements ...................... 34
10.2 DMD Power Supply Power-Up Procedure ........... 34
10.3 DMD Power Supply Power-Down Procedure ...... 34
Absolute Maximum Ratings ...................................... 9
Storage Conditions.................................................... 9
ESD Ratings............................................................ 10
Recommended Operating Conditions..................... 10
Thermal Information ................................................ 12
Electrical Characteristics......................................... 13
Timing Requirements .............................................. 14
System Mounting Interface Loads .......................... 18
Micromirror Array Physical Characteristics ............. 18
Micromirror Array Optical Characteristics ............. 19
Window Characteristics......................................... 20
Chipset Component Usage Specification ............. 21
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 37
12 Device Documentation Support......................... 41
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Parameter Measurement Information ................ 21
Detailed Description ............................................ 22
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
42
42
42
42
42
42
13 Mechanical, Packaging, and Orderable
Information ........................................................... 42
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
August 2017
*
Initial release.
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DLPS097 – AUGUST 2017
5 Pin Configuration and Functions
FYE Package
350-Pin CPGA
Top View
Pin Functions
PIN (1)
(2)
SIGNAL
DATA
RATE (3)
INTERNAL
TERM (4)
B14
I
LVDS
DDR
Differential
Data, negative
494.88
D_AN(1)
B15
I
LVDS
DDR
Differential
Data, negative
486.18
D_AN(2)
C16
I
LVDS
DDR
Differential
Data, negative
495.16
D_AN(3)
K24
I
LVDS
DDR
Differential
Data, negative
485.67
D_AN(4)
B18
I
LVDS
DDR
Differential
Data, negative
494.76
D_AN(5)
L24
I
LVDS
DDR
Differential
Data, negative
490.63
D_AN(6)
C19
I
LVDS
DDR
Differential
Data, negative
495.16
D_AN(7)
H24
I
LVDS
DDR
Differential
Data, negative
485.55
D_AN(8)
H23
I
LVDS
DDR
Differential
Data, negative
495.16
D_AN(9)
B25
I
LVDS
DDR
Differential
Data, negative
485.59
D_AN(10)
D24
I
LVDS
DDR
Differential
Data, negative
495.16
D_AN(11)
E25
I
LVDS
DDR
Differential
Data, negative
495.16
D_AN(12)
F25
I
LVDS
DDR
Differential
Data, negative
490.04
D_AN(13)
H25
I
LVDS
DDR
Differential
Data, negative
485.91
D_AN(14)
L25
I
LVDS
DDR
Differential
Data, negative
495.16
D_AN(15)
G24
I
LVDS
DDR
Differential
Data, negative
495.16
D_AP(0)
C14
I
LVDS
DDR
Differential
Data, positive
494.84
D_AP(1)
B16
I
LVDS
DDR
Differential
Data, positive
486.22
D_AP(2)
C17
I
LVDS
DDR
Differential
Data, positive
494.65
NAME
TYPE
NO.
DESCRIPTION
TRACE
(mils) (5)
DATA BUS A
D_AN(0)
(1)
(2)
(3)
(4)
(5)
The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
I = Input, O = Output, G = Ground
DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Timing Requirements for specifications and relationships.
Internal term - CMOS level internal termination. Refer to Recommended Operating Conditions for differential termination specification.
Dielectric Constant for the DMD S600 ceramic package is approximately 9.6. For the package trace lengths shown: Propagation Speed
= 11.8 / sqrt(9.6) = 3.808 in/ns. Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
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Pin Functions (continued)
PIN
NAME
(1)
TYPE
NO.
(2)
SIGNAL
DATA
RATE (3)
INTERNAL
TERM (4)
DESCRIPTION
TRACE
(mils) (5)
D_AP(3)
K23
I
LVDS
DDR
Differential
Data, positive
488.42
D_AP(4)
B19
I
LVDS
DDR
Differential
Data, positive
495.16
D_AP(5)
L23
I
LVDS
DDR
Differential
Data, positive
490.67
D_AP(6)
C20
I
LVDS
DDR
Differential
Data, positive
498.11
D_AP(7)
J24
I
LVDS
DDR
Differential
Data, positive
486.22
D_AP(8)
J23
I
LVDS
DDR
Differential
Data, positive
495.47
D_AP(9)
C25
I
LVDS
DDR
Differential
Data, positive
485.94
D_AP(10)
E24
I
LVDS
DDR
Differential
Data, positive
495.16
D_AP(11)
D25
I
LVDS
DDR
Differential
Data, positive
494.13
D_AP(12)
G25
I
LVDS
DDR
Differential
Data, positive
488.98
D_AP(13)
J25
I
LVDS
DDR
Differential
Data, positive
492.56
D_AP(14)
K25
I
LVDS
DDR
Differential
Data, positive
495.16
D_AP(15)
F24
I
LVDS
DDR
Differential
Data, positive
495.16
D_BN(0)
Z14
I
DDR
Differential
Data, negative
494.92
D_BN(1)
Z15
I
DDR
Differential
Data, negative
486.18
D_BN(2)
Y16
I
DDR
Differential
Data, negative
496.46
D_BN(3)
P24
I
DDR
Differential
Data, negative
493.74
D_BN(4)
Z18
I
DDR
Differential
Data, negative
494.76
D_BN(5)
N24
I
DDR
Differential
Data, negative
495.16
D_BN(6)
Y19
I
DDR
Differential
Data, negative
492.16
D_BN(7)
T24
I
DDR
Differential
Data, negative
492.68
D_BN(8)
T23
I
DDR
Differential
Data, negative
484.45
D_BN(9)
Z25
I
DDR
Differential
Data, negative
492.09
D_BN(10)
X24
I
DDR
Differential
Data, negative
497.72
D_BN(11)
W25
I
DDR
Differential
Data, negative
495.16
D_BN(12)
V25
I
DDR
Differential
Data, negative
484.17
D_BN(13)
T25
I
DDR
Differential
Data, negative
481.42
D_BN(14)
N25
I
DDR
Differential
Data, negative
495.16
D_BN(15)
U24
I
DDR
Differential
Data, negative
489.8
D_BP(0)
Y14
I
DDR
Differential
Data, positive
494.88
D_BP(1)
Z16
I
DDR
Differential
Data, positive
486.26
D_BP(2)
Y17
I
DDR
Differential
Data, positive
495.16
D_BP(3)
P23
I
DDR
Differential
Data, positive
492.48
D_BP(4)
Z19
I
DDR
Differential
Data, positive
495.16
D_BP(5)
N23
I
DDR
Differential
Data, positive
497.99
D_BP(6)
Y20
I
DDR
Differential
Data, positive
495.16
D_BP(7)
R24
I
DDR
Differential
Data, positive
492.05
D_BP(8)
R23
I
DDR
Differential
Data, positive
484.45
D_BP(9)
Y25
I
DDR
Differential
Data, positive
492.24
D_BP(10)
W24
I
DDR
Differential
Data, positive
495.16
D_BP(11)
X25
I
DDR
Differential
Data, positive
494.72
D_BP(12)
U25
I
DDR
Differential
Data, positive
483.78
D_BP(13)
R25
I
DDR
Differential
Data, positive
489.13
D_BP(14)
P25
I
DDR
Differential
Data, positive
499.53
D_BP(15)
V24
I
DDR
Differential
Data, positive
488.66
DATA BUS B
4
LVDS
LVDS
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Pin Functions (continued)
PIN
(1)
NAME
TYPE
NO.
(2)
SIGNAL
DATA
RATE (3)
INTERNAL
TERM (4)
DESCRIPTION
TRACE
(mils) (5)
SERIAL CONTROL
SCTRL_AN
C23
I
DDR
Differential
Serial control, negative
492.95
SCTRL_BN
Y23
I
DDR
Differential
Serial control, negative
493.78
SCTRL_AP
C24
I
DDR
Differential
Serial control, negative
493.78
SCTRL_BP
Y24
I
DDR
Differential
Serial control, negative
493.11
DCLK_AN
B23
I
Differential
Clock, negative
480.35
DCLK_BN
Z23
I
Differential
Clock, negative
486.22
DCLK_AP
B22
I
Differential
Clock, negative
485.83
DCLK_BP
Z22
I
Differential
Clock, negative
491.93
LVDS
CLOCKS
LVDS
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DO
B8
O
SDR
Serial communications port output
SCP_DI
B7
I
SDR
Serial communication port data I
LVCMOS
SCP_CLK
B6
I
SCP_ENZ
C8
I
Active-low serial communications port
enable
Pull-Down
Serial communications port clock
MICROMIRROR RESET CONTROL
RESET_ADDR(0)
X9
I
Reset driver address select
RESET_ADDR(1)
X8
I
Reset driver address select
RESET_ADDR(2)
Z8
I
Reset driver address select
RESET_ADDR(3)
Z7
I
Reset driver address select
RESET_MODE(0)
W11
I
RESET_MODE(1)
Z10
I
Reset driver mode select
RESET_SEL(0)
Y10
I
Reset driver level select
RESET_SEL(1)
Y9
I
Reset driver level select
RESET_STROBE
Y7
I
Reset address, mode, and level
latched on rising-edge
LVCMOS
Pull-Down
Reset driver mode select
ENABLES & INTERRUPTS
PWRDNZ
D2
I
Pull-Down
Active-low device reset
RESET_OEZ
W7
I
Pull-Down
Active-low output enable for DMD
reset driver circuits
RESETZ
Z6
I
Pull-Down
Active-low sets reset circuits in
known VOFFSET state
RESET_IRQZ
Z5
O
LVCMOS
Active-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
Active-low fault from external VBIAS
regulator
PG_BIAS
E11
I
PG_OFFSET
B10
I
PG_RESET
D11
I
EN_BIAS
D9
O
Active-high enable for external VBIAS
regulator
EN_OFFSET
C9
O
Active-high enable for external
VOFFSET regulator
EN_RESET
E9
O
Active-high enable for external
VRESET regulator
Pull-Up
LVCMOS
Active-low fault from external
VOFFSET regulator
Active-low from external VRESET
regulator
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Pin Functions (continued)
PIN
(1)
NAME
TYPE
NO.
(2)
SIGNAL
DATA
RATE (3)
INTERNAL
TERM (4)
DESCRIPTION
TRACE
(mils) (5)
LEAVE PIN UNCONNECTED
MBRST(0)
C2
O
MBRST(1)
C3
O
MBRST(2)
C5
O
MBRST(3)
C4
O
MBRST(4)
E5
O
MBRST(5)
E4
O
MBRST(6)
E3
O
MBRST(7)
G4
O
MBRST(8)
G3
O
MBRST(9)
G2
O
MBRST(10)
J4
O
MBRST(11)
J3
O
MBRST(12)
J2
O
MBRST(13)
L4
O
MBRST(14)
L3
O
MBRST(15)
L2
O
Analog
Pull-Down
LVCMOS
Pull-Down
For proper DMD operation, do not
connect
LEAVE PIN UNCONNECTED
RESERVED_PFE
E7
I
RESERVED_TM
D13
I
RESERVED_Xl1
E13
I
RESERVED_TP0
W12
I
RESERVED_TP1
Y11
I
RESERVED_TP2
X11
I
For proper DMD operation, do not
connect
Analog
LEAVE PIN UNCONNECTED
RESERVED_BA
Y12
O
RESERVED_BB
C12
O
RESERVED_TS
D5
O
LVCMOS
For proper DMD operation, do not
connect
LEAVE PIN UNCONNECTED
NO CONNECT
B11
NO CONNECT
C11
NO CONNECT
C13
NO CONNECT
E12
NO CONNECT
E14
NO CONNECT
E23
NO CONNECT
H4
NO CONNECT
N2
NO CONNECT
N3
NO CONNECT
N4
NO CONNECT
R2
NO CONNECT
R3
NO CONNECT
R4
NO CONNECT
T4
6
For proper DMD operation, do not
connect
For proper DMD operation, do not
connect
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Pin Functions (continued)
PIN
(1)
TYPE
NAME
NO.
NO CONNECT
U2
NO CONNECT
U3
NO CONNECT
U4
NO CONNECT
W3
NO CONNECT
W4
NO CONNECT
W5
NO CONNECT
W13
NO CONNECT
W14
NO CONNECT
W23
NO CONNECT
X4
NO CONNECT
X5
NO CONNECT
X13
NO CONNECT
Y2
NO CONNECT
Y3
NO CONNECT
Y4
NO CONNECT
Y5
NO CONNECT
Z11
(2)
SIGNAL
DATA
RATE (3)
INTERNAL
TERM (4)
DESCRIPTION
TRACE
(mils) (5)
For proper DMD operation, do not
connect
For proper DMD operation, do not
connect
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Power Pin Functions
PIN
8
(1)
SIGNAL
DESCRIPTION
NO.
VBIAS
A6, A7, A8, AA6, AA7, AA8
Analog
Supply voltage for positive Bias
level of Micromirror reset signal
A3, A4, A25
Analog
Supply voltage for HVCMOS
logic
B26, L26, M26
Analog
Supply voltage for stepped high
voltage at Micromirror address
electrodes
N26, Z26, AA3, AA4
Analog
Supply voltage for positive Offest
level of Micromirror reset signal.
VRESET
G1, H1, J1, R1, T1, U1
Analog
Supply voltage for negative
Reset level of Micromirror reset
signal.
VCC
A9, B3, B5, B12, C1, C6, C10,
D4, D6, D8, E1, E2, E10, E15,
E16, E17, F3, H2, K1, K3, M4,
P1, P3, T2, V3, W1, W2, W6,
W9, W10, W15, W16, W17, X3,
X6, Y1, Y8, Y13, Z1, Z3, Z12,
AA2, AA9, AA10
Analog
Supply voltage for LVCMOS core
logic. Supply voltage for normal
high level at Micromirror address
electrodes. Supply voltage for
positive Offset level of
Micromirror reset signal during
Power Down sequence.
VCCI
A16, A17, A18, A20, A21, A23,
AA16, AA17, AA18, AA20, AA21,
AA23
Analog
Supply voltage for LVDS
receivers.
VSS
A5, A10, A11, A19, A22, A24,
B2, B4, B9, B13, B17, B20, B21,
B24, C7, C15, C18, C21, C22,
C26, D1, D3, D7, D10, D12,
D14, D15, D16, D17, D18, D19,
D20, D21, D22, D23, D26, E6,
E8, E18, E19, E20, E21, E22,
E26, F1, F2, F4, F23, F26, G23,
G26, H3, H26, J26, K2, K4, K26,
L1, M1, M2, M3, M23, M24,
M25, N1, P2, P4, P26, R26, T3,
T26, U23, U26, V1, V2, V4, V23,
V26, W8, W18, W19, W20, W21,
W22, W26, X1, X2, X7, X10,
X12, X14, X15, X16, X17, X18,
X19, X20, X21, X22, X23, X26,
Y6, Y15, Y18, Y21, Y22, Y26,
Z2, Z4, Z9, Z13, Z17, Z20, Z21,
Z24, AA5, AA11, AA19, AA22,
AA24
Analog
Device ground. Common return
for all power.
VOFFSET
(1)
(2)
TYPE (I/O/P)
NAME (2)
P
P = Power
The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
4
V
–0.5
4
V
–0.5
9
V
SUPPLY VOLTAGES
VCC
Supply voltage for LVCMOS core logic
(2)
(2)
VCCI
Supply voltage for LVDS receivers
VOFFSET
Supply voltage for HVCMOS and micromirror electrode
(2) (3)
VBIAS
Supply voltage for micromirror electrode
(2)
VRESET
Supply voltage for micromirror electrode
(2)
| VCC – VCCI |
Supply voltage change (absolute value)
(4)
0.3
V
| VBIAS – VOFFSET | Supply voltage change (absolute value)
(5)
8.75
V
–0.5
VCC + 0.15
V
–0.5
VCCI + 0.15
V
700
mV
7
mA
460
MHz
10
90
ºC
10
70
ºC
–40
80
ºC
81
ºC
–0.5
17
V
–11
0.5
V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins
Input voltage for all other LVDS input pins
| VID |
Input differential voltage (absolute value)
IID
Input differential current
(2)
(2) (6)
(7)
(7)
CLOCKS
ƒclock
Clock frequency for LVDS interface, DCLK (all channels)
ENVIRONMENTAL
Temperature: operational : Reference Locations TP2 and TP3 (8)
TARRAY and TWINDOW
Temperature: operational : Reference Locations TP1
Temperature: non–operational
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(9)
Dew Point temperature, operating and non-operating (noncondensing)
TDP
(1)
(8) (9)
(9)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected.
VOFFSET supply transients must fall within specified voltages.
To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Requirements for additional information.
This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors
Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential
temperature, or illumination power density reduces the device lifetime.
The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation) or of any point along the
Window Edge as defined in Figure 15. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 15 are intended to
measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher
temperature, add a test point to that location.
6.2 Storage Conditions
applicable before the DMD is installed in the final product
TDMD
DMD storage temperature
TDP-AVG
Average dew point temperature (non-condensing)
TDP-ELR
Elevated dew point temperature range (non-condensing)
CTELR
Cumulative time in elevated dew point temperature range
(1)
(2)
MIN
MAX
UNIT
–40
80
°C
28
°C
(1)
(2)
28
36
°C
24
Months
The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of
CTELR.
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6.3 ESD Ratings
Electrostatic
discharge
V(ESD)
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY VOLTAGES (1)
MIN
NOM
MAX
UNIT
(2)
VCC
Supply voltage for LVCMOS core logic
3.15
3.3
3.45
V
VCCI
Supply voltage for LVDS receivers
3.15
3.3
3.45
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrodes (2)
8.25
8.5
8.75
V
VBIAS
Supply voltage for micromirror electrodes
15.5
16
16.5
V
VRESET
Supply voltage for micromirror electrodes
–9.5
–10
–10.5
V
|VCCI–VCC|
Supply voltage change (absolute value)
0
0.3
V
|VBIAS–VOFFSET|
Supply voltage change (absolute value) (4)
8.75
V
VCC + 0.15
V
0.7
V
(3)
LVCMOS PINS
VIH
High level Input voltage
(5)
1.7
(5)
– 0.3
2.5
VIL
Low level Input voltage
IOH
High level output current at VOH = 2.4 V
–20
mA
IOL
Low level output current at VOL = 0.4 V
15
mA
TPWRDNZ
PWRDNZ pulse width (6)
10
ns
SCP INTERFACE (7)
ƒclock
SCP clock frequency (8)
tSCP_SKEW
Time between valid SCPDI and rising edge of SCPCLK (9)
tSCP_DELAY
Time between valid SCPDO and rising edge of SCPCLK (9)
tSCP_BYTE_INTERVAL
Time between consecutive bytes
tSCP_NEG_ENZ
Time between falling edge of SCPENZ and the first rising edge of
SCPCLK
tSCP_PW_ENZ
SCPENZ inactive pulse width (high level)
tSCP_OUT_EN
Time required for SCP output buffer to recover after SCPENZ (from
tri-state)
ƒclock
SCP circuit clock oscillator frequency
(10)
–800
500
kHz
800
ns
700
ns
1
µs
30
ns
1
µs
9.6
1.5
ns
11.1
MHz
(1)
(2)
(3)
(4)
Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to the Power Supply
Requirements section for additional information.
(5) Tester conditions for VIH and VIL:
Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the
SCPDO output pin.
(7) For all Serial Communications Port (SCP) operations, DCLK_A and DCLK_B are required.
(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Refer to Figure 2.
(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
10
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
100
400
MAX
UNIT
400
MHz
600
mV
LVDS INTERFACE
ƒclock
Clock frequency for LVDS interface, DCLK (all channels)
|VID|
Input differential voltage (absolute value) (11)
(11)
VCM
Common mode
VLVDS
LVDS voltage (11)
tLVDS_RSTZ
Time required for LVDS receivers to recover from PWRDNZ
ZIN
Internal differential termination resistance
95
Line differential impedance (PWB/trace)
90
ZLINE
ENVIRONMENTAL
TARRAY
1200
0
100
mV
2000
mV
10
ns
105
Ω
110
Ω
(12)
Array temperature – operational, long-term
Array temperature – operational, short-term
(13) (14) (15)
(13) (14) (17)
10
40 to 70 (16)
0
10
°C
TWINDOW
Window temperature – operational (18)
85
°C
T|DELTA |
Absolute temperature change between any point on the window
edge and the ceramic test point TP1. (19)
26
°C
TDP-AVG
Average dew point temperature (non-condensing)
28
°C
TDP-ELR
Elevated dew point temperature range (non-condensing)
CTELR
Cumulative time in elevated dew point temperature range
ILLUV
Illumination, wavelength < 395 nm
ILLVIS
Illumination, wavelength between 395 nm and 800 nm
ILLIR
Illumination, wavelength > 800 nm
(20)
(21)
(21)
28
0.68
36
°C
24
Months
2.0 mW/cm2
Thermally
Limited
10 mW/cm2
(11) Refer to Figure 3, Figure 4, and Figure 5.
(12) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage
and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that
application-specific effects be considered as early as possible in the design cycle.
(13) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces
device lifetime.
(14) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 15 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation.
(15) Long-term is defined as the average over the usable life.
(16) Per Figure 1, base the maximum operational case temperature derating on the micromirror landed duty cycle that the DMD experiences
in the end application. Refer to Micromirror Landed-on or Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
(17) Array temperatures beyond the specified long-term operational DMD temperature are recommended for short-term conditions only (for
example, power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(18) The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 15 are intended to measure the highest window edge
temperature. If a particular application causes another point on the window edge to be at a higher temperature, add a test point to that
location. This ensures that the window bond temperature does not exceed the limits in Absolute Maximum Ratings
(19) Temperature change is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 15 The window test points TP2, TP3, TP4 and TP5 shown in Figure 15 are intended to result in the worst-case temperature
change. If a particular application causes another point on the window edge to result in a larger temperature change, use that point.
(20) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
(21) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of
CTELR.
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6.5 Thermal Information
DLP650NE
THERMAL METRIC (1)
FYE (CPGA)
UNIT
350 PINS
RARRAY–TO–CERA
Active Area-to-Case Ceramic Thermal resistance
(2)
0.6
°C/W
MIC
(1)
Max Recommended DMD Temperature –
Operational (°C)
(2)
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions table. The total heat load on the DMD is largely driven by the incident light absorbed by the active
area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array.
Design optical systems to minimize the light energy falling outside the window clear aperture because any additional thermal load in this
area can significantly degrade the reliability of the device.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
Micromirror Landed Duty Cycle
60/40
55/45
D001
Figure 1. Recommended Maximum DMD Temperature – Derating Curve
12
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
VCC = 3.3 V, IOH = –20 mA
VOL
Low -level output voltage
VCC = 3.45 V, IOL = 15 mA
0.4
V
IIH
High-level input current (2)
VCC = 3.45 V , VI = VCC
250
µA
IlL
Low-level input current
VCC = 3.45 V, VI = 0
IOZ
High–impedance output current
VCC = 3.45 V
10
VCC = 3.45 V
1100
VCCI = 3.45 V
500
(3)
2.4
V
–250
µA
µA
CURRENT
ICC
ICCI
IOFFSET
IBIAS
IRESET
ITOTAL
Supply current
(4)
Supply current
(5)
Supply current
VOFFSET = 8.75 V
25
VBIAS = 16.5 V
14
VRESET = –10.5 V
11
Total Sum
1650
mA
mA
mA
CAPACITANCE
CI
Input capacitance
ƒ = 1 MHz
10
pF
CO
Output capacitance
ƒ = 1 MHz
10
pF
390
pF
CM
(1)
(2)
(3)
(4)
(5)
Reset group capacitance
MBRST(14:0)
ƒ = 1 MHz
all inputs interconnected,
(1920 x 1080) array
330
All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected.
Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.
LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and
Functions to determine pull-up or pull-down configuration used.
To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit.
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6.7 Timing Requirements
Over Recommended Operating Conditions unless otherwise noted. (1)
DESCRIPTION (2)
SCP INTERFACE
MIN
TYP
MAX
UNIT
(3)
tr
Rise time
20% to 80%
200
ns
tƒ
Fall time
80% to 20%
200
ns
LVDS INTERFACE (3)
tr
Rise time
20% to 80%
100
400
ps
tƒ
Fall time
80% to 20%
100
400
ps
DCLK_A, 50% to 50%
2.5
DCLK_B, 50% to 50%
2.5
DCLK_A, 50% to 50%
1.19
1.25
DCLK_B, 50% to 50%
1.19
1.25
LVDS CLOCKS (4)
tc
Cycle time
tw
Pulse duration
ns
ns
LVDS INTERFACE (4)
tsu
Setup time
tsu
Setup time
th
Hold time
th
Hold time
D_A(15:0) before rising or falling edge of DCLK_A
0.1
D_B(15:0) before rising or falling edge of DCLK_B
0.1
SCTRL_A before rising or falling edge of DCLK_A
0.1
SCTRL_B before rising or falling edge of DCLK_B
0.1
D_A(15:0) after rising or falling edge of DCLK_A
0.4
D_B(15:0) after rising or falling edge of DCLK_B
0.4
SCTRL_A after rising or falling edge of DCLK_A
0.3
SCTRL_B after rising or falling edge of DCLK_B
0.3
ns
ns
ns
ns
LVDS INTERFACE (5)
tskew
(1)
(2)
(3)
(4)
(5)
14
Skew time
Channel B relative to
Channel A (5)
Channel A includes the
following LVDS pairs:
DCLK_AP and DCLK_AN
SCTRL_AP and
SCTRL_AN
D_AP(15:0) and
D_AN(15:0)
Channel B includes the
following LVDS pairs:
DCLK_BP and DCLK_BN
SCTRL_BP and
SCTRL_BN
D_BP(15:0) and
D_BN(15:0)
–1.25
1.25
ns
Tested at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into
account
Refer to Pin Configuration and Functions for pin details.
Refer to Figure 6.
Refer to Figure 7.
Refer to Figure 8.
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tc
SCPCLK
fclock = 1 / tc
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Not to scale.
Refer to SCP Interface section of the Recommended Operating Conditions table.
Figure 2. SCP Timing Parameters
(VIP + VIN) / 2
DCLK_P , SCTRL_P , D_P(0:?)
LVDS
Receiver
VID
VIP
DCLK_N , SCTRL_N , D_N(0:?)
VCM
VIN
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Refer to Pin Configuration and Functions for list of LVDS pins.
Figure 3. LVDS Voltage Definitions (References)
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VLVDS max = VCM max + | 1/2 * VID max |
VCM
VID
VLVDS min = VCM min ± | 1/2 * VID max |
Not to scale.
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Figure 4. LVDS Voltage Parameters
DCLK_P , SCTRL_P , D_P(0:?)
ESD
Internal
Termination
LVDS
Receiver
DCLK_N , SCTRL_N , D_N(0:?)
ESD
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Refer to for list of LVDS pins.
Figure 5. LVDS Equivalent Input Circuit
LVDS Interface
SCP Interface
1.0 * VCC
1.0 * VID
VCM
0.0 * VCC
0.0 * VID
tr
tf
tr
tf
Not to scale.
Refer to the Timing Requirements
Refer to in for list of LVDS pins and SCP pins.
Figure 6. Rise Time and Fall Time
16
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tc
tw
tw
DCLK_P
DCLK_N
50%
th
th
tsu
tsu
D_P(0:?)
D_N(0:?)
50%
th
th
tsu
tsu
SCTRL_P
SCTRL_N
50%
Not to scale.
Refer to LVDS INTERFACE section in the Timing Requirements table.
Figure 7. Timing Requirement Parameter Definitions
DCLK_P
DCLK_N
50%
D_P(0:?)
D_N(0:?)
50%
SCTRL_P
SCTRL_N
50%
tskew
DCLK_P
DCLK_N
50%
D_P(0:?)
D_N(0:?)
50%
SCTRL_P
SCTRL_N
50%
Not to scale.
Refer to LVDS INTERFACE section in the Timing Requirements table.
Figure 8. LVDS Interface Channel Skew Definition
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6.8 System Mounting Interface Loads (1) (2)
PARAMETER
CONDITION
Maximum system mounting interface
load (3)
Maximum load applied
(1)
(2)
(3)
(4)
MIN
NOM
11.30
Electrical Interface areas
11.30
Thermal interface area
(4)
MAX
Thermal interface area
UNIT
kg
0
Electrical interface areas
kg
22.60
See Figure 9
Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum
“A” area (300 + 35 – Datum “A").
Evenly distributed within each area
Unevenly distributed within each area.
Electrical Interface Area
Thermal Interface Area
Figure 9. System Mounting Interface Loads
6.9 Micromirror Array Physical Characteristics
VALUE
UNIT
M
Number of active columns
1920
micromirrors
N
Number of active rows
1080
micromirrors
P
Micromirror (pixel) pitch
7.56
µm
mm
(1)
18
See Figure 10
Micromirror active array width
M×P
14.5152
Micromirror active array height
N×P
8.1648
mm
Micromirror active border
Pond of micromirrors (POM) (1)
14
micromirrors /side
The structure and qualities of the border around the active array includes a band of partially functional micromirrors (POM). These
micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to
tilt toward OFF.
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0
1
2
3
M±4
M±3
M±2
M±1
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0
1
2
3
DMD Active Array
NxP
M x N Micromirrors
N±4
N±3
N±2
N±1
MxP
P
Border micromirrors omitted for clarity.
Details omitted for clarity.
P
Not to scale.
P
P
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 10. Micromirror Array Physical Characteristics
6.10 Micromirror Array Optical Characteristics
See Optical Interface and System Image Quality for important information
PARAMETER
α
Micromirror tilt angle
β
Micromirror tilt angle tolerance (1)
Micromirror tilt direction (5)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
CONDITIONS
DMD landed state
(2) (3) (4) (5)
MIN
(1)
NOM
12
–1
(6) (7)
MAX
44
45
UNIT
°
1
°
46
°
Measured relative to the plane formed by the overall micromirror array. For more information please refer to Figure 14
Additional variation exists between the micromirror array and the package datums.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations, system efficiency variations or system contrast variations.
When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction.
Refer to Figure 11.
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Micromirror Array Optical Characteristics (continued)
See Optical Interface and System Image Quality for important information
PARAMETER
Number of out-of-specification micromirrors
Micromirror crossover time
CONDITIONS
MIN
NOM
MAX
Adjacent micromirrors
(8)
0
Non-adjacent micromirrors
(9) (10)
10
Typical performance
UNIT
micromirrors
2.5
Mirror Metal Specular Reflectivity within the wavelength range
420nm – 700nm
89.4%
DMD photopic efficiency within the wavelength range 420 nm
to 700 nm (11)
66%
μs
(8)
An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the
specified Micromirror Switching Time.
(9) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.
(10) Performance as measured at the start of life.
(11) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform
pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this
number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.
M±4
M±3
M±2
M±1
illumination
0
1
2
3
Not To Scale
0
1
2
3
On-State
Tilt Direction
45°
Off-State
Tilt Direction
N±4
N±3
N±2
N±1
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 11. Micromirror Landed Orientation and Tilt
6.11 Window Characteristics
PARAMETER (1)
CONDITIONS
Window material designation
S600
Corning Eagle XG
Window refractive index
at wavelength 546.1 nm
MIN
See
Illumination overfill
Refer to Illumination Overfill
20
MAX
UNIT
1.5119
(2)
Window aperture
(1)
(2)
NOM
See Window Characteristics and Optics for more information.
For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical
ICD in the Mechanical, Packaging, and Orderable Information section.
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Window Characteristics (continued)
PARAMETER (1)
Window transmittance,
single–pass through both
surfaces and glass (3)
(3)
(4)
CONDITIONS
MIN
Minimum window transmittance TMIN measured at all
angles between 0 AOI and 30 AOI (single pass) over the
wavelength range (between 420 nm and 680 nm)
97%
Average Window Transmittance Tave measured at all
angles 0 – 30 AOI (single pass) over the wavelength
range (420 nm – 680 nm) (4)
99%
Average Window Transmittance Tave measured at all
angles 30 – 45 AOI (single pass) over the wavelength
range (420nm – 680nm)
97%
NOM
MAX
UNIT
See the TI application report Wavelength Transmittance Considerations for DLP® DMD Window, .
Angle of incidence 0° to 45° at 420 nm to 680 nm. Double pass system. Two AR coating surfaces at 0.5% reflectivity per AR coating up
to 30° AOI.
6.12 Chipset Component Usage Specification
The DLP650NE is a component of one or more DLP chipsets. Reliable function and operation of the DLP650NE
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology are the TI
technology and devices for operating or controlling a DLP DMD.
7 Parameter Measurement Information
Figure 12 shows an equivalent test load circuit for the output under test. The load capacitance value stated is
only for characterization and measurement of AC timing signals. This load capacitance value does not indicate
the maximum load the device is capable of driving.
Timing reference loads are not intended as a precise representation of any particular system environment or
depiction of the actual load presented by a production test. Use IBIS or other simulation tools to correlate the
timing reference load to a system environment. Refer to the Application and Implementation section.
Device pin
output under test
Tester channel
CLOAD
Figure 12. Test Load Circuit
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8 Detailed Description
8.1 Overview
DLP650NE is a 0.65 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 10.
The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical
interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).
DLP650NE DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a
grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram.
The positive or negative deflection angle of the micromirrors can be individually controlled by changing the
address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes
underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror
Array Optical Characteristics. The micromirrors are electrically tied to the micromirror reset signals (MBRST) and
the micromirror array is divided into reset groups.
Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt
toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or
out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative
(–) tilt angle state corresponds to an 'off' pixel.
Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration
and Functions for more information on micromirror reset control.
8.2 Functional Block Diagram
The main LVDS lines going to the DMD are connected via channel A and B. However, the LVDS lines come from
channel C and D off the DLPC4422. Please refer to the DLPC4422 datasheet for more information.
22
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DATA_C
SCTRL_C
DCLK_C
VSS
VCC
VOFFSET
VRESET
MBRST
VBIAS
PWRDNZ
SCP
Functional Block Diagram (continued)
Channel C Interface
Column Read and Write
Control
Bit Lines
Control
(0,0)
Voltages
Word Lines
Bit Lines
Micromirror Array
Row
(M-1, N-1)
Bit Lines
Voltage
Generators
Column Read and Write
Control
Control
DATA_D
SCTRL_D
DCLK_D
VSS
VCC
VOFFSET
VRESET
VBIAS
MBRST
RESET_CTRL
Channel D Interface
For pin details on Channels A, B, C, and D, refer to Pin Configuration and Functions and LVDS Interface section of
Timing Requirements .
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8.3 Feature Description
8.3.1 Micromirrors
DLP650NE device consists of highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors)
organized in a two-dimensional orthogonal pixel array. Refer to Figure 10 and Figure 13.
Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular
positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to
Micromirror Array Optical Characteristics and Figure 14.
The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel
to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is
perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package,
as shown in Figure 13.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual micromirrors
changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory
cell data update.
Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror
switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the
corresponding micromirror switching to a – α position.
Updating the angular position of the micromirror array consists of two steps:
• Update the contents of the CMOS memory.
• Apply a micromirror reset to all or a portion of the micromirror array (depending upon the configuration of the
system).
Micromirror reset pulses are generated internally by the DLP650NE DMD, with application of the pulses being
coordinated by the DLPC4422 display controller.
For more information, see the TI application report DLPA008A, DMD101: Introduction to Digital Micromirror
Device (DMD) Technology.
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Feature Description (continued)
Incident
Illumination
Package Pin
A1 Corner
Details Omitted For Clarity.
Not To Scale.
DMD
Micromirror
Array
0
(Border micromirrors eliminated for clarity)
M±1
Active Micromirror Array
0
N±1
Micromirror Hinge-Axis Orientation
Micromirror Pitch
P (um)
45°
P (um)
P (um)
³2Q-6WDWH´
Tilt Direction
³2II-6WDWH´
Tilt Direction
P (um)
Refer to Micromirror Array Physical Characteristics, Figure 10, and Figure 11
Figure 13. Micromirror Array, Pitch, Hinge Axis Orientation
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Feature Description (continued)
g
n t -L i
de n
ci tio
In ina
m
u
Ill
Details Omitted For Clarity.
ht
Not To Scale.
Pa
th
Package Pin
A1 Corner
DMD
Incident
Illumination
Two
³2Q-6WDWH´
Micromirrors
Two
³2II-6WDWH´
Micromirrors
nt t Path
ide
Inc n-Ligh
tio
ina
Projected-Light
Path
m
Illu
nt t Path
ide
Inc n-Ligh
tio
ina
m
Illu
For Reference
gh
Li
eat th
t
S a
ff- P
O
a±b
Flat-State
( ³SDUNHG´ )
Micromirror Position
t
-a ± b
Silicon Substrate
³2Q-6WDWH´
Micromirror
Silicon Substrate
³2II-6WDWH´
Micromirror
Figure 14. Micromirror States: On, Off, Flat
26
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Feature Description (continued)
8.3.2 Timing
The data sheet provides timing analysis as measured at the device pin. For output timing analysis, the tester pin
electronics and its transmission line effects must be taken into account. Figure 12 shows an equivalent test load
circuit for the output under test. Timing reference loads are not intended as a precise representation of any
particular system environment or depiction of the actual load presented by a production test. TI suggests that
system designers use IBIS or other simulation tools to correlate the timing reference load to a system
environment. The load capacitance value stated is only for characterization and measurement of AC timing
signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
8.3.3 Power Interface
The DMD requires five (5) DC voltage input signals.
• DMD_P3P3V
• DMD_P1P8V
• VOFFSET
• VRESET
• VBIAS
The DMD_P3P3V signal is created by the power and motor driver of the DLPA100 device. It is used on the DMD
board to create the other four (4) DMD voltage inputs, as well as powering various peripherals (for example,
TMP411, I2C, and TI level translators). The DMD_P1P8V signal is created by the TI PMIC LP38513S and
provides the VCC voltage required by the DMD. the other signals, (VOFFSET (8.5 V), VRESET (–10 V), and
VBIAS(16.5 V)) are created by the TI PMIC TPS65145 device and are supplied to the DMD to control the
micromirrors
8.3.4 Window Characteristics and Optics
CAUTION
TI assumes no responsibility for image quality artifacts or DMD failures caused by
optical system operating conditions exceeding limits described previously.
8.3.4.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
8.3.4.2 Numerical Aperture and Stray Light Control
Ensure that the angle defined by the numerical aperture of the illumination and projection optics at the DMD
optical area are the same. This angle must not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
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Feature Description (continued)
8.3.4.3 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the display’s border and/or active area, which may require additional system apertures
to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
8.3.4.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. Design the illumination
optical system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of
the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light
may have to be further reduced below the suggested 10% level in order to be acceptable.
8.3.5 Micromirror Array Temperature Calculation
Figure 15. DMD Thermal Test Points
28
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Feature Description (continued)
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load.
The relationship between micromirror array temperature and the reference ceramic temperature is provided by
the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC)
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
(1)
(2)
where
•
•
•
•
•
•
•
TARRAY = Computed micromirror array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 15
RARRAY–TO–CERAMIC = DMD package thermal resistance from micromirror array to outside ceramic (°C/W)
specified in Thermal Information
QARRAY = Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics
CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
SL = Measured ANSI screen lumens (lm)
(3)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. The nominal electrical power dissipation to use when calculating array temperature is 2.9 W.
Absorbed optical power from the illumination source is variable and depends on the operating state of the
micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with
total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and
16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00293
W/lm.
Equation 4 through Equation 9 show sample calculations for a typical projection application.
TCERAMIC = 55°C
where
• assumed system measurement
• see Recommended Operating Conditions for specific limits
SL = 3000 lm
QELECTRICAL = 2.9 W
(4)
(5)
(6)
For Equation 6, see the maximum power specifications in .
CL2W = 0.00274 W/lm
QARRAY = 2.9 W + (0.00274 × 3000) = 11.12 W
TARRAY = 55°C + (11.12 W × 0.6 C/W) = 61.7°C
(7)
(8)
(9)
8.3.6 Micromirror Landed-on or Landed-Off Duty Cycle
8.3.6.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
The micromirror landed-on or landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON–state versus the amount of time the same
micromirror is landed in the OFF–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON–state 100% of the
time (and in the OFF–state 0% of the time); whereas 0/100 would indicate that the pixel is in the OFF–state
100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
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Feature Description (continued)
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
8.3.6.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
Individual DMD mirror duty cycles vary by application as well as the mirror location on the DMD within any
specific application. DMD mirror useful life are maximized when every individual mirror within a DMD approaches
50/50 (or 1/1) duty cycle. Therefore, for the DLPC4422 and DLP650NE chipset, it is recommended that the DMD
Idle Mode be enabled as often as possible. Examples are whenever the system is idle, the illumination is
disabled, between sequential pattern exposures (if possible), or when the exposure pattern sequence is stopped
for any reason. This software mode provides a 50/50 duty cycle across the entire DMD mirror array, where the
mirrors are continuously flipped between the on and off states. Refer to the DLPC4422 Software Programmer’s
Guide DLPU018 for a description of the DMD Idle Mode command. For the DLPC910 and DLP650NE chipset, it
is recommended that the controlling applications processor provide a 50/50 pattern sequence to the DLPC910
for display on the DLP650NE as often as possible, similar to the above examples stated for the DLPC4422. The
pattern provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously
flipped between the ON and OFF states.
8.3.6.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD usable life, and this interaction
can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the usable life of the
DMD. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature required for DMD operation at for a
give long-term average Landed Duty Cycle.
8.3.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given time period, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel operates under a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 1.
Table 1. Grayscale Value and Landed Duty Cycle
30
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
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Table 1. Grayscale Value and Landed Duty
Cycle (continued)
GRAYSCALE VALUE
LANDED DUTY CYCLE
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where color cycle time is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated in Equation 10.
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%
× Blue_Scale_Value)
where
•
•
•
Red_Cycle_% represents the percentage of the frame time that Red is displayed to achieve the desired white
point
Green_Cycle_% represents the percentage of the frame time that Green is displayed to achieve the desired
white point
Blue_Cycle_%, represents the percentage of the frame time that Blue is displayed to achieve the desired white
point
(10)
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
blue color intensities would be as shown in Table 2.
Table 2. Example Landed Duty Cycle for Full-Color
CYCLE PERCENTAGE
Red
50%
Green
20%
Blue
30%
Red Scale Value
Green Scale Value
Blue Scale Value
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
Landed Duty Cycle
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
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8.4 Device Functional Modes
When the DMD is controlled by the DLPC4422, the digital controller has four modes of operation.
• Video mode
• Video pattern mode
• Pre-stored pattern mode
• Pattern on-the-fly mode
DMD functional modes are controlled by the DLPC4422 display controller. See the DLPC4422 display controller
data sheet or contact a TI applications engineer.
DMD functional modes are controlled by the DLPC4422 digital display controller. See the DLPC4422 data sheet.
Contact a TI applications engineer for more information.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Texas Instruments DLP technology is a micro-electro-mechanical systems (MEMS) technology that modulates
light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light
from an illumination source to one of two directions, towards the projection optics or collection optics. The large
micromirror array size and ceramic package provides great thermal performance for bright display applications.
Typical applications using the DLP650NE include home theater, digital signage, interactive display, low-latency
gaming display, portable smart displays.
9.2 Typical Application
The DLP650NE DMD combined with a DLPC4422 digital controller and DLPA100 power management device
provides full HD resolution for bright, colorful display applications. A typical display system using the DLP650NE
and additional system components can be seen in Figure 16.
Figure 16. Typical DLPC4422 Application Schematic
9.2.1 Design Requirements
A DLP650NE projection system is created by using the DMD chipset, including the DLP650NE, DLPC4422, and
DLPA100. The DLP650NE is used as the core imaging device in the display system and contains a 0.65-inch
array of micromirrors. The DLPC4422 controller is the digital interface between the DMD and the rest of the
system, taking digital input from front end receiver that converts the data from the source and using the
converted data for driving the DMD over a LVDS interface. The DLPA100 power management device provides
voltage regulators for the DMD, controller, and illumination functionality.
Other core components of the display system include an illumination source, an optical engine for the illumination
and projection optics, other electrical and mechanical components, and software. The illumination source options
include lamp, LED, laser or laser phosphor. The type of illumination used and desired brightness affects the
overall system design and size.
9.2.2 Detailed Design Procedure
For a complete the DLP system, an optical module or light engine is required that contains the DLP650NE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DLP650NE DMD must always be used with the DLPC4422 display controllers
and a DLPA100 PMIC driver.
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10 Power Supply Requirements
10.1 DMD Power Supply Requirements
The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET.
VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the
DLPC4422 device.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power-up and
power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS,
and VRESET power supplies have to be coordinated during power-up and powerdown operations. VSS must also be connected. Failure to meet any of the below
requirements results in a significant reduction in the DMD’s reliability and lifetime.
Refer to Figure 17.
10.2 DMD Power Supply Power-Up Procedure
•
•
•
•
•
During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
During power-up, it is a strict requirement that the change between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. During power-up, VBIAS does not have to start
after VOFFSET.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements listed in the Absolute Maximum Ratings table, in the Recommended Operating Conditions table,
and in the DMD Power Supply Sequencing Requirements section.
During power-up, LVCMOS input pins must not be driven high until after VCC and VCCI have settled at
operating voltages listed in Recommended Operating Conditions table.
10.3 DMD Power Supply Power-Down Procedure
•
•
•
•
•
34
During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are
discharged to within the specified limit of ground. Refer to Table 3.
During power-down, it is a strict requirement that the change between VBIAS and VOFFSET must be within
the specified limit shown in the Recommended Operating Conditions table. During power-down, it is not
mandatory to stop driving VBIAS prior to VOFFSET.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 17.
During power-down, LVCMOS input pins must be less than specified in the Recommended Operating
Conditions table.
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DMD Power Supply Power-Down Procedure (continued)
EN_BIAS, EN_OFFSET, and EN_RESET are disabled by DLP controller software or PWRDNZ signal control
VBIAS, VOFFSET, and VRESET are disabled by DLP controller software
Mirror Park Sequence
RESET_OEZ
VSS
¸¸
Note 3
Power Off
VCC / VCCI
Note 6
VSS
VCC / VCCI
PWRDNZ
¸¸
VSS
VCC
VCCI
VCC / VCCI
VSS
EN_BIAS
EN_OFFSET
EN_RESET VSS
VCC / VCCI
VBIAS
VSS
¸¸
VSS
¸¸
¸¸
Note 3
VSS
VBIAS
VBIAS
VBIAS < Specification
Note 1
Note 1
VSS
¨9 < Specification
VOFFSET
¨9 < Specification
¸¸
Note 4
VSS
VOFFSET
VOFFSET
VOFFSET < Specification
Note 4
VSS
VSS
Note 5
VSS
Refer to specifications listed in Recommended Operating Conditions.
Waveforms are not to scale. Details are omitted for clarity.
VRESET < Specification
Note 4
VSS
VRESET
VRESET > Specification
VRESET
¸¸
VRESET
VCC
LVCMOS
Inputs
VSS
LVDS
Inputs
VSS
¸¸
Note 2
VSS
Note 2
¸¸
VSS
(1)
To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified in the
Recommended Operating Conditions table. OEMs may find that the most reliable way to ensure this is to power
VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.
(2)
LVDS signals are less than the input differential voltage (VID) maximum specified in the Recommended Operating
Conditions table. During power-down, LVDS signals are less than the high level input voltage (VIH) maximum
specified in the Recommended Operating Conditions table.
(3)
When system power is interrupted, the DLP DLPC4422 initiates a hardware power-down that activates PWRDNZ and
disables VBIAS, VRESET and VOFFSET after the micromirror park sequence. Software power-down disables VBIAS,
VRESET, and VOFFSET after the micromirror park sequence through software control. For either case, enable
signals EN_BIAS, EN_OFFSET, and EN_RESET are used to disable VBIAS, VOFFSET, and VRESET, respectfully.
(4)
Refer to Table 3.
(5)
Figure not to scale. Details have been omitted for clarity. Refer to the Recommended Operating Conditions table.
(6)
EN_BIAS, EN_OFFSET, and EN_RESET are disabled by DLP controller software or PWRDNZ signal control.
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DMD Power Supply Power-Down Procedure (continued)
(7)
VBIAS, VOFFSET, and VRESET are disabled by DLP controller software
Figure 17. DMD Power Supply Sequencing Requirements
Table 3. DMD Power-Down Sequence Requirements
PARAMETER
MIN
VBIAS
VOFFSET
Supply voltage level during power–down sequence
VRESET
–4.0
MAX
UNIT
4.0
V
4.0
V
0.5
V
11 Layout
11.1 Layout Guidelines
The DLP650NE along with one DLPC4422 controller provides a solution for many applications including
structured light and video projection. This section provides layout guidelines for the DLP650NE.
11.1.1 General PCB Recommendations
The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to
IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches +/- 10%, using standard FR-4
material, and applies after all lamination and plating processes, measured from copper to copper.
Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.
Refer to Related Documents for the DLPC4422 Digital Controller Data Sheet for related information on the DMD
Interface Considerations.
High-speed interface waveform quality and timing on the DLPC4422 controller (that is, the LVDS DMD interface)
is dependent on the following factors:
• Total length of the interconnect system
• Spacing between traces
• Characteristic impedance
• Etch losses
• How well matched the lengths are across the interface
Thus, ensuring positive timing margin requires attention to many factors.
As an example, DMD interface system timing margin can be calculated as follows:
• Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI
degradation)
• Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI
degradation)
The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as
simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise.
The DLPC4422 Digital Controller data sheet reports the I/O timing parameters. Any PCB routing mismatches can
be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as easy to
determine.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design
guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing
requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these
recommendations may allow the device to operate, but be sure to confirm system integrity with PCB analysis or
lab measurements.
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11.2 Layout Example
11.2.1 Board Stack and Impedance Requirements
Refer to Figure 18 for guidance on the parameters.
PCB design:
Configuration:
Asymmetric dual stripline
Etch thickness (T):
1.0-oz copper (1.2 mil)
Flex etch thickness (T):
0.5-oz copper (0.6 mil)
Single-ended signal impedance:
50 Ω (±10%)
Differential signal impedance:
100 Ω (±10%)
PCB stack-up:
Reference plane 1 is assumed to be a ground plane for proper return path.
Reference plane 2 is assumed to be the I/O power plane or ground.
Dielectric FR4, (Er):
4.2 (nominal)
Signal trace distance to reference plane 1
(H1):
5.0 mil (nominal)
Signal trace distance to reference plane 2
(H2):
34.2 mil (nominal)
Reference Plane 1
W.
T
W.
Trace
S.
H1
Trace
H2
Dialectric Er
H2
T
Trace
Trace
H1
Reference Plane 2
Figure 18. PCB Stack Geometries
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Layout Example (continued)
Table 4. General PCB Routing (1)
PARAMETER
Line width (W)
APPLICATION
SINGLE-ENDED SIGNALS
DIFFERENTIAL PAIRS
UNIT
Escape routing in ball field
4
(0.1)
4
(0.1)
mil
(mm)
PCB etch data or control
7
(0.18)
4.25
(0.11)
mil
(mm)
PCB etch clocks
7
(0.18)
4.25
(0.11)
mil
(mm)
PCB etch data or control
N/A
5.75 (2)
–0.15
mil
(mm)
PCB etch clocks
N/A
5.75 (2)
–0.15
mil
(mm)
PCB etch data or control
N/A
20
(0.51)
mil
(mm)
PCB etch clocks
N/A
20
(0.51)
mil
(mm)
Escape routing in ball field
4
(0.1)
4
(0.1)
mil
(mm)
PCB etch data or control
10
(0.25)
20
(0.51)
mil
(mm)
PCB etch clocks
20
(0.51)
20
(0.51)
mil
(mm)
N/A
12
0.3
mil
(mm)
Differential signal pair spacing (S)
Minimum differential pair-to-pair
spacing (S)
Minimum line spacing to other
signals (S)
Maximum differential pair P-to-N
length mismatch
(1)
(2)
Total data
Applies to all corresponding PCB signals
Spacing may vary to maintain differential impedance requirements
Table 5. DMD Interface Specific Routing
SIGNAL GROUP LENGTH MATCHING
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH
UNIT
DMD (LVDS)
SCTRL_AN / SCTRL_AP
D_AP(15:0)/ D_AN(15:0)
DCKA_P/ DCKA_N
± 150
(± 3.81)
mil
(mm)
DMD (LVDS)
SCTRL_BN/ SCTRL_BP
D_BP(15:0)/ D_BN(15:0)
DCKB_P/ DCKB_N
± 150
(± 3.81)
mil
(mm)
Number of layer changes:
• Single-ended signals: Minimize
• Differential signals: If individual differential pairs are be routed on different layers, ensure the signals of a
given pair do not change layers.
Table 6. DMD Signal Routing Length (1)
BUS
MIN
MAX
UNIT
DMD (LVDS)
50
375
mm
(1)
Maximum signal routing length includes escape routing.
Stubs: Stubs, such as test points, must not be placed on a LVDS line.
Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω
internally.
Connector (DMD-LVDS interface bus only):
High-speed connectors that meet the following requirements should be used:
• Differential crosstalk: < 5%
• Differential impedance: 75 Ω to 125 Ω
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Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed
in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference
for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should
be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers
shall have the predominant traces routed orthogonal to each other.
These guidelines produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4 ps,
assuming 175 ps/inch FR4 propagation delay.
These PCB routing guidelines results in approximately 25-ps system setup margin and 25-ps system hold margin
for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.
Both the DLPC4422 output timing parameters and the DLP650NE DMD input timing parameters include timing
budget to account for their respective internal package routing skew.
11.2.1.1 Power Planes
Signal routing is NOT allowed on the power and ground planes. Ensure that all device pin and via connections to
this plane use a thermal relief with a minimum of four spokes. The power plane must clear the edge of the PCB
by 0.2”.
Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid
PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital
ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes
should be connected together with a minimum distance between connections of 0.5”. Extra vias are not required
if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and
signal vias should be inside the perimeter ring of ground vias.
Power and Ground pins of each component shall be connected to the power and ground planes with one via for
each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”).
Unused or spare device pins that are connected to power or ground may be connected together with a single via
to power or ground. Ground plane slots are NOT allowed.
Route VOFFSET, VBIAS, and VRESET as a wide trace >20 mils (wider if space allows) with 20 mils spacing.
11.2.1.2 LVDS Signals
It is recommended that the LVDS signals should be routed first. Each pair of differential signals must be routed
together at a constant separation such that constant differential impedance (as in section Board Stack and
Impedance Requirements) is maintained throughout the length. Avoid sharp turns and layer switching while
keeping lengths to a minimum. The distance from one pair of differential signals to another shall be at least 2
times the distance within the pair.
11.2.1.3 Critical Signals
The critical signals on the board must be hand routed in the order specified below. In case of length matching
requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a
minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB.
Table 7. Timing Critical Signals
GROUP
1
2
SIGNAL
CONSTRAINTS
D_AP(0:15), D_AN(0:15), DCLK_AP,
DCLK_AN, SCTRL_AN, SCTRL_AP,
D_BP(0:15), D_BN (0:15), DCLK_BP,
DCLK_BN, SCTRL_BN, SCTRL_BP
RESET_ADDR_(0:3),
RESET_MODE_(0:1),
RESET_OEZ,
RESET_SEL_(0:1)
RESET_STROBE,
RESET_IRQZ.
3
SCP_CLK, SCP_DO,
SCP_DI, SCP_DMD_CSZ.
4
Others
ROUTING LAYERS
Internal signal layers. Avoid layer switching
when routing these signals.
Refer to Table 4 and Table 5
Internal signal layers. Top and bottom as
required.
Any
No matching/length requirement
Any
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11.2.1.4 Device Placement
Unless otherwise specified, all major components should be placed on top layer. Small components such as
ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high
frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly
around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the
case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are
side by side as much as possible and place the smaller value capacitor closer to the device.
11.2.1.5 Device Orientation
It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If
polarized capacitors are oriented both horizontally and vertically, then be sure to orient all horizontal capacitors
and the positive terminal in the same direction and likewise for the vertically -oriented capacitors.
11.2.1.6 Fiducials
Follow these guidelines for fiducial placement for automatic component insertion on the board or on
recommendation from manufacturer:
• Place fiducials for optical auto insertion alignment on three corners of both sides of the PWB.
• Place fiducials in the center of the land patterns for fine pitch components (lead spacing <0.05").
• Ensure fiducials are 0.050-inch copper with a 0.100-inch cutout (antipad).
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12 Device Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Table 8. Package Specific Information
PACKAGE TYPE
PINS
CONNECTOR
FYE
350
PGA
DLP650NE FXG
Package type
Device descriptor
Figure 19. Device Number Description
12.1.2 Device Markings
The device marking will include both human-readable information and a 2-dimensional matrix code. The humanreadable information is described in Figure 20. The 2-dimensional matrix code is an alpha-numeric character
string that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first
character of the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial
Number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias
voltage bin letter.
Examples: *1910-6037E GHXXXXX LLLLLLM
2-Dimension matrix code
(device number and serial number)
TI internal numbering
DMD part number
YYYYYYY
*1912-5bbcB
GHXXXXX
LLLLLLM
Part 1 of serial number
(7 characters)
Part 2 of serial number
(7 characters)
Figure 20. DMD Marking
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12.2 Documentation Support
12.2.1 Related Documentation
The following documents contain additional information related to the use of the DLP650NE device.
Table 9. Related Documents
DOCUMENT
DLPC4422 Digital Controller Data Sheet
DLPS074
TPS65145 Triple output LCD Supply With Linear Regulator and Power Good
SLVS497F
DLPA100 Power Management and Motor Driver
DLPS082
DMD101: Introduction to Digital Micromirror Device (DMD) Technology
DLPA008
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLP650NEFYE
ACTIVE
Package Type Package Pins Package
Drawing
Qty
CPGA
FYE
350
21
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
RoHS &
non-Green
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
10 to 90
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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