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Texas Instruments DLPC900 Programmer's (Rev. E) User guides
DLPC900 Programmer's Guide
Programmer's Guide
Literature Number: DLPU018E
October 2014 – Revised April 2019
Contents
Preface ........................................................................................................................................ 6
1
Interface Protocol................................................................................................................. 7
1.1
1.2
1.3
2
DLPC900 Control Commands
2.1
2.2
2.3
2
I2C Interface .................................................................................................................. 7
1.1.1 I2C Transaction Structure .......................................................................................... 7
1.1.1.1
I2C START Condition......................................................................................... 7
1.1.1.2
I2C STOP Condition .......................................................................................... 7
1.1.1.3
DLPC900 Slave Address ................................................................................... 7
1.1.1.4
DLPC900 Sub-Address and Data Bytes................................................................... 8
1.1.2 Example I2C Read Command Sequence ........................................................................ 8
1.1.2.1
Read Command Example with Parameters ............................................................... 9
1.1.3 Example I2C Write Command Sequence ........................................................................ 9
USB Interface ............................................................................................................... 10
1.2.1 USB Transaction Sequence ..................................................................................... 10
1.2.2 USB Read Transaction Sequence Example ................................................................... 12
1.2.3 USB Write Transaction Sequence Example ................................................................... 13
INIT_DONE Signal ......................................................................................................... 13
.............................................................................................. 14
DLPC900 Status Commands .............................................................................................
2.1.1 Hardware Status ...................................................................................................
2.1.2 System Status .....................................................................................................
2.1.3 Main Status ........................................................................................................
2.1.4 Retrieve Firmware Version .......................................................................................
2.1.5 Reading Hardware Configuration and Firmware Tag Information ..........................................
2.1.6 Read Error Code ..................................................................................................
2.1.7 Read Error Description ...........................................................................................
DLPC900 Firmware Programming Commands ........................................................................
2.2.1 Read Status ........................................................................................................
2.2.2 Enter Program Mode ..............................................................................................
2.2.3 Exit Program Mode................................................................................................
2.2.4 Read Control .......................................................................................................
2.2.5 Start Address ......................................................................................................
2.2.6 Erase Sector .......................................................................................................
2.2.7 Download Flash Data Size .......................................................................................
2.2.8 Download Data ....................................................................................................
2.2.9 Calculate Checksum ..............................................................................................
2.2.10 Dual Controller Control ..........................................................................................
Chipset Control Commands...............................................................................................
2.3.1 Chipset Configuration Commands .............................................................................
2.3.1.1
Power Mode .................................................................................................
2.3.1.2
DMD Park/Unpark...........................................................................................
2.3.1.3
Curtain Color.................................................................................................
2.3.2 Parallel Interface Configuration ..................................................................................
2.3.2.1
Input Data Channel Swap..................................................................................
2.3.3 Input Source Commands .........................................................................................
2.3.3.1
Port and Clock Configuration .............................................................................
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2.4
2.3.3.2
Input Source Configuration ................................................................................
2.3.3.3
Input Pixel Data Format ...................................................................................
2.3.3.4
Internal Test Pattern Select ................................................................................
2.3.3.5
Internal Test Patterns Color ...............................................................................
2.3.3.6
Load Image ..................................................................................................
2.3.4 Image Flip ..........................................................................................................
2.3.4.1
Long-Axis Image Flip .......................................................................................
2.3.4.2
Short Axis Image Flip .......................................................................................
2.3.4.3
IT6535 Power Mode .......................................................................................
2.3.5 LED Driver Commands ...........................................................................................
2.3.5.1
LED Enable Outputs ........................................................................................
2.3.5.1.1 LED PWM Polarity......................................................................................
2.3.5.2
LED Driver Current .........................................................................................
2.3.5.3
Set Minimum LED Pulse Width ...........................................................................
2.3.5.4
Get Minimum LED Pattern Exposure .....................................................................
2.3.6 GPIO Commands .................................................................................................
2.3.6.1
GPIO Configuration .........................................................................................
2.3.6.2
GPIO Clock Configuration .................................................................................
2.3.7 Pulse Width Modulated (PWM) Control ........................................................................
2.3.7.1
PWM Setup ..................................................................................................
2.3.7.2
PWM Enable .................................................................................................
2.3.8 Batch File Commands ............................................................................................
2.3.8.1
Batch File Name ............................................................................................
2.3.8.2
Batch File Execute ..........................................................................................
2.3.8.3
Batch File Delay .............................................................................................
2.3.8.4
Batch File Example .........................................................................................
Display Mode Commands .................................................................................................
2.4.1 Display Mode Selection ..........................................................................................
2.4.1.1
Video Mode Resolution ....................................................................................
2.4.1.2
Input Display Resolution ...................................................................................
2.4.1.3
DMD Block Load ...........................................................................................
2.4.1.4
DMD Idle Mode ..............................................................................................
2.4.2 Image Header ......................................................................................................
2.4.3 Pattern Image Compression .....................................................................................
2.4.3.1
Run-Length Encoding ......................................................................................
2.4.3.1.1 RLE Compression Example ...........................................................................
2.4.3.2
Enhanced Run-Length Encoding .........................................................................
2.4.3.2.1 Enhanced RLE Compression Example ..............................................................
2.4.4 Pattern Display Commands ......................................................................................
2.4.4.1
Trigger Commands .........................................................................................
2.4.4.1.1 Trigger Out1 .............................................................................................
2.4.4.1.2 Trigger Out2 .............................................................................................
2.4.4.1.3 Trigger In1 ...............................................................................................
2.4.4.1.4 Trigger In2 ...............................................................................................
2.4.4.2
LED Enable Delay Commands ............................................................................
2.4.4.2.1 Red LED Enable ........................................................................................
2.4.4.2.2 Green LED Enable .....................................................................................
2.4.4.2.3 Blue LED Enable .......................................................................................
2.4.4.3
Pattern Display Commands................................................................................
2.4.4.3.1 Pattern Display Start/Stop .............................................................................
2.4.4.3.2 Pattern Display Invert Data............................................................................
2.4.4.3.3 Pattern Display LUT Configuration ...................................................................
2.4.4.3.4 Pattern Display LUT Reorder Configuration ........................................................
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2.4.4.3.5 Pattern Display LUT Definition ........................................................................
2.4.4.4
Pattern On-The-Fly Commands ...........................................................................
2.4.4.4.1 Initialize Pattern BMP Load ...........................................................................
2.4.4.4.2 Pattern BMP Load ......................................................................................
2.4.4.5
I2C Pass Through Commands .............................................................................
2.4.4.5.1 I2C Pass Through Configuration ......................................................................
2.4.4.5.2 I2C Pass Through Write ................................................................................
2.4.4.5.3 I2C Pass Through Read................................................................................
3
DLPC900 Fault Status ......................................................................................................... 62
3.1
3.2
4
Video Pattern Mode Example ............................................................................................
Pre-Stored Pattern Mode Example ......................................................................................
Pattern On-The-Fly Example .............................................................................................
I2C Pass Through Write Example ........................................................................................
I2C Pass Through Read Example ........................................................................................
64
64
65
65
65
Register Quick Reference .................................................................................................... 66
A.1
A.2
B
Power Up .................................................................................................................... 63
Power Down ................................................................................................................ 63
Power-Up Auto-Initialization .............................................................................................. 63
Command Examples ........................................................................................................... 64
5.1
5.2
5.3
5.4
5.5
A
DLPC900 FAULT_STATUS Location(s) ................................................................................ 62
DLPC900 FAULT_STATUS Interpretation .............................................................................. 62
Power-Up and Power-Down and Initialization Considerations .................................................. 63
4.1
4.2
4.3
5
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59
59
59
60
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I2C Register Quick Reference ............................................................................................ 66
Command Guide ........................................................................................................... 68
Batch File Command Descriptors ......................................................................................... 70
B.1
Command Descriptors ..................................................................................................... 70
Revision History .......................................................................................................................... 72
4
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List of Figures
1-1.
I2C Read Command Waveform Diagram ................................................................................. 8
1-2.
I2C Read Data Waveform Diagram ........................................................................................ 9
1-3.
I2C Write Command Waveform Diagram ................................................................................ 10
1-4.
USB HID Protocol .......................................................................................................... 10
1-5.
USB Multi-Transfer Transaction .......................................................................................... 11
2-1.
Flash Device Layout ....................................................................................................... 19
2-2.
Image Long-Axis Flip Example ........................................................................................... 32
2-3.
Image Short-Axis Flip Example........................................................................................... 32
2-4.
DLPC900 System Block Diagram ........................................................................................ 42
2-5.
Bit-Planes of a 24-Bit RGB Image ....................................................................................... 43
2-6.
Bit Partition in a Frame for an 8-Bit Monochrome Image ............................................................. 43
2-7.
Video Pattern Mode Timing Diagram Example ......................................................................... 51
2-8.
Pre-Stored Pattern Mode Timing Diagram Example
3-1.
DLPC900 FAULT_STATUS Format ..................................................................................... 62
..................................................................
51
(1) (2)
(1)
(2)
LightCrafter, E2E are trademarks of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
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List of Figures
5
Preface
DLPU018E – October 2014 – Revised April 2019
Read This First
About This Manual
This document specifies the command and control interface to the DLPC900 controller and defines all
applicable commands, default settings, and control register bit definitions.
Related Documents from Texas Instruments
•
•
•
•
•
DLPC900 Data Sheet, DLPS037
DLP6500FLQ Data Sheet, DLPS040
DLP6500FYE Data Sheet, DLPS053
DLP9000FLS Data Sheet, DLPS036
DLP® LightCrafter™ 6500 and 9000 Evaluation Module (EVM) User's Guide, DLPU028
If You Need Assistance
Visit the TI E2E™ support forums at DLP Products and MEMS TI E2E Community.
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Chapter 1
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Interface Protocol
This chapter describes the interface protocol between the DLPC900 and a host processor. The DLPC900
supports two host interface protocols: I2C and USB 1.1 slave interfaces.
1.1
I2C Interface
The DLPC900 controller uses the I2C protocol to exchange commands and data with a host processor.
The I2C protocol is a two-wire serial data bus that conforms to the NXP I2C specification. One wire, SCL,
serves as a serial clock, while the second wire, SDA, serves as serial data. Several different devices can
be connected together in an I2C bus. Each device is software addressable by a unique address.
Communication between devices occurs in a simple master-to-slave relationship.
1.1.1 I2C Transaction Structure
All I2C transactions are composed of a number of bytes, combined in the following order:
START Condition, 7-Bit Slave Address Byte + 1 R/W Bit, Sub-Address Byte, N-Data Bytes, STOP
Condition
Where N in N-Data Bytes varies based on the sub-address.
1.1.1.1
I2C START Condition
All I2C transactions begin with a START condition. A START condition is defined by a high-to-low
transition on the SDA line, followed by a high-to-low transition on the SCL line.
1.1.1.2
I2C STOP Condition
All I2C transactions end with a STOP condition. A STOP condition is defined by a low-to-high transition on
the SDA line, followed by a low-to-high transition on the SCL line.
1.1.1.3
DLPC900 Slave Address
The DLPC900 offers a programmable slave address. Refer to the App Defaults Settings found in the DLP
LightCrafter 6500 & 9000 GUI Firmware tab to set a different slave address. The default I2C settings are
shown in Table 1-1. The Write Slave Address must be an even 7-bit address, and the Read Slave
Address must be the Write Slave Address plus 1.
Table 1-1. I2C Slave Settings
ADDRESSING
MODE
DEFAULT WRITE ADDRESS
DEFAULT READ ADDRESS
MAXIMUM CLOCK RATE (kHz)
7-bit
0x34
0x35
400
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Interface Protocol
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I2C Interface
1.1.1.4
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DLPC900 Sub-Address and Data Bytes
The DLPC900 I2C sub-address corresponds to the byte address of the DLPC900 commands described in
Appendix A. Most I2C sub-addresses have a Read and Write command pair where the Write command
equals the Read command with the most significant bit set. For example, Table 1-2 and Table 1-4 show
the Input Data Channel Swap sub-address command pair is (0x04,0x84), where the Write sub-address
command 0x84 is the Read sub-address command 0x04 with the most significant bit set. Each subaddress command requires a certain number of data bytes, and each command is followed by variable
length data where the least significant byte is first for each parameter.
NOTE: The DLPC900 I2C command data is formatted with the least significant byte first for each
parameter in the data. This maintains the same format with the USB protocol. However, it
deviates from the DLPC350 I2C format where the most significant byte is first.
The DLPC900 internal command buffer has a maximum of 512 bytes and it is shared between the Read
and Write commands; therefore, whenever a Read command is executed it must be followed by I2C
operation with the Read Slave Address to retrieve the data otherwise the data will be overwritten by the
next command executed. See Section 1.1.2 for a Read command example.
1.1.2 Example I2C Read Command Sequence
To execute a command to read the Input Data Channel Swap setting, the host builds a sequence of bytes
containing the slave address, the sub-address, and the data (if any), and performs the following steps:
1.
2.
3.
4.
5.
The host performs the required START condition followed by sending the sequence of bytes.
The DLPC900 will hold the SCL line low to indicate it is busy.
The host waits for the DLPC900 to release the SCL line.
Once the SCL line goes high, the host performs a STOP condition.
The host then performs a START condition followed by sending the Read Slave Address (0x35), and
then reads the required number of bytes and concludes with a STOP condition.
An example of the above read command sequence is shown in Table 1-2, and a waveform diagram of a
host executing this read sequence is shown in Figure 1-1 and Figure 1-2.
Table 1-2. Read Command Sequence Example (1)
SLAVE
ADDRESS
SUB-ADDRESS
34
04
DATA
35
(1)
03
All values shown are in HEX notation.
START
Slave Write Address
ACK
Sub-address
SCL held low by
DLPC900
ACK
STOP
SCL
SDA
0x34
0x04
Figure 1-1. I2C Read Command Waveform Diagram
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START
Slave Read Address
ACK
Data
ACK
STOP
SCL
SDA
0x03
0x35
Figure 1-2. I2C Read Data Waveform Diagram
1.1.2.1
Read Command Example with Parameters
Some Read sub-address commands require a parameter(s) to be included in the sequence. For example,
the command in Section 2.3.6.1 has multiple GPIO to choose from. Therefore, the GPIO selection
parameter must be included in the Read byte sequence in order to retrieve the configuration for the GPIO
chosen. Table 1-3 shows the two I2C operations, where the first row contains the parameter data 06 which
indicates GPIO 6. The second row is the returned data of 06 03, where 06 was the chosen GPIO 6 and
has a configuration of 03.
Table 1-3. Read Command with Parameter Sequence Example
SLAVE
ADDRESS
SUB-ADDRESS
34
44
DATA
06
35
(1)
(1)
06 03
All values shown are in HEX notation.
1.1.3 Example I2C Write Command Sequence
To execute a command to set the Input Data Channel Swap value, the host builds a sequence of bytes
containing the slave address, the sub-address, and the data, and performs the following steps.
1. The host performs the required START condition followed by sending the sequence of bytes.
2. The host performs a STOP condition.
An example of the above write command sequence is shown in Table 1-4, and a waveform diagram of a
host executing this write sequence is shown in Figure 1-3.
Table 1-4. Write Command Sequence Example (1)
(1)
SLAVE
ADDRESS
SUB-ADDRESS
DATA
34
84
02
All values shown are in HEX notation.
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USB Interface
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Slave Write Address
ACK
Sub-address
Data
ACK
ACK
STOP
SCL
SDA
0x84
0x34
0x02
Figure 1-3. I2C Write Command Waveform Diagram
1.2
USB Interface
The DLPC900 controller also supports the USB 1.1 human interface device (HID) to exchange commands
and data with a host processor. The USB commands are variable length data packets that are sent with
the least significant byte first for each parameter.
1.2.1 USB Transaction Sequence
The USB 1.1 HID protocol has the structure shown in Figure 1-4. The host must build a stream of bytes
that consist of the Report ID, Header, and the payload. The following is a description of these three parts.
Report ID: The Report ID is always set to 0 and always the leading byte of all transfers.
Header: The header consists of four bytes.
1) Flag Byte: Shown in Figure 1-4 and described in the Read and Write examples in Section 1.2.2 and
Section 1.2.3.
2) Sequence Byte: The sequence byte can be a rolling counter. It is used primarily when the host
wants a response from the DLPC900. The DLPC900 will respond with the same sequence byte that
the host sent. The host can then match the sequence byte from the command it sent with the
sequence byte from the DLPC900 response.
3) Length: Two bytes in length, this denotes the number of data bytes in the Payload only.
Payload Bytes: The payload bytes consist of the USB command followed by the data that is associated
with the command.
USB Transaction Sequence
Header Bytes
Report ID = 0
Byte 0
Payload Bytes
USB Command
Flag Byte Sequence Byte Length LSB Length MSB
Byte 1
Byte 2
Byte 3
LSB
MSB
Byte 4
R/W
Reply
Error
Reserved
Destination
Bit 7
Bit 6
Bit 5
Bit 4:3
Bit 2:0
Data...
Bytes 5 ...N
Figure 1-4. USB HID Protocol
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During a Write operation, the host transmits the entire transaction sequence to the DLPC900, and the
DLPC900 performs the operation associated with the Write command. During a Read operation, the host
transmits the entire transaction sequence to the DLPC900, and the DLPC900 performs the operation
associated with the Read command. Therefore, both Write and Read transactions are considered writes to
the DLPC900 where the host performs an API level Writefile to the HID driver. The difference is when the
DLPC900 executes a Read operation, where the DLPC900 places the response into its internal buffer and
waits for the host to perform an API level Readfile to the HID driver and only then does the DLPC900
transmit the response data back to the host.
The DLPC900 internal command buffer has a maximum of 512 bytes and it is shared between both the
Write and Read operations; therefore, whenever the host performs a Read operation, it must be followed
by the Readfile to the HID driver to get the response otherwise the response data will be overwritten by
the next Write or Read operation.
The HID protocol is limited to 64 byte transfers in both directions. Therefore, commands that are larger
than 64 bytes require multiple transfers. Whenever such a command is used, only the very first transfer
requires the Header and the USB Command. The Report ID is always the leading byte of all transfers.
Figure 1-5 shows an example of a Write command that contains 76 bytes and requires two transfers.
Notice that the first transfer contains 65 bytes, which is correct. The host hardware level HID driver will
extract the Report ID before transmitting or receiving the data over the USB bus.
Multiple USB Transaction Transfers
Header Bytes
First transfer
Report ID = 0
Byte 0
Payload Bytes
USB Command
0x00
0x17
0x4C
Byte 1
Byte 2
Byte 3
0x00
0x12
Byte 4
0x20
0x12 0x83 ««««...
Bytes 5 - 64
Payload Bytes
Second transfer
Report ID = 0
0x45 0xAE 0xF7 «««««««..0x3B 0x1D 0xC5
Byte 65
Bytes 66 - 83
Figure 1-5. USB Multi-Transfer Transaction
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1.2.2 USB Read Transaction Sequence Example
To perform a Read operation on the DLPC900, the host must assemble a sequence of bytes that
corresponds to the command being used. The following Table 1-5 shows an example on how to read the
curtain color intensity of each color.
Table 1-5. Read Operation Example
REPORT ID
BYTE
FLAG
BYTE
SEQUENCE
BYTE
00
C0
11
LENGTH
(2)
(1)
USB COMMAND
02 00
(2)
00 11
(1) All values shown are in HEX notation.
(2) LSB precedes the MSB for each parameter.
1. Report ID byte: Always set to 0.
2. Flag byte. Where:
• Bits 2:0 are set to 0x0 for regular DLPC900 operation.
• Bit 6 is set to 0x1 to indicate the host wants a reply from the device.
• Bit 7 is set to 0x1 to indicate a read transaction.
3. Sequence byte: The sequence byte can be a rolling counter. It is used primarily when the host wants a
response from the DLPC900. The DLPC900 will respond with the same sequence byte that the host
sent. The host can then match the sequence byte from the command it sent with the sequence byte
from the DLPC900 response.
4. Length: Two bytes in length, this denotes the number of data bytes in the sequence and excludes the
number of bytes in steps 1 through 4. It denotes the total number of bytes sent in steps 5 (command
bytes).
5. USB Command: Two byte USB command.
6. Once the host transmits the data over the USB interface, the DLPC900 will respond to the Read
operation by placing the response data in its internal buffer. The host must then perform a HID driver
read operation. Table 1-6 shows the response data sent back from the DLPC900.
A. Report ID: Always set to 0.
B. Flag byte: The same as was sent plus error bit. The host may check the error flag (bit 5) as
follows.
1. 0 = No errors.
2. 1 = Command not found or command failed.
C. Sequence byte: The same as was sent. The host may match the sent sequence byte with the
response sequence byte.
D. Length: Number of data bytes. The host must assemble the data according to the definition of the
command.
Table 1-6. Read Response Example
REPORT ID
BYTE
FLAG
BYTE
SEQUENCE
BYTE
00
C0
11
LENGTH
(2)
(1)
DATA
06 00
(2)
FF 01 FF 01 FF 01
(1) All values shown are in HEX notation.
(2) LSB precedes the MSB for each parameter.
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1.2.3 USB Write Transaction Sequence Example
To perform a Write operation on the DLPC900, the host must assemble a sequence of bytes that
corresponds to the command being used. The following Table 1-7 shows an example on how to set the
curtain color intensity of each color to 511.
Table 1-7. Write Operation Example
REPORT ID
BYTE
FLAG
BYTE
SEQUENCE
BYTE
00
00
12
LENGTH
08 00
(2)
USB COMMAND
00 11
(1)
(2)
DATA
(2)
FF 01 FF 01 FF 01
(1) All values shown are in HEX notation.
(2) LSB precedes the MSB for each parameter.
1. Report ID byte: Always set to 0.
2. Flag byte. Where:
• Bits 2:0 are set to 0x0 for regular DLPC900 operation.
• Bit 6 is set to 0x0 to indicate the host does not want a reply from the device. This bit is set to 0x1
only if a reply is needed, which is usually not required.
• Bit 7 is set to 0x0 to indicate a write transaction.
3. Sequence byte: The sequence byte can be a rolling counter. It is used primarily when the host wants a
response from the DLPC900. Normally during a write operation, the DLPC900 does not respond;
however, the host can continue to increment the sequence byte for the next command operation.
4. Length: Two bytes in length, this denotes the number of data bytes in the sequence and excludes the
number of bytes in steps 1 through 4. It denotes the total number of bytes sent in steps 5 (command
bytes) and 6 (data bytes).
5. USB Command: Two byte USB command.
6. Data: The data appropriate to the command.
1.3
INIT_DONE Signal
The DLPC900 does not have a dedicated INIT_DONE signal output to indicate that it has completed its
power-up initialization and is ready to accept commands. The user may configure one of the nine GPIOs
available as an INIT_DONE signal output simply by adding the GPIO configuration into the default batch
file that is executed at power-up. A 10-kΩ pull-down resistor must be connected to the GPIO that will be
used.
The following is an example of adding the configuration for GPIO_08 to a batch file, where GPIO_08 is
configured as an output and the signal is set high. When this command is added to the top of the batch
file, the GPIO output will go high in approximately 800 ms from the time POSENSE goes high:
GPIO_CONFIG: 0x8 0x3
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Chapter 2
DLPU018E – October 2014 – Revised April 2019
DLPC900 Control Commands
This chapter lists the DLPC900 control commands.
The following sections list the supported control commands of the DLPC900. In the Type column, ‘wr’ type
is a writeable field through I2C or USB write transactions. Data can also be read through I2C or USB read
transactions for ‘wr’ type bits. Type r is read-only. Write transactions to read-only fields are ignored.
The Reset column in all of the following command tables is the default value after power up. These values
may be overwritten after power up.
NOTE:
Reserved bits and registers. When writing to valid command bit fields, all bits marked as
unused or reserved should be set to 0, unless specified otherwise.
NOTE:
Momentary Image Corruption During Command Writes. Certain commands may cause
brief visual artifacts in the display image under some circumstances. Command data values
may always be read without impacting displayed image. To avoid momentary image
corruption due to a command, disable the LEDs prior to the command write, then reenable
the LEDs after all commands have been issued.
NOTE:
2.1
Writing or reading from undocumented registers is NOT recommended.
DLPC900 Status Commands
The DLPC900 has the following set of status commands:
Hardware Status
System Status
Main Status
Retrieve Firmware Version
Read Error Codes
14
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2.1.1 Hardware Status
The hardware status command provides status information on the sequencer, digital micromirror device
(DMD) controller, and initialization of DLPC900.
Table 2-1. Hardware Status Command
I2C
USB
Read
0x1A0A
0x20
Table 2-2. Hardware Status Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d1
r
d0
r
d0
r
d0
r
d0
r
d0
r
d0
r
d0
r
Internal Initialization
0
0 = Error
1 = Successful
1
0 = No Error
1 = Incompatible Controller or DMD
DMD Reset Controller Error
2
0 = No error has occurred
1 = Multiple overlapping bias or reset operations are accessing the same
DMD block.
Forced Swap Error
0
3
0 = No error has occurred.
1 = Forced Swap Error occurred.
4(1)
5
0 = No Slave Controller Present
1 = Slave Controller Present and Ready
Reserved
Sequencer Abort Status Flag
6
0 = No error has occurred
1 = Sequencer has detected an error condition that caused an abort
Sequencer Error
7
0 = No error has occurred.
1 = Sequencer detected an error.
(1) When the DLPC900 is combined with a DLP6500, this bit will be 0. When two DLPC900 controllers are combined with a
DLP9000, this bit must be 1 for proper operation. If the bit is 0 and the DLPC900 is combined with a DLP9000, this indicates a
malfunction in one or both controllers.
NOTE:
Any error condition indicates a fault condition and it must be corrected.
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2.1.2 System Status
The system status command provides the DLPC900 status on internal memory tests.
Table 2-3. System Status Command
I2C
USB
Read
0x1A0B
0x21
Table 2-4. System Status Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d1
r
d0
r
Internal Memory Test
0
0
0 = Internal Memory Test failed
1 = Internal Memory Test passed
1:7
Reserved
2.1.3 Main Status
The main status command provides the status of DMD park and DLPC900 sequencer, frame buffer, and
gamma correction.
Table 2-5. Main Status Command
I2C
USB
Read
0x1A0C
0x22
Table 2-6. Main Status Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d1
r
d0
r
d0
r
d0
r
d0
r
d0
r
d0
r
DMD Park Status
0
0 = DMD micromirrors are not parked
1 = DMD micromirrors are parked
Sequencer Run Flag
1
0 = Sequencer is stopped
1 = Sequencer is running normally
Video Frozen Flag
2
0 = Video is running (Normal frame change)
1 = Video is frozen (Displaying single frame)
0
External video source locked
3
0 = External source not locked
1 = External source locked
Port 1 syncs valid
4
0 = Port 1 syncs not valid
1 = Port 1 syncs valid
Port 2 syncs valid
5
0 = Port 2 syncs not valid
1 = Port 2 syncs valid
7:6
16
DLPC900 Control Commands
Reserved
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2.1.4 Retrieve Firmware Version
This command reads the version information of the DLPC900 firmware.
Table 2-7. Retrieve Firmware Version Command
I2C
USB
Read
0x0205
0x11
Table 2-8. Get Version Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
Will match firmware version.
r
d0
r
d0
r
d0
r
Application software revision:
3:0
15:0
Application software patch number
23:16
Application software minor revision
31:24
Application software major revision
API software revision:
7:4
15:0
API patch number
23:16
API minor revision
31:24
API major revision
Software configuration revision:
11:8
15:0
Software configuration patch number
23:16
Software configuration minor revision
31:24
Software configuration major revision
Sequencer configuration revision:
15:12
15:0
Sequencer configuration patch number
23:16
Sequencer configuration minor revision
31:24
Sequencer configuration major revision
2.1.5 Reading Hardware Configuration and Firmware Tag Information
This command reads the hardware configuration of the system and also returns the 31 byte ASCII
firmware tag information.
Table 2-9. Reading Hardware Configuration and Firmware Tag Information Command
I2C
USB
Read
0x0206
0x12
Table 2-10. Reading Hardware Configuration and Firmware Tag Command Response
BYTE
0
VALUE
DESCRIPTION
0x00
Unknown
0x01
DLP6500 hardware
0x02
DLP9000 hardware
32:1
RESET
TYPE
0
r
31 byte ASCII firmware tag information
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2.1.6 Read Error Code
This command retrieves the error code number from the DLPC900 of the last executed command.
Table 2-11. Read Error Code Command
I2C
USB
Read
0x0100
0x32
Table 2-12. Read Error Code Command Definition
BYTE
0
VALUE
DESCRIPTION
0
No error
1
Batch file checksum error
2
Device failure
3
Invalid command number
4
Incompatible controller / DMD
5
Command not allowed in current mode
6
Invalid command parameter
7
Item referred by the parameter is not present
8
Out of resource (RAM / Flash)
9
Invalid BMP compression type
10
Pattern bit number out of range
11
Pattern BMP not present in flash
12
Pattern dark time is out of range
13
Signal delay parameter is out of range
14
Pattern exposure time is out of range
15
Pattern number is out of range
16
Invalid pattern definition (errors other than 9-15)
17
Pattern image memory address is out of range
18-254
255
RESET
TYPE
0
r
Not defined
Internal Error
2.1.7 Read Error Description
This command retrieves the error descriptive string from the DLPC900 of the last executed command. The
string is composed of character bytes ending with a null termination character.
Table 2-13. Read Error Description Command
I2C
USB
Read
0x0101
0x33
Table 2-14. Read Error Description Command Definition
BYTE
127:0
18
BITS
DESCRIPTION
RESET
TYPE
All
Error description for the last executed command.
0 terminated string of character bytes.
0
r
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2.2
DLPC900 Firmware Programming Commands
The Programming commands manage downloading a new firmware image into flash memory. This can be
done over I2C or USB interfaces. The commands in the DLPC900 Programming Commands section are
only valid in program mode except for Enter Program Mode (I2C: 0x30 or USB 0x3001), which exits
normal mode and enters program mode. Once in program mode, the user must issue the proper Exit
Program Mode (I2C: 0x30 or USB 0x0030) command to return to normal mode. While in program mode,
commands outside of this section will not work.
Flash memory has the layout shown in Figure 2-1. The design includes three flash devices, each
measuring 16 Megabytes, for storing the firmware. The firmware consists of the bootloader, the main
application, any images stored in flash (optional), and 1 Megabyte of reserved space. The bootloader is
located at the beginning of the flash on chip select 1 (CS1). The size of the bootloader is 128 kilobytes,
beginning at address 0xF9000000. The bootloader is necessary for operation. If the bootloader becomes
corrupted in some way it may render the device inoperable. The bootloader is followed by the main
application and then image data. When writing to the flash, the location indexes sequentially, from CS1 to
CS2. At the end of CS2, location 0xFAFFFFFF, the index moves to location 0xF8000000, CS0 (see note).
There is 1 Megabyte of reserved space in CS0 from 0xF8F00000 to 0xF8FFFFFF. This is necessary for
operation and must not be overwritten.
NOTE:
Writing data from CS2 to CS0: Patterns must not span across CS2 and CS0 because the
addresses do not ascend linearly between CS2 and CS0. If a pattern does not fit in CS2, the
full, 24-bit image (or composite image) must be moved into CS0.
Figure 2-1. Flash Device Layout
2.2.1 Read Status
This command indicates if the flash is ready to be programmed and also if a flash operation is in progress.
Table 2-15. Read Status Command
I2C
USB
Read
0x0000
0x23
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Table 2-16. Read Status Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
Master ready
0
0 = Master not ready
d1
1 = Master ready
Slave ready (Valid only on DLP9000)
1
d0 (DLP6500)
d1 (DLP9000)
0 = Slave not ready
1 = Slave ready
Slave controller flash busy (Valid only on DLP9000)
2
0 = Slave not busy
d0
1 = Slave busy
Master controller flash busy
0
3
0 = Master not busy
d0
1 = Master busy
4
Reserved
d0
Slave controller present (Valid only on DLP9000)
5
d0 (DLP6500)
d1 (DLP9000)
0 = Slave not present
1 = Slave present
Slave controller program mode (Valid only on DLP9000)
6
d0 (DLP6500)
d1 (DLP9000)
0 = Slave not in program mode
1 = Slave in program mode
Master controller program mode
7
0 = Master not in program mode
d1
r
1 = Master in program mode
3:0
Major Version
x
7:4
Minor version
x
2
7:0
Patch version
x
3
7:0
Controller ID
x52
4
7:0
Bootloader ID
65h = DLP6500
90h = DLP9000
5
7:0
1
x65 (DLP6500)
x90 (DLP9000)
Bytes 1 - 15 are from master or slave
0 = Bytes 1 - 15 are from Slave
d1
1 = Bytes 1 - 15 are from Master
20
6
7:0
Data (LSB)
d0
7
7:0
Data
d0
8
7:0
Data
d0
d0
9
7:0
Data (MSB)
10
7:0
Reserved
x3
11
7:0
Reserved
d0
12
7:0
Data (LSB)
d0
13
7:0
Data
d0
14
7:0
Data
d0
15
7:0
Data (MSB)
d0
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2.2.2 Enter Program Mode
This command tells the controller to enter its programming mode and jump to the boot loader. If the boot
loader receives this command, then the command has no effect.
Table 2-17. Enter Program Mode Command
I2C
USB
Write
0x3001
0x30
Table 2-18. Enter Program Mode Command Definition
BYTE
0
BITS
1:0
7:2
DESCRIPTION
RESET
TYPE
d0
w
Program Mode
1 = Enter Program Mode – Jump to boot loader
Reserved
2.2.3 Exit Program Mode
This command tells the controller to exit its programming mode. If the application receives the exit
command, the command has no effect.
Table 2-19. Exit Program Mode Command
I2C
USB
Write
0x0030
0x30
Table 2-20. Exit Program Mode Command Definition
BYTE
0
BITS
1:0
7:2
DESCRIPTION
RESET
TYPE
d0
w
Program Mode
2 = Exit Program Mode – Reset controller and run application
Reserved
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2.2.4 Read Control
This command reads the Flash Manufacturer and Device IDs, as well as the Checksum, after the
Calculate Checksum command is executed.
Table 2-21. Read Control Command
I2C
USB
Read
0x0015
0x15
Table 2-22. Query Flash IDs Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
r
ID
0 = Request Checksum
0
3:0
xB = Request Number of flash present
xC = Requests Flash Manufacturer ID
xD = Requests Flash Device ID
7:4
Reserved
2.2.5 Start Address
The Start Address command serves three purposes.
1) Specifies the start address of the flash download write operation. It is the responsibility of the user to
ensure that the start address is on a sector boundary in the current flash device.
2) Specifies the start address where checksum operation begins.
3) Specifies the sector address to be erased. The address should be the start of a sector.
The Flash Data Size command should always follow 1 and 2 above, which defines how many bytes to be
downloaded or how many bytes to include for the checksum operation.
The user must avoid erasing the first 128 kilobytes of the boot flash as this contains the boot
image. The user must also avoid erasing other sectors that contain firmware that are required for
proper controller operation.
Table 2-23. Start Address Command
I2C
USB
Read
0x0032
0x32
Table 2-24. Start Address Command Definition
BYTE
3:0
22
BITS
31:0
DLPC900 Control Commands
DESCRIPTION
4 byte flash address. Valid Range: 0xF8000000 – 0xFAFFFFFF.
Byte 0 is LSB, byte 4 is MSB.
RESET
TYPE
x0
w
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2.2.6 Erase Sector
This is a system write command to erase a sector of flash memory. This command should not be
executed until valid data has been written to the Flash Start Address. Users are responsible for ensuring
that a valid address has been written. The Busy bit will be set in the Boot Loader status byte while the
sector erase is in progress. There is no data associated with this command.
Table 2-25. Erase Sector Command
2
IC
USB
Write
0x0028
0x28
NOTE:
TI cautions against erasing the boot sector of the device as this contains key initialization
parameters and the flash programming functionality. Only the sector that contains the start
address will be erased, not all sectors from the start address to the end of the device. Users
must either pre-erase all sectors to be programmed, or erase and program each sector
individually.
2.2.7 Download Flash Data Size
System write command to specify the size of the following flash download. The data size is sent to tell the
Boot Loader how many bytes to expect to program into the flash device. It is also used for specifying the
checksum range when requesting that operation.
Table 2-26. Download Flash Data Size Command
2
IC
USB
Write
0x0033
0x33
Table 2-27. Download Data Size Command Definition
BYTE
3:0
BITS
31:0
DESCRIPTION
4 Byte flash size. Valid Range 4 - 0x2FFFFFF.
Byte 0 is LSB, byte 3 is MSB.
RESET
TYPE
x0
w
2.2.8 Download Data
This command contains the flash data to be programmed. The maximum data size which can be sent in
each command is 512 bytes, which corresponds to a data length of 514. The number of bytes downloaded
by consecutive download data commands must match the predefined Flash Data Size for the operation to
be successful.
Table 2-28. Download Data Command
I2C
USB
Write
0x0025
0x25
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Table 2-29. Download Data Command Definition
BYTE
BITS
0
7:0
Length LSB
DESCRIPTION
1
7:0
Length MSB
513:2
4095:0
514
7:0
Up to 512 Data Bytes
RESET
TYPE
x0
w
Checksum
2.2.9 Calculate Checksum
This command calculates the checksum. Executing this command causes the Boot Loader to read the
data in the flash memory and calculate a 4-byte 8-bit checksum. The Busy bit will be set in the Boot
Loader status byte while the checksum computation is in progress. After completion, the 4-byte checksum
can be read back through the Read Control command. The data range to be summed is specified by
writing appropriate data with the Flash Start Address and Flash Data Size commands. There is no data
associated with this command.
Table 2-30. Calculate Checksum Command
I2C
USB
Write
0x0026
0x26
2.2.10 Dual Controller Control
This command stops the given controller from executing any further commands until enabled by the same
command. This command is intended to be used when two DLPC900 controllers are combined with one
DLP9000 DMD, where one controller is the master and the other is the slave.
Table 2-31. Dual Controller Control Command
2
IC
USB
Write
0x0031
0x31
Table 2-32. Dual Controller Control Definition
BYTE
BITS
0
0
1
7:2
24
DLPC900 Control Commands
DESCRIPTION
1 – Disable Master Controller
0 – Enable Master Controller
1 – Disable Slave Controller
0 – Enable Slave Controller
Reserved
RESET
TYPE
x0
w
x0
w
x0
w
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2.3
Chipset Control Commands
The DLPC900 I2C and USB control commands are accepted in any order, except when special
sequencing is required (for example, setting up the flash). Each control command is validated for subaddress and parameter errors as it is received. Commands failing validation are ignored. On power up, it
is necessary to wait for DLPC900 to complete its initialization before sending any I2C or USB commands.
2.3.1 Chipset Configuration Commands
The Chipset Configuration commands enable control of the power mode, DMD park state and image
curtain display.
2.3.1.1
Power Mode
The Power Control places the DLPC900 in a standby state and powers down the DMD interface. Enter
Standby mode prior to any planned system power shutdowns to safely park the micro-mirrors. Standby
mode should only be enabled after all data for the last frame to be displayed has been transferred to the
DLPC900. Standby mode must be disabled prior to sending any new data. After executing this command,
the host may poll the system status using I2C commands 0x20, x21, and 0x22 or USB commands
0x1A0A, 0x1A0B, and 0x1A0C to attain status.
Table 2-33. Power Mode Command
I2C
USB
Read
Write
0x07
0x87
0x0200
Table 2-34. Power Mode Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
Power Mode
0 = Return to Normal mode from Standby Mode of operation. In Normal
mode, the selected external source will be displayed.
1:0
0
1 = Enter Standby mode to place the DMD in a standby state. Standby
will disable the front end input data interfaces and park and power down
parts of the DMD.
2 = Perform a software reset
3 = Reserved
7:2
2.3.1.2
Reserved
DMD Park/Unpark
The DMD Park/Unpark command parks or unparks the mirrors of the DMD. Parking the DMD mirrors is
recommended prior to a planned or unplanned power down event. By monitoring the input supply voltage
to the system, a processor (external to the DLPC900) can send the Park command to initiate DMD mirror
parking quickly before the individual power supplies fall below acceptable levels. Since the Standby
command execution includes the parking of the DMD, the Park command is unneeded for planned power
down events where Standby is used. If the Display Mode is set to Pre-stored pattern mode, Video pattern
mode or Pattern On-The-Fly mode, the pattern sequence must be stopped prior to execution of this
command. This is done by calling Pattern Display Start/Stop (Section 2.4.4.3.1).
If the system is not going to be powered down it is recommended to set the DMD to Idle Mode (see
Section 2.4.1.4).
Table 2-35. DMD Park/Unpark Command
2
IC
USB
Read
Write
0x14
0x94
0x0609
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Table 2-36. DMD Park/Unpark Command Definition
BYTE
BITS
0
0
7:1
2.3.1.3
DESCRIPTION
RESET
TYPE
0 = Unpark DMD. Controller returns to the last commanded operating
mode.
1= Park DMD. Mirrors go to parked state. LED outputs are disabled.
d0
wr
Reserved
d0
r
Curtain Color
This register provides image curtain control. When enabled and the input source is set to external video
with no video source connected, a solid color field is displayed on the entire DMD display. The Display
Curtain Control provides an alternate method of masking temporary source corruption from reaching the
display due to on-the-fly reconfiguration. It is also useful for optical test and debug support.
Table 2-37. Curtain Color Command
I2C
USB
Read
Write
0x06
0x86
0x1100
Table 2-38. Display Curtain Command Definition
BYTE
BITS
9:0
1:0
15:10
9:0
3:2
15:10
9:0
5:4
15:10
DESCRIPTION
RESET
TYPE
Red color intensity in a scale from 0 to 1023
d0
wr
Reserved
d0
r
Green color intensity in a scale from 0 to 1023
d0
wr
Reserved
Blue color intensity in a scale from 0 to 1023
Reserved
d0
r
d1023
wr
d0
r
2.3.2 Parallel Interface Configuration
The Parallel Interface Configuration manages the operation of the RGB parallel interface.
2.3.2.1
Input Data Channel Swap
The Input Data Channel Swap commands configure the specified input data ports and maps the data
subchannels. The DLPC900 interprets channel A as Green, channel B as Red, and channel C as Blue.
Table 2-39. Input Data Channel Swap Command
I2C
26
USB
Read
Write
0x04
0x84
DLPC900 Control Commands
0x1A37
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Table 2-40. Input Data Channel Swap Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
0
w
d4
wr
d0
r
Port Number
0
0 – Port 1
1 – Port 2
Swap Parallel Interface Data Subchannel:
0 - ABC = ABC, No swapping of data subchannels
1 - ABC = CAB, Data subchannels are right shifted and circularly rotated
0
2 - ABC = BCA, Data subchannels are left shifted and circularly rotated
3:1
3 - ABC = ACB, Data subchannels B and C are swapped
4 - ABC = BAC, Data subchannels A and B are swapped
5 - ABC = CBA, Data subchannels A and C are swapped
6 - Reserved
7 - Reserved
7:4
2.3.3
Reserved
Input Source Commands
The Input Source Selection determines the input source for the DLPC900 data display.
2.3.3.1
Port and Clock Configuration
This command selects which port the RGB data is on and which pixel clock, data enable, and syncs to
use. The user must select the correct port and clock configuration according to the PCB layout routing.
Table 2-41. Port and Clock Configuration Command
I2C
USB
Read
Write
0x03
0x83
0x1A03
Table 2-42. Port and Clock Configuration Command Definition
BYTE
BITS
DESCRIPTION
(1) (2)
RESET
TYPE
d0
wr
0 - Data Port 1, Single Pixel mode
1:0
1 - Data Port 2, Single Pixel mode
2 - Data Port 1-2, Dual Pixel mode. Even pixel on port 1, Odd pixel on port 2
3 - Data Port 2-1, Dual Pixel mode. Even pixel on port 2, Odd pixel on port 1
0 - Pixel Clock 1
0
3:2
1 - Pixel Clock 2
2 - Pixel Clock 3
3 - Reserved
4
5
7:6
0 - Data Enable 1
1 - Data Enable 2
0 - P1 VSync and P1 HSync
1 - P2 VSync and P2 HSync
Reserved
(1) Single Pixel refers to the parallel data that is connected to port 1 or port 2 and the input source pixel clock that is less than 175
MHz. Both ports cannot be used simultaneously in single pixel mode.
(2) Dual Pixel refers to the parallel data that is connected to port 1 and port 2 and the input source pixel clock that is less than 141
MHz.
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Input Source Configuration
The Input Source Configuration command selects the input source to be displayed by the DLPC900: 30-bit
parallel port, Internal Test Pattern or flash memory. After executing this command, the host may poll the
system status using I2C commands: 0x20, 0x21, and 0x22, or the respective USB commands: 0x1A0A,
0x1A0b, and 0x1A0C.
Table 2-43. Input Source Configuration Command
2
IC
USB
Read
Write
0x00
0x80
0x1A00
Table 2-44. Input Source Configuration Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d1
wr
d0
r
Select the input source and interface mode:
0 = Primary parallel interface with 16-bit, 20-bit, 24-bit, or 30-bit RGB or YUV
data formats.
2:0
1 = Internal test pattern generator.
2 = Flash. Images are 24-bit single-frame, still images stored in flash that are
uploaded on command.
3 = Solid curtain.
0
Parallel Interface bit depth
0 = 30 bits
4:3
1 = 24 bits
2 = 20 bits
3 = 16 bits
7:5
28
Reserved
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2.3.3.3
Input Pixel Data Format
The Input Pixel Data Format command defines the pixel data input format to the DLPC900.
Table 2-45. Input Pixel Data Format Command
I2C
USB
Read
Write
0x02
0x82
0x1A02
Table 2-46. Input Pixel Data Format Command Definition
BYTE
BITS
DESCRIPTION
Select the pixel data format:
0
3:0
7:4
2.3.3.4
RESET TYPE
Supported Pixel Formats vs Source Type
Parallel
Test Pattern
Flash Image
0 - RGB (30 bit)
Yes
Yes
Yes
1 - YCrCb 4:4:4 (30 bit)
Yes
No
No
2 - YCrCb 4:2:2
Yes
No
Yes
Reserved
d0
wr
d0
r
Internal Test Pattern Select
When the internal test pattern is the selected input, the Internal Test Pattern Select defines the test pattern
displayed on the screen. These test patterns are internally generated; therefore, all image processing is
performed on the test images. The resolution of the Test Pattern will be native to the DLP6500 or the
DLP9000.
Table 2-47. Internal Test Pattern Select Command
I2C
USB
Read
Write
0x0A
0x8A
0x1203
Table 2-48. Internal Test Patterns Select Command Definition
BYTE
BITS
DESCRIPTION
Internal Test Patterns Select:
RESET
TYPE
d8
wr
0 = Solid field
1 = Horizontal ramp
2 = Vertical ramp
3 = Horizontal lines
4 = Diagonal lines
0
3:0
5 = Vertical lines
6 = Grid
7 = Checkerboard
8 = RGB ramp
9 = Color bars
10 = Step bars
11 - 15 = Reserved
7:4
Reserved
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Internal Test Patterns Color
When the internal test pattern is the selected input, the Internal Test Patterns Color Control defines the
colors of the test pattern displayed on the screen. These test patterns are internally generated; therefore,
all image processing is performed on the test images. All command registers should be set up as if the
test images are input from an RGB 8:8:8 external source. The foreground color setting affects all test
patterns. The background color setting affects those test patterns that have a foreground and background
component, such as Horizontal Lines, Diagonal Lines, Vertical Lines, Grid, and Checkerboard.
Table 2-49. Internal Test Patterns Color Command
I2C
USB
Read
Write
0x1A
0x9A
0x1204
Table 2-50. Internal Test Patterns Color Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
x3FF
wr
x3FF
wr
x3FF
wr
x0
wr
x0
wr
x0
wr
Red Foreground Color intensity in a scale from 0 to 1023
1:0
9:0
0x0 = No Red Foreground color intensity
...
0x3FF = Full Red Foreground color intensity
Green Foreground Color intensity in a scale from 0 to 1023
3:2
9:0
0x0 = No Green Foreground color intensity
...
0x3FF = Full Green Foreground color intensity
Blue Foreground Color intensity in a scale from 0 to 1023
5:4
9:0
0x0 =No Blue Foreground color intensity
...
0x3FF = Full Blue Foreground color intensity
Red Background Color intensity in a scale from 0 to 1023
7:6
9:0
0x0 = No Red Background color intensity
...
0x3FF = Full Red Background color intensity
Green Background Color intensity in a scale from 0 to 1023
9:8
9:0
0x0 = No Green Background color intensity
...
0x3FF = Full Green Background color intensity
Blue Background Color intensity in a scale from 0 to 1023
11:10
9:0
0x0 = No Blue Background color intensity
...
0x3FF = Full Blue Background color intensity
30
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2.3.3.6
Load Image
This command loads an image from flash memory and then displays it on the DMD. After executing this
command, the host may poll the system status using I2C commands: 0x20, 0x21, and 0x22, or using the
respective USB commands: 0x1A0A, 0x1A0B, and 0x1A0C.
Table 2-51. Load Image Command
I2C
USB
Read
Write
0x7F
0xFF
0x1A39
Table 2-52. Load Image Command Definition
BYTE
BITS
0
7:0
DESCRIPTION
RESET TYPE
Image Index. Loads the image at this index. Reading this back provides the index that was
loaded most recently through this command.
d0
wr
2.3.4 Image Flip
The DLPC900 supports long- and short-axis image flips to support rear- and front-projection, as well as
table- and ceiling-mounted projection.
NOTE:
2.3.4.1
If showing image from Flash, load image (I2C: 0x7F, USB: 0x1A39), this must be called to
update the image flip setting.
Long-Axis Image Flip
The Long-Axis Image Flip defines whether the input image is flipped across the long axis of the DMD. If
this parameter is changed while displaying a still image, the input still image should be re-sent. If the
image is not re-sent, the output image might be slightly corrupted. Figure 2-2 shows an example of a longaxis image flip. In Structured Light mode, the image flip will take effect on the next bit-plane, image, or
video frame load. The DLPC900 does not support long axis image flip when combined with a
DLP9000 DMD.
Table 2-53. Long-Axis Image Flip Command
I2C
USB
Read
Write
0x08
0x88
0x1008
Table 2-54. Long Axis Image Flip Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
Flips image along the long side of the DMD:
0
0
0 = Disable flip
1 = Enable flip
7:1
Reserved
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DMD
Flip Disabled
Flip Enabled
Figure 2-2. Image Long-Axis Flip Example
2.3.4.2
Short Axis Image Flip
The Short-Axis Image Flip defines whether the input image is flipped across the short axis of the DMD. If
this parameter is changed while displaying a still image, the input still image should be resent. If the image
is not re-sent, the output image might be slightly corrupted. Figure 2-3 shows an example of a short axis
image flip. In Structured Light mode, the image flip will take effect on the next bit-plane, image, or video
frame load.
Table 2-55. Short Axis Image Flip Command
I2C
USB
Read
Write
0x09
0x89
0x1009
Table 2-56. Short-Axis Image Flip Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
Flips image along the short side of the DMD:
0
0
0 - Disable flip
1 - Enable flip
7:1
DMD
Reserved
Flip Disabled
Flip Enabled
Figure 2-3. Image Short-Axis Flip Example
32
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2.3.4.3
IT6535 Power Mode
The IT6535 Power Mode command allows the user to power-down and tri-state the IT6535 digital receiver
data and sync outputs. This command is ignored if the IT6535 is not present or has been disabled.
Table 2-57. IT6535 Power Mode Command
I2C
USB
Read
Write
0x0C
0x8C
0x1A01
Table 2-58. IT6535 Power Mode Command Definition
BYTE
BITS
DESCRIPTION
RESET TYPE
0 = Power-Down. (Outputs will be tri-stated)
0
1:0
1 = Power-Up for HDMI input.
2 = Power-Up for DisplayPort input.
d0
wr
d0
r
3 = Reserved
7:2
Reserved.
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2.3.5 LED Driver Commands
LED driver operation is a function of the individual red, green, and blue LED-enable software-control
parameters. The recommended order for initializing LED drivers is to:
1. Program the individual red, green, and blue LED driver currents.
2. Program the LED PWM polarity.
3. Enable the individual LED enable outputs.
4. Turn ON the DLP display sequence (see Section 2.4.1).
The LED-current software-control parameters define PWM values that drive corresponding LED current.
The LED enables indicate which LED will be activated.
CAUTION
Careful control of LED current is needed to prevent damage to LEDs. Follow all
LED manufacturer recommendations and maintain LED current levels within
recommended operating conditions. The setting of the LED current depends on
many system and application parameters (including projector thermal design,
LED specifications, selected display mode, and so forth). Therefore, the
recommended and absolute-maximum settings vary greatly.
2.3.5.1
LED Enable Outputs
The DLPC900 offers three sets of pins to control the LED enables:
• LEDR_EN for the red LED
• LEDG_EN for the green LED
• LEDB_EN for the blue LED
After reset, all LED enables are placed in the inactive state until the board initializes.
Table 2-59. LED Enable Outputs Command
I2C
USB
Read
Write
0x10
0x90
0x1A07
Table 2-60. LED Enable Outputs Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
wr
d0
wr
d1
wr
d0
r
Red LED Enable
0
0 - Red LED is disabled
1 - Red LED is enabled
Green LED Enable
1
0 - Green LED is disabled
1 - Green LED is enabled
Blue LED Enable
0
2
0 - Blue LED is disabled
1 - Blue LED is enabled
LED Enable Control
3
0 - All LED enables are controlled by bits 2:0 and ignore Sequencer control
1 - All LED enables are controlled by the Sequencer and ignore the settings
in bits 2:0
7:4
34
DLPC900 Control Commands
Reserved
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2.3.5.1.1 LED PWM Polarity
The LED PWM Polarity command sets the polarity of all PWM signals. This command must be issued
before powering up the LED drivers.
Table 2-61. LED PWM Polarity Command
I2C
USB
Read
Write
0x0B
0x8B
0x1A05
Table 2-62. LED PWM Polarity Command Definition
BYTE
BITS
DESCRIPTION
Polarity of PWM signals
1:0
0
RESET
TYPE
d0
wr
d0
r
(1)
0 - Normal polarity. PWM 0 value corresponds to no current while PWM
255 value corresponds to maximum current.
1 - Inverted polarity. PWM 0 value corresponds to maximum current while
PWM 255 value corresponds to no current.
7:2
Reserved
(1) Depending on the LED driver design, the polarity chosen may have an opposite effect.
2.3.5.2
LED Driver Current
This parameter controls the pulse duration of the specific LED PWM modulation output pin. The resolution
is 8 bits and corresponds to a percentage of the LED current. The PWM value can be set from 0 to 100%
in 256 steps. If the LED PWM polarity is set to normal polarity, a setting of 0xFF gives the maximum PWM
current. The LED current is a function of the specific LED driver design.
Table 2-63. LED Driver Current Command
I2C
USB
Read
Write
0x4B
0xCB
0x0B01
CAUTION
Care should be taken when using this command. Improper use of this
command can lead to damage to the system. The setting of the LED current
depends on many system and application parameters (including projector
thermal design, LED specifications, selected display mode, and so forth).
Therefore, recommended and absolute-maximum settings vary greatly.
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Table 2-64. LED Driver Current Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
x97
wr
x78
wr
x7D
wr
Red LED PWM current control
Valid range, assuming normal polarity of PWM signals, is:
0x00 (0% duty cycle → Red LED driver generates no current)
0
7:0
to
0xFF (100% duty cycle → Red LED driver generates maximum current)
The current level corresponding to the selected PWM duty cycle is a function of
the specific LED driver design and thus varies by design.
Green LED PWM current control
Valid range, assuming normal polarity of PWM signals, is:
0x00 (0% duty cycle → Green LED driver generates no current)
1
7:0
to
0xFF (100% duty cycle → Green LED driver generates maximum current)
The current level corresponding to the selected PWM duty cycle is a function of
the specific LED driver design and thus varies by design.
Blue LED PWM current control
Valid range, assuming normal polarity of PWM signals, is:
0x00 (0% duty cycle → Blue LED driver generates no current)
2
7:0
to
0xFF (100% duty cycle → Blue LED driver generates maximum current)
The current level corresponding to the selected PWM duty cycle is a function of
the specific LED driver design and thus varies by design.
2.3.5.3
Set Minimum LED Pulse Width
This parameter sets the minimum LED pulse width restriction in microseconds for the implementation of
high speed illumination-modulated 8-bit patterns. A value of 0 indicates that there is no illumination
modulation.
Table 2-65. Set Minimum LED Pulse Width Command
I2C
Read
USB
Write
0x1A41
0x62
Table 2-66. Set Minimum LED Pulse Width Command Definition Table
2.3.5.4
BYTE
BITS
0
7:0
DESCRIPTION
Minimum pulse width in microseconds
RESET
TYPE
d0
wr
Get Minimum LED Pattern Exposure
This parameter gets the stored minimum LED pattern exposure, in microseconds.
Table 2-67. Get Minimum LED Pattern Exposure Command
2
IC
Read
USB
Write
0x63
36
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0x1A42
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Table 2-68. Get Minimum LED Pattern Exposure Command Definition Table
BYTE
0-15
BITS
DESCRIPTION
RESET
TYPE
7:0
16 bytes are returned. Each two bytes represent the Minimum Pattern Exposure
for each bit depth (from 0 to 8) in microseconds.
d0
r
2.3.6 GPIO Commands
DLPC900 offers 9 general-purpose input/output pins (GPIO). Some of these pins can be configured for
PWM output, PWM input, or clock output functionality. By default, all pins are configured as GPIO inputs.
2.3.6.1
GPIO Configuration
The GPIO Configuration command enables GPIO functionality on a specific set of DLPC900 pins. The
command sets their direction, output buffer type, and output state.
Table 2-69. GPIO Configuration Command
I2C
USB
Read
Write
0x44
0xC4
0x1A38
Table 2-70. GPIO Configuration Command Definition
BYTE
BITS
0
7:0
DESCRIPTION
GPIO selection. See Table 2-71 for description of available pins
RESET
TYPE
d0
wr
Output state
0
0 = Low
d0
wr
1 = High
1
1
2
7:3
0 – Configure pin as intput
1 – Configure pin as output
0 – Configure as normal mode
1 – Configure as open drain mode
Reserved
d0
wr
d0
wr
d0
r
Table 2-71. GPIO Selection
GPIO Selection
DLPC900 GPIO Pin
Function
Alternate Function
0
GPIO_PWM_0
GPIO
PWM Output
1
GPIO_PWM_1
GPIO
PWM Output
2
GPIO_PWM_2
GPIO
PWM Output
3
GPIO_PWM_3
GPIO
PWM Output
4
GPIO_4
GPIO
None
5
GPIO_5
GPIO
None
6
GPIO_6
GPIO
None
7
GPIO_7
GPIO
None
8
GPIO_8
GPIO
None
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GPIO Clock Configuration
DLPC900 supports one clock output capability. The OCLKA Clock Configuration command enables the
clock output functionality and sets the clock frequency.
Table 2-72. GPIO Clock Configuration Command
I2C
USB
Read
Write
0x48
0xC8
0x0807
Table 2-73. GPIO Clock Configuration Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
d0
wr
d0
r
x7F
wr
Clock Selection
0
0
0 = OCLKA
1 = Reserved
7:1
Reserved
Clock Functionality Disable
0
1
0 = Disable clock functionality on selected pin
1 = Enable clock functionality on selected pin
7:1
Reserved
Clock Divider. Allowed values in the range of 2 to 127. Output frequency =
100 MHz / (Clock Divider)
0x0 = Reserved
0x1 = Reserved
2
7:0
0x2 = 2
...
0x7F = 127
0xFF:0x80 = Reserved
2.3.7 Pulse Width Modulated (PWM) Control
DLPC900 provides four general-purpose PWM channels that can be used for a variety of control
applications, such as fan speed. If the PWM functionality is not needed, these signals can be programmed
as GPIO pins. To enable the PWM signals:
1. Program the PWM signal using the PWM Setup command.
2. Enable the PWM signal with the PWM Enable command.
2.3.7.1
PWM Setup
The PWM Setup command sets the clock period and duty cycle of the specified PWM channel. The PWM
frequency and duty cycle is derived from an internal 18.67 MHz clock. To calculate the desired PWM
period, divide the desired clock frequency from the internal 18.67 MHz clock. For example, a PWM
frequency of 2 kHz, requires a 18666667 / 2000 = 9333 or 0x2475.
Table 2-74. PWM Setup Command
2
IC
38
USB
Read
Write
0x41
0xC1
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Table 2-75. PWM Setup Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
PWM Channel Output Select
0 - PWM channel 0 (GPIO_PWM_0)
1:0
0
1 - PWM channel 1 (GPIO_PWM_1)
2 - PWM channel 2 (GPIO_PWM_2)
3 - PWM channel 3 (GPIO_PWM_3)
4:1
5
2.3.7.2
7:2
Reserved
d0
r
31:0
Clock Period in increments of 53.57 ns. Clock Period = (value + 1) × 53.5
ns
d0
wr
6:0
Duty Cycle = (value + 1)% Value range is 1% to 99%
d0
wr
Reserved
d0
r
7
PWM Enable
After the PWM Setup command configures the clock period and duty cycle, the PWM Enable command
activates the PWM signals.
Table 2-76. PWM Enable Command
I2C
USB
Read
Write
0x40
0xC0
0x1A10
Table 2-77. PWM Enable Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
d0
wr
PWM Channel Output Select
0 - PWM channel 0 (GPIO_PWM_0)
1:0
1 - PWM channel 1 (GPIO_PWM_1)
2 - PWM channel 2 (GPIO_PWM_2)
0
3 - PWM channel 3 (GPIO_PWM_3)
6:2
Reserved
PWM Channel Enable
7
0 - Disable selected PWM Channel
1 - Enable selected PWM Channel
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2.3.8 Batch File Commands
During power-up and initialization or during normal operation, the DLPC900 can be commanded to
execute a batch file containing a set of commands. The set of commands are created and saved in a text
file. The text file then becomes an additional part of the firmware and is uploaded into the flash memory.
The user can also specify a default batch file that the DLPC900 will execute during its power-up
sequence.
2.3.8.1
Batch File Name
This is a read command that returns the name of the given batch file index. This is useful for listing the set
of batch files available for the user to execute. To list all the batch file names, the user should iterate
through all numbers from 0 to n until an error is returned, which identifies the end of the list.
Table 2-78. Batch File Name Command
2
IC
USB
Read
0x1A14
0x3A
Table 2-79. Batch File Name Command Definition
2.3.8.2
BYTES
BITS
RESET
TYPE
0
7:0
Batch Command Index (Read parameter)
DESCRIPTION
d0
w
15:1
All
Batch Command Name String (Read result)
d0
r
RESET
TYPE
d0
w
Batch File Execute
This command executes all the commands in a given batch file at the given index.
Table 2-80. Batch File Execute Command
I2C
USB
Write
0x1A15
0xBB
Table 2-81. Batch File Execute Command Definition
2.3.8.3
BYTES
BITS
0
7:0
DESCRIPTION
Batch command index to be executed.
Batch File Delay
This command is useful for introducing the given amount of delay between batch commands within the
same batch file. This command by itself does not perform any action.
Table 2-82. Batch File Delay Command
I2C
USB
Write
0x1A16
0xBC
Table 2-83. Batch File Delay Command Definition
40
BYTES
BITS
3:0
31:0
DLPC900 Control Commands
DESCRIPTION
Delay to be introduced in milliseconds
RESET
TYPE
d0
w
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2.3.8.4
Batch File Example
The following table shows an example of a batch file. Only command descriptors with parameters are
allowed in the batch file.
Table 2-84. Batch File Example
COMMAND DESCRIPTOR
PARAMETERS
DESCRIPTION
VIDEO_CONT_SEL
0x01
Power on the IT6535 for HDMI input.
DELAY
0xC8
Delay 200 ms.
CHANNEL_SWAP
0x04
Select input data channel swap to ABC = BAC
FLIP_LONG
0x01
Flip the image on long axis.
When saving the batch file to a text file, only save the command descriptor and the parameters as shown
below with a colon after the command descriptor and space delimited. See Appendix B for a list of the
supported command descriptors. Once the batch file has been created and saved as a text file, see the
DLP LightCrafter 6500 & 9000 EVM User's Guide on how to add batch files to the firmware.
VIDEO_CONT_SEL:
DELAY:
CHANNEL_SWAP:
FLIP_LONG:
2.4
0x01
0xC8
0x04
0x01
Display Mode Commands
The DLPC900 display consists of several parameters which dictate the loading of the DMD and the control
of PWM to the LEDs. The DLPC900 supports four main display modes:
• Video mode
• Video Pattern mode
• Pre-Stored Pattern mode
• Pattern On-The-Fly mode
The Display Mode Selection command (Section 2.4.1) selects between these modes.
In Video mode, the DLPC900 30-bit RGB interface supports up to 1080p at 120 Hz with a DLP6500 and
WQXGA at 120 Hz with a DLP9000. The DLPC900 processes the digital input image and converts the
data into the appropriate format for the DLP6500 or the DLP9000 DMDs.
The DLPC900 offers scaling and cropping functions to appropriately display resolutions from SVGA to
1080p on a DLP6500.
The DLPC900 combined with a DLP9000 does not support scaling or cropping functions.
In the latter three modes, the DLPC900 provides high-speed pattern rates. These modes support only 24bit data input through the DLPC900 RGB interface, from flash memory, or dynamically loaded using
Pattern On-The-Fly modes. These modes are well-suited for techniques such as structured light, additive
manufacturing, or digital exposure. The DLPC900 also has the capability to display a set of patterns and
signal a camera to capture when these patterns are displayed. Figure 2-4 shows the DLPC900/DLP6500
block diagram and the main functional blocks for the four display modes. Table 2-85 lists the allowed
pattern combinations of bit-depth, number of patterns, and maximum pattern speed.
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USB_DN,DP
I2C
LED EN[2:0]
LED PWM[2:0]
I2C_SCL0, I2C_SDA0
P1_A[9:0]
Digital Receiver
P1_B[9:0]
P1_C[9:0]
HDMI
HDMI
DP
PWM
P1A_CLK, P1_DATEN,
P1_VSYNC, P1_HSYNC
TRIG_OUT[1:0]
Camera
TRIG_IN[1:0]
Processor
Crystal
DMD_A,B[15:0]
DMD Control
DMD SSP
POWER RAILS
PWRGOOD
POSENSE
MOSC
JTAG
LEDs
DLPC900
DISPLAYPORT
GUI
RAM
FAN
LED
Status
LED Driver
USB
HEARTBEAT
FAULT_STATUS
PM_ADDR[22:0],WE
DATA[15:0],OE,CS
TDO[1:0],TRST,TCK
RMS[1:0],RTCK
Flex
Parallel
Flash
Host
I2C_SCL1
I2C_SDA1
DLP6500
Power
Management
I2C
VCC
12V DC IN
Figure 2-4. DLPC900 System Block Diagram
Table 2-85. Allowed Pattern Display Combinations
BIT-DEPTH
MAXIMUM EXTERNAL
INPUT PATTERN RATE
FOR VIDEO PATTERN
MODE
(Hz)
MAXIMUM PATTERN
RATE FOR PRE-LOADED
PATTERNS WITH
INTERNAL TRIGGER
(Hz)
MAXIMUM PATTERN
RATE FOR PRE-LOADED
PATTERNS WITH
EXTERNAL TRIGGER
(Hz) (1)
MAXIMUM NUMBER OF
PATTERNS FOR PRELOADED PATTERNS (2)
1
2880
9523
8333
400
2
1440
3289
3125
200
3
960
2544
2380
133
4
720
1215
1190
100
5
480
823
813
80
6
480
672
664
66
7
360
500
496
57
8
247
247 (3)
246 (3)
50
(1)
(2)
(3)
The reduction in pattern rates are due to interrupt processing and sequence setup time from the time the external interrupt
occurs.
Numbers are based on compressed patterns.
These are the maximum 8-bit pattern rates using illumination sequences built into the DLPC900 controller. The faster pattern
rates shown in the DMD data sheets (see Related Documents from Texas Instruments) can be achieved using eight 1-bit
patterns and a user defined solid state illumination sequence to create an 8-bit grayscale image.
In Video mode, the DLPC900 operates on a per-frame basis where it takes the input data and
appropriately allocates it in a frame. For example, a 24-bit RGB input image is allocated into a 60-Hz
frame by dividing each color (red, green, and blue) into specific percentages of the frame. Therefore, for a
40% red, 45% green, and 15% blue ratio, the red, green, and blue colors would have a 6.67-, 7.5-, and
2.54-ms time slot allocated, respectively. Because each color has an 8-bit depth, each color time slot is
further divided into bit-planes, as shown in Figure 2-5. A bit-plane is the two-dimensional arrangement of
one bit extracted from all the pixels in the full color 2D image.
42
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Figure 2-5. Bit-Planes of a 24-Bit RGB Image
The length of each bit-plane in the time slot is weighted by the corresponding power of two of its binary
representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB
input has three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the
sum of the weight of all bit planes in the time slot equal to 256. See Figure 2-6 for an illustration of this
partition of the bits in a frame.
Figure 2-6. Bit Partition in a Frame for an 8-Bit Monochrome Image
Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be
either on or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane.
With binary pulsewidth modulation, the intensity level of the color is reproduced by controlling the amount
of time the mirror is on. For a 24-bit RGB frame image inputted to the DLPC900 controller, the DLPC900
controller creates 24 bit-planes, stores them in internal embedded DRAM, and sends them to the DMD,
one bitplane at a time. The bit weight controls the illumination intensity of the bit-plane where smaller the
bit weight is the less intense the bit-plane becomes. To improve image quality in video frames, these bitplanes, time slots, and color frames are shuffled and interleaved within the pixel processing functions of
the DLPC900 controller.
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For other applications where one-to-one pixel mapping to the DMD micromirror is required, the scaling,
cropping, and pixel processing functions are disabled and a specific set of patterns is used. The bit-depth
of the pattern is then allocated into the corresponding binary weighted time slots. Furthermore, output
trigger signals are also synchronized with these time slots to indicate when the image is displayed. For
structured light applications, this mechanism provides the capability to display a set of patterns and signal
a camera to capture these patterns overlaid on an object.
2.4.1 Display Mode Selection
The Display Mode Selection command switches the internal image processing functions of the DLPC900
to operate in the mode selected. After executing this command, the host may poll the system status using
I2C commands: 0x20, 0x21, and 0x22 or the respective USB commands: 0x1A0A, 0x1A0B, and 0x1A0C.
Table 2-86. Display Mode Selection Command
I2C
USB
Read
Write
0x69
0xE9
0x1A1B
Table 2-87. Display Mode Selection Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d1
wr
d0
r
0 = Video mode
0
1:0
1 = Pre-stored pattern mode (Images from flash)
2 = Video pattern mode
3 = Pattern On-The-Fly mode (Images loaded through USB/I2C)
7:2
44
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2.4.1.1
Video Mode Resolution
When Display Mode is set to Video Mode, Table 2-88 shows the resolutions supported by the DLPC900
when combined with a DLP6500 or a DLP9000.
Table 2-88. Resolution Supported
2.4.1.2
DLP LIGHTCRAFTER
RESOLUTION
6500
Standard Video Sources from
SVGA to 1080p
MAX RATE (Hz)
120
See DLPC900 data sheet for reduced blanking
requirements for 1080p at 120 Hz
NOTES
9000
WQXGA
120
See DLPC900 data sheet under Two Controller
Considerations.
Input Display Resolution
The Input Display Resolution command defines the active input resolution and active output (displayed)
resolution. This command provides the option to define a subset of active input frame data using pixel
(column) and line (row) counts relative to the source-data enable signal (DATEN). In other words, this
feature allows the source image to be cropped as the first step in the processing chain. After executing
this command, the host may poll the system status using I2C commands: 0x20, 0x21, and 0x22, or the
respective USB commands: 0x1A0A, 0x1A0B, and 0x1A0C. This command is not supported when
DLPC900 is combined with a DLP9000 DMD.
Table 2-89. Input Display Resolution Command
I2C
USB
Read
Write
0x7E
0xFE
0x1000
Table 2-90. Input Display Resolution Command Definition
BYTE
BITS
DESCRIPTION
RESET
1:0
15:0
Input image, first active pixel (column) of cropped area
d0
3:2
15:0
Input image, first active line (row) of cropped area
d0
5:4
15:0
Input image vertical resolution, pixels (columns) per line (row) of cropped
area
d0
7:6
15:0
Input image horizontal resolution, lines (rows) per frame of cropped area
d0
9:8
15:0
Output image, first active pixel (column) of displayed image
d0
11:10
15:0
Output image, first active line (row) of displayed image
d0
13:12
15:0
Output image horizontal resolution, pixels (columns) per line (row)
d
(1)
15:14
15:0
Output image vertical resolution, lines (rows) per frame
d
(2)
TYPE
wr
(1) Maximum 1920 or 1280.
(2) Maximum 1080 or 1600.
2.4.1.3
DMD Block Load
The DMD Block Load command allows the user to specify which of the DMD blocks are active. Only
adjacent blocks are allowed. Mirrors in blocks that are not active will be set to their off state prior to the
pattern sequence running. Selecting a reduced number of active DMD blocks allows for an increase in
pattern speeds. See Table 2-93.
Block Load is only applicable for 1-bit depth patterns. The entire 1-bit pattern data must be sent to the
controller when using video pattern mode, pattern on the fly, or pre-stored pattern mode. The controller
loads the selected block(s) based on the rows selected in Block Load.
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NOTE: The performance of mirrors in blocks that are not active will be affected by prolonged use of
being in the off state. To optimize the mirrors, DMD Idle Mode should be enabled as often as
possible. This mode will provide a 50/50 duty cycle across the entire DMD mirror array,
where the mirrors are continuously flipped between the on and off states. See command in
Section 2.4.1.4.
Table 2-91. DMD Block Load Command
I2C
USB
Read
Write
0x60
0xE0
0x1A40
Table 2-92. DMD Block Load Command Definition
BYTE
BITS
0
1
DESCRIPTION
(1)
RESET
TYPE
4:0
Start block. Range (0 - 0x0E on DLP6500) or (0 - 0xF on DLP9000)
0
wr
7:5
Reserved
0
r
4:0
Number of blocks. Range (0x1 - 0x0F on DLP6500) or (0x1 - 0x10 on
DLP9000)
0xF or
0x10
wr
7:5
Reserved
0
r
(1) When short and long axes are disabled, block 0 begins at pixel (0,0) on the DMD.
Table 2-93. DMD Block Load Minimum Exposure Times
NUMBER OF DMD ACTIVE
BLOCKS
DLP6500 (µs) (1)
DLP9000 (µs) (2)
1
24
24
2
45
42
3
45
42
4
45
42
5
48
45
6
54
51
7
60
56
8
66
61
9
72
67
10
78
72
11
84
77
12
90
83
13
96
88
14
101
93
15
105
99
16
N/A
105
(1) Each block contains 72 rows.
(2) Each block contains 100 rows.
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Table 2-94. Minimum Exposure in Any Pattern Modes
(1)
(1)
BIT DEPTH
DLP6500 (µs)
DLP9000 (µs)
1
105
105
2
304
304
3
394
380
4
823
733
5
1215
1215
6
1487
1487
7
1998
1998
8
4046
4046
The maximum pattern rate for pre-loaded patterns with external trigger will be slightly less than the listed values for pre-loaded patterns
with internal trigger
2.4.1.4
DMD Idle Mode
It is strongly recommended that anytime the DMD is idle and not actively projecting data that the DMD Idle
Mode be enabled to assist in maximizing DMD lifetime. This mode enables a 50/50 duty cycle pattern
sequence, where the entire mirror array is continuously flipped approximately every 105 μs between the
on and off states. Whenever this mode is enabled, the LED Enable outputs are disabled to prevent
illumination on the DMD. When operating with a subset of DMD blocks, this mode should be enabled as
often as possible. For example, whenever the system is idle, between exposures if the application allows
for it, or when the exposure pattern sequence is stopped. To enable this mode, the pattern sequences
must first be stopped. To restart the pattern sequence, this mode must be disabled. This mode can be
enabled in any operating mode except for Video Mode. This mode can also be enabled to optimize the
mirrors that experience prolonged use of being in the on or off states when all DMD blocks are active.
Table 2-95. DMD Idle Mode Command
I2C
USB
Read
Write
0x0D
0x8D
0x0201
Table 2-96. DMD Idle Mode Command Definition
BYTE
0
BITS
0
7:1
RESET
TYPE
0 - Idle mode disabled
1 - Idle mode enabled
DESCRIPTION
d0
wr
Reserved
0
r
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2.4.2 Image Header
The image data should be preceded by the image header (48 Bytes) shown in Table 2-97.
Table 2-97. Image Header
NUMBER OF BYTES
DESCRIPTION
4
Signature (should be 53 70 6C 64)
2
Image width
2
Image height
4
Number of bytes in the encoded image data
8
Reserved (should be FF FF FF FF FF FF FF FF)
4
Background color (BB GG RR 00)
1
Reserved (should be 00)
1
Compression
0 – Uncompressed
1 – RLE compression
2 – Enhanced RLE compression
1
Reserved (should be 01)
21
Reserved (should be 00…)
2.4.3 Pattern Image Compression
In order to minimize Flash storage requirements, it is recommended (but not required) that pattern images
be stored in a compressed format. The compression format supported by the DLPC900 is a subset of
BMP Run-Length Encoding (RLE). The DLPC900 is able to perform the decompression of pattern images
as they are loaded from external flash or when using Pattern On-The-Fly mode to its internal memory. The
DLPC900 can also perform no decompression if the images are not compressed.
For most efficient storage and compression of images, stored images should be packed into groups of 24bit RGB bitmap images.
NOTE: Compressed images must be stored right side up instead of upside down as in standard
BMP format images.
NOTE: With RLE, there is always a question of whether or not the compressed image will be larger
or smaller than the uncompressed image. The method to decide which to choose from is left
up to the programmer.
2.4.3.1
Run-Length Encoding
Table 2-98 defines the RLE Control Bytes recognized by the DLPC900. The DLPC900 firmware
automatically decompresses the image when operating in Pre-Stored Pattern Mode or Pattern On-The-Fly
Mode.
Table 2-98. RLE Control Bytes
48
CONTROL BYTE (n)
COLOR BYTE (c)
0
0
End-of-Line
0
1
End-of-Image (required)
0
>= 2
n>0
n/a
DLPC900 Control Commands
RESULT
Uncompressed. The next c pixels are uncompressed
Repeat; Repeat the next RGB pixel (or the next dual y/c pixel
pair) n times
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2.4.3.1.1 RLE Compression Example
Table 2-99 shows the hexadecimal values of a 2-line packed 24-bit compressed bitmap. The compressed
data on the left is stored sequentially in Flash memory. The DLPC900 firmware automatically expands the
data as shown on the right which is stored in internal memory.
Table 2-99. RLE Compression Example
COMPRESSED DATA (HEX)
2.4.3.2
EXPANDED DATA (HEX)
03 040506
040506 040506 040506
05 777777
777777 777777 777777 777777 777777
00 03 040506 070809 0A0B0C
040506 070809 0A0B0C
02 789ABC
789ABC 789ABC
00 00
(End-of-Line Command)
00 00 00
00 00 00 00 00 00 00 00 00 (End-of-Line Padding)
07 1D1E1F
1D1E1F 1D1E1F 1D1E1F 1D1E1F 1D1E1F 1D1E1F 1D1E1F
06 212223
212223 212223 212223 212223 212223 212223
00 01
(End-of-File command)
00 01 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 (End-of-Image Padding)
Enhanced Run-Length Encoding
To achieve higher compression ratios, this compression format takes advantage of the similarities from
line-to-line and uses one or two bytes to encode the length. Table 2-100 defines the RLE Control Bytes
recognized by the DLPC900. The DLPC900 firmware automatically decompresses the image when
operating in Pre-Stored Pattern Mode or Pattern On-The-Fly Mode.
Table 2-100. Enhanced RLE Control Bytes
CONTROL BYTE 1
CONTROL BYTE 2
CONTROL BYTE 3
0
0
n/a
RESULT
0
1
n
0
n>1
n/a
n uncompressed sequence of pixels
n>1
n/a
n/a
Repeat following pixel n times
End of Image
Copy n pixels from previous line
If n is < 128 then encode it with 1 byte.
If n is >= 128 then encode it with 2 bytes in the following manner:
• Byte0 = ( n & 0x7F ) | 0x80
• Byte1 = ( n >> 7)
• Example: Number 0x1234 is encoded as 0xB4, 0x24
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2.4.3.2.1 Enhanced RLE Compression Example
Table 2-101 shows an example of this RLE compression.
Table 2-101. Enhanced RLE Compression Example
COMPRESSED DATA (HEX)
EXPANDED DATA (HEX)
03 040506
040506 040506 040506
05 777777
777777 777777 777777 777777 777777
00 03 040506 070809 0A0B0C
040506 070809 0A0B0C
82 01 789ABC
789ABC 789ABC … (513 times)
00 00
(End of line) (1)
01 010203
010203
00 01 09
040506 040506 777777 777777 777777 777777 777777 040506 070809
00 01 00
(End-of-Image Padding)
(1) End-of-Line Command and End-of-Line Padding is optional for this RLE compression.
NOTE: All padding should end on a 4 byte boundary.
2.4.4 Pattern Display Commands
In pattern display modes 0, 2, and 3, the DLPC900 supports 1-, 2-, 3-, 4-, 5-, 6-, 7-, and 8-bit images with
a 1080p or WQXGA pixel resolution streamed through the 24-bit RGB parallel interface, pre-stored
patterns in the flash memory, or dynamically with Pattern On-The-Fly. The following commands are only
supported in display modes 1, 2, and 3:
•
•
•
•
Trigger Commands
LED Enable Delay Commands
Pattern Display Commands
Pattern On-The-Fly Commands
NOTE:
2.4.4.1
If the pattern display is already active, it must be stopped using I2C command 0x65 or USB
0x1A24 before calling these commands.
Trigger Commands
To synchronize a camera with the displayed patterns, the DLPC900 supports three pattern modes:
• Video Pattern Mode (applicable when pattern data from RGB parallel port):
– VSYNC used as trigger input.
– TRIG_OUT1 frames the exposure time of the pattern.
– TRIG_OUT2 : marks the beginning of each pattern start with 20-µs pulse. This can be selectively
disabled for individual patterns.
• Pre-Stored Pattern Mode (applicable for pattern data from flash):
– TRIG_IN1 advances to next pattern, while TRIG_IN2 starts and pauses the pattern sequence.
– TRIG_OUT1 frames the exposure time of the pattern.
– TRIG_OUT2 : marks the beginning of each pattern start with 20-µs pulse. This can be selectively
disabled for individual patterns.
• Pattern On-The-Fly Mode (patterns downloaded over USB/I2C)
– Triggers are the same as Pre-Stored Pattern Mode
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Figure 2-7 shows an example in video pattern mode. The VSYNC starts the pattern sequence display.
The pattern sequence consists of a series of four patterns followed by a series of three patterns and then
repeats. The first pattern sequence consists of P1, P2, P3, and P4. The second pattern sequence consists
of P5, P6, and P7. TRIG_OUT_1 frames each pattern exposed while TRIG_OUT_2 is user programmable
and in this example, indicates the start of each pattern in the sequence. If the pattern sequence is
configured without dark time between patterns, then the TRIG_OUT_1 output would be high enough for
the entire pattern sequence. This example uses internal triggering, so TRIG_IN signals are not used.
Figure 2-7. Video Pattern Mode Timing Diagram Example
Figure 2-8 shows an example in pre-stored pattern mode. Pattern sequences of four are displayed.
TRIG_OUT_1 frames each pattern exposed, while TRIG_OUT_2 is user programmable and in this
example, indicates the start of each pattern in the sequence. If the pattern sequence is configured without
dark time between patterns, then the TRIG_OUT_1 output would be high for the entire pattern sequence.
This example uses internal triggering, so TRIG_IN signals are not used.
Figure 2-8. Pre-Stored Pattern Mode Timing Diagram Example
2.4.4.1.1 Trigger Out1
The Trigger Out1 command sets the polarity, rising edge delay, and falling edge delay of the
TRIG_OUT_1 signal. The delays are compared to when the pattern is displayed on the DMD. Before
executing this command, stop the current pattern sequence.
Table 2-102. Trigger Out1 Command
I2C
USB
Read
Write
0x6A
0xEA
0x1A1D
Table 2-103. Trigger Out1 Command Definition
BYTE
0
BITS
0
DESCRIPTION
0 = Non inverted trigger output
(3)
RESET
TYPE
d0
wr
(1)
1 = Inverted trigger output (2)
7:1
Reserved
d0
r
2:1
15:0
Trigger output Raising Edge delay in micro seconds (int16 number) Valid
Range : -20 to 20000 (4)
d0
wr
4:3
15:0
Trigger output Falling Edge delay in micro seconds (int16 number) Valid
Range : -20 to 20000 (4)
d0
wr
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(1) When non inverted output is selected, the rising edge must be less than or equal to the falling edge.
(2) When inverted output is selected, the rising edge must be greater than or equal to the falling edge.
(3) Minimum pulse width is 20 µs.
(4) The minimum delay is affected when the number of active blocks is reduced. The formula to calculate the minimum delay
is: –(min_exposure – 5) µs. See Table 2-93 for the min_exposure for the number of active DMD blocks.
2.4.4.1.2 Trigger Out2
The Trigger Out2 Control command sets the polarity and rising edge delay of the TRIG_OUT_2 signal.
The delay is compared to when the pattern is displayed on the DMD. Before executing this command,
stop the current pattern sequence.
Table 2-104. Trigger Out2 Command
I2C
USB
Read
Write
0x6B
0xEB
0x1A1E
Table 2-105. Trigger Out2 Command Definition
BYTE
BITS
0
0
DESCRIPTION
0 = Non inverted trigger output
(3)
RESET
TYPE
d0
wr
(1)
1 = Inverted trigger output (2)
7:1
Reserved
d0
r
2:1
15:0
Trigger output Raising Edge delay in micro seconds (int16 number) Valid
Range : -20 to 20000 (4)
d0
wr
4:3
15:0
Trigger output Falling Edge delay in micro seconds (int16 number) Valid
Range : -20 to 20000 (4)
d0
wr
(1) When non inverted output is selected, the rising edge must be less than the falling edge.
(2) When inverted output is selected, the rising edge must be greater than the falling edge.
(3) Minimum pulse width is 20 µs.
(4) The minimum delay is affected when the number of active blocks is reduced. The formula to calculate the minimum delay
is: –(min_exposure – 5) µs. See Table 2-93 for the min_exposure for the number of active DMD blocks.
2.4.4.1.3 Trigger In1
The Trigger In1 command sets the rising edge delay of the TRIG_IN_1 signal compared to when the
pattern is displayed on the DMD. The polarity of TRIG_IN_1 is set in the lookup table of the pattern
sequence. Before executing this command, stop the current pattern sequence.
Table 2-106. Trigger In1 Command
2
IC
USB
Read
Write
0x79
0xF9
0x1A35
Table 2-107. Trigger In1 Command Definition
BYTE
BITS
1:0
15:0
2
0
7:1
52
DLPC900 Control Commands
DESCRIPTION
RESET
TYPE
d105
wr
0 – Pattern advances on rising edge
1 – Pattern advances on falling edge
d0
wr
Reserved
d0
r
Trigger 1 delay in micro seconds. This is the time after which the pattern is
displayed from trigger active edge.
A minimum delay of 104 µs is required by the HW
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2.4.4.1.4 Trigger In2
In Video Pattern and Pre-Stored Pattern modes, the TRIG_IN_2 acts as a start or stop signal. If the
sequence was not already started by a software command, the rising edge on the TRIG_IN_2 signal input
will start or resume the pattern sequence. If the pattern sequence is active, the falling edge on the
TRIG_IN_2 signal input stops the pattern sequence. Before executing this command, stop the current
pattern sequence.
Table 2-108. Trigger In2 Command
I2C
USB
Read
Write
0x7A
0xFA
0x1A36
Table 2-109. Trigger In2 Command Definition
BYTE
BITS
0
0
7:1
2.4.4.2
DESCRIPTION
0 – Pattern started on rising edge stopped on falling edge
1 – Pattern started on falling edge stopped on rising edge
Reserved
RESET
TYPE
d0
wr
d0
r
LED Enable Delay Commands
The LED Enable Delay commands set the rising and falling edge offsets of the LED enable signals
compared to when the pattern is displayed on the DMD. This command is only for Pattern Display mode.
When in a video mode, these delays should be set to 0x0.
2.4.4.2.1 Red LED Enable
The Red LED Enable Delay command sets the rising and falling edge delay of the Red LED enable signal.
Table 2-110. Red LED Enable Command
2
IC
USB
Read
Write
0x6C
0xEC
0x1A1F
Table 2-111. Red LED Enable Command Definition
BYTE
BITS
DESCRIPTION
(1)
1:0
15:0
LED Enable Raising Edge delay in micro seconds (int16 number)
Valid Range : -20 to 20000
3:2
15:0
LED Enable Falling Edge delay in micro seconds (int16 number)
Valid Range : -20 to 20000
RESET
TYPE
d0
wr
d0
wr
(1) The minimum delay is affected when the number of active blocks is reduced. The formula to calculate the minimum delay
is: –(min_exposure – 5) µs. See Table 2-93 for the min_exposure for the number of active DMD blocks.
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2.4.4.2.2 Green LED Enable
The Green LED Enable Delay command sets the rising and falling edge delay of the Green LED enable
signal.
Table 2-112. Green LED Enable Command
I2C
USB
Read
Write
0x6D
0xED
0x1A20
Table 2-113. Green LED Enable Command Definition
BYTE
BITS
DESCRIPTION
(1)
1:0
15:0
LED Enable Raising Edge delay in micro seconds (int16 number)
Valid Range : -20 to 20000
3:2
15:0
LED Enable Falling Edge delay in micro seconds (int16 number)
Valid Range : -20 to 20000
RESET
TYPE
d0
wr
d0
wr
(1) The minimum delay is affected when the number of active blocks is reduced. The formula to calculate the minimum delay
is: –(min_exposure – 5) µs. See Table 2-93 for the min_exposure for the number of active DMD blocks.
2.4.4.2.3 Blue LED Enable
The Blue LED Enable Delay command sets the rising and falling edge delay of the Blue LED enable
signal.
Table 2-114. Blue LED Enable Command
I2C
USB
Read
Write
0x6E
0xEE
0x1A21
Table 2-115. Blue LED Enable Command Definition
BYTE
BITS
DESCRIPTION
(1)
1:0
15:0
LED Enable Raising Edge delay in micro seconds (int16 number)
Valid Range : -20 to 20000
3:2
15:0
LED Enable Falling Edge delay in micro seconds (int16 number)
Valid Range : -20 to 20000
RESET
TYPE
d0
wr
d0
wr
(1) The minimum delay is affected when the number of active blocks is reduced. The formula to calculate the minimum delay
is: –(min_exposure – 5) µs. See Table 2-93 for the min_exposure for the number of active DMD blocks.
2.4.4.3
Pattern Display Commands
2.4.4.3.1 Pattern Display Start/Stop
The Pattern Display Start/Stop command starts or stops the programmed pattern sequence. After
executing this command, the host may poll the system status using I2C commands: 0x20, 0x21, and 0x22
or the respective USB commands: 0x1A0A, 0x1A0B, and 0x1A0C.
Table 2-116. Pattern Display Start/Stop Command
I2C
54
USB
Read
Write
0x65
0xE5
DLPC900 Control Commands
0x1A24
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Table 2-117. Pattern Display Start/Stop Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
0 = Stop Pattern Display Sequence. The next Start command will restart the
pattern sequence from the beginning.
1 = Pause Pattern Display Sequence. The next Start command will start the
pattern sequence by re-displaying the current pattern in the sequence.
1:0
0
2 = Start Pattern Display Sequence
3 = Reserved
7:2
Reserved
2.4.4.3.2 Pattern Display Invert Data
The Pattern Display Invert Data command dictates how the DLPC900 interprets a value of 0 or 1 to
control mirror position for displayed patterns. Before executing this command, stop the current pattern
sequence. Once the command has been sent to the DLPC900, the Pattern Display LUT Definition for all
the patterns must be re-sent to the DLPC900.
Table 2-118. Pattern Display Invert Data Command
2
IC
USB
Read
Write
0x74
0xF4
0x1A30
Table 2-119. Pattern Display Invert Data Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
r
Pattern Display Invert Data
0
0
0 = Normal operation. A data value of 1 will flip the mirror to output light,
while a data value of 0 will flip the mirror to block light
1 = Inverted operation. A data value of 0 will flip the mirror to output light,
while a data value of 1 will flip the mirror to block light
7:1
Reserved
2.4.4.3.3 Pattern Display LUT Configuration
The Pattern Display LUT Configuration command controls the execution of patterns stored in the lookup
table (LUT). Before executing this command, stop the current pattern sequence.
This command should be issued after any Pattern Display LUT Definition command has been issued.
NOTES:
• This command makes all Pattern Display LUT Definition data effective and sets the Pattern Display
LUT default order which will display all patterns in the DLPC900 pattern memory in the order they are
defined by the pattern index in Pattern Display LUT Definition.
• When this command is executed any pattern that precedes a pattern with an input trigger in the Pattern
Display LUT Definition, will have a black pattern loaded at the end. This causes the system to display a
darkness until the trigger is received to start the triggered pattern. If the triggered pattern is the very
first pattern in the Pattern Display LUT Definition then the very last pattern in the in the Pattern Display
LUT Definition will be treated as the pattern preceding it.
Table 2-120. Pattern Display LUT Configuration Command
2
IC
USB
Read
Write
0x75
0xF5
0x1A31
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Table 2-121. Pattern Display LUT Configuration Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
d0
wr
Number of LUT entries (range 1 through 400)
1 = One entry
10:0
1:0
2 = Two entries
...
512 = 512 entries
15:11
Reserved
31:0
Number of times to repeat the pattern sequence
5:2
2.4.4.3.4 Pattern Display LUT Reorder Configuration
The Pattern Display LUT Reorder Configuration command reorders the lookup table (Pattern Display LUT)
so that the patterns stored in memory will display in the order defined by this command. Before executing
this command, stop the current pattern sequence. This command is only applicable in Pre-stored Pattern
Mode and Pattern On-The-Fly Mode.
Patterns can be referenced in any order and can be repeated in the Pattern Display LUT. Moreover, a
subset of patterns stored in the DLPC900 pattern memory can be referenced.
NOTES:
• The default display order must be set by issuing a Pattern Display LUT Configuration command before
this command can be used.
• The pattern index numbers used must be less than or equal to the number of entries -1 defined by the
Pattern Display LUT Configuration command.
• The Pattern index number must be less than or equal to the number of entries -1 defined in the Pattern
Display LUT Configuration command.
Table 2-122. Pattern Display LUT Reorder Configuration Command
I2C
USB
Read
Write
0x1A32
0x76
Table 2-123. Pattern Display LUT Reorder Configuration Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
wr
Number of LUT entries (range 1 through 512)
1 = One entry
1:0
10:0
2 = Two entries
…
512 = 512 entries
5:2
31:0
Number of times to repeat the pattern sequence
d0
wr
7:6
15:0
Pattern index number to be displayed first
d0
wr
9:8
15:0
Pattern index number to be displayed second
d0
wr
…
…
d0
wr
…
Pattern index number to be displayed in Nth position
…
15:0
NOTE: N = number of LUT entries (BYTE 1:0)
NOTE: the Pattern index to be displayed must be <= number of entries - 1
defined in 0x1A31
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Input Trigger considerations:
Patterns with input triggers, as defined by the Pattern Display LUT Definition commands, are attached to
the pattern. Therefore the system will wait for a trigger whenever the pattern index number is referenced in
the re-ordered Display Pattern LUT. Moreover, the pattern that originally preceded the triggered pattern in
the default Display Pattern LUT order will display 105 µs of dark time at the end of it regardless of where it
appears in the re-ordered Display Pattern LUT. In addition, if a pattern that was not preceding the
triggered pattern in the default Display Pattern LUT order is placed immediately in front of the triggered
pattern, the last bit pattern of that pattern will display until the trigger is received.
There are several methods that can be employed to manage this behavior:
•
•
•
Consider the triggered pattern and the pattern preceding it in the default Display Pattern LUT order as
a set that must be kept together.
Add a 1-bit all-black pattern with the shortest duration allowed (105 μs) preceding the triggered pattern
in the default Display Pattern LUT order. Now consider these patterns as a set that must be kept
together.
Add a 1-bit all-black pattern with the shortest duration allowed (105 μs) followed by a triggered 1-bit allblack pattern (also 105 μs duration), and remove the trigger from the pattern originally to be triggered
in the default Display Pattern LUT order. These two patterns will now be a versatile trigger set that can
be used repeatedly wherever a trigger is desired. Since the triggered pattern is black, even if your
exposure integration begins with the triggered black pattern there will be no additonal light contributing
to your exposure.
2.4.4.3.5 Pattern Display LUT Definition
The Pattern Display LUT Definition contains the definition of each pattern to be displayed during the
pattern sequence. Display Mode must be set before sending any pattern LUT definition data. If the
Pattern Display Data Input Source is set to streaming, the image indexes do not need to be set.
After any Pattern Display LUT Definition command is issued a Pattern Display LUT Configuration
command must be issued. Regardless of the input source, the pattern definition must be set.
NOTES:
• Pattern definition data can be changed using this command without reloading pattern data into the
DLPC900 pattern memory.
• It is possible to use Pattern Display LUT Definition commands to change the pattern definitions for
some or all of the patterns in a previously set default Display Pattern LUT . Only those pattern indices
that are to be changed need to entered. (For the changes to take effect a Pattern Display LUT
Configuration command must again be issued.)
Table 2-124. Pattern Display LUT Definition Command
I2C
USB
Write
0x1A34
0xF8
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Table 2-125. Pattern Display LUT Definition Command Definition
BYTE
BITS
1:0
15:0
Pattern Index (range 0 through 511)
23:0
Pattern exposure in micro seconds
31:24
Reserved
4:2
0
DESCRIPTION
RESET
TYPE
w
Clear the pattern after exposure. This is only applicable for 1 bit patterns
with an external trigger. For other patterns, the clear is automatically
handled.
w
Select desired bit-depth
b000 = 1 bit
3:1
b001 = 2 bit
w
b010 = 3 bit
...
b111 = 8 bit
5
6:4
7
8:6
9
d0
w
1 = Wait for trigger before displaying the pattern
0 = Continue running after previous pattern
23:0
Dark display time following the exposure (in micro seconds)
31:24
Reserved
w
1 = Disable trigger 2 output for this pattern
0 = Enable trigger 2 output for this pattern
w
7:1
Reserved
w
10:0
Image pattern index (Not applicable in video pattern mode) Valid Range 0255
w
15:11
Bit position in the image pattern (Frame in video pattern mode) Valid range
0-23
w
0
11:10
2.4.4.4
b000 = All LEDs disabled
b001 = Red
b010 = Green
b011 = Yellow (Green + Red)
b100 = Blue
b101 = Magenta (Blue + Red)
b110 = Cyan (Blue + Green)
b111 = White (Blue + Green + Red)
Pattern On-The-Fly Commands
These commands allow the user to dynamically upload the pattern images over the I2C or USB interface
and store them directly into internal memory. The user can preview the pattern sequence to verify that the
patterns and the pattern sequence are correct before actually writing the patterns to the flash. These
commands should be used only in Pattern On-The-Fly mode and requires Display Mode to be set before
sending any pattern LUT definition data. After any Pattern Display LUT Definition command is
issued a Pattern Display LUT Configuration command must be issued. Section 5.3 shows a Pattern
On-The-Fly example.
2.4.4.4.1 Initialize Pattern BMP Load
When the Initialize Pattern BMP Load command is issued, the patterns in the flash are not used until the
pattern mode is disabled by command. This command should be followed by the Pattern BMP Load
command to load the images. The images should be loaded in the reverse order. Suppose there are 3
images 0,1 and 2 then the order for loading the image is 2, 1 and 0. When the DLPC900 is combined
with a DLP9000 DMD, the user must perform the same operation on both the master and slave
controllers by choosing the appropriate command in the command table.
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Table 2-126. Initialize Pattern BMP Load Command
I2C
Controller
USB
Read
Write
Master
0x2A
0xAA
0x1A2A
Slave
0x2C
0xAC
0x1A2C
Table 2-127. Initialize Pattern BMP Load Command Definition
BYTE
1:0
5:2
BITS
DESCRIPTION
4:0
Image Index (0 – 17). In 24 bit format.
This be referred in LUT command.
Always load the images in reverse order.
15:5
Reserved
31:0
Number of bytes in the compressed image including the 48 byte header
RESET
TYPE
d0
wr
d0
wr
2.4.4.4.2 Pattern BMP Load
This command is used for updating the pattern images on-the-fly. This loads the full compressed 24 bit
BMP images into the internal memory of the DLPC900. This command is issued after the Init pattern BMP
command and multiple times until all the bytes are sent. Images should be compressed using Run-Length
Encoding (RLE). See Section 2.4.3 for a description of the compression formats. When the DLPC900 is
combined with a DLP9000 DMD, the user must load the images to both the master and slave
controllers by choosing the appropriate command in the command table. The full WQXGA image
must be divided in half where the master controller gets the left half and the slave controller gets
the right half.
NOTE: The images must be re-downloaded to the DLPC900 whenever changes are made to the
number of entries in the Pattern Display LUT Configuration or changing the images, bit
depth, image index, or bit position in the Pattern Display LUT Definition
Table 2-128. Pattern BMP Load Command
2
Controller
IC
USB
Read
Write
Master
0x2B
0xAB
0x1A2B
Slave
0x2D
0xAD
0x1A2D
Table 2-129. Pattern BMP Load Command
BYTES
1:0
n:2
2.4.4.5
BITS
9:0
15:10
All
DESCRIPTION
Number of bytes in this packet
Reserved
Compressed BMP Data
RESET
TYPE
d0
w
d0
w
I2C Pass Through Commands
The I2C Pass Through commands allow the user to use I2C port 1 or port of 2 the controller to control
external devices.
2.4.4.5.1 I2C Pass Through Configuration
The I2C Pass Through Configuration command configures the I2C port to be used.
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2
Table 2-130. I C Pass Through Configuration Command
I2C
USB
Write
0x1A4E
0xC5
Table 2-131. I2C Pass Through Configuration Command Definition
BYTE
BITS
DESCRIPTION
RESET
TYPE
d0
w
d0
w
d0
w
I2C Port number 1 or 2
0 = Invalid Port
1:0
1 = Port 1
2 = Port 2
3 = Invalid Port
0
3:2
Reserved
Device addressing mode
0 – 7 bit addressing
1 – 10 bit addressing
4
4:1
7:5
Reserved
31:0
I2C Clock rate 100000 – 400000 Hz (Actual rate may not be exactly as
entered due to the dividers used in calculating the rate)
2.4.4.5.2 I2C Pass Through Write
The I2C Pass Through Write command allows the user to send data to the specified I2C device on the port
that was configured by the Pass Through Configuration command.
Table 2-132. I2C Pass Through Write Command
I2C
USB
Write
0x1A4F
0xCF
Table 2-133. I2C Pass Through Write Command Definition
BYTE
BITS
1:0
15:0
DESCRIPTION
Number of bytes to write (1 – 512)
RESET
TYPE
d0
w
d0
w
d0
w
d0
w
2
I C Port number 1 or 2. (Port configuration of the port being used must have
been done prior to using this command)
0 = Invalid Port
2
1:0
1 = Port 1
2 = Port 2
3 = Invalid Port
4:3
n:5
7:2
Reserved
10:0
Slave Address
15:11
Reserved
All
Bytes to be written
2.4.4.5.3 I2C Pass Through Read
The I2C Pass Through Read command allows the user to read data from the specified I2C device on the
port that was configured by the Pass Through Configuration command.
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2
Table 2-134. I C Pass Through Read Command
I2C
USB
Read
0x1A4F
0x4F
Table 2-135. I2C Pass Through Read Command Definition
BYTE
BITS
RESET
TYPE
1:0
15:0
Number of bytes to write (1-512)
DESCRIPTION
d0
w
3:2
15:0
Number of bytes to read (1-512)
d0
w
d0
w
d0
w
2
I C Port number 1 or 2 (Port configuration of the port being used must have
been done prior to using this command)
0 = Invalid Port
4
1:0
1 = Port 1
2 = Port 2
3 = Invalid Port
6:5
7:2
Reserved
10:0
Slave Address
15:11
Reserved
n:7
All
Data to be written
d0
w
m:0
All
Data bytes read
d0
r
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Chapter 3
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DLPC900 Fault Status
3.1
DLPC900 FAULT_STATUS Location(s)
The DLPC900 produces error codes, or fault statuses, under certain error conditions. The
FAULT_STATUS pin on the DLPC900 is #AC11 (See DLPC900 datasheet DLPS037 for pin details).
3.2
DLPC900 FAULT_STATUS Interpretation
The format of the DLPC900 FAULT_STATUS signal is shown in Figure 3-1. The signal begins with a
pulse, or pulses, indicating the critical error type. The number of critical error pulses indicates the critical
error type - LLFAULT_MAIN, LLFAULT_SYS, or LLFAULT_EX. The critical error pulses are then followed
by a short pause and one or more module error pulses. A longer pause follows the module error type,
indicating that the fault status sequence will then repeat. In Table 3-1, the fault status can be interpreted
by finding the status matching the number of critical error pulses followed by the number of module error
pulses.
Figure 3-1. DLPC900 FAULT_STATUS Format
Table 3-1. DLPC900 Fault Status Description
Number of Critical
Error Pulses
Number of Module
Error Pulses
1
1
Missing flash table signature
2
2
Mismatched controller SW configuration versions
4
Error in first initialization of I2C
7
DMD Initialization error
8
DMD/controller incompatibility fatal error
3
Description
For any combination of pulses not listed please contact TI for more information.
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Chapter 4
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Power-Up and Power-Down and Initialization
Considerations
This chapter describes the initial power-up and power-down considerations, as well as other initialization
considerations.
4.1
Power Up
The DLPC900 is initialized and ready to process commands some time after the signal RESET is driven
high. Detailed power-up timing is given in the DLPC900 data sheet, DLPS037.
4.2
Power Down
A Power Standby command (Section 2.3.1.1)is required at power down of the DLPC900. Please see the
Power-Down requirements in the DLPC900 data sheet, DLPS037.
4.3
Power-Up Auto-Initialization
Upon release of system reset, the DLPC900 executes an auto-initialization routine that is automatically
uploaded from flash. This initialization process consists of setting specific configurations, uploading
specific configuration tables (such as sequence), and displaying a defined splash screen. The goal of the
auto-initialization process is to allow the DLPC900 to fully configure itself for default operation with no
external I2C control.
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63
Chapter 5
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Command Examples
5.1
Video Pattern Mode Example
The following table lists the step for a Video Pattern Mode example with two exposures. Start with the
system powered on and displaying a video source in Video Mode.
NOTE: An error will occur if an attempt is made to switch to Video Pattern Mode if there is not a video
source with a sync lock.
Table 5-1. Video Pattern Mode Example
STEP
2
IC
(1)
USB
(1)
DATA
(1)
DESCRIPTION
1
E9
1A1B
02
Set video pattern mode
2
F8
1A34
00 00 C8 00 00 90 00 00 00 00 00 00
Define pattern 0 (200 µs red 1 bit) and wait for
trigger
3
F8
1A34
01 00 90 01 00 21 00 00 00 00 00 08
Define pattern 1 (400 µs green 2 bit)
4
F5
1A31
02 00 00 00 00 00
Number of patterns 2 with indefinite repeat
5
E5
1A24
02
Start running the pattern
(2)
(1) All bytes are in HEX notation.
(2) A video source must be connected before performing this step.
5.2
Pre-Stored Pattern Mode Example
The following table lists the steps for a Pre-Stored Pattern Mode example with two exposures. Start with
the system powered on.
Table 5-2. Pre-Stored Pattern Mode Example
STEP
I2C
(1)
USB (1)
DATA
(1)
DESCRIPTION
1
E9
1A1B
01
Set pre-stored pattern mode
2
F8
1A34
00 00 C8 00 00 10 00 00 00 00 00 00
Define pattern 0 (200 µs red 1 bit)
3
F8
1A34
01 00 90 01 00 21 00 00 00 00 00 08
Define pattern 1 (400 µs green 2 bit)
4
F5
1A31
02 00 00 00 00 00
Number of patterns 2 and indefinite repeat
5
E5
1A24
02
Start running the pattern
(2)
(1) All bytes are in HEX notation.
(2) There must be at least two pattern images in flash memory.
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5.3
Pattern On-The-Fly Example
The following table lists the steps for Image On-The-Fly Pattern Mode example with two images. Start with
the system powered on. Images should be compressed using Run-Length Encoding (RLE).
Table 5-3. Pattern On-The-Fly Example
STEP
I2C
(1)
USB (1)
DATA
(1)
DESCRIPTION
1
E9
1A1B
03
Set on-the-fly pattern mode
2
F8
1A34
00 00 C8 00 00 10 00 00 00 00 00 00
Define pattern 0 from image 0 (200 µs red 1 bit)
3
F8
1A34
01 00 90 01 00 21 00 00 00 00 01 08
Define pattern 1 from image 1 (400 µs green 2 bit)
4
AA
1A2A
01 00 E8 03 00 00
Set BMP 1 Size to 1000 (0x03E8)
5
AB
1A2B
F8 01 XX XX …… XX
Load 504 byte of compressed BMP 1 Data
6
AB
1A2B
E0 01 XX XX ….. XX
Load 480 bytes of compressed BMP 1 Data
7
AA
1A2A
00 00 D0 07 00 00
Set BMP 0 Size to 2000 (0x07D0)
8
AB
1A2B
F8 01 XX XX …… XX
Load 504 byte of compressed BMP 0 Data
9
AB
1A2B
F8 01 XX XX …… XX
Load 504 byte of compressed BMP 0 Data
10
AB
1A2B
F8 01 XX XX …… XX
Load 504 byte of compressed BMP 0 Data
11
AB
1A2B
E8 01 XX XX …… XX
Load 488 bytes of compressed BMP 0 Data
12
F5
1A31
02 00 00 00 00 00
Number of patterns 2 and indefinite repeat
13
E5
1A24
02
Start running the pattern
(1) All bytes are in HEX notation.
5.4
I2C Pass Through Write Example
The following table lists the steps to communicate with an external device using one of the DLPC900 I2C
ports. The example shows how to write 16 bytes to an EEPROM starting at address location 16.
Table 5-4. I2C Pass Through Write Example
STEP
I2C
(1)
USB (1)
DATA
(1)
DESCRIPTION
1
C5
1A4E
01 A0 86 01 00
Address mode = 7-bits, port = 1, and clock =
100 kHz
2
CF
1A4F
11 00 01 A0 00 00 10 01 18 01 03 A5 00 00
00 DA 04 85 A0 57 4A 9B 26
Number of bytes = 17, port = 1, device address
= A0, EEPROM address location = 16, and 16
bytes of data.
(1) All bytes are in HEX notation.
5.5
I2C Pass Through Read Example
The following table lists the steps to communicate with an external device using one of the DLPC900 I2C
ports. The example shows how to read 16 bytes from an EEPROM starting at address location 16.
Table 5-5. I2C Pass Through Read Example
STEP
I2C
(1)
USB
(1)
(1)
DESCRIPTION
1
C5
1A4E
01 A0 86 01 00
Address mode = 7-bits, port = 1, and clock =
100 kHz
2
4F
1A4F
01 00 10 00 01 A0 00 10
Number of bytes to write = 1, number of bytes to
read = 16, port = 1, device address = A0,
EEPROM address location = 16
01 18 01 03 A5 00 00 00 DA 04 85 A0 57 4A
9B 26
The host performs an I2C read operation to
retrieve the data.
3
(1)
DATA
All bytes are in HEX notation.
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Appendix A
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Register Quick Reference
This appendix provides a quick reference summary of all available sub-address commands.
A.1
I2C Register Quick Reference
Table A-1. Register Quick Reference
I2C SUBADDRESS
66
USB
DESCRIPTION
TYPE
RESET VALUE
DEFAULT ACTION
Read
Write
0x00
0x80
0x1A00
Input Source
Select
WR
0x8
24-bit parallel interface
0x02
0x82
0X1A02
Pixel Format
WR
0x0
RGB
0x03
0x83
0x1A03
Port and Clock
Configuration
WR
0x0
Single Pixel, Pixel Clock 1, Data
enable 1
0x04
0x84
0x1A37
Channel Swap
WR
0x8
ABC = BAC
0x06
0x86
0x1100
Curtain Color
WR
0x0 0x0 0x0 0x0 0x0 0x0
Curtain is black
0x07
0x87
0x0200
Power Mode
WR
0x0
Normal operation
0x08
0x88
0x1008
Long Axis Flip
WR
0x0
Flip disabled
0x09
0x89
0x1009
Short Axis Flip
WR
0x0
Flip disabled
0x0A
0x8A
0x1203
Test Pattern
Select
WR
0x0
Solid Field
0x0B
0x8B
0x1A05
LED PWM
Polarity
WR
0x0
Normal polarity
0x0C
0x8C
0x1A01
IT6535 Power
Mode
WR
0x0
Power down
0x0D
0x8D
0x0201
DMD Idle Mode
WR
0x0
Disabled
0x10
0x90
0x1A07
LED Enable
WR
0x8
LEDs controlled by Sequencer
0x11
0x0205
Get Version
R
Will match firmware version
Will match firmware version
0x12
0x0206
Get firmware type
R
0x0
Will match firmware type:
DLP6500 or DLP9000
0x14
0x94
0x0609
DMD Park /
Unpark
WR
0x0
Unpark DMD
0x1A
0x9A
0x1204
Test Pattern
Color
WR
0x3FF 0x3FF 0x3FF 0x0
0x0 0x0
White foreground, black
background
0x20
0x1A0A
Hardware Status
R
0x1
No errors
0x21
0x1A0B
System Status
R
0x1
No errors
0x22
0x1A0C
Main Status
R
0x0
No errors
0x32
0x0100
Read Error Code
R
0x0
No errors
0x33
0x0101
Read Error Code
Description
R
0x0
No description
0xAA
0x1A2A
Initialize Pattern
BMP Load
W
0x0
See Command Description
0xAB
0x1A2B
Pattern BMP
Load
W
0x0
See Command Description
0xAC
0x1A2C
Initialize Pattern
BMP Load
W
0x0
See Command Description
Register Quick Reference
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I2C Register Quick Reference
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Table A-1. Register Quick Reference (continued)
2
I C SUBADDRESS
0xAD
0x3A
USB
DESCRIPTION
0x1A2D
Pattern BMP
Load
0x1A14
Batch File Name
0xBB
0x1A15
Batch File
Execute
TYPE
RESET VALUE
DEFAULT ACTION
W
0x0
See Command Description
WR
0x0
Index
W
0x0
Index
W
0xBC
0x1A16
Batch File Delay
0x0
Delay
0x40
0xC0
0x1A10
PWM Enable
WR
Channel dependent
Channel dependent
0x41
0xC1
0x1A11
PWM Setup
WR
Channel dependent
Channel dependent
0x44
0xC4
0x1A38
GPIO
Configuration
WR
Channel dependent
Channel dependent
0xC5
0x1A4E
I2C Pass Through
Configuration
W
0x0 0x0 0x0 0x0 0x0
See Command Description
0x48
0xC8
0x0807
Clock
Configuration
WR
Channel dependent
Channel dependent
0x4B
0xCB
0x0B01
LED Current
WR
0x97 0x78 0x7D
LED PWMs
2
0x4F
0xCF
0x1A4F
I C Pass Through
Read or Write
WR
See Command Description
See Command Description
0x60
0xE0
0x1A40
DMD Block Load
WR
0x0 0xF or 0x0 0x10
All blocks active
0x62
0x1A41
Set Minimum
LED Pulse Width
WR
0x0
0x0
0x1A42
Get Minimum
Pattern Exposure
R
0x0
0x0
0x63
0x65
0xE5
0x1A24
Pattern Start/Stop
WR
0x0
Pattern stopped
0x69
0xE9
0x1A1B
Display Mode
WR
0x0
Video Mode
0x6A
0xEA
0x1A1D
Trigger Out 1
WR
0x0 0x0 0x0 0x0 0x0
Normal Polarity with no rising or
falling delay
0x6B
0xEB
0x1A1E
Trigger Out 2
WR
0x0 0x0 0x0 0x0 0x0
Normal Polarity with no rising
delay
0x6C
0xEC
0x1A1F
Red Enable
Delay
WR
0x0 0x0 0x0 0x0
No rising or falling delay
0x6D
0xED
0x1A20
Green Enable
Delay
WR
0x0 0x0 0x0 0x0
No rising or falling delay
0x6E
0xEE
0x1A21
Blue Enable
Delay
WR
0x0 0x0 0x0 0x0
No rising or falling delay
0x74
0xF4
0x1A30
Invert Data
WR
0x0
Normal operation
0x75
0xF5
0x1A31
Pattern LUT
Configuration
WR
See Command Description
See Command Description
0x76
0x1A34
Pattern LUT
Reorder
Configuration
W
See Command Description
See Command Description
0xF8
0x1A34
Pattern LUT
Definition
W
See Command Description
See Command Description
0x79
0xF9
0x1A35
Trigger In 1
WR
0x69
No delay
0x7A
0xFA
0x1A36
Trigger In 2
WR
0x0
Advance Pattern Pair on Rising
Edge (for Trigger Mode 2)
0x7E
0xFE
0x1000
Manual Input
Display
Resolution
WR
0x0
Output Display Resolution is DMD
Dependant
0x7F
0xFF
0x1A39
Image Load
WR
0x0
Image Index
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Command Guide
A.2
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Command Guide
This section shows which commands can be used in which modes. I2C control and USB commands are
accepted in any order, except when special sequencing is required (for example, setting up the flash).
Table A-2. Command Matrix
I2C
COMMAND NAME
NORMAL
POWER
MODE
STANDBY
POWER
MODE
VIDEO
MODE
VIDEO
PATTERN
MODE
PRESTORED
PATTERN
MODE
PATTERN
ON-THEFLY MODE
x
x
Read
Write
Input Source Select
0x00
0x80
0x1A00
x
x
x
Pixel Format
0x02
0x82
0x1A02
x
x
x
Port and Clock
Configuration
0x03
0x83
0x1A03
x
x
x
x
Channel Swap
0x04
0x84
0x1A37
x
x
x
x
Curtain Color
0x06
0x86
0x1100
x
x
x
Power Mode
0x07
0x87
0x0200
x
x
x
x
IT6535 Power Mode
0x0C
0x8C
0x1A01
x
x
x
Long Axis Flip
0x08
0x88
0x1008
x
x
x
x
x
Short Axis Flip
0x09
0x89
0x1009
x
x
x
x
x
Test Pattern Select
0x0A
0x8A
0x1203
x
LED PWM Polarity
0x0B
0x8B
0x1A05
x
x
x
x
x
x
DMD Idle Mode
0x0D
0x8D
0x0201
x
x
LED Enable
0x10
0x90
0x1A07
x
Get Version
0x11
0x0205
x
x
Test Pattern Color
0x1A
0x9A
0x1204
x
x
DMD Park / Unpark
0x14
0x94
0x0609
x
Hardware Status
0x20
0x1A0A
x
System Status
0x21
0x1A0B
Main Status
0x22
0x1A0C
Read Error Code
0x32
Read Error Code
Description
0x33
Initialize Pattern
BMP Load
0xAA
x
x
x
x
x
x
x
x
x
x
x
x
x (1)
x (1)
x (1)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x0100
x
x
x
x
x
x
0x0101
x
x
x
x
x
x
0x1A2A
x
x
Pattern BMP Load
0xAB
0x1A2B
x
x
Initialize Pattern
BMP Load
0xAC
0x1A2C
x
x
Pattern BMP Load
0xAD
0x1A2D
x
x
Batch File Name
0x1A14
x
x
x
x
x
x
Batch File Execute
0x3A
0xBB
0x1A15
x
x
x
x
x
x
Batch File Delay
0xBC
0x1A16
x
x
x
x
x
x
PWM Enable
0x40
0xC0
0x1A10
x
x
x
x
x
x
PWM Setup
0x41
0xC1
0x1A11
x
x
x
x
x
x
GPIO Configuration
0x44
0xC4
0x1A38
x
x
x
x
x
x
0xC5
0x1A4E
x
x
x
x
x
x
I2C Pass Through
Configuration
Clock Configuration
0x48
0xC8
0x0807
x
x
x
x
x
x
LED Current
0x4B
0xCB
0x0B01
x
x
x
x
x
x
I C Pass Through
Read or Write
0x4F
0xCF
0x1A4F
x
x
x
x
x
x
DMD Block Load
0x60
0xE0
0x1A40
x
x
x
x
x
x
2
(1)
68
USB
This command can only be used in this mode when the pattern display has been stopped or has not yet been started.
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Command Guide
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Table A-2. Command Matrix (continued)
I2C
COMMAND NAME
USB
NORMAL
POWER
MODE
STANDBY
POWER
MODE
VIDEO
MODE
VIDEO
PATTERN
MODE
PRESTORED
PATTERN
MODE
PATTERN
ON-THEFLY MODE
x
x
x
x
x
x
Pattern Start/Stop
0x65
0xE5
0x1A24
x
Display Mode
0x69
0xE9
0x1A1B
x
Trigger Out 1
0x6A
0xEA
0x1A1D
x
x
x
x
x
Trigger Out 2
0x6B
0xEB
0x1A1E
x
x
x
x
x
Red Enable Delay
0x6C
0xEC
0x1A1F
x
x
x
x
x
Green Enable Delay
0x6D
0xED
0x1A20
x
x
x
x
x
Blue Enable Delay
0x6E
0xEE
0x1A21
x
x
x
x
x
Invert Data
0x74
0xF4
0x1A30
x
x
x
x
Pattern LUT
Configuration
0x75
0xF5
0x1A31
x
x
x
x
Pattern LUT Reorder
Configuration
0x76
0x1A34
x
x
x
Pattern LUT
Definition
0xF8
0x1A34
x
x
x
x
x
Trigger In 1
0x79
0xF9
0x1A35
x
x
x
x
x
Trigger In 2
0x7A
0xFA
0x1A36
x
x
x
x
x
Manual Input Display
Resolution
0x7E
0xFE
0x1000
x
x
Image Load
0x7F
0xFF
0x1A39
x
x
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Appendix B
DLPU018E – October 2014 – Revised April 2019
Batch File Command Descriptors
This appendix provides a quick reference to all supported batch file command descriptors.
B.1
Command Descriptors
Command descriptors are followed by a colon. Each line in the batch file is space delaminated and saved
as a text file.
Table B-1. Command Descriptors
COMMAND DESCRIPTOR
70
DESCRIPTION
SOURCE_SEL
Input Source Select Section 2.3.3.2
PIXEL_FORMAT
Pixel Format Section 2.3.3.3
CLK_SEL
Port and Clock Configuration Section 2.3.3.1
CHANNEL_SWAP
Channel Swap Section 2.3.2.1
POWER_CONTROL
Power Mode Section 2.3.1.1
FLIP_LONG
Long Axis Flip Section 2.3.4.1
FLIP_SHORT
Short Axis Flip Section 2.3.4.2
TPG_SEL
Test Pattern Select Section 2.3.3.4
PWM_INVERT
LED PWM Invert Section 2.3.5.1.1
LED_ENABLE
LED Enable Section 2.3.5.1
PWM_ENABLE
PWM Enable Section 2.3.7.2
PWM_SETUP
PWM Setup Section 2.3.7.1
GPIO_CONFIG
GPIO Configuration Section 2.3.6.1
LED_CURRENT
LED Current Section 2.3.5.2
DISP_CONFIG
Display Configuration Section 2.4.1.2
DISP_MODE
Display Mode Section 2.4.1
TRIG_OUT1_CTL
Trigger 1 Output Control Section 2.4.4.1.1
TRIG_OUT2_CTL
Trigger 2 Output Control Section 2.4.4.1.2
RED_LED_ENABLE_DLY
Red LED Enable Delay Section 2.4.4.2.1
GREEN_LED_ENABLE_DLY
Green LED Enable Delay Section 2.4.4.2.2
BLUE_LED_ENABLE_DLY
Blue LED Enable Delay Section 2.4.4.2.3
PAT_START_STOP
Pattern Start, Pause, and Stop Section 2.4.4.3.1
TRIG_IN1_CTL
Trigger Input 1 Control Section 2.4.4.1.3
TRIG_IN2_CTL
Trigger Input 2 Control Section 2.4.4.1.4
INVERT_DATA
Invert Data Section 2.4.4.3.2
PAT_CONFIG
Pattern LUT Configuration Section 2.4.4.3.3
MBOX_ADDRESS
Pattern Display LUT Reorder ConfigurationSection 2.4.4.3.4
MBOX_DATA
Pattern LUT Definition Section 2.4.4.3.5
SPLASH_LOAD
Image Load Section 2.3.3.6
GPCLK_CONFIG
Clock Output Configuration Section 2.3.6.2
TPG_COLOR
Test Pattern Color Table 2-49
I2C_PASSTHRU
I2C Pass Through Section 2.4.4.5.2
VIDEO_CONT_SEL
IT6535 Power Mode Section 2.3.4.3
Batch File Command Descriptors
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Command Descriptors
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Table B-1. Command Descriptors (continued)
COMMAND DESCRIPTOR
DESCRIPTION
PATMEM_LOAD_INIT_MASTER
Initialize BMP Pattern On-The-Fly Master Section 2.4.4.4.1
PATMEM_LOAD_DATA_MASTER (1)
Load BMP Pattern On-The-Fly Master Section 2.4.4.4.2
PATMEM_LOAD_INIT_SLAVE
Initialize BMP Pattern On-The-Fly Slave Section 2.4.4.4.1
PATMEM_LOAD_DATA_SLAVE
(1)
Load BMP Pattern On-The-Fly Slave Section 2.4.4.4.2
DELAY
Batch File Delay Section 2.3.8.3
I2C_CONFIG
I2C Pass Through Configuration Section 2.4.4.5.1
CURTAIN_COLOR
Curtain Color Section 2.3.1.3
BATCHFILE_EXECUTE
Batch File Execute Section 2.3.8.2
DMD_BLOCKS
DMD Block Load Section 2.4.1.3
DMD_IDLE
DMD Idle Mode (50/50 Duty Cycle) Section 2.4.1.4
(1) These commands are not allowed to be included in a batch file that is added to the firmware.
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from D Revision (July 2017) to E Revision ...................................................................................................... Page
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Updated E2E link to current forum. ..................................................................................................... 6
Changed Reading "Firmware Type" to "Hardware Configuration" in Section 2.1.5 ............................................. 17
Added recommendation to put DMD in Idle Mode if it is going to be idle but not powered down. ............................ 25
Deleted 4:4:4 from RGB in pixel format since RGB does not support chroma sub-sampling ................................. 29
Changed note regarding maximum number of patterns from "uncompressed" to "compressed" ............................ 42
Added note about using a user defined solid state illumination sequence with eight 1-bit patterns to achieve maximum 8bit pattern rates shown in the DMD data sheets. ................................................................................... 42
Image Header moved from Appendix C to its own section ........................................................................ 48
Added notes to the Pattern Display LUT Configuration command ................................................................ 55
Added Pattern Display LUT Reorder Configuration command .................................................................... 56
Added Input Trigger Considerations to the Pattern Display LUT Reorder Configuration command ....................... 57
Changed From requiring a Pattern Display LUT Configuration command before to after using Pattern Display LUT
Definition commands ................................................................................................................... 57
Added notes to the Pattern Display LUT Definition command ..................................................................... 57
Changed requirements for Pattern On-The-Fly Mode to issue a Pattern LUT Configuration after any Patter LUT
Definition .................................................................................................................................. 58
Removed "Internal error, contact TI for more information" entries from the Table 3-1 table and added a note to contact TI
regarding any combinations not listed................................................................................................. 62
Changed Power down instruction to include Power Standby command.......................................................... 63
Added note that the system must have a sync lock by displaying video in Video Mode to switch to Video Pattern
mode. ...................................................................................................................................... 64
Corrected hex value in Command Examples to 0x00C8 to match 200 µs pattern display time .............................. 64
Deleted "displaying a video source" from Pre-Stored Pattern Mode example. .................................................. 64
Changed pattern data load sizes in Pattern On-The-Fly Example ................................................................ 65
Deleted 4:4:4 from RGB in pixel format since RGB does not support chroma sub-sampling ................................. 66
Added Pattern LUT Reorder Configuration to reference tables ................................................................... 67
Added cross references to sections in Batch File Command Descriptors table ................................................. 70
Changes from C Revision (March 2017) to D Revision .................................................................................................. Page
•
•
•
•
•
•
•
•
Moved "Enter Standby mode prior to any planned system power shutdowns" from Table 2-34 ..............................
Updated Power Mode Command Definition ..........................................................................................
Changed Power Mode 0, 1 descriptive text ..........................................................................................
Added Section DMD Park / Unpark ...................................................................................................
Updated DMD Idle Mode ...............................................................................................................
Changed Idle mode recommendation. ................................................................................................
Added 0x14 DMD Park / Unpark ......................................................................................................
Added DMD Park / Unpark .............................................................................................................
25
25
25
25
47
47
66
68
Changes from B Revision (July 2015) to C Revision ..................................................................................................... Page
•
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•
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72
Added Section 2.1.5 .....................................................................................................................
Added Table 2-9 to Section 2.1.5......................................................................................................
Changed "Enter Program Mode" value to "1" in Table 2-18 .......................................................................
Changed "Exit Program Mode" value to "2" in Table 2-20 .........................................................................
Corrected 128 kB to 128 kB to describe the size of the boot flash sector in Section 2.2.5 ....................................
Changed IT6535 (0x0C) bits to 1:0 and 7:2 in Table 2-58 .........................................................................
Added Minimum LED Pulse Width command in Table 2-65 .......................................................................
Revision History
17
17
21
21
22
33
36
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Revision History
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•
•
•
•
Added Get Minimum LED Pattern Exposure command Table 2-67 ..............................................................
Changed WQXGA refresh rate from 60 Hz to 120 Hz in Section 2.4 .............................................................
Corrected supported display modes from "0, 2, and 3" to "1, 2, and 3" in Section 2.4.4 ......................................
Moved Section 3.1 DLPC900 FAULT_STATUS Location(s) and Section 3.2 DLPC900 FAULT_STATUS Interpretation
36
41
50
62
Changes from A Revision (November 2014) to B Revision ........................................................................................... Page
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Added EVM User's Guide to related documents ...................................................................................... 6
General changes to layout ............................................................................................................... 6
Corrected bits to byte in table header ................................................................................................. 16
Added bit to check if external video source is locked ............................................................................... 16
Added bit to check if port syncs are valid ............................................................................................ 16
Corrected bits to value in table header ............................................................................................... 18
Added bit to check if pattern image memory address is out of range ............................................................ 18
Added information, image, and notes on flash memory ............................................................................ 19
Updated Read Status Command Definition Table to reflect firmware 2.0........................................................ 20
Added bit to request number of flash devices present .............................................................................. 22
Changed location size of the boot loader to match firmware 2.0 and later ...................................................... 22
Corrected blue curtain color intensity reset value ................................................................................... 26
Removed Allowed Pattern Display Combinations table ............................................................................ 42
Added clarification on how and when block load is used. .......................................................................... 45
Corrected minimum exposure values for number of active DMD blocks ......................................................... 46
Added table with minimum exposure based on bit depth .......................................................................... 47
Added DMD Idle Mode command ..................................................................................................... 47
Corrected video pattern mode trigger description and timing diagram ........................................................... 51
Corrected pre-stored pattern mode trigger description and timing diagram ..................................................... 51
Corrected trigger output1 rising and falling edge minimum delay to -20 μs...................................................... 51
Corrected trigger output2 rising and falling edge minimum delay to -20 μs...................................................... 52
Corrected red LED enable rising and falling edge minimum delay to -20 μs .................................................... 53
Corrected green LED enable rising and falling edge minimum delay to -20 μs ................................................. 54
Corrected blue LED enable rising and falling edge minimum delay to -20 μs ................................................... 54
Added that Initialize Pattern BMP Load Command size must include header................................................... 59
Added DLPC900 fault status table .................................................................................................... 62
Corrected the step order on the Pattern on the Fly example ...................................................................... 65
PWM Capture register is unavailable and was removed from table .............................................................. 67
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