Texas Instruments | ADC322x Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters (Rev. D) | Datasheet | Texas Instruments ADC322x Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters (Rev. D) Datasheet

Texas Instruments ADC322x Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters (Rev. D) Datasheet
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ADC3221, ADC3222, ADC3223, ADC3224
SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
ADC322x
Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters
1 Features
3 Description
•
•
•
•
•
•
The ADC322x are a high-linearity, ultra-low power,
dual-channel, 12-bit, 25-MSPS to 125-MSPS, analogto-digital converter (ADC) family. The devices are
designed specifically to support demanding, high
input frequency signals with large dynamic range
requirements. An input clock divider allows more
flexibility for system clock architecture design and the
SYSREF
input
enables
complete
system
synchronization. The ADC322x family supports serial
low-voltage differential signaling (LVDS) in order to
reduce the number of interface lines, thus allowing for
high system integration density. The serial LVDS
interface is two-wire, where each ADC data are
serialized and output over two LVDS pairs.
Optionally, a one-wire serial LVDS interface is
available. An internal phase-locked loop (PLL)
multiplies the incoming ADC sampling clock to derive
the bit clock that is used to serialize the 12-bit output
data from each channel. In addition to the serial data
streams, the frame and bit clocks are also transmitted
as LVDS outputs.
1
•
•
•
•
•
•
Dual channel
12-Bit resolution
Single supply: 1.8 V
Serial LVDS interface (SLVDS)
Flexible input clock buffer with divide-by-1, -2, -4
SNR = 70.2 dBFS, SFDR = 87 dBc at
fIN = 70 MHz
Ultra-low power consumption:
– 116 mW/Ch at 125 MSPS
Channel isolation: 105 dB
Internal dither and chopper
Support for multi-chip synchronization
Pin-to-pin compatible with 14-Bit version
Package: VQFN-48 (7 mm × 7 mm)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Multi-carrier, multi-mode cellular base stations
Radar and smart antenna arrays
Munitions guidance
Motor control feedback
Network and vector analyzers
Communications test equipment
Nondestructive testing
Microwave receivers
Software-defined radios (SDRs)
Quadrature and diversity radio receivers
Handheld radio and instrumentation
Device Information(1)
PART NUMBER
ADC322x
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
space
space
Performance at fS = 125 MSPS, fIN = 10 MHz
(SNR = 70.6 dBFS, SFDR = 100 dBc)
0
-10
-20
Amplitude (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D201
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC3221, ADC3222, ADC3223, ADC3224
SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
1
1
1
2
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics: General ............................ 7
Electrical Characteristics: ADC3221, ADC3222 ....... 8
Electrical Characteristics: ADC3223, ADC3224 ....... 8
AC Performance: ADC3221...................................... 9
AC Performance: ADC3222.................................... 11
AC Performance: ADC3223.................................. 13
AC Performance: ADC3224.................................. 15
Digital Characteristics ........................................... 17
Timing Requirements: General ............................. 17
Timing Requirements: LVDS Output..................... 18
Typical Characteristics: ADC3221 ........................ 19
Typical Characteristics: ADC3222 ........................ 24
Typical Characteristics: ADC3223 ........................ 29
Typical Characteristics: ADC3224 ........................ 34
7.19 Typical Characteristics: Common ......................... 39
7.20 Typical Characteristics: Contour ........................... 40
8
Parameter Measurement Information ................ 41
9
Detailed Description ............................................ 43
8.1 Timing Diagrams ..................................................... 41
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
43
43
44
49
50
54
10 Applications and Implementation...................... 65
10.1 Application Information.......................................... 65
10.2 Typical Applications .............................................. 66
11 Power Supply Recommendations ..................... 68
12 Layout................................................................... 69
12.1 Layout Guidelines ................................................. 69
12.2 Layout Example .................................................... 69
13 Device and Documentation Support ................. 70
13.1
13.2
13.3
13.4
13.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
70
70
70
70
70
14 Mechanical, Packaging, and Orderable
Information ........................................................... 70
4 Revision History
Changes from Revision C (July 2019) to Revision D
Page
•
Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity ................................................................ 22
•
Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity ................................................................ 27
•
Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity ................................................................ 32
•
Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity ................................................................ 37
Changes from Revision B (March 2016) to Revision C
Page
•
Added text to the Description: Optionally, a one-wire serial LVDS interface is available. .................................................... 1
•
Changed the description of pin AVDD, DVDD, GND, and PDN pins in the Pin Functions table .......................................... 5
•
Changed the condition statement for Electrical Characteristics: General .............................................................................. 7
•
Moved the location of Electrical Characteristics: General ...................................................................................................... 7
•
Changed the parameter description of EG(REF) in Electrical Characteristics: General ............................................................ 7
•
Deleted EG(CHAN) from Electrical Characteristics: General ...................................................................................................... 7
•
Changed the parameter description of α(EGCHAN) in Electrical Characteristics: General ......................................................... 7
•
Changed the condition statement for Electrical Characteristics: ADC3221, ADC3222.......................................................... 8
•
Changed ADC clock frequency (ADC3241) From: MAX = 125 MSPS To: MAX = 25 MSPS in Electrical
Characteristics: ADC3221, ADC3222..................................................................................................................................... 8
•
Changed ADC clock frequency (ADC3242) From: MAX = 125 MSPS To: MAX = 50 MSPS in Electrical
Characteristics: ADC3221, ADC3222..................................................................................................................................... 8
•
Changed the condition statement for Electrical Characteristics: ADC3223, ADC3224.......................................................... 8
2
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•
Changed the condition statement for Electrical Characteristics: ADC3221 ........................................................................... 9
•
Changed the condition statement for Electrical Characteristics: ADC3222 ......................................................................... 11
•
Changed the condition statement for Electrical Characteristics: ADC3223 ......................................................................... 13
•
Changed the condition statement for Electrical Characteristics: ADC3224 ......................................................................... 15
•
Added Differential swing to DIGITAL INPUTS (SYSREFP, SYSREFM).............................................................................. 17
•
Deleted VIH and VIL from DIGITAL INPUTS (SYSREFP, SYSREFM).................................................................................. 17
•
added table note: SYSREF is internally biased to 0.9 V.to Digital Characteristics .............................................................. 17
•
Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity .................................................................. 22
•
Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity .................................................................. 27
•
Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity .................................................................. 32
•
Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity .................................................................. 37
•
Changed the Overview section............................................................................................................................................. 43
•
Added Using the SYSREF Input section .............................................................................................................................. 46
•
Changed the Register Initialization through SPI section ...................................................................................................... 53
•
Changed the Detailed Design Procedure section ................................................................................................................ 66
Changes from Revision A (March 2015) to Revision B
Page
•
Added Digital Inputs section to Digital Characteristics table ................................................................................................ 17
•
Updated Figure 19, Figure 20, Figure 23, Figure 24, Figure 25 and, Figure 26 ................................................................. 22
•
Updated Figure 50, Figure 53, Figure 54, Figure 55, and Figure 56 ................................................................................... 27
•
Updated Figure 79, Figure 80, Figure 83, Figure 84, Figure 85, and Figure 86 ................................................................. 32
•
Updated Figure 109, Figure 110, Figure 113, Figure 114, Figure 115, and Figure 116. ..................................................... 37
•
Changed conditions of Figure 122 and Figure 124 ............................................................................................................. 39
•
Changed Figure 129............................................................................................................................................................. 41
•
Changed SNR and Clock Jitter section: changed typical thermal noise value in description of and changed
Figure 138 to reflect updated thermal noise value .............................................................................................................. 46
•
Changed Table 3 .................................................................................................................................................................. 47
•
Changed Lane to Wire in Figure 139 .................................................................................................................................. 48
•
Changed Register Map Summary table: changed FLIP BITS to FLIP WIRE in register 04h, changed bit 7 in register
70Ah, and added register 13h .............................................................................................................................................. 54
•
Changed Summary of Special Mode Registers section: changed title, moved section to correct location ......................... 55
•
Changed lane to wire in register 03h description ................................................................................................................ 55
•
Changed register 04h: changed FLIP BITS to FLIP WIRE and changed description of bit 0.............................................. 56
•
Changed register 0Ah and 0Bh descriptions........................................................................................................................ 58
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Added register 13h ............................................................................................................................................................... 59
•
Changed register 70Ah to include the DIS CLK FILT register bit ........................................................................................ 64
Changes from Original (July 2014) to Revision A
•
Page
Released to Production Data.................................................................................................................................................. 1
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5 Device Comparison Table
INTERFACE
RESOLUTION
(Bits)
25 MSPS
50 MSPS
80 MSPS
125 MSPS
160 MSPS
12
ADC3221
ADC3222
ADC3223
ADC3224
—
14
ADC3241
ADC3242
ADC3243
ADC3244
—
12
—
ADC32J22
ADC32J23
ADC32J24
ADC32J2x5
14
—
ADC32J42
ADC32J43
ADC32J44
ADC32J45
Serial LVDS
JESD204B
6 Pin Configuration and Functions
DA0M
DA0P
DA1M
DA1P
DCLKM
DCLKP
FCLKM
FCLKP
DB0M
DB0P
DB1M
DB1P
48
47
46
45
44
43
42
41
40
39
38
37
RGZ Package
48-Pin VQFN
Top View
GND
1
36
GND
DV DD
2
35
DV DD
GND
3
34
GND
DV DD
4
33
DV DD
GND
5
32
GND
AVDD
6
31
PDN
30
AVDD
Th ermal
4
Pad
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23
24
VCM
AVDD
SYSREFM
25
22
12
SYSREFP
AVDD
21
INBM
RE SET
26
20
11
AVDD
INAM
19
INBP
CL KP
27
18
10
CL KM
INAP
17
AVDD
AVDD
28
16
9
SDOUT
AVDD
15
AVDD
SEN
29
14
8
SDATA
AVDD
13
7
SCLK
AVDD
No t to scale
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AVDD
6, 7, 8, 9, 12, 17,
20, 25, 28, 29, 30
I
Analog 1.8-V power supply, decoupled with capacitors.
CLKM
18
I
Negative differential clock input for the ADC
CLKP
19
I
Positive differential clock input for the ADC
DA0M
48
O
Negative serial LVDS output for channel A0
DA0P
47
O
Positive serial LVDS output for channel A0
DA1M
46
O
Negative serial LVDS output for channel A1
DA1P
45
O
Positive serial LVDS output for channel A1
DB0M
40
O
Negative serial LVDS output for channel B0
DB0P
39
O
Positive serial LVDS output for channel B0
DB1M
38
O
Negative serial LVDS output for channel B1
DB1P
37
O
Positive serial LVDS output for channel B1
DCLKM
44
O
Negative bit clock output
DCLKP
43
O
Positive bit clock output
DVDD
2, 4, 33, 35
I
Digital 1.8-V power supply, decoupled with capacitors.
FCLKM
42
O
Negative frame clock output
FCLKP
41
O
Positive frame clock output
GND
1, 3, 5, 32, 34, 36
I
Ground, 0 V. Connect to the printed circuit board (PCB) ground plane. PowerPAD™
INAM
11
I
Negative differential analog input for channel A
INAP
10
I
Positive differential analog input for channel A
INBM
26
I
Negative differential analog input for channel B
INBP
27
I
Positive differential analog input for channel B
PDN
31
I
Power-down control; active high. This pin may be configured through the SPI.
This pin has an internal 150-kΩ pull-down resistor.
RESET
21
I
Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor.
SCLK
13
I
Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA
14
I
Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT
16
O
Serial interface data output
SEN
15
I
Serial interface enable; active low.
This pin has an internal 150-kΩ pull-up resistor to AVDD.
SYSREFM
23
I
Negative external SYSREF input
SYSREFP
22
I
Positive external SYSREF input
VCM
24
O
Common-mode voltage for analog inputs
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Analog supply voltage range, AVDD
–0.3
2.1
V
Digital supply voltage range, DVDD
V
Voltage applied to input pins
Temperature
–0.3
2.1
INAP, INBP, INAM, INBM
–0.3
min (1.9, AVDD + 0.3)
CLKP, CLKM
–0.3
AVDD + 0.3
SYSREFP, SYSREFM
–0.3
AVDD + 0.3
SCLK, SEN, SDATA, RESET, PDN
–0.3
3.9
Operating free-air, TA
–40
85
Operating junction, TJ
Storage, Tstg
(1)
V
125
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage range
1.7
1.8
1.9
V
DVDD
Digital supply voltage range
1.7
1.8
1.9
V
ANALOG INPUT
VID
Differential input voltage
VIC
Input common-mode voltage
For input frequencies < 450 MHz
2
For input frequencies < 600 MHz
1
VPP
VCM ± 0.025
V
CLOCK INPUT
Input clock frequency
Sampling clock frequency
Sine wave, ac-coupled
Input clock amplitude (differential)
15 (2)
0.2
125 (3)
1.5
LVPECL, ac-coupled
1.6
LVDS, ac-coupled
0.7
Input clock duty cycle
35%
Input clock common-mode voltage
MSPS
50%
VPP
65%
0.95
V
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to GND
3.3
pF
RLOAD
Differential load resistance placed externally
100
Ω
(1)
(2)
(3)
6
To reset the device for the first time after power-up, only use the RESET pin; see the Register Initialization section.
See Table 3 for details.
With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.
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7.4 Thermal Information
ADC322x
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
25.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.9
°C/W
RθJB
Junction-to-board thermal resistance
3.0
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: General
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
12
Bits
ANALOG INPUT
2.0
VPP
RIN
Differential input full-scale
Input resistance
Differential at dc
6.6
kΩ
CIN
Input capacitance
Differential at dc
3.7
pF
VOC(VCM)
VCM common-mode voltage output
0.8
VCM output current capability
0.95
1.1
V
10
mA
Input common-mode current
Per analog input pin
1.5
µA/MSPS
Analog input bandwidth (3 dB)
50-Ω differential source driving 50-Ω
termination across INP and INM
540
MHz
DC ACCURACY
EO
Offset error
–25
αEO
Temperature coefficient of offset
error
EG(REF)
E_G Overall dc gain error of a
channel
α(EGCHAN)
Temperature coefficient of overall
gain error
25
±0.024
–2%
mV
mV/C
2%
±0.008
Δ%FS/°C
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk (1)
(1)
fIN = 10 MHz
105
fIN = 100 MHz
105
fIN = 200 MHz
105
fIN = 230 MHz
105
fIN = 300 MHz
105
dB
Crosstalk is measured with a –1-dBFS input signal on one channel and no input on the other channel.
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7.6 Electrical Characteristics: ADC3221, ADC3222
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3241
PARAMETER
MIN
TYP
ADC clock frequency
ADC3242
MAX
MIN
TYP
25
MAX
UNIT
50
MSPS
mA
1.8-V analog supply current
31
71
39
81
1.8-V digital supply current
35
65
43
75
mA
118
205
147
245
mW
Total power dissipation
Global power-down dissipation
Standby power-down dissipation
5
17
5
17
mW
78
103
78
103
mW
7.7 Electrical Characteristics: ADC3223, ADC3224
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3243
PARAMETER
MIN
TYP
ADC clock frequency
MIN
TYP
80
MAX
UNIT
125
MSPS
mA
1.8-V analog supply current
50
91
65
106
1.8-V digital supply current
52
85
64
95
mA
183
285
233
325
mW
Total power dissipation
Global power-down dissipation
Standby power-down dissipation
8
ADC3244
MAX
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5
17
5
17
mW
72
103
78
103
mW
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7.8 AC Performance: ADC3221
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3221 (fS = 25 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
TYP
DITHER OFF
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
70.9
71.2
70.8
71.1
fIN = 70 MHz
70.6
70.9
fIN = 100 MHz
70.3
70.6
fIN = 170 MHz
69.7
69.9
fIN = 230 MHz
68.8
69
fIN = 10 MHz
70.2
70.6
fIN = 20 MHz
70.2
70.5
fIN = 70 MHz
69.9
70.2
fIN = 100 MHz
69.6
69.9
fIN = 170 MHz
69.2
69.3
fIN = 230 MHz
68.2
68.4
fIN = 10 MHz
–141.9
–142.2
fIN = 20 MHz
–141.8 –139.5
–142.1
fIN = 70 MHz
–141.6
–141.9
fIN = 100 MHz
–141.3
–141.6
fIN = 170 MHz
–140.7
–140.9
fIN = 230 MHz
–139.8
–140.0
70.9
71.1
fIN = 20 MHz
Signal-to-noise ratio
(from 1-MHz offset)
SNR
Signal-to-noise ratio
(full Nyquist band)
NSD (1)
Noise spectral density
(averaged across Nyquist zone)
68.5
fIN = 10 MHz
fIN = 20 MHz
SINAD (1)
Signal-to-noise and distortion ratio
70.8
71
fIN = 70 MHz
70.6
70.7
fIN = 100 MHz
70.2
70.3
fIN = 170 MHz
69.6
69.6
fIN = 230 MHz
68.5
68.5
fIN = 10 MHz
11.5
11.5
11.5
11.5
fIN = 70 MHz
11.4
11.5
fIN = 100 MHz
11.4
11.4
fIN = 170 MHz
11.3
11.3
fIN = 230 MHz
11.1
11.1
96
88
93
89
fIN = 70 MHz
93
87
fIN = 100 MHz
85
82
fIN = 170 MHz
86
83
fIN = 230 MHz
81
80
fIN = 20 MHz
ENOB (1)
Effective number of bits
68.1
11
fIN = 10 MHz
fIN = 20 MHz
SFDR
(1)
Spurious-free dynamic range
82
dBFS
dBFS
dBFS/Hz
dBFS
Bits
dBc
Reported from a 1-MHz offset.
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AC Performance: ADC3221 (continued)
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3221 (fS = 25 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
fIN = 10 MHz
Second-order harmonic distortion
95
fIN = 70 MHz
101
95
fIN = 100 MHz
95
93
fIN = 170 MHz
88
87
fIN = 230 MHz
81
81
96
88
93
92
fIN = 70 MHz
93
87
fIN = 100 MHz
85
82
fIN = 170 MHz
87
83
fIN = 230 MHz
82
80
fIN = 10 MHz
99
92
fIN = 20 MHz
Non
HD2, HD3
Spurious-free dynamic range
(excluding HD2, HD3)
IMD3
10
Total harmonic distortion
Two-tone, third-order
intermodulation distortion
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82
101
91
fIN = 70 MHz
99
93
fIN = 100 MHz
98
92
fIN = 170 MHz
99
92
fIN = 230 MHz
97
93
fIN = 10 MHz
94
85
92
85
fIN = 70 MHz
91
85
fIN = 100 MHz
86
82
fIN = 170 MHz
84
81
fIN = 230 MHz
78
77
fIN1 = 45 MHz,
fIN2 = 50 MHz
–95
–94
fIN1 = 185 MHz,
fIN2 = 190 MHz
–90
–89
fIN = 20 MHz
THD
TYP
97
fIN = 20 MHz
Third-order harmonic distortion
MIN
102
82
fIN = 10 MHz
HD3
DITHER OFF
MAX
106
fIN = 20 MHz
HD2
TYP
87
80
MAX
UNIT
dBc
dBc
dBc
dBc
dBFS
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7.9 AC Performance: ADC3222
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3222 (fS = 50 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
TYP
DITHER OFF
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
70.9
71.1
70.9
71.1
fIN = 70 MHz
70.7
70.9
fIN = 100 MHz
70.5
70.7
fIN = 170 MHz
70
70.1
fIN = 230 MHz
69.3
69.6
fIN = 10 MHz
70.3
70.5
fIN = 20 MHz
70.1
70.3
fIN = 70 MHz
70.1
70.3
fIN = 100 MHz
69.9
70.2
fIN = 170 MHz
69.5
69.5
fIN = 230 MHz
68.7
69
fIN = 10 MHz
–144.9
–145.1
fIN = 20 MHz
–144.9 –142.5
–145.1
fIN = 70 MHz
–144.7
–144.9
fIN = 100 MHz
–144.5
–144.7
fIN = 170 MHz
–144.0
–144.1
fIN = 230 MHz
–143.3
–143.6
70.8
71
fIN = 20 MHz
Signal-to-noise ratio
(from 1-MHz offset)
SNR
Signal-to-noise ratio
(full Nyquist band)
NSD (1)
Noise spectral density
(averaged across Nyquist zone)
68.5
fIN = 10 MHz
fIN = 20 MHz
SINAD (1)
Signal-to-noise and distortion ratio
70.8
71
fIN = 70 MHz
68
70.6
70.8
fIN = 100 MHz
70.4
70.6
fIN = 170 MHz
69.8
69.9
fIN = 230 MHz
69
69.1
11.5
11.5
11.5
11.5
fIN = 70 MHz
11.4
11.5
fIN = 100 MHz
11.4
11.4
fIN = 170 MHz
11.3
11.3
fIN = 230 MHz
11.2
11.2
89
95
95
91
fIN = 70 MHz
95
93
fIN = 100 MHz
88
86
fIN = 170 MHz
85
83
fIN = 230 MHz
82
81
fIN = 10 MHz
fIN = 20 MHz
ENOB (1)
Effective number of bits
11
fIN = 10 MHz
fIN = 20 MHz
SFDR
(1)
Spurious-free dynamic range
82
dBFS
dBFS/Hz
dBFS
Bits
dBc
Reported from a 1-MHz offset.
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AC Performance: ADC3222 (continued)
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3222 (fS = 50 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
fIN = 10 MHz
Second-order harmonic distortion
94
fIN = 70 MHz
97
94
fIN = 100 MHz
94
93
fIN = 170 MHz
89
89
fIN = 230 MHz
83
83
89
96
94
95
fIN = 70 MHz
95
93
fIN = 100 MHz
88
86
fIN = 170 MHz
85
83
fIN = 230 MHz
83
81
fIN = 10 MHz
99
95
fIN = 20 MHz
Non
HD2, HD3
Spurious-free dynamic range
(excluding HD2, HD3)
IMD3
12
Total harmonic distortion
Two-tone, third-order
intermodulation distortion
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82
101
93
fIN = 70 MHz
99
94
fIN = 100 MHz
100
94
fIN = 170 MHz
99
93
fIN = 230 MHz
97
93
fIN = 10 MHz
89
89
93
87
fIN = 70 MHz
92
88
fIN = 100 MHz
90
86
fIN = 170 MHz
83
81
fIN = 230 MHz
80
78
fIN1 = 45 MHz,
fIN2 = 50 MHz
–95
–92
fIN1 = 185 MHz,
fIN2 = 190 MHz
–92
–92
fIN = 20 MHz
THD
TYP
97
fIN = 20 MHz
Third-order harmonic distortion
MIN
100
82
fIN = 10 MHz
HD3
DITHER OFF
MAX
103
fIN = 20 MHz
HD2
TYP
87
80
MAX
UNIT
dBc
dBc
dBc
dBc
dBFS
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7.10 AC Performance: ADC3223
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3223 (fS = 80 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
TYP
DITHER OFF
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
70.7
70.9
70.6
70.8
fIN = 100 MHz
70.5
70.7
fIN = 170 MHz
70.1
70.3
fIN = 230 MHz
69.7
69.9
fIN = 10 MHz
70.3
70.5
fIN = 70 MHz
70.2
70.5
fIN = 100 MHz
70.1
70.4
fIN = 170 MHz
69.7
69.9
fIN = 70 MHz
Signal-to-noise ratio
(from 1-MHz offset)
SNR
Signal-to-noise ratio
(full Nyquist band)
68.5
fIN = 230 MHz
NSD
(1)
Noise spectral density
(averaged across Nyquist zone)
69.4
69.6
fIN = 10 MHz
–146.7
–146.9
fIN = 70 MHz
–146.6 –144.5
–146.8
fIN = 100 MHz
–146.5
–146.7
fIN = 170 MHz
–146.1
–146.3
fIN = 230 MHz
–145.7
–145.9
70.7
70.9
fIN = 10 MHz
fIN = 70 MHz
SINAD (1)
Signal-to-noise and distortion ratio
70.6
70.8
fIN = 100 MHz
70.5
70.6
fIN = 170 MHz
70
70.2
fIN = 230 MHz
69.5
69.6
fIN = 10 MHz
11.4
11.5
11.4
11.5
fIN = 100 MHz
11.4
11.4
fIN = 170 MHz
11.3
11.4
fIN = 230 MHz
11.3
11.3
88
95
fIN = 70 MHz
ENOB
(1)
Effective number of bits
68.1
11.02
fIN = 10 MHz
fIN = 70 MHz
SFDR
(1)
Spurious-free dynamic range
94
93
fIN = 100 MHz
82
93
92
fIN = 170 MHz
88
87
fIN = 230 MHz
85
84
dBFS
dBFS/Hz
dBFS
Bits
dBc
Reported from a 1-MHz offset.
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AC Performance: ADC3223 (continued)
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3223 (fS = 80 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
fIN = 10 MHz
Second-order harmonic distortion
Third-order harmonic distortion
94
fIN = 100 MHz
95
93
fIN = 170 MHz
88
87
fIN = 230 MHz
85
85
fIN = 10 MHz
89
95
94
94
fIN = 100 MHz
95
96
fIN = 170 MHz
93
90
fIN = 230 MHz
89
85
82
94
93
100
95
fIN = 100 MHz
99
96
fIN = 170 MHz
99
95
fIN = 230 MHz
98
95
fIN = 10 MHz
88
91
fIN = 70 MHz
Spurious-free dynamic range
(excluding HD2, HD3)
fIN = 70 MHz
THD
IMD3
14
Total harmonic distortion
Two-tone, third-order
intermodulation distortion
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TYP
99
82
fIN = 10 MHz
Non
HD2, HD3
MIN
95
fIN = 70 MHz
HD3
DITHER OFF
MAX
104
fIN = 70 MHz
HD2
TYP
87
91
89
fIN = 100 MHz
79.5
91
88
fIN = 170 MHz
86
84
fIN = 230 MHz
83
81
fIN1 = 45 MHz,
fIN2 = 50 MHz
–94
–94
fIN1 = 185 MHz,
fIN2 = 190 MHz
–92
–90
MAX
UNIT
dBc
dBc
dBc
dBc
dBFS
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7.11 AC Performance: ADC3224
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3224 (fS = 125 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
TYP
DITHER OFF
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
70.5
70.8
70.4
70.7
fIN = 100 MHz
70.3
70.6
fIN = 170 MHz
69.9
70.2
fIN = 230 MHz
69.4
69.8
fIN = 10 MHz
70.3
70.6
fIN = 70 MHz
70.2
70.5
fIN = 100 MHz
70.2
70.4
fIN = 170 MHz
69.7
70.0
fIN = 70 MHz
Signal-to-noise ratio
(from 1-MHz offset)
SNR
Signal-to-noise ratio
(full Nyquist band)
68.5
fIN = 230 MHz
NSD
(1)
Noise spectral density
(averaged across Nyquist zone)
69.2
69.6
fIN = 10 MHz
–148.5
–148.8
fIN = 70 MHz
–148.4 –146.5
–148.7
fIN = 100 MHz
–148.3
–148.6
fIN = 170 MHz
–147.9
–148.2
fIN = 230 MHz
–147.4
–147.8
70.5
70.6
fIN = 10 MHz
fIN = 70 MHz
SINAD (1)
Signal-to-noise and distortion ratio
70.4
70.6
fIN = 100 MHz
70.2
70.3
fIN = 170 MHz
69.7
69.9
fIN = 230 MHz
69.2
69.5
fIN = 10 MHz
11.4
11.4
11.4
11.4
fIN = 100 MHz
11.4
11.4
fIN = 170 MHz
11.3
11.3
fIN = 230 MHz
11.2
11.2
93
87
fIN = 70 MHz
ENOB
(1)
Effective number of bits
68
11
fIN = 10 MHz
fIN = 70 MHz
SFDR
(1)
Spurious-free dynamic range
95
89
fIN = 100 MHz
82
89
86
fIN = 170 MHz
86
85
fIN = 230 MHz
83
83
dBFS
dBFS/Hz
dBFS
Bits
dBc
Reported from a 1-MHz offset.
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AC Performance: ADC3224 (continued)
At maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input. Typical values are
specified at an ambient temperature of 25°C. Minimum and maximum values are specified over an ambient temperature
range of –40°C to +85°C (unless otherwise noted).
ADC3224 (fS = 125 MSPS)
DITHER ON
PARAMETER
TEST CONDITIONS
MIN
fIN = 10 MHz
Second-order harmonic distortion
Third-order harmonic distortion
96
fIN = 100 MHz
91
91
fIN = 170 MHz
86
85
fIN = 230 MHz
83
83
fIN = 10 MHz
94
87
95
89
fIN = 100 MHz
91
86
fIN = 170 MHz
96
89
fIN = 230 MHz
88
85
99
96
99
95
fIN = 100 MHz
99
95
fIN = 170 MHz
99
92
fIN = 230 MHz
97
92
fIN = 10 MHz
91
85
fIN = 70 MHz
Spurious-free dynamic range
(excluding HD2, HD3)
fIN = 70 MHz
THD
IMD3
16
Total harmonic distortion
Two-tone, third-order
intermodulation distortion
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TYP
96
84
82
fIN = 10 MHz
Non
HD2, HD3
MIN
96
fIN = 70 MHz
HD3
DITHER OFF
MAX
96
fIN = 70 MHz
HD2
TYP
87
91
86
fIN = 100 MHz
80
87
83
fIN = 170 MHz
85
82
fIN = 230 MHz
82
80
fIN1 = 45 MHz,
fIN2 = 50 MHz
–96
–95
fIN1 = 185 MHz,
fIN2 = 190 MHz
–92
–88
MAX
UNIT
dBc
dBc
dBc
dBc
dBFS
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7.12 Digital Characteristics
the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1; AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)
VIH
High-level input voltage
All digital inputs support 1.8-V and
3.3-V CMOS logic levels
VIL
Low-level input voltage
All digital inputs support 1.8-V and
3.3-V CMOS logic levels
IIH
High-level input
current
Low-level input
current
IIL
RESET, SDATA, SCLK,
PDN
1.3
V
0.4
VHIGH = 1.8 V
10
VHIGH = 1.8 V
0
RESET, SDATA, SCLK,
PDN
VLOW = 0 V
0
SEN
VLOW = 0 V
10
SEN
(1)
V
µA
µA
DIGITAL INPUTS (SYSREFP, SYSREFM)
Differential swing
0.2
0.8
Common-mode voltage for SYSREF (2)
1
V
0.9
V
DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT)
VOH
High-level output voltage
VOL
Low-level output voltage
DVDD – 0.1
DVDD
V
0
0.1
V
DIGITAL OUTPUTS, LVDS INTERFACE
VODH
High-level output differential voltage
With an external
100-Ω termination
280
350
460
mV
VODL
Low-level output differential voltage
With an external
100-Ω termination
–460
–350
–280
mV
VOCM
Output common-mode voltage
(1)
(2)
1.05
V
SEN has an internal 150-kΩ pull-up resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8-V or 3.3-V CMOS buffers.
SYSREF is internally biased to 0.9 V.
7.13 Timing Requirements: General
typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); minimum
and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C
tA
Aperture delay
MIN
TYP
MAX
UNIT
1.24
1.44
1.64
ns
Aperture delay matching between two channels of the same device
Aperture delay variation between two devices at same temperature and supply voltage
tJ
Aperture jitter
Wake-up time
ADC latency (1)
tSU_SYSREF
tH_SYSREF
(1)
SYSREF reference time
±70
ps
±150
ps
130
fS rms
Time to valid data after exiting standby power-down mode
35
65
Time to valid data after exiting global power-down mode
(in this mode, both channels power down)
85
140
2-wire mode (default)
9
1-wire mode
8
Setup time for SYSREF referenced to input clock rising edge
1000
Hold time for SYSREF referenced to input clock rising edge
100
µs
Clock
cycles
ps
Overall latency = ADC latency + tPDI (see Figure 131)
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7.14 Timing Requirements: LVDS Output
typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x serialization (2-wire mode), CLOAD
= 3.3 pF (1), and RLOAD = 100 Ω (2) (unless otherwise noted); minimum and maximum values are across the full temperature
range: TMIN = –40°C to TMAX = 85°C (3) (4)
MIN
TYP
tSU
Data setup time: data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) (5)
MAX
0.43
0.5
ns
tHO
Data hold time: zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid (5)
0.48
0.58
ns
Clock propagation delay: input clock falling edge cross-over to 1-wire mode
frame clock rising edge cross-over
2-wire mode
(15 MSPS < sampling frequency < 125 MSPS)
2.7
4.5
tPDI
tDELAY
Delay time
6.5
0.44 × tS + tDELAY
3
4.5
UNIT
5.9
ns
ns
LVDS bit clock duty cycle: duty cycle of differential clock
(CLKOUTP – CLKOUTM)
49%
tFALL,
tRISE
Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
15 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.11
ns
tCLKRISE,
tCLKFALL
Output clock rise time, output clock fall time: rise time measured from
–100 mV to 100 mV, 10 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.11
ns
(1)
(2)
(3)
(4)
(5)
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Timing parameters are ensured by design and characterization and are not tested in production.
Data valid refers to a logic high of 100 mV and a logic low of –100 mV.
Table 1. LVDS Timing at Lower Sampling Frequencies: 6X Serialization (2-Wire Mode)
SETUP TIME
(tSU, ns)
HOLD TIME
(tHO, ns)
SAMPLING FREQUENCY
(MSPS)
MIN
TYP
MIN
TYP
25
2.61
3.06
2.75
3.12
40
1.69
1.9
1.8
1.98
60
1.11
1.23
1.18
1.31
80
0.81
0.89
0.88
0.97
100
0.6
0.68
0.68
0.77
MAX
MAX
Table 2. LVDS Timings at Lower Sampling Frequencies: 12X Serialization (1-Wire Mode)
SETUP TIME
(tSU, ns)
SAMPLING FREQUENCY
(MSPS)
18
MIN
TYP
25
1.3
40
0.76
50
HOLD TIME
(tHO, ns)
MIN
TYP
1.48
1.32
1.57
0.88
0.79
0.97
0.57
0.68
0.61
0.77
60
0.42
0.55
0.45
0.62
70
0.35
0.44
0.4
0.51
80
0.26
0.35
0.35
0.43
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MAX
MAX
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7.15 Typical Characteristics: ADC3221
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-60
-70
-80
-90
-100
-100
-110
-110
-120
0
2.5
5
7.5
Frequency (MHz)
10
0
12.5
2.5
D801
SFDR = 95.2 dBc, SNR = 71.2 dBFS, SINAD = 71.2 dBFS,
THD = 94.1 dBc, HD2 = 106.0 dBc, HD3 = 95.2 dBc
5
7.5
Frequency (MHz)
10
12.5
D802
SFDR = 90.4 dBc, SNR = 71.6 dBFS, SINAD = 71.5 dBFS,
THD = 88.6 dBc, HD2 = 90.4 dBc, HD3 = 105.5 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
-50
-90
-120
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
2.5
5
7.5
Frequency (MHz)
10
12.5
0
2.5
D803
SFDR = 91.6 dBc, SNR = 71.1 dBFS, SINAD = 71.1 dBFS,
THD = 91 dBc, HD2 = 105.3 dBc, HD3 = 91.6 dBc
5
7.5
Frequency (MHz)
10
12.5
D804
SFDR = 90.6 dBc, SNR = 71.4 dBFS, SINAD = 71.3 dBFS,
THD = 88.4 dBc, HD2 = 90.6 dBc, HD3 = 101.1 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
-40
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
2.5
5
7.5
Frequency (MHz)
10
12.5
D805
0
2.5
5
7.5
Frequency (MHz)
10
12.5
D806
SFDR = 86.8 dBc, SNR = 70.2 dBFS, SINAD = 70.1 dBFS,
THD = 84.8 dBc, HD2 = 89.9 dBc, HD3 = 86.8 dBc
SFDR = 88.2 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS,
THD = 85.7 dBc, HD2 = 88.2 dBc, HD3 = 92.3 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
Copyright © 2014–2019, Texas Instruments Incorporated
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Typical Characteristics: ADC3221 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
2.5
5
7.5
Frequency (MHz)
10
12.5
0
2.5
D807
5
7.5
Frequency (MHz)
10
12.5
D808
SFDR = 75.3 dBc, SNR = 68.7 dBFS, SINAD = 67.7 dBFS,
THD = 73.8 dBc, HD2 = 75.3 dBc, HD3 = 79.8 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 75.7 dBc, SNR = 68.6 dBFS, SINAD = 67.8 dBFS,
THD = 74.9 dBc, HD2 = 75.7 dBc, HD3 = 82.8 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
2.5
5
7.5
Frequency (MHz)
10
12.5
0
2.5
D809
5
7.5
Frequency (MHz)
10
12.5
D810
SFDR = 68.2 dBc, SNR = 66.5 dBFS, SINAD = 66.5 dBFS,
THD = 87.1 dBc, HD2 = 68.2 dBc, HD3 = 92.7 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 68.2 dBc, SNR = 66.6 dBFS, SINAD = 66.6 dBFS,
THD = 92.7 dBc, HD2 = 68.2 dBc, HD3 = 87.8 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
2.5
5
7.5
Frequency (MHz)
10
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 84 dBFS,
each tone at –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
20
-40
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12.5
D811
0
2.5
5
7.5
Frequency (MHz)
10
12.5
D812
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Characteristics: ADC3221 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
2.5
5
7.5
Frequency (MHz)
10
12.5
0
2.5
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 91 dBFS,
each tone at –7 dBFS
10
12.5
D814
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-85
-85
-90
-90
Two-Tone IMD (dBFS)
Two-Tone IMD (dBFS)
5
7.5
Frequency (MHz)
D813
-95
-100
-105
-95
-100
-105
-110
-35
-31
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-110
-35
-7
-31
D815
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-7
D816
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
100
72.5
Dither_EN
Dither_DIS
71.5
Dither_EN
Dither_DIS
95
SFDR (dBc)
SNR (dBFS)
90
70.5
69.5
68.5
85
80
75
70
67.5
65
60
66.5
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D817
Figure 17. Signal-to-Noise Ratio vs Input Frequency
Copyright © 2014–2019, Texas Instruments Incorporated
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D818
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
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Typical Characteristics: ADC3221 (continued)
71.5
200
71
160
70.5
120
70
80
69.5
40
-50
-40
-30
Amplitude (dBFS)
-20
-10
71
150
70
100
69
50
68
-70
0
-60
72
250
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 200
0
0
-60
-50
D819
Figure 19. Performance vs Input Amplitude (30 MHz)
78
-40
-30
Amplitude (dBFS)
-20
-10
D820
Figure 20. Performance vs Input Amplitude (170 MHz)
105
76
88
76
100
74
95
72
90
70
85
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
SNR (dBFS)
SNR
SFDR
SFDR (dBc)
SNR (dBFS)
SNR
SFDR
68
0.85
80
1.1
74
86
72
84
70
82
68
80
66
0.85
D821
Figure 21. Performance vs Input Common-Mode Voltage
(30 MHz)
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
78
1.1
D822
Figure 22. Performance vs Input Common-Mode Voltage
(170 MHz)
102
72
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
100
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
71.6
98
SNR (dBFS)
SFDR (dBc)
0
SFDR (dBc)
69
-70
SNR (dBFS)
72
SNR (dBFS)
73
280
SNR (dBFS)
SFDR (dBc)
240
SFDR (dBFS)
SFDR (dBc,dBFS)
72.5
SFDR (dBc,dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
96
AVDD = 1.85 V
AVDD = 1.9 V
71.2
70.8
94
70.4
92
90
-40
-15
10
35
Temperature (°C)
60
85
D823
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
22
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70
-40
-15
10
35
Temperature (°C)
60
85
D824
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Characteristics: ADC3221 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
72
99
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
98
71.6
SNR (dBFS)
97
SFDR (dBc)
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
96
DVDD = 1.85 V
DVDD = 1.9 V
71.2
70.8
95
70.4
94
10
35
Temperature (°C)
60
70
-40
85
Figure 25. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
75
76
85
D826
74
96
SNR
SFDR 92
72
88
72
92.5
70
84
71
90
68
80
70
87.5
66
76
69
85
64
72
68
82.5
62
68
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
2
SNR (dBFS)
95
SFDR (dBc)
SNR (dBFS)
60
73
67
0.2
80
2.2
60
0.2
71.5
96
70.9
94
70.7
92
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
90
70
D829
Figure 29. Performance vs Clock Duty Cycle (30 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
SNR (dBFS)
71.1
64
2.2
D828
90
SNR
SFDR
70.4
SFDR (dBc)
98
2
70.6
100
71.3
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
Figure 28. Performance vs Differential Clock Amplitude
(150 MHz)
SNR
SFDR
70.5
30
0.4
D827
Figure 27. Performance vs Differential Clock Amplitude
(40 MHz)
SNR (dBFS)
10
35
Temperature (°C)
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
100
SNR
SFDR 97.5
74
-15
D825
SFDR (dBc)
-15
88
70.2
86
70
84
69.8
82
69.6
80
69.4
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
SFDR (dBc)
93
-40
78
70
D830
Figure 30. Performance vs Clock Duty Cycle (150 MHz)
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7.16 Typical Characteristics: ADC3222
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-70
-80
-90
-100
-110
-110
-120
5
10
15
Frequency (MHz)
20
0
25
5
D601
SFDR = 88.5 dBc, SFDR = 99.8 dBc (non 23), SNR = 71.1 dBFS,
SINAD = 71 dBFS, THD = 88.1 dBc, HD2 = 109.9 dBc,
HD3 = 88.5 dBc
-10
-20
-20
-30
-30
Amplitude (dBFS)
0
-10
-50
-60
-70
-80
20
25
D602
Figure 32. FFT for 10-MHz Input Signal (Dither Off)
0
-40
10
15
Frequency (MHz)
SFDR = 84.6 dBc, SFDR = 96.1 dBc (non 23), SNR = 71.4 dBFS,
SINAD = 71.1 dBFS, THD = 83.2 dBc, HD2 = 91.6 dBc,
HD3 = 84.6 dBc
Figure 31. FFT for 10-MHz Input Signal (Dither On)
Amplitude (dBFS)
-60
-100
0
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
5
10
15
Frequency (MHz)
20
25
0
5
D603
SFDR = 101.6 dBc, SFDR = 100.3 dBc (non 23),
SNR = 70.9 dBFS, SINAD = 70.9 dBFS, THD = 98.1 dBc,
HD2 = 106.6 dBc, HD3 = 101.6 dBc
-10
-20
-20
-30
-30
Amplitude (dBFS)
0
-10
-50
-60
-70
-80
25
D604
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
20
Figure 34. FFT for 70-MHz Input Signal (Dither Off)
0
-40
10
15
Frequency (MHz)
SFDR = 90.2 dBc, SFDR = 94.7 dBc (non 23), SNR = 71.2 dBFS,
SINAD = 71.1 dBFS, THD = 86.7 dBc, HD2 = 90.6 dBc,
HD3 = 90.2 dBc
Figure 33. FFT for 70-MHz Input Signal (Dither On)
Amplitude (dBFS)
-50
-90
-120
-120
0
5
10
15
Frequency (MHz)
20
25
D605
SFDR = 85.9 dBc, SFDR = 99.1 dBc (non 23), SNR = 70.4 dBFS,
SINAD = 70.2 dBFS, THD = 84.8 dBc, HD2 = 92.7 dBc,
HD3 = 85.9 dBc
Figure 35. FFT for 170-MHz Input Signal (Dither On)
24
-40
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0
5
10
15
Frequency (MHz)
20
25
D606
SFDR = 89.3 dBc, SFDR = 93 dBc (non 23), SNR = 70.7 dBFS,
SINAD = 70.6 dBFS, THD = 85.8 dBc, HD2 = 89.3 dBc,
HD3 = 111.9 dBc
Figure 36. FFT for 170-MHz Input Signal (Dither Off)
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Characteristics: ADC3222 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
5
10
15
Frequency (MHz)
20
25
0
5
D607
SFDR = 74.7 dBc, SFDR = 95.2 dBc (non 23), SNR = 69.2 dBFS,
SINAD = 68.1 dBFS, THD = 73.7 dBc, HD2 = 74.7 dBc,
HD3 = 80.9 dBc
-10
-20
-20
-30
-30
Amplitude (dBFS)
0
-10
-50
-60
-70
-80
20
25
D608
Figure 38. FFT for 270-MHz Input Signal (Dither Off)
0
-40
10
15
Frequency (MHz)
SFDR = 74.5 dBc, SFDR = 91.1 dBc (non 23), SNR = 69.4 dBFS,
SINAD = 68.1 dBFS, THD = 72.9 dBc, HD2 = 74.5 dBc,
HD3 = 78.2 dBc
Figure 37. FFT for 270-MHz Input Signal (Dither On)
Amplitude (dBFS)
-40
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
5
10
15
Frequency (MHz)
20
25
0
5
D609
10
15
Frequency (MHz)
20
25
D610
SFDR = 68.1 dBc, SNR = 67.7 dBFS, SINAD = 67.6 dBFS,
THD = 86.6 dBc, HD2 = 68.1 dBc, HD3 = 87.3 dBc
Figure 39. FFT for 450-MHz Input Signal (Dither On)
Figure 40. FFT for 450-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 68.2 dBc, SNR = 67.4 dBFS, SINAD = 67.3 dBFS,
THD = 86.4 dBc, HD2 = 68.2 dBc, HD3 = 87.3 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
5
10
15
Frequency (MHz)
20
25
D611
0
5
10
15
Frequency (MHz)
20
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 85.4 dBFS,
each tone at –7 dBFS
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 103 dBFS,
each tone at –36 dBFS
Figure 41. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 42. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
25
D612
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25
ADC3221, ADC3222, ADC3223, ADC3224
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www.ti.com
Typical Characteristics: ADC3222 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
5
10
15
Frequency (MHz)
20
25
0
5
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 95 dBFS,
each tone at –7 dBFS
-80
-80
-85
-85
Two-Tone IMD (dBFS)
Two-Tone IMD (dBFS)
25
D614
Figure 44. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-90
-95
-100
-105
-90
-95
-100
-105
-31
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-110
-35
-7
-31
D615
Figure 45. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-7
D616
Figure 46. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
100
72
Dither_EN
Dither_DIS
Dither_EN
Dither_DIS
95
71
90
SFDR (dBc)
SNR (dBFS)
20
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 43. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
-110
-35
10
15
Frequency (MHz)
D613
70
69
85
80
75
70
68
65
60
67
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D617
Figure 47. Signal-to-Noise Ratio vs Input Frequency
26
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0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D618
Figure 48. Spurious-Free Dynamic Range vs
Input Frequency
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
ADC3221, ADC3222, ADC3223, ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Characteristics: ADC3222 (continued)
71
160
70.5
120
70
80
69.5
40
71.5
240
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 200
71
160
70.5
120
70
80
69.5
40
0
-60
-50
-40
-30
-20
Input Amplitude (dBFS)
-10
69
-70
0
0
-60
-50
D619
Figure 49. Performance vs Input Amplitude (30 MHz)
78
-40
-30
Amplitude (dBFS)
-20
-10
D620
Figure 50. Performance vs Input Amplitude (170 MHz)
94
76
88
76
92
74
90
72
88
70
86
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
SNR (dBFS)
SNR
SFDR
SFDR (dBc)
SNR (dBFS)
SNR
SFDR
68
0.85
0
84
1.1
74
86
72
84
70
82
68
80
66
0.85
D621
Figure 51. Performance vs Input Common-Mode Voltage
(30 MHz)
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
SFDR (dBc)
69
-70
72
SNR (dBFS)
71.5
240
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 200
SFDR (dBc,dBFS)
SNR (dBFS)
72
SFDR (dBc,dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
78
1.1
D622
Figure 52. Performance vs Input Common-Mode Voltage
(170 MHz)
72
96
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
94
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
71.6
AVDD = 1.85 V
AVDD = 1.9 V
90
SNR (dBFS)
SFDR (dBc)
92
88
86
71.2
70.8
84
70.4
82
80
-40
-15
10
35
Temperature (°C)
60
85
D623
Figure 53. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
70
-40
-15
10
35
Temperature (°C)
60
85
D624
Figure 54. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
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ADC3221, ADC3222, ADC3223, ADC3224
SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
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Typical Characteristics: ADC3222 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
72
92
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
71.6
90
SNR (dBFS)
SFDR (dBc)
91
DVDD = 1.85 V
DVDD = 1.9 V
89
DVDD = 1.85 V
DVDD = 1.9 V
71.2
70.8
88
70.4
87
10
35
Temperature (°C)
60
70
-40
85
Figure 55. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
71
86
69
84
67
82
65
80
63
78
61
0.2
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
2
77
SNR (dBFS)
73
90
SNR
SFDR 88
76
2.2
86
71
84
69
82
67
80
65
78
63
76
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
90
70.7
88
70.5
86
84
70
D629
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SNR (dBFS)
70.9
Figure 59. Performance vs Clock Duty Cycle (30 MHz)
28
D628
70.6
SFDR (dBc)
SNR (dBFS)
92
65
74
2.2
90
SNR
SFDR
71.1
45
50
55
60
Input Clock Duty Cycle (%)
2
Figure 58. Performance vs Differential Clock Amplitude
(150 MHz)
94
40
D626
73
SNR
SFDR
35
85
90
SNR
SFDR 88
61
0.2
Figure 57. Performance vs Differential Clock Amplitude
(40 MHz)
70.3
30
60
75
D627
71.3
10
35
Temperature (°C)
Figure 56. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
SFDR (dBc)
SNR (dBFS)
75
-15
D625
SFDR (dBc)
-15
70.4
88
70.2
86
70
84
69.8
82
69.6
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
SFDR (dBc)
86
-40
80
70
D630
Figure 60. Performance vs Clock Duty Cycle (150 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
ADC3221, ADC3222, ADC3223, ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
7.17 Typical Characteristics: ADC3223
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
8
16
24
Frequency (MHz)
32
0
40
8
D401
16
24
Frequency (MHz)
32
40
D402
SFDR = 83.9 dBc, SNR = 71.1 dBFS, SINAD = 70.9 dBFS,
THD = 82.6 dBc, HD2 = 91.8 dBc, HD3 = 83.9 dBc
Figure 61. FFT for 10-MHz Input Signal (Dither On)
Figure 62. FFT for 10-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 88.9 dBc, SNR = 70.9 dBFS, SINAD = 70.8 dBFS,
THD = 88.6 dBc, HD2 = 108.1 dBc, HD3 = 88.9 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
8
16
24
Frequency (MHz)
32
40
0
8
D403
16
24
Frequency (MHz)
32
40
D404
SFDR = 85.5 dBc, SNR = 71.1 dBFS, SINAD = 70.9 dBFS,
THD = 83.8 dBc, HD2 = 91.9 dBc, HD3 = 85.5 dBc
Figure 63. FFT for 70-MHz Input Signal (Dither On)
Figure 64. FFT for 70-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 91.6 dBc, SNR = 70.8 dBFS, SINAD = 70.8 dBFS,
THD = 91 dBc, HD2 = 112.2 dBc, HD3 = 91.6 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
8
16
24
Frequency (MHz)
32
40
D405
0
8
16
24
Frequency (MHz)
32
40
D406
SFDR = 95.8 dBc, SNR = 70.4 dBFS, SINAD = 70.3 dBFS,
THD = 92.9 dBc, HD2 = 102.1 dBc, HD3 = 95.8 dBc
SFDR = 91.0 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 88 dBc, HD2 = 91.0 dBc, HD3 = 97.2 dBc
Figure 65. FFT for 170-MHz Input Signal (Dither On)
Figure 66. FFT for 170-MHz Input Signal (Dither Off)
Copyright © 2014–2019, Texas Instruments Incorporated
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Typical Characteristics: ADC3223 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
8
16
24
Frequency (MHz)
32
40
0
8
D407
16
24
Frequency (MHz)
32
40
D408
SFDR = 75.6 dBc, SNR = 69.7 dBFS, SINAD = 68.6 dBFS,
THD = 74.5 dBc, HD2 = 75.6 dBc, HD3 = 81.6 dBc
Figure 67. FFT for 270-MHz Input Signal (Dither On)
Figure 68. FFT for 270-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 75.8 dBc, SNR = 69.4 dBFS, SINAD = 68.5 dBFS,
THD = 74.6 dBc, HD2 = 75.8 dBc, HD3 = 80.9 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
8
16
24
Frequency (MHz)
32
40
0
8
D409
16
24
Frequency (MHz)
32
40
D410
SFDR = 78.4 dBc, SNR = 67.9 dBFS, SINAD = 67.5 dBFS,
THD = 77 dBc, HD2 = 78.4 dBc, HD3 = 84.3 dBc
Figure 69. FFT for 450-MHz Input Signal (Dither On)
Figure 70. FFT for 450-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 77.7 dBc, SNR = 67.7 dBFS, SINAD = 67.3 dBFS,
THD = 77.2 dBc, HD2 = 77.7 dBc, HD3 = 89.0 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
30
-40
8
16
24
Frequency (MHz)
32
40
D411
0
8
16
24
Frequency (MHz)
32
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 87.5 dBFS,
each tone at –7 dBFS
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 71. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 72. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
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40
D412
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
ADC3221, ADC3222, ADC3223, ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Characteristics: ADC3223 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-60
-70
-80
-90
-100
-100
-110
-110
-120
0
8
16
24
Frequency (MHz)
32
40
0
8
16
24
Frequency (MHz)
D413
32
40
D414
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 89 dBFS,
each tone at –7 dBFS
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 73. FFT FOR Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 74. FFT FOR Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-80
-85
-85
Two-Tone IMD (dBFS)
-90
Two-Tone IMD (dBFS)
-50
-90
-120
-95
-100
-105
-110
-35
-90
-95
-100
-105
-31
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-110
-35
-7
-31
D415
Figure 75. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-7
D416
Figure 76. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
100
72
Dither_EN
Dither_DIS
Dither_EN
Dither_DIS
95
SFDR (dBc)
71
SNR (dBFS)
-40
70
69
90
85
80
68
75
70
67
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D417
Figure 77. Signal-to-Noise Ratio vs Input Frequency
Copyright © 2014–2019, Texas Instruments Incorporated
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D418
Figure 78. Spurious-Free Dynamic Range vs
Input Frequency
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31
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Typical Characteristics: ADC3223 (continued)
71
160
70.5
120
70
80
69.5
40
71
180
SNR (dBFS)
SFDR (dBc)
160
SFDR (dBFS)
140
70.5
120
70
100
71.5
69.5
80
69
60
68.5
40
0
-60
-50
-40
-30
Amplitude (dBFS)
-20
-10
68
-70
0
20
-60
-50
D419
Figure 79. Performance vs Input Amplitude (30 MHz)
76
-40
-30
Amplitude (dBFS)
-20
-10
D421
D420
Figure 80. Performance vs Input Amplitude (170 MHz)
92
76
92
74
90
72
88
70
86
68
84
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
SNR (dBFS)
SNR
SFDR
SFDR (dBc)
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
66
0.85
82
1.1
72
88
70
86
68
84
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
82
1.1
D422
D420
D421
71
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
70.6
SNR (dBFS)
93
SFDR (dBc)
90
Figure 82. Performance vs Input Common-Mode Voltage
(170 MHz)
95
91
89
87
AVDD = 1.85 V
AVDD = 1.9 V
70.2
69.8
69.4
-15
10
35
Temperature (°C)
60
85
D423
Figure 83. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
32
74
66
0.85
Figure 81. Performance vs Input Common-Mode Voltage
(30 MHz)
85
-40
0
SFDR (dBc)
69
-70
72
SNR (dBFS)
71.5
240
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 200
SFDR (dBc,dBFS)
SNR (dBFS)
72
SFDR (dBc,dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
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69
-40
-15
10
35
Temperature (°C)
60
85
D424
Figure 84. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: ADC3221 ADC3222 ADC3223 ADC3224
ADC3221, ADC3222, ADC3223, ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Characteristics: ADC3223 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
71
95
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
70.6
SNR (dBFS)
91
89
70.2
69.8
69.4
87
-15
10
35
Temperature (°C)
60
69
-40
85
Figure 85. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
72.5
99
70.5
98
70
97
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
2
SNR (dBFS)
71
93
90
70
87
68
84
66
81
0.4
D427
Figure 87. Performance vs Differential Clock Amplitude
(40 MHz)
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
92
88
70.7
86
70.5
84
65
82
70
D429
Figure 89. Performance vs Clock Duty Cycle (30 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
SNR (dBFS)
70.9
45
50
55
60
Input Clock Duty Cycle (%)
D428
70.8
SFDR (dBc)
SNR (dBFS)
90
40
78
2.2
92
SNR
SFDR
71.1
35
2
Figure 88. Performance vs Differential Clock Amplitude
(150 MHz)
SNR
SFDR
70.3
30
D426
72
64
0.2
96
2.2
71.3
85
SNR
SFDR
SFDR (dBc)
SNR (dBFS)
100
60
74
101
71.5
10
35
Temperature (°C)
Figure 86. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
102
SNR
SFDR
72
-15
D425
SFDR (dBc)
85
-40
69.5
0.2
DVDD = 1.85 V
DVDD = 1.9 V
70.6
90
70.4
88
70.2
86
70
84
69.8
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
SFDR (dBc)
SFDR (dBc)
93
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
82
70
D430
Figure 90. Performance vs Clock Duty Cycle (150 MHz)
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7.18 Typical Characteristics: ADC3224
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
0
62.5
SFDR = 101.1 dBc, SNR = 70.6 dBFS, SINAD = 70.6 dBFS,
THD = 97.6 dBc, HD2 = 107.0 dBc, HD3 = 106.0 dBc
50
62.5
D202
Figure 92. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
25
37.5
Frequency (MHz)
SFDR = 90.6 dBc, SNR = 70.9 dBFS, SINAD = 70.8 dBFS,
THD = 86 dBc, HD2 = 91.8 dBc, HD3 = 90.6 dBc
Figure 91. FFT for 10 MHz Input Signal
(Chopper On, Dither On)
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
0
12.5
D203
25
37.5
Frequency (MHz)
50
62.5
D204
SFDR = 91.1 dBc, SNR = 70.8 dBFS, SINAD = 70.8 dBFS,
THD = 86.8 dBc, HD2 = 91.1 dBc, HD3 = 95.1 dBc
Figure 93. FFT for 70-MHz Input Signal (Dither On)
Figure 94. FFT for 70-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 99.2 dBc, SNR = 70.5 dBFS, SINAD = 70.5 dBFS,
THD = 94.8 dBc, HD2 = 102.9 dBc, HD3 = 99.2 dBc
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
34
12.5
D201
12.5
25
37.5
Frequency (MHz)
50
62.5
D205
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D206
SFDR = 93.6 dBc, SNR = 70.0 dBFS, SINAD = 70.0 dBFS,
THD = 91.4 dBc, HD2 = 93.6 dBc, HD3 = 101.3 dBc
SFDR = 90.6 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS,
THD = 87.8 dBc, HD2 = 98.6 dBc, HD3 = 90.6 dBc
Figure 95. FFT for 170-MHz Input Signal (Dither On)
Figure 96. FFT for 170 MHz Input Signal (Dither Off)
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Typical Characteristics: ADC3224 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
0
12.5
D207
25
37.5
Frequency (MHz)
50
62.5
D208
SFDR = 76.1 dBc, SNR = 69.7 dBFS, SINAD = 68.8 dBFS,
THD = 74.9 dBc, HD2 = 76.1 dBc, HD3 = 81.5 dBc
Figure 97. FFT for 270-MHz Input Signal (Dither On)
Figure 98. FFT for 270-MHz Input Signal (Dither Off)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
SFDR = 76.2 dBc, SNR = 69.4 dBFS, SINAD = 68.6 dBFS,
THD = 74.9 dBc, HD2 = 76.2 dBc, HD3 = 81.2 dBc
-40
-50
-60
-70
-80
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
0
12.5
D209
SFDR = 75.5 dBc, SNR = 67.4 dBFS, SINAD = 66.7 dBFS,
THD = 73.8 dBc, HD2 = 75.5 dBc, HD3 = 78.7 dBc
-10
-20
-20
-30
-30
Amplitude (dBFS)
0
-10
-50
-60
-70
-80
50
62.5
D210
Figure 100. FFT for 450-MHz Input Signal (Dither Off)
0
-40
25
37.5
Frequency (MHz)
SFDR = 75.2 dBc, SNR = 68 dBFS, SINAD = 67.0 dBFS,
THD = 72.5 dBc, HD2 = 76.5 dBc, HD3 = 75.2 dBc
Figure 99. FFT for 450-MHz Input Signal (Dither On)
Amplitude (dBFS)
-40
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88 dBFS,
each tone at –7 dBFS
Figure 101. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
D211
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D212
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 102. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
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Typical Characteristics: ADC3224 (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
0
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 87.5 dBFS,
each tone at –7 dBFS
-80
-85
-85
Two-Tone IMD (dBFS)
Two-Tone IMD (dBFS)
-80
-90
-95
-100
62.5
D214
-90
-95
-100
-105
-31
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-110
-35
-7
-31
D215
Figure 105. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-7
D216
Figure 106. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
100
72
Dither_EN
Dither_DIS
Dither_EN
Dither_DIS
95
SFDR (dBc)
71
SNR (dBFS)
50
Figure 104. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-105
70
69
90
85
80
68
75
70
67
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D217
Figure 107. Signal-to-Noise Ratio vs Input Frequency
36
25
37.5
Frequency (MHz)
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 96.5 dBFS,
each tone at –36 dBFS
Figure 103. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
-110
-35
12.5
D213
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0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
D218
Figure 108. Spurious-Free Dynamic Range vs
Input Frequency
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Typical Characteristics: ADC3224 (continued)
71
160
70.5
120
70
80
69.5
40
71
180
SNR (dBFS)
SFDR (dBc)
160
SFDR (dBFS)
140
70.5
120
70
100
71.5
69.5
80
69
60
68.5
40
0
-60
-50
-40
-30
Amplitude (dBFS)
-20
-10
68
-70
0
20
-60
-50
D219
Figure 109. Performance vs Input Amplitude (30 MHz)
76
-40
-30
Amplitude (dBFS)
-20
92
SNR (dBFS)
SFDR (dBc)
72
92
70
90
68
88
SNR (dBFS)
94
SFDR (dBc)
SNR (dBFS)
74
0.95
1
1.05
Input Common-Mode Voltage (V)
74
90
72
88
70
86
68
84
66
0.85
86
1.1
D221
Figure 111. Performance vs Input Common-Mode Voltage
(30 MHz)
0.9
0.95
1
1.05
Input Common-Mode Voltage (V)
82
1.1
D001
D222
Figure 112. Performance vs Input Common-Mode Voltage
(170 MHz)
92
72
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
71.2
SFDR (dBc)
90
SFDR (dBc)
D220
Figure 110. Performance vs Input Amplitude (170 MHz)
SNR
SFDR
0.9
0
76
96
66
0.85
-10
SFDR (dBc)
69
-70
72
SNR (dBFS)
71.5
240
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 200
SFDR (dBc,dBFS)
SNR (dBFS)
72
SFDR (dBc,dBFS)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
88
86
84
AVDD = 1.85 V
AVDD = 1.9 V
70.4
69.6
68.8
82
-40
-15
10
35
Temperature (°C)
60
85
D223
Figure 113. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
Copyright © 2014–2019, Texas Instruments Incorporated
68
-40
-15
10
35
Temperature (°C)
60
85
D224
Figure 114. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
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Typical Characteristics: ADC3224 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
71
92
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
70.6
SNR (dBFS)
88
86
70.2
69.8
69.4
84
-15
10
35
Temperature (°C)
60
69
-40
85
Figure 115. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
94
SNR (dBFS)
93
71.5
92
71
91
70.5
90
70
89
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
2
73
SNR (dBFS)
SNR
SFDR
86
70
84
69
82
68
80
67
78
66
76
0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
Differential Clock Amplitude (Vpp)
92
70.3
90
69.9
88
86
70
D229
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SNR (dBFS)
70.7
Figure 119. Performance vs Clock Duty Cycle (30 MHz)
38
D228
70.5
SFDR (dBc)
SNR (dBFS)
94
65
74
2.2
90
SNR
SFDR
71.1
45
50
55
60
Input Clock Duty Cycle (%)
2
Figure 118. Performance vs Differential Clock Amplitude
(150 MHz)
96
40
D226
71
SNR
SFDR
35
85
90
SNR
SFDR 88
D227
Figure 117. Performance vs Differential Clock Amplitude
(40 MHz)
69.5
30
60
72
65
0.2
88
2.2
71.5
10
35
Temperature (°C)
Figure 116. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
SFDR (dBc)
72.5
72
-15
D225
SFDR (dBc)
82
-40
69.5
0.2
DVDD = 1.85 V
DVDD = 1.9 V
70.3
87.5
70.1
85
69.9
82.5
69.7
80
69.5
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
SFDR (dBc)
SFDR (dBc)
90
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
77.5
70
D230
Figure 120. Performance vs Clock Duty Cycle (150 MHz)
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7.19 Typical Characteristics: Common
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted).
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
-5
-10
Amplitude (dBFS)
-15
CMRR (dB)
-20
-25
-30
-35
-40
-45
-50
-55
-60
0
50
100
150
200
250
Frequency of Input Common-Mode Signal (MHz)
0
300
50
62.5
D006
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP,
SINAD = 69.66 dBFS, SFDR = 75.66 dBc
Figure 121. Common-Mode Rejection Ratio vs
Common-Mode Signal Frequency
Figure 122. Common-Mode Rejection Ratio Spectrum
0
-10
Amplitude (dBFS)
-15
PSRR (dB)
25
37.5
Frequency (MHz)
fIN = 30 MHz, AIN = –1 dBFS,
common-mode signal amplitude = 50 mVPP
-5
-20
-25
-30
-35
-40
-45
-50
0
12.5
D005
50
100
150
200
250
Frequency of Signal on Supply (MHz)
300
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
D007
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
25
37.5
Frequency (MHz)
50
62.5
D008
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP,
SINAD = 58.51 dBFS, SFDR = 60.53 dBc
Figure 123. Power-Supply Rejection Ratio vs
Power-Supply Signal Frequency
Figure 124. Power-Supply Rejection Ratio Spectrum
200
180
AVDD POWER
DVDD POWER
TOTAL POWER
Power (mW)
160
140
120
100
80
60
40
10
20
30
40
50
60
Sampling Speed (MSPS)
70
80
D009
Figure 125. Power vs Sampling Speed
(One-Wire Mode)
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7.20 Typical Characteristics: Contour
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when is chopper enabled (unless otherwise noted).
90
110
Sampling Frequency, MSPS
80
85
120
80
90
100
75
90
90
85
80
75
80
70
70
60
90
50
85
40
30
90
50
100
150
70
75
80
200
250
300
Input Frequency, MHz
70
75
350
80
400
450
85
90
Figure 126. Spurious-Free Dynamic Range (SFDR)
120
70.5
Sampling Frequency, MSPS
110
69.5
70
69
68.5
100
68
90
80
70.5
70
69.5
70
69
68.5
60
68
50
40
30
70.5
71
50
66.5
100
67
69.5
70
150
67.5
68.5
69
200
250
300
Input Frequency, MHz
68
68.5
69
67.5
68
69.5
350
67
400
70
70.5
450
71
Figure 127. Signal-to-Noise Ratio (SNR)
40
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8 Parameter Measurement Information
8.1 Timing Diagrams
DAn_P
DBn_P
Logic 0
Logic 1
VODL = -410 mV
(1)
VODH = +410 mV
(1)
DAn_M
DBn_M
VOCM
GND
(1)
With an external 100-Ω termination.
Figure 128. Serial LVDS Output Voltage Levels
CLKIN
FCLK
DCLK
1-Wire (12x Serialization)
Dx0P
Dx0M
D
9
D
10
D
11
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
0
DCLK
Dx0P
Dx0M
Dx1P
Dx1M
SAMPLE N-1
D
5
D
0
D
1
D
2
D
3
D
4
D
5
D
0
D
11
D
6
D
7
D
8
D
9
D
10
D
11
D
6
SAMPLE N
2-Wire (6x Serialization)
SAMPLE N+1
Figure 129. Output Timing Diagram
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Timing Diagrams (continued)
DCLK
t HO
Dx0P
Dx0M
t SU
Figure 130. Setup and Hold Time
N+10
N+1
N+9
Sample N
TA
Input Signal
on INxP, INxM Pins
Data Latency(1) = 9 Input Clock Cycles
Sample N
CLKINP,
CLKINM
tPDI
FCLKP,
FCLKM
DCLKP,
DCLKM
(1)
DCLK edges are centered within the data valid
window.
DA0P, DA0M,
DB0P, DB0M
4
5 0
1
2
3
DA1P, DA1M,
DB1P, DB1M
10 11 6
7
8
9 10 11
tsu
th
4
5
Sample N
4
5
0
1
2
3
6
7
8
9 10 11
Sample N+1
Overall latency = data latency + tPDI.
Figure 131. Latency Diagram
42
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9 Detailed Description
9.1 Overview
The devices are designed specifically to support demanding, high input frequency signals with large dynamic
range requirements. An input clock divider allows more flexibility for system clock architecture design while the
SYSREF input enables complete system synchronization by resetting the clock divider. The ADC322x family
supports serial LVDS interface in order to reduce the number of interface lines, thus allowing for high system
integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over
two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the
bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams,
the frame and bit clocks are also transmitted as LVDS outputs.
9.2 Functional Block Diagram
INAP
INAM
12-Bit
ADC
CLKP
CLKM
DA0P
DA0M
Digital Encoder
and Serializer
Divide by
1,2,4
DA1P
DA1M
Bit Clock
DCLKP
DCLKM
PLL
Frame Clock
SYSREFP
SYSREFM
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DB1P
DB1M
SDOUT
SDATA
SCLK
Configuration Registers
RESET
Common
Mode
DB0P
DB0M
Digital Encoder
and Serializer
PDN
VCM
12-Bit
ADC
SEN
INBP
INBM
FCLKP
FCLKM
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9.3 Feature Description
9.3.1 Analog Inputs
The ADC322x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing
symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing.
The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving a 50-Ω
termination between INP and INM).
9.3.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC322x can be driven by the transformercoupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in
Figure 132, Figure 133, and Figure 134. See Figure 135 for details regarding the internal clock buffer.
0.1 …F
0.1 …F
ZO
CLKP
Differential
Sine-Wave
Clock Input
0.1 …F
RT
CLKP
Typical LVDS
Clock Input
TI Device
100 Ÿ
TI Device
0.1 …F
ZO
CLKM
CLKM
RT = termination resistor, if necessary.
Figure 132. Differential Sine-Wave Clock Driving
Circuit
ZO
Figure 133. LVDS Clock Driving Circuit
0 …F
CLKP
150 Ÿ
Typical LVPECL
Clock Input
100 Ÿ
ZO
TI Device
0 …F
CLKM
150 Ÿ
Figure 134. LVPECL Clock Driving Circuit
44
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Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
5 kW
CEQ
CEQ
RESR
100 W
1.4 V
LPKG
2 nH
20 W
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 135. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 136. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 …F
CMOS
Clock Input
CLKP
TI Device
0.1 …F
CLKM
Figure 136. Single-Ended Clock Driving Circuit
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9.3.2.1 Using the SYSREF Input
The ADC344x has a SYSREF input pin that can be used when the clock-divider feature is used. A logic low-tohigh transition on the SYSREF pin aligns the falling edge of the divided clock with the next falling edge of the
input clock, essentially resetting the phase of the divided clock, as shown in Figure 137. When multiple ADC344x
devices are onboard and the clock divider option is used, the phase of the divided clock among the devices may
not be the same. The phase of the divided clock in each device can be synchronized to the common sampling
clock by using the SYSREF pins. SYSREF can applied as mono-shot or periodic waveform. When applied as
periodic waveform, its period must be integer multiple of period of the divided clock. When not used, the
SYSREFP and SYSREFM pins can be connected to AVDD and GND, respectively. Alternatively, the SYSREF
buffer inside the device can be powered down using the PDN SYSREF register bit.
TI Device
Input Clock
(CLKP-CLKM)
Clock Divider
(Divide-by-2,
-4)
Divided Clock
SYSREF
(SYSREFP-SYSREFM)
SYSREF is sampled by this edge.
The falling edge of the input clock
and the divided clock are aligned
after a sampling low-to-high
transition on SYSREF.
SYSREF
Input Clock
Divided
Clock
Copyright © 2016, Texas Instruments Incorporated
Figure 137. Using SYSREF for Synchronization
9.3.2.2 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization
noise (typically 74 dB for a 12-bit ADC) and thermal noise limit SNR at low input frequencies, and clock jitter sets
SNR for higher input frequencies.
SNR ADC [dBc]
§
20 ˜ log ¨ 10
¨
©
SNRQuantization _ Noise
20
·
¸
¸
¹
2
§
¨ 10
¨
©
SNRThermal _ Noise
20
·
¸
¸
¹
2
§
¨10
¨
©
SNRJitter
20
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.
SNRJitter [dBc]
20 ˜ log 2S ˜ fin ˜ t Jitter
·
¸
¸
¹
2
(1)
(2)
The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device), which is set by
the noise of the clock input buffer, and the external clock. TJitter can be calculated with Equation 3.
t Jitter
t Jitter,Ext.Clock _ Input
2
t Aperture _ ADC
2
(3)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input and a faster clock slew rate improves ADC aperture jitter. The devices have a typical
thermal noise of 73.5 dBFS and an internal aperture jitter of 130 fs. The SNR, depending on the amount of
external jitter for different input frequencies. Figure 138 shows SNR (from 1 MHz offset leaving the 1/f flicker
noise) for different jitter of clock driver.
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72
Ext Clock Jitter
35 fs
50 fs
100 fs
150 fs
200 fs
71
SNR (dBFS)
70
69
68
67
66
65
64
10
100
Input Frequency (MHz)
1000
Figure 138. SNR vs Frequency for Different Clock Jitter
9.3.3 Digital Output Interface
The devices offer two different output format options, thus making interfacing to a field-programmable gate array
(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using
the serial interface, as shown in Table 3. The output interface options are:
• One-wire, 1X frame clock, 12X serialization with the DDR bit clock and
• Two-wire, 1X frame clock, 6X serialization with the DDR bit clock.
Table 3. Interface Rates
MAXIMUM RECOMMENDED SAMPLING
FREQUENCY (MSPS)
INTERFACE
OPTIONS
One-wire
Two-wire
(1)
SERIALIZATIO
N
12X
6X
MIN
MAX
BIT CLOCK
FREQUENCY
(MHz)
FRAME
CLOCK
FREQUENCY
(MHz)
SERIAL DATA
RATE PER
WIRE (Mbps)
90
15
180
65
390
65
780
60
20
120
125
375
125
750
15 (1)
20
(1)
Use the LOW SPEED ENABLE register bits for low speed operation; see Table 22.
9.3.3.1 One-Wire Interface: 12X Serialization
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The
data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at
the rising edge of every frame clock, starting with the MSB. The data rate is a 12X sample frequency (12X
serialization).
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9.3.3.2 Two-Wire Interface: 6X Serialization
The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is a 6X
sample frequency because six data bits are output every clock cycle on each differential pair. Each ADC sample
is sent over the two wires with the six MSBs on Dx1P, Dx1M and the six LSBs on Dx0P, Dx0M, as shown in
Figure 139.
CLKIN
FCLK
DCLK
1-Wire (12x Serialization)
Dx0P
Dx0M
D
9
D
10
D
11
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
0
DCLK
Dx0P
Dx0M
Dx1P
Dx1M
D
5
D
0
D
1
D
2
D
3
D
4
D
5
D
0
D
11
D
6
D
7
D
8
D
9
D
10
D
11
D
6
SAMPLE N-1
SAMPLE N
2-Wire (6x Serialization)
SAMPLE N+1
Figure 139. Output Timing Diagram
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9.4 Device Functional Modes
9.4.1 Input Clock Divider
The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a
faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for
operation with a 125-MHz clock; the divide-by-2 option supports a maximum input clock of 250 MHz and the
divide-by-4 option provides a maximum input clock frequency of 500 MHz.
9.4.2 Chopper Functionality
0
0
-20
-20
-40
-40
Attenuation (dB)
Attenuation (dB)
The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC
noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 140 shows the noise spectrum with the chopper
off and Figure 141 shows the noise spectrum with the chopper on. This function is especially useful in
applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper
can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper
function creates a spur at fS / 2 that must be filtered out digitally.
-60
-80
-100
-60
-80
-100
-120
-120
0
10
20
30
40
Frequency (MHz)
50
60
0
10
D016
fS = 125 MSPS, fIN = 10 MHz
20
30
40
Frequency (MHz)
50
60
D017
fS = 125 MSPS, fIN = 10 MHz
Figure 140. Chopper Off
Figure 141. Chopper On
9.4.3 Power-Down Control
The power-down functions of the ADC322x can be controlled either through the parallel control pin (PDN) or
through an SPI register setting (see register 15h). The PDN pin can also be configured via the SPI to a global
power-down or standby functionality, as shown in Table 4.
Table 4. Power-Down Modes
FUNCTION
POWER CONSUMPTION (mW)
WAKE-UP TIME (µs)
Global power-down
5
85
Standby
81
35
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9.4.3.1 Improving Wake-Up Time From Global Power-Down
The device has an internal low-pass filter in the sampling clock path. This low-pass filter helps improve the
aperture jitter of the device. However, in applications where input frequencies are < 200 MHz, noise from the
aperture jitter does not dominate the overall SNR of the device. In such applications, the wake-up time from a
global power-down can be reduced by bypassing the low-pass filter using the DIS CLK FILT register bit (write
80h to register address 70Ah). As shown in Table 5, setting the DIS CLK FILT bit improves the wake-up time
from a global power-down from 85 µs to 55 µs.
Table 5. Wake-Up Time From Global Power-Down
WAKE-UP TIME
DIS CLK FILT
REGISTER BIT
GLOBAL PDN
REGISTER BIT
TYP
MAX
UNIT
0
0→1→0
85
140
µs
1
0→1→0
55
81
µs
9.4.4 Internal Dither Algorithm
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
The ADC322x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither
algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm
can be turned off by using the DIS DITH CHx registers bits. Figure 142 and Figure 143 show the effect of using
dither algorithms.
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
0
12.5
25
37.5
Frequency (MHz)
50
fS = 125 MSPS, SNR = 70.5 dBFS, fIN = 70 MHz,
SFDR = 99.2 dBc
Figure 142. FFT with Dither On
62.5
D203
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D204
fS = 125 MSPS, SNR = 70.8 dBFS, fIN = 70 MHz,
SFDR = 91.1 dBc
Figure 143. FFT Dither Off
9.5 Programming
The ADC322x can be configured using a serial programming interface, as described in this section.
9.5.1 Serial Interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are
ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can
function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%
SCLK duty cycle.
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Programming (continued)
9.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 144. If required,
the serial interface registers can be cleared during operation either:
1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
9.5.1.1.1 Serial Register Write
The device internal register can be programmed with these steps:
1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be
written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.
Figure 144 and Table 6 show the timing requirements for the serial register write operation.
Register Address [13:0]
SDATA
R/W
1
A13
A12
A11
A1
Register Data [7:0]
A0
D7
D6
D5
D4
=0
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 144. Serial Register Write Timing Diagram
Table 6. Serial Interface Timing (1)
MIN
TYP
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDIO setup time
25
ns
tDH
SDIO hold time
25
ns
(1)
> dc
MAX
Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise
noted.
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9.5.1.1.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A[13:0]) whose content must be read.
5. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.
When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the
SDOUT pin must float. Figure 145 shows a timing diagram of the serial register read operation. Data appear on
the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 146.
Register Address [13:0]
SDATA
R/W
1
A13
A12
A11
A1
Register Data: 'RQ¶W &DUH
A0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
=1
Register Read Data [7:0]
SDOUT
D7
D6
D5
D4
D3
D2
SCLK
SEN
Figure 145. Serial Register Read Timing Diagram
SCLK
tSD_DELAY
SDOUT
Figure 146. SDOUT Timing Diagram
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9.5.2 Register Initialization through SPI
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in Figure 147 and Table 7.
Power
Supplies
t1
RESET
t2
t3
SEN
Figure 147. Initialization of Serial Registers after Power-Up
Table 7. Power-Up Timing
MIN
t1
Power-on delay from power up to active high RESET pulse
t2
t3
TYP
MAX
UNIT
1
ms
Reset pulse duration: active high RESET pulse duration
10
ns
Register write delay from RESET disable to SEN active
100
ns
If required, the serial interface registers may be cleared during operation either:
1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
to high. This setting initializes the internal registers to the default values and then self-resets the RESET bit
low. In this case, the RESET pin is kept low.
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9.6 Register Maps
Table 8. Register Map Summary
REGISTER
ADDRESS
REGISTER DATA
A[13:0] (Hex)
7
6
Register 01h
0
0
Register 03h
0
0
Register 04h
0
Register 05h
0
5
4
3
0
0
0
0
0
0
0
ODD EVEN
0
0
0
0
0
0
FLIP WIRE
0
0
0
0
0
0
1W-2W
TEST PATTERN
EN
RESET
DIS DITH CHA
1
DIS DITH CHB
0
Register 06h
0
0
0
0
0
0
Register 07h
0
0
0
0
0
0
0
OVR ON LSB
0
ALIGN TEST
PATTERN
DATA FORMAT
Register 09h
0
0
0
0
Register 0Ah
0
0
0
0
Register 0Bh
CHB TEST PATTERN
0
CHA TEST PATTERN
0
Register 0Eh
0
0
0
0
0
0
0
LOW SPEED ENABLE
CUSTOM PATTERN[11:4]
Register 0Fh
CUSTOM PATTERN[3:0]
0
Register 13h
0
0
0
0
0
0
Register 15h
0
CHA PDN
CHB PDN
0
STANDBY
GLOBAL PDN
0
CONFIG PDN PIN
Register 25h
LVDS SWING
Register 27h
CLK DIV
0
0
0
0
0
0
Register 41Dh
0
0
0
0
0
0
HIGH IF MODE0
0
Register 422h
0
0
0
0
0
0
DIS CHOP CHA
0
Register 434h
0
0
DIS DITH CHA
0
DIS DITH CHA
0
0
0
Register 439h
0
0
0
0
SP1 CHA
0
0
0
Register 51Dh
0
0
0
0
0
0
HIGH IF MODE1
0
Register 522h
0
0
0
0
0
0
DIS CHOP CHB
0
Register 534h
0
0
DIS DITH CHB
0
DIS DITH CHB
0
0
0
Register 539h
0
0
0
0
SP1 CHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN SYSREF
Register 608h
Register 70Ah
54
2
HIGH IF MODE[3:2]
DIS CLK FILT
0
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9.6.1 Summary of Special Mode Registers
Table 9 lists the location, value, and functions of special mode registers in the device.
Table 9. Special Modes Summary
MODE
REGISTER SETTINGS
DESCRIPTION
Special modes
Registers 439h (bit 3) and 539h (bit 3)
Always set these bits high for best performance
Disable dither
Registers 1h (bits 5-2), 434h (bits 5 and 3), and
534h (bits 5 and 3)
Disable dither to improve SNR
Disable chopper
Registers 422h (bit 1) and 522h (bit 1)
Disable chopper to shift 1/f noise floor at dc
High IF modes
Registers 41Dh (bit 1), 51Dh (bit 1), and
608h (bits 7-6)
Improves HD3 for IF > 100 MHz
9.6.2 Serial Register Description
9.6.2.1 Register 01h
Figure 148. Register 01h
7
0
W-0h
6
0
W-0h
5
4
3
DIS DITH CHA
R/W-0h
2
1
0
W-0h
DIS DITH CHB
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 10. Register 01h Description
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
0h
These bits enable or disable the on-chip dither.
Control this bit with bits 5 and 3 of register 434h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
5-4
DIS DITH CHA
R/W
3-2
DIS DITH CHB
R/W
0h
These bits enable or disable the on-chip dither.
Control this bit with bits 5 and 3 of register 434h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
1-0
0
W
0h
Must write 0
9.6.2.2 Register 03h
Figure 149. Register 03h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
ODD EVEN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 11. Register 03h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
ODD EVEN
R/W
0h
This bit selects the bit sequence on the output wires
(in 2-wire mode only).
0 = Bits 0, 1, and 2 appear on wire 0; bits 7, 8, and 9 appear on wire 1
1 = Bits 0, 2, and 4 appear on wire 0; bits 1, 3, and 5 appear on wire 1
0
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9.6.2.3 Register 04h
Figure 150. Register 04h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
FLIP WIRE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 12. Register 04h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0h
This bit flips the data on the output wires. Valid only in two wire
configuration.
0 = Default
1 = Data on output wires is flipped. Pin D0x becomes D1x, and
vice versa.
0
FLIP WIRE
R/W
9.6.2.4 Register 05h
Figure 151. Register 05h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
1W-2W
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 13. Register 05h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0h
This bit transmits output data on either one or two wires.
0 = Output data are transmitted on two wires (Dx0P, Dx0M and
Dx1P, Dx1M)
1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this
mode, the recommended fS is less than 62.5 MSPS.
0
1W-2W
R/W
9.6.2.5 Register 06h
Figure 152. Register 06h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
TEST PATTERN EN
R/W-0h
0
RESET
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 14. Register 06h Description
56
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
TEST PATTERN EN
R/W
0h
This bit enables test pattern selection for the digital outputs.
0 = Normal output
1 = Test pattern output enabled
0
RESET
W
0h
This bit applies a software reset.
This bit resets all internal registers to the default values and selfclears to 0.
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9.6.2.6 Register 07h
Figure 153. Register 07h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
OVR ON LSB
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 15. Register 07h Description
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
OVR ON LSB
R/W
0h
This bit provides the overrange (OVR) information on the LSB bits.
0 = Output data bit 0 functions as the LSB of the 12-bit data
1 = Output data bit 0 carries the OVR information.
0
9.6.2.7 Register 09h
Figure 154. Register 09h
7
6
5
4
3
2
0
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
1
ALIGN TEST
PATTERN
R/W-0h
0
DATA FORMAT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 16. Register 09h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
ALIGN TEST PATTERN
R/W
0h
This bit aligns the test patterns across the outputs of both channels.
0 = Test patterns of both channels are free running
1 = Test patterns of both channels are aligned
0
DATA FORMAT
R/W
0h
This bit programs the digital output data format.
0 = Twos complement
1 = Offset binary
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9.6.2.8 Register 0Ah
Figure 155. Register 0Ah
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
CHA TEST PATTERN
R/W-0h
0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 17. Register 0Ah Description
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
0h
These bits control the test pattern for channel A after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 101010101010 and
010101010101
0100 = Digital ramp: data increment by 1 LSB every clock cycle from
code 0 to 4095
0101 = Custom pattern: output data are the same as programmed by
the CUSTOM PATTERN register bits
0110 = Deskew pattern: data are AAAh
1000 = PRBS pattern: data are a sequence of pseudo random
numbers
1001 = 8-point sine-wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 599, 2048, 3496,
4095, 3496, 2048, and 599
Others = Do not use
3-0
CHA TEST PATTERN
R/W
9.6.2.9 Register 0Bh
Figure 156. Register 0Bh
7
6
5
CHB TEST PATTERN
R/W-0h
4
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 18. Register 0Bh Description
Bit
58
Field
Type
Reset
Description
7-4
CHB TEST PATTERN
R/W
0h
These bits control the test pattern for channel B after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 101010101010 and
010101010101
0100 = Digital ramp: data increment by 1 LSB every clock cycle from
code 0 to 4095
0101 = Custom pattern: output data are the same as programmed by
the CUSTOM PATTERN register bits
0110 = Deskew pattern: data are AAAh
1000 = PRBS pattern: data are a sequence of pseudo random
numbers
1001 = 8-point sine-wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 599, 2048, 3496,
4095, 3496, 2048, and 599
Others = Do not use
3-0
0
W
0h
Must write 0
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9.6.2.10 Register 0Eh
Figure 157. Register 0Eh
7
6
5
4
3
CUSTOM PATTERN[11:4]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Register 0Eh Description
Bit
Field
Type
Reset
Description
7-0
CUSTOM PATTERN[11:4]
R/W
0h
These bits set the 12-bit custom pattern (bits 11-4) for all channels.
9.6.2.11 Register 0Fh
Figure 158. Register 0Fh
7
6
5
CUSTOM PATTERN[3:0]
R/W-0h
4
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 20. Register 0Fh Description
Bit
Field
Type
Reset
Description
7-4
CUSTOM PATTERN[3:0]
R/W
0h
These bits set the 12-bit custom pattern (bits 3-0) for all channels.
3-0
0
W
0h
Must write 0
9.6.2.12 Register 13h
Figure 159. Register 13h
7
0
W-0h
6
0
R/W-0h
5
0
R/W-0h
4
0
W-0h
3
0
R/W-0h
2
0
R/W-0h
1
0
LOW SPEED ENABLE
W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 21. Register 13h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
LOW SPEED ENABLE
R/W
0h
Enables low speed operation in 1-wire and 2-wire mode. Depending
upon sampling frequency, write this bit as per Table 22.
Table 22. LOW SPEED ENABLE Register Bit Settings Across fS
fS (MSPS)
REGISTER BIT LOW SPEED ENABLE
MIN
MAX
1-WIRE MODE
2-WIRE MODE
25
125
00
00
20
25
10
11
15
20
10
Not supported
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9.6.2.13 Register 15h
Figure 160. Register 15h
7
0
W-0h
6
CHA PDN
R/W-0h
5
CHB PDN
R/W-0h
4
0
W-0h
3
STANDBY
R/W-0h
2
GLOBAL PDN
R/W-0h
1
0
W-0h
0
CONFIG PDN PIN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 23. Register 15h Description
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
CHA PDN
R/W
0h
0 = Normal operation
1 = Power-down channel A
5
CHB PDN
R/W
0h
0 = Normal operation
1 = Power-down channel B
4
0
W
0h
Must write 0
3
STANDBY
R/W
0h
The ADCs of both channels enter standby.
0 = Normal operation
1 = Standby
2
GLOBAL PDN
R/W
0h
0 = Normal operation
1 = Global power-down
1
0
W
0h
Must write 0
0h
This bit configures the PDN pin as either a global power-down or
standby pin.
0 = Logic high voltage on the PDN pin sends the device into global
power-down
1 = Logic high voltage on the PDN pin sends the device into standby
0
CONFIG PDN PIN
R/W
9.6.2.14 Register 25h
Figure 161. Register 25h
7
6
5
4
3
2
1
0
LVDS SWING
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Register 25h Description
Bit
Field
Type
Reset
Description
7-0
LVDS SWING
R/W
0h
These bits control the swing of the LVDS outputs (including the
data output, bit clock, and frame clock). For details see
Table 25.
Table 25. LVDS Output Swing
60
BITS 7-4
BITS 3-0
0h
0h
Default (±425 mV)
Dh
9h
Swing reduces by 50 mV
Eh
Ah
Swing reduces by 100 mV
Fh
Dh
Swing reduces by 300 mV
Ch
Eh
Swing increases by 100 mV
Others
Others
Do not use
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9.6.2.15 Register 27h
Figure 162. Register 27h
7
6
CLK DIV
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 26. Register 27h Description
Bit
Field
Type
Reset
Description
7-6
CLK DIV
R/W
0h
These bits set the internal clock divider for the input sampling clock.
00 = Divide-by-1
01 = Divide-by-1
10 = Divide-by-2
11 = Divide-by-4
5-0
0
W
0h
Must write 0
9.6.2.16 Register 41Dh
Figure 163. Register 41Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
HIGH IF MODE0
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 27. Register 41Dh Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
HIGH IF MODE0
R/W
0h
This bit improves HD3 for IF > 100 MHz.
0 = Normal operation
For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.
0
0
W
0h
Must write 0
9.6.2.17 Register 422h
Figure 164. Register 422h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
DIS CHOP CHA
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 28. Register 422h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
DIS CHOP CHA
R/W
0h
Disable chopper.
Set this bit to shift a 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered at
dc
0
0
W
0h
Must write 0
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9.6.2.18 Register 434h
Figure 165. Register 434h
7
0
W-0h
6
0
W-0h
5
DIS DITH CHA
R/W-0h
4
0
W-0h
3
DIS DITH CHA
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 29. Register 434h Description
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
5
DIS DITH CHA
R/W
0h
Set this bit with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
4
0
W
0h
Must write 0
3
DIS DITH CHA
R/W
0h
Set this bit with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
0
W
0h
Must write 0
2-0
9.6.2.19 Register 439h
Figure 166. Register 439h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
SP1 CHA
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 30. Register 439h Description
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
SP1 CHA
R/W
0h
Special mode for best performance on channel A.
Always write 1 after reset.
0
W
0h
Must write 0
3
2-0
9.6.2.20 Register 51Dh
Figure 167. Register 51Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
HIGH IF MODE1
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 31. Register 51Dh Description
62
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
HIGH IF MODE1
R/W
0h
This bit improves HD3 for IF > 100 MHz.
0 = Normal operation
For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.
0
0
W
0h
Must write 0
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9.6.2.21 Register 522h
Figure 168. Register 522h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
DIS CHOP CHB
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 32. Register 522h Description
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
DIS CHOP CHB
R/W
0h
Disable chopper.
Set this bit to shift a 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
0
0
W
0h
Must write 0
9.6.2.22 Register 534h
Figure 169. Register 534h
7
0
W-0h
6
0
W-0h
5
DIS DITH CHA
R/W-0h
4
0
W-0h
3
DIS DITH CHA
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 33. Register 534h Description
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
5
DIS DITH CHA
R/W
0h
Set this bit with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
4
0
W
0h
Must write 0
3
DIS DITH CHA
R/W
0h
Set this bit with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz.
0
W
0h
Must write 0
2-0
9.6.2.23 Register 539h
Figure 170. Register 539h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
SP1 CHB
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 34. Register 539h Description
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3
SP1 CHB
R/W
0h
Special mode for best performance on channel B.
Always write 1 after reset.
0
0
W
0h
Must write 0
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9.6.2.24 Register 608h
Figure 171. Register 608h
7
6
HIGH IF MODE[3:2]
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 35. Register 608h Description
Bit
Field
Type
Reset
Description
7-6
HIGH IF MODE[3:2]
R/W
0h
This bit improves HD3 for IF > 100 MHz.
0 = Normal operation
For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.
5-0
0
W
0h
Must write 0
9.6.2.25 Register 70Ah
Figure 172. Register 70Ah
7
DIS CLK FILT
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
PDN SYSREF
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 36. Register 70Ah Description
Bit
7
6-1
0
64
Field
Type
Reset
Description
DIS CLK FILT
R/W
0h
Set this bit to improve wake-up time from global power-down
mode; see the Improving Wake-Up Time From Global PowerDown section for details.
0
W
0h
Must write 0
0h
If the SYSREF pins are not used in the system, the SYSREF
buffer must be powered down by setting this bit.
0 = Normal operation
1 = Powers down the SYSREF buffer
PDN SYSREF
R/W
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at the ADC
inputs. When designing the dc-driving circuits, the ADC input impedance must be considered. Figure 173 and
Figure 174 show the impedance (Zin = Rin || Cin) across the ADC input pins.
6
Differential Capacitance, Cin (pF)
Differential Resistance, Rin (kOhm)
10
1
0.1
5
4
3
2
1
0.01
0
100
200
300
400 500 600 700
Frequency (MHz)
800
900 1000
Figure 173. Differential Input Resistance (RIN)
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D024
0
100
200
300
400 500 600 700
Frequency (MHz)
800
900 1000
D025
D001
Figure 174. Differential Input Capacitance (CIN)
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10.2 Typical Applications
10.2.1 Driving Circuit Design: Low Input Frequencies
0.1 µF
0.1 µF
INP
50
50 Ÿ
25 Ÿ
TI Device
0.1 µF
22 pF
25 Ÿ
50 Ÿ
50
1:1
1:1
INM
0.1 µF
VCM
Figure 175. Driving Circuit for Low Input Frequencies
10.2.1.1 Design Requirements
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in
series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may
have to be designed to minimize the affect of kick-back noise generated by sampling switches opening and
closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched
impedance to the source.
10.2.1.2 Detailed Design Procedure
A typical application involving using two back-to-back coupled transformers is shown in Figure 175. This circuit is
optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used
with the series inductor (39 nH); this combination helps absorb the sampling glitches.
To improve phase and amplitude balance of first transformer, the termination resistors can be split between two
transformers. For example, 25-Ω to 25-Ω termination across the secondary winding of the second transformer
can be changed to 50-Ω to 50-Ω termination and another 50-Ω to 50-Ω resistor can be placed inside the dashed
box between the transformers in Figure 175.
10.2.1.3 Application Curve
Figure 176 shows the performance obtained by using the circuit shown in Figure 175.
0
-10
-20
Amplitude (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D201
fS = 125 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz, SFDR = 101.1 dBc
Figure 176. Performance FFT at 10 MHz (Low Input Frequency)
66
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
Typical Applications (continued)
10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
0.1 µF
10
0.1 µF
INP
0.1 pF
15 Ÿ
25 Ÿ
TI Device
10 pF
56 nH
25 Ÿ
15 Ÿ
1:1
1:1
INM
10
0.1 µF
VCM
Figure 177. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)
10.2.2.1 Design Requirements
See the Design Requirements section for further details.
10.2.2.2 Detailed Design Procedure
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize
performance, as shown in Figure 177.
10.2.2.3 Application Curve
Figure 178 shows the performance obtained by using the circuit shown in Figure 177.
0
-10
-20
Amplitude (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D205
fS = 125 MSPS, SNR = 70 dBFS, fIN = 170 MHz, SFDR = 93.6 dBc
Figure 178. Performance FFT at 170 MHz (Mid Input Frequency)
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
www.ti.com
Typical Applications (continued)
10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
0.1 µF
0.1 µF
10 Ÿ
INP
0.1 µF
25
TI Device
25
10 Ÿ
INM
1:1
1:1
0.1 µF
VCM
Figure 179. Driving Circuit for High Input Frequencies (fIN > 230 MHz)
10.2.3.1 Design Requirements
See the Design Requirements section for further details.
10.2.3.2 Detailed Design Procedure
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant
improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 179.
10.2.3.3 Application Curve
Figure 180 shows the performance obtained by using the circuit shown in Figure 179.
0
-10
-20
Amplitude (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
Frequency (MHz)
50
62.5
D209
fS = 125 MSPS, SNR = 67.4 dBFS, fIN = 450 MHz, SFDR = 75.5 dBc
Figure 180. Performance FFT at 450 MHz (High Input Frequency)
11 Power Supply Recommendations
The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply
requirements during device power-up. AVDD and DVDD can power up in any order.
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ADC3221, ADC3222, ADC3223, ADC3224
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
12 Layout
12.1 Layout Guidelines
The ADC322x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram
of the EVM top layer is provided in Figure 181. Some important points to remember during laying out the board
are:
1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the
package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions,
as shown in the reference layout of Figure 181 as much as possible.
2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 181
as much as possible.
3. Keep digital outputs away from analog inputs. When these digital outputs exit the pin out, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver (such
as an FPGA or an ASIC) must be matched in length to avoid skew among outputs.
4. At each power-supply pin (AVDD and DVDD), a 0.1-µF decoupling capacitor must be kept close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and
0.1-µF capacitors can be kept close to the supply source.
12.2 Layout Example
Analog
Input
Routing
Sampling
Clock
Routing
ADC32xx
Digital
Output
Routing
Figure 181. Typical Layout of the ADC322x Board
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SBAS672D – JULY 2014 – REVISED SEPTEMBER 2019
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 37. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADC3221
Click here
Click here
Click here
Click here
Click here
ADC3222
Click here
Click here
Click here
Click here
Click here
ADC3223
Click here
Click here
Click here
Click here
Click here
ADC3224
Click here
Click here
Click here
Click here
Click here
13.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC3221IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3221
ADC3221IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3221
ADC3222IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3222
ADC3222IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3222
ADC3223IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3223
ADC3223IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3223
ADC3224IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3224
ADC3224IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ3224
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADC3221IRGZR
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3221IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3222IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3222IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3223IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3223IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3224IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADC3224IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC3221IRGZR
VQFN
RGZ
48
2500
350.0
350.0
43.0
ADC3221IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADC3222IRGZR
VQFN
RGZ
48
2500
350.0
350.0
43.0
ADC3222IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADC3223IRGZR
VQFN
RGZ
48
2500
350.0
350.0
43.0
ADC3223IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADC3224IRGZR
VQFN
RGZ
48
2500
350.0
350.0
43.0
ADC3224IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
7 x 7, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048D
VQFN - 1 mm max height
SCALE 1.900
PLASTIC QUAD FLATPACK - NO LEAD
7.1
6.9
B
A
0.5
0.3
PIN 1 INDEX AREA
7.1
6.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
5.6
0.1
2X 5.5
(0.2) TYP
13
44X 0.5
24
12
25
EXPOSED
THERMAL PAD
2X
5.5
49
SYMM
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
36
37
48
SYMM
48X
0.5
0.3
48X
0.30
0.18
0.1
0.05
C A B
4219046/B 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 5.6)
SYMM
48
37
48X (0.6)
1
36
48X (0.24)
6X
(1.22)
44X (0.5)
10X
(1.33)
49
SYMM
(6.8)
(R0.05)
TYP
( 0.2) TYP
VIA
25
12
24
13
10X (1.33)
6X (1.22)
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219046/B 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.665 TYP)
(1.33) TYP
16X ( 1.13)
37
48
48X (0.6)
49
1
36
48X (0.24)
44X (0.5)
(1.33)
TYP
(0.665)
TYP
SYMM
(6.8)
(R0.05) TYP
25
12
METAL
TYP
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4219046/B 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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