Texas Instruments | ADS1283 High-Resolution, Analog-to-Digital Converter (Rev. C) | Datasheet | Texas Instruments ADS1283 High-Resolution, Analog-to-Digital Converter (Rev. C) Datasheet

Texas Instruments ADS1283 High-Resolution, Analog-to-Digital Converter (Rev. C) Datasheet
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ADS1283
SBAS565C – JANUARY 2014 – REVISED AUGUST 2019
ADS1283 High-Resolution, Analog-to-Digital Converter
1 Features
3 Description
•
The ADS1283 is an extremely high-performance,
single-chip, analog-to-digital converter (ADC) with an
integrated, low-noise programmable gain amplifier
(PGA) and two-channel input multiplexer (mux). The
ADS1283 is suitable for the demanding needs of
seismic monitoring equipment.
1
•
•
•
•
•
•
•
•
•
•
High Resolution:
– SNR: 130 dB (250 SPS, PGA = 1)
High Accuracy:
– THD: –122 dB
Low Power Consumption:
– 18 mW (PGA = 1, 2, 4, or 8)
– Shutdown Mode: 10 μW
Low-Noise PGA: 5 nV/√Hz
Two-Channel Input Multiplexer
Inherently-Stable Modulator With Fast Responding
Overrange Detector
Flexible Digital Filter:
– Sinc + FIR + IIR (Selectable)
– Linear or Minimum Phase Response
– Programmable High-Pass Filter
– Selectable FIR Data Rates:
250 SPS to 4 kSPS
Offset and Gain Calibration Engine
SYNC Input
Analog Supply: 5 V or ±2.5 V
Digital Supply: 1.8 V to 3.3 V
Energy Exploration
Seismic Monitoring
High-Accuracy Instrumentation
Mux
Input 1
Input 2
PGA
VREFN VREFP
4th-Order
û
Modulator
Calibration
Serial
Interface
CLK
ADS1283A
CS
ADS1283B
Control
Control
DOUT
DRDY
SYNC
PWDN
DGND
VQFN (24)
5.00 mm × 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Device Comparison
RESET
AVSS
BODY SIZE (NOM)
SCLK
DIN
ADS1283
PACKAGE
ADS1283
VCOM
Overrange
The synchronization input (SYNC) can be used to
synchronize the conversions of multiple ADS1283
devices.
PART NUMBER
DVDD
Programmable
Digital
Filter
The digital filter provides selectable data rates from
250 to 4000 samples per second (SPS). The highpass filter (HPF) features an adjustable corner
frequency. On-chip gain and offset scaling registers
support system calibration.
Device Information(1)
Simplified Schematic
AVDD
The flexible input mux provides an additional external
input for measurement, as well as internal self-test
input connections. The PGA features outstanding low
noise (5 nV/√Hz) and very-high input impedance,
allowing easy interfacing to geophones and
hydrophones over a wide range of gains.
The ADS1283 is available in a compact 24-lead, 5mm × 4-mm VQFN package, and is fully specified
from –40°C to +85°C, with a maximum operating
temperature range of –50°C to +125°C.
2 Applications
•
•
•
The converter uses a fourth-order, inherently stable,
delta-sigma (ΔΣ) modulator that provides outstanding
noise and linearity performance. The modulator digital
output is digitally filtered and decimated by the onchip digital filter to yield the ADC conversion result.
PART NUMBER
OFFSET OPTION
THD (TYP)
GAIN
ADS1283
100 mV
–122 dB
1 to 64
ADS1283A
100 mV
–118 dB
1, 4, 16
ADS1283B
75 mV, 100 mV
–122 dB
1 to 64
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1283
SBAS565C – JANUARY 2014 – REVISED AUGUST 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
1
1
1
2
4
5
Absolute Maximum Ratings .................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements............................................... 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
7
Parameter Measurement Information ................ 14
8
Detailed Description ............................................ 15
7.1 Noise Performance ................................................. 14
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
15
16
16
32
44
48
Application and Implementation ........................ 52
9.1 Application Information............................................ 52
9.2 Typical Applications ................................................ 52
9.3 Initialization Set Up ................................................. 55
10 Device and Documentation Support ................. 56
10.1
10.2
10.3
10.4
10.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
56
56
56
56
56
11 Mechanical, Packaging, and Orderable
Information ........................................................... 56
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2017) to Revision C
•
Page
Changed document to release full version to web ................................................................................................................. 1
Changes from Revision A (May 2015) to Revision B
Page
•
Added ADS1283B device and related content to data sheet ................................................................................................. 1
•
Added Device Information and Device Comparison tables .................................................................................................... 1
•
Added Recommended Operating Conditions table; content moved from Electrical Characteristics table. No values
changed .................................................................................................................................................................................. 5
•
Deleted ADS1283A text from test condition in Electrical Characteristic table........................................................................ 6
•
Added new row for ADS1283B test condition to Offset parameter in the Electrical Characteristics table............................. 7
•
Added Switching Characteristics table; content moved from Timing Requirements table. No values changed .................... 9
•
Changed text in Offset section for 75-mV option ................................................................................................................. 22
•
Changed Figure 45 to include CLK to SYNC timing ............................................................................................................ 32
•
Deleted tCSHD and tSCSU from Table 12 ................................................................................................................................ 32
•
Added CLK to SYNC timing to Table 12 .............................................................................................................................. 32
•
Changed text in last paragraph of Pulse-Sync Mode section ............................................................................................. 33
•
Changed pulse-sync timing text to include CLK to SYNC timing ........................................................................................ 33
•
Changed Figure 46 to include CLK to SYNC timing ........................................................................................................... 33
•
Changed opcode text of WREG command from 001 to 010 ............................................................................................... 47
•
Added new OFFSET control bit to ID_CFG (register 00h) for ADS1283B device; no change to ADS1283 and
ADS1283A functionality ........................................................................................................................................................ 48
•
Changed format of register description tables ..................................................................................................................... 48
2
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Changes from Original (January 2014) to Revision A
Page
•
Added ADS1283A device and related content to data sheet ................................................................................................. 1
•
Added text regarding CS high to Read Data Requirement section. .................................................................................... 44
•
Added text regarding CS high to SDATAC: Stop Read Data Continuous section ............................................................... 45
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ADS1283
SBAS565C – JANUARY 2014 – REVISED AUGUST 2019
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5 Pin Configuration and Functions
SCLK
CLK
BYPAS
DGND
DVDD
24
23
22
21
20
RHF Package
5-mm × 4-mm 24-Pin VQFN
Top View
DRDY
1
19
RESET
DOUT
2
18
PWDN
DIN
3
17
VREFP
Thermal
CS
4
16
VREFN
SYNC
5
15
AVSS
MFLAG
6
14
AVDD
DGND
7
13
AINN1
12
AINP1
11
10
AINP2
AINN2
9
CAPP
CAPN
8
Pad
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AINN1
13
Analog input
Negative analog input 1
AINN2
11
Analog input
Negative analog input 2
AINP1
12
Analog input
Positive analog input 1
AINP2
10
Analog input
Positive analog input 2
AVDD
14
Analog supply
Positive analog power supply
AVSS
15
Analog supply
Negative analog power supply
BYPAS
22
Analog
1.8-V sub-regulator output: connect 1-μF capacitor to DGND
CAPN
8
Analog
PGA output: connect 10-nF capacitor from CAPP to CAPN
CAPP
9
Analog
PGA output: connect 10-nF capacitor from CAPP to CAPN
CLK
23
Digital input
Master clock input (4.096 MHz)
CS
4
Digital input
Serial interface chip select, active low
DGND
7
Ground
Digital ground (tie to digital ground plane)
DGND
21
Ground
Digital ground (tie to digital ground plane)
DIN
3
Digital input
DOUT
2
Digital output
Serial Interface data output
DRDY
1
Digital output
Data ready output: active low
DVDD
20
Digital supply
Digital power supply: 1.65 V to 3.6 V
MFLAG
6
Digital output
Modulator overrange flag: 0 = normal, 1 = modulator overrange
PWDN
18
Digital input
Power-down input, active low
RESET
19
Digital input
Reset input, active low
SCLK
24
Digital input
Serial interface shift clock input
SYNC
5
Digital input
Synchronize input, rising edge active
VREFN
16
Analog input
Negative reference input
VREFP
17
Analog input
Positive reference input
Thermal pad
4
Serial interface data input
Do not electrically connect the thermal pad. The thermal pad must be soldered to PCB.
Thermal pad vias are optional and can be removed.
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6 Specifications
Absolute Maximum Ratings (1)
6.1
Over operating free-air temperature range (unless otherwise noted).
MIN
MAX
UNIT
AVDD to AVSS
–0.3
5.5
V
AVSS to DGND
–2.8
0.3
V
DVDD to DGND
–0.3
3.9
V
AVSS – 0.3
AVDD + 0.3
V
Digital input voltage to DGND
–0.3
DVDD + 0.3
V
Input current, continuous
–10
10
mA
Operating temperature
–50
125
°C
150
°C
150
°C
Analog input voltage
Junction temperature
Storage temperature, Tstg
(1)
–60
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVSS
Negative analog supply (relative to DGND)
AVDD
Positive analog supply (relative to AVSS)
DVDD
Digital supply (relative to DGND)
–2.6
0
V
AVSS + 4.75
AVSS + 5.25
V
1.65
3.6
V
106
%FSR
ANALOG INPUTS
FSR
Full-scale input voltage range (VIN = AINP – AINN)
±VREF / (2 × PGA)
V
Calibration margin (1)
AINP or
AINN
Absolute input voltage range
AVSS + 0.7
AVDD – 1.25
V
(AVDD – AVSS) + 0.2
V
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF = VREFP – VREFN)
1
5
VREFN
Negative reference input
AVSS – 0.1
VREFP – 1
V
VREFP
Positive reference input
VREFN + 1
AVDD + 0.1
V
V
DIGITAL INPUTS
VIH
High-level input voltage
0.8 × DVDD
DVDD
VIL
Low-level input voltage
DGND
0.2 × DVDD
fCLK
Clock input
1
4.096
MHz
fSCLK
Serial clock rate
fCLK / 2
MHz
V
TEMPERATURE
Specified temperature
(1)
–40
85
°C
Calibration margin is the maximum allowable input voltage after user calibration of offset and gain errors.
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6.4 Thermal Information
ADS1283
THERMAL METRIC (1)
RHF (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
30.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.5
°C/W
RθJB
Junction-to-board thermal resistance
8.5
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET bit = 1 (enabled), CHOP bit = 1
(enabled), and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
PGA input voltage noise density
Differential input impedance (1)
IIB
5
CHOP enabled
1
CHOP disabled
100
nV/√Hz
GΩ
Common-mode input impedance
1
GΩ
Input bias current
1
nA
Crosstalk
f = 31.25 Hz
–135
dB
Mux switch on-resistance
Each switch
30
Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range
AVSS + 0.4
PGA differential output impedance
AVDD – 0.4
V
Ω
600
Output impedance tolerance
±10%
External bypass capacitance
10
Modulator differential input impedance
55
kΩ
124
dB
100
nF
AC PERFORMANCE
Signal-to-noise ratio (2)
SNR
Total harmonic distortion (3)
THD
120
ADS1283,
ADS1283B
ADS1283A
SFDR
(1)
(2)
(3)
6
PGA =
1, 2, 4, 8, 16
–122
–114
PGA = 32
–117
–110
PGA = 64
–114
PGA = 1, 4, 16
–118
Spurious-free dynamic range
123
dB
–106
dB
PGA chop feature is disabled by setting CHOP bit = '0'. See Table 4
Inputs shorted; see Table 1.
Input signal = 31.25 Hz, –0.5 dBFS.
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Electrical Characteristics (continued)
maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET bit = 1 (enabled), CHOP bit = 1
(enabled), and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
Resolution
fDATA
Data rate
Offset (4)
31
250
4000
Sinc filter mode
8000
128,000
OFFSET disabled
±50
OFFSET disabled, CHOP disabled
300
OFFSET
enabled
ADS1283B only
Gain error
100 / PGA
105 / PGA
70 / PGA
75 / PGA
80 / PGA
0.03
CHOP disabled
0.5
–1.5%
Gain error after calibration (5)
PSR
Common-mode rejection
Power-supply rejection
mV
–1.0%
μV
μV/°C
–0.5%
0.0002%
PGA = 1
2
PGA = 16
9
Gain matching (7)
CMR
µV
1
CHOP enabled
(6)
Gain drift
SPS
±200
95 / PGA
Offset after calibration (5)
Offset drift
Bits
FIR filter mode
0.3%
fCM = 60 Hz, 1.25 VPP (8)
fPS = 60 Hz, 100
mVPP (8)
95
110
AVDD, AVSS
80
90
DVDD
90
115
ppm/°C
0.8%
dB
dB
VOLTAGE REFERENCE INPUTS
Reference input impedance
85
kΩ
DIGITAL FILTER RESPONSE
Pass-band ripple
±0.003
Pass band (–0.01dB)
0.375 × fDATA
Bandwidth (–3dB)
0.413 × fDATA
High-pass filter corner
0.1
Stop band attenuation (9)
135
Stop band
Group delay
Settling time (latency)
Hz
Hz
10
Hz
dB
0.500 × fDATA
Minimum phase filter (10)
dB
5 / fDATA
Linear phase filter
31 / fDATA
Minimum phase filter
62 / fDATA
Linear phase filter
62 / fDATA
Hz
s
s
(4)
(5)
(6)
(7)
(8)
(9)
Offset specification is input referred. The offset scales by the reference voltage (VREF).
Calibration accuracy is on the level of noise reduced by four (calibration averages 16 readings).
The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
Gain match relative to gain = 1.
fCM is the input common-mode frequency. fPS is the power-supply frequency.
Input frequencies in the range of NfCLK / 1024 ± fDATA / 2 (where N = 1, 2, 3...) can intermodulate with the modulator chopper clock (and
N multiples). At these frequencies, intermodulation = –120 dB, typ.
(10) At dc; see Figure 42.
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Electrical Characteristics (continued)
maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET bit = 1 (enabled), CHOP bit = 1
(enabled), and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
VOH
High-level output voltage
IOH = 1 mA
VOL
Low-level output voltage
IOL = 1 mA
Ilkg
Input leakage
0 < VDIGITAL IN < DVDD
0.8 × DVDD
V
0.2 × DVDD
V
±10
μA
POWER SUPPLY
Operating PGA = 1, 2, 4, 8
AVDD, AVSS current
DVDD current
3.2
5.5
Operating PGA = 16, 32, 64
4
6
Standby mode
1
15
Power-down mode
1
15
Operating
0.6
0.8
Standby mode
25
50
1
15
Operating PGA = 1, 2, 4, 8
18
30
Operating PGA = 16, 32, 64
22
33
Standby mode
90
250
Power-down mode
10
125
Power-down mode (11)
Power dissipation
|mA|
|μA|
mA
μA
mW
μW
(11) CLK input stopped.
8
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6.6
SBAS565C – JANUARY 2014 – REVISED AUGUST 2019
Timing Requirements
at TA = –40°C to +85°C and DVDD = 1.65 V to 3.6 V (unless otherwise noted)
MIN
tCSSC
CS low to SCLK high: setup time
tSCLK
SCLK period
tSPWH, L
MAX
UNIT
40
ns
2
16
1 / fCLK
SCLK pulse duration, high and low (1)
0.8
10
1 / fCLK
tDIST
DIN valid to SCLK high: setup time
50
ns
tDIHD
Valid DIN to SCLK high: hold time
50
ns
tCSH
CS high pulse
tSCCS
SCLK high to CS high
(1)
100
ns
24
1/fCLK
Holding SCLK low for 64 DRDY falling edges resets the serial interface.
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tCSDOD
CS low to DOUT driven: propagation
delay
tDOPD
SCLK low to valid new DOUT:
propagation delay
tDOHD
SCLK low to DOUT invalid: hold
time
tCSDOZ
CS high to DOUT tristate
TYP
Load on DOUT = 20 pF || 100 kΩ
MAX
UNIT
60
ns
100
ns
0
ns
40
t SPWH
t SCLK
CS
MIN
t CSH
t SPWL
t CSSC
ns
t SCCS
SCLK
t DIST
DIN
B7
B6
B5
B4
B3
B2
t DIHD
B1
B0
t DOPD
DOUT
B7
t DOHD
t CSDOD
t CSDOZ
Figure 1. Serial Interface Timing Diagram
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6.8 Typical Characteristics
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET enabled,
CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted). For ADS1283A, the electrical characteristics apply at PGA = 1, 4, and 16
only.
0
0
8192-Point FFT
Shorted Input
PGA = 1
SNR = 123.7 dB
±20
±40
Amplitude (dB)
Amplitude (dB)
±40
8192-Point FFT
Shorted Input
PGA = 8
SNR = 121.1 dB
±20
±60
±80
±100
±120
±60
±80
±100
±120
±140
±140
±160
±160
±180
±180
0
50
100
150
200
250
300
350
400
450
0
500
Frequency (Hz)
50
250
300
350
400
450
500
C003
0
8192-Point FFT
Shorted Input
PGA = 1
CHOP DIsabled
SNR = 123.5 dB
±40
±60
8192-Point FFT
Shorted Input
PGA = 8
CHOP Disabled
SNR = 117.5 dB
±20
±40
Amplitude (dB)
±20
Amplitude (dB)
200
Figure 3. Output Spectrum
Figure 2. Output Spectrum
±80
±100
±120
±60
±80
±100
±120
±140
±140
±160
±160
±180
±180
0
50
100
150
200
250
300
350
400
450
Frequency (Hz)
500
0
50
100
150
200
250
300
350
400
450
Frequency (Hz)
C004
Figure 4. Output Spectrum
500
C005
Figure 5. Output Spectrum
0
0
8192-Point FFT
V IN = 31.25 Hz, -0.5 dBFS
PGA = 1
THD = -124 dB
±20
8192-Point FFT
V IN = 31.25 Hz, -0.5 dBFS
PGA = 8
THD = -125 dB
±20
±40
Amplitude (dB)
±40
Amplitude (dB)
150
Frequency (Hz)
0
±60
±80
±100
±120
±60
±80
±100
±120
±140
±140
±160
±160
±180
±180
0
50
100
150
200
250
300
350
Frequency (Hz)
400
450
500
0
C002
Figure 6. Output Spectrum
10
100
C002
50
100
150
200
250
300
350
Frequency (Hz)
400
450
500
C002
Figure 7. Output Spectrum
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted). For ADS1283A, the electrical
characteristics apply at PGA = 1, 4, and 16 only.
0
0
8192-Point FFT
V IN = 31.25 Hz, -20 dBFS
PGA = 1
THD = -122 dB
±20
±40
Amplitude (dB)
Amplitude (dB)
±40
8192-Point FFT
V IN = 31.25 Hz, -20 dBFS
PGA = 8
THD = -121 dB
±20
±60
±80
±100
±120
±60
±80
±100
±120
±140
±140
±160
±160
±180
±180
0
50
100
150
200
250
300
350
400
450
Frequency (Hz)
500
0
50
100
PGA = 1
PGA = 4
PGA = 16
PGA = 64
V IN = -0.5 dBFS
Total HarmonicDistortion (dB)
Total Harmonic Distortion (dB)
±105
250
300
350
400
450
500
C002
Figure 9. Output Spectrum
±100
PGA = 1
PGA = 4
PGA = 16
PGA = 64
200
Frequency (Hz)
Figure 8. Output Spectrum
±100
150
C002
±110
±115
±120
±125
±105
VIN = 31.25 Hz, -0.5 dBFS
±110
±115
±120
±125
±130
±130
0
10
20
30
40
50
60
70
80
±55
90 100 110 120
Signal Frequency (Hz)
±35
±15
5
25
45
65
85
105
Temperature (ƒC)
C002
125
C007
Figure 11. THD vs Temperature
Figure 10. THD vs Signal Frequency
140
140
130
120
Power Supply Rejection (dB)
Common Mode Rejection (dB)
PGA = 1
120
110
100
90
80
PGA = 1
PGA = 8
70
10
100
100
80
60
40
DVDD
AVDD
AVSS
20
0
1000
10000
100000
1000000
Common Mode Frequency (Hz)
10
100
Figure 12. CMR vs Common-Mode Frequency
1000
10000
100000
1000000
Power Supply Frequency (Hz)
C007
C007
Figure 13. PSR vs Power-Supply Frequency
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted). For ADS1283A, the electrical
characteristics apply at PGA = 1, 4, and 16 only.
Figure 14. Offset-Voltage Histogram
Occurences
70
60
50
40
30
20
Gain Error (%)
±0.60
±0.65
±0.70
±0.75
±0.80
±0.85
±0.90
±0.95
±1.00
±1.05
±1.10
±1.15
±1.20
±1.25
±1.30
±1.35
±1.40
10
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
200
175
150
125
75
PGA = 1,2,4
30 units based on 20•C intervals
over the range -40ƒC to +85ƒ•C
PGA = 16
PGA = 8,32,64
±15
±14
±13
±12
±11
±10
±9
±8
±7
±6
±5
±4
±3
±2
±1
0
1
2
3
4
5
80
Occurrences (%)
100
Figure 15. Offset-Voltage Drift Histogram
30 Units
PGA = 1
90
Gain Drift (ppm/ƒC)
C010
C010
Figure 16. Gain-Error Histogram
Figure 17. Gain-Error Drift Histogram
125
Worst case gain match
30 units, relative PGA = 1
over -40 ƒC to +85ƒC range
Signal-to-Noise Ratio (dB)
120
115
110
105
PGA = 1
100
PGA = 4
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
±0.1
±0.2
±0.3
±0.4
95
±0.5
Occurrences
50
C010
C010
100
120
110
100
90
80
70
60
50
40
30
20
10
0
0
Offset Drift (nV/ƒC)
Offset (mV)
0
25
0
96.0
96.5
97.0
97.5
98.0
98.5
99.0
99.5
100.0
100.5
101.0
101.5
102.0
102.5
103.0
103.5
104.0
104.5
105.0
105.5
106.0
10
±25
20
±50
30
±75
40
±100
50
±125
60
PGA = 1
PGA = 8
30 units based on
20 •C intervals
over the range
-40•C to +85 •C
±150
70
Occurrences
Occurrences (%)
80
120
110
100
90
80
70
60
50
40
30
20
10
0
±175
30 Units
OFFSET Enabled
90
±200
100
PGA = 16
Shorted Input
PGA = 64
90
±55
±35
±15
5
25
45
65
85
Temperature (ƒC)
Gain Match (%)
105
125
C008
C010
Figure 19. SNR vs Temperature
Figure 18. Gain-Match Histogram
12
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted). For ADS1283A, the electrical
characteristics apply at PGA = 1, 4, and 16 only.
0
±40
20
±60
Power (mW)
Amplitude (dB)
25
8192-Point FFT (IN1)
IN1: Shorted
IN2: 31.25 Hz, -0.5 dBFS
PGA = 8
±20
±80
±100
±120
±140
15
10
5
PGA = 1,2,4,8
±160
±180
PGA = 16,32,64
0
0
50
100
150
200
250
300
350
400
450
Frequency (Hz)
500
±55
±35
1.0
P Input, T = 25ƒC
N Input, T = 25ƒC
P Input, T = 85ƒC
N Input, T = 85ƒC
25
45
65
85
105
125
C009
Figure 21. Power vs Temperature
2.0
CHOP Enabled
PGA = 1
P Input, T = 25ƒC
N Input, T = 25ƒC
P Input, T = 85ƒC
N Input, T = 85ƒC
1.5
Input Bias Current (nA)
Input Bias Current (nA)
1.5
5
Temperature (ƒC)
Figure 20. Crosstalk Output Spectrum
2.0
±15
C005
0.5
0.0
±0.5
±1.0
±1.5
1.0
CHOP Disabled
PGA = 1
0.5
0.0
±0.5
±1.0
±1.5
±2.0
±2.5 ±2.0 ±1.5 ±1.0 ±0.5
0.0
0.5
1.0
1.5
2.0
Differential Input Voltage (V)
±2.0
±2.5 ±2.0 ±1.5 ±1.0 ±0.5
2.5
0.0
0.5
1.0
1.5
2.0
Differential Input Voltage (V)
C002
Figure 22. Input Bias Current vs Input Voltage
2.5
C002
Figure 23. Input Bias Current vs Input Voltage
Reference Input Impedance (k )
86
84
82
80
78
76
±55
±35
±15
5
25
45
65
Temperature (ƒC)
85
105
125
C002
Figure 24. Reference Input Impedance vs Temperature
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7 Parameter Measurement Information
7.1 Noise Performance
The ADS1283 offers outstanding signal-to-noise ratio (SNR). The SNR depends on the ADC data rate and the
PGA gain selected. As the bandwidth is reduced by decreasing the data rate, the SNR improves
correspondingly. Similarly, as gain is increased, the input-referred noise decreases. The PGA noise is
independent of gain; therefore, as the gain increases, the input range correspondingly decreases, resulting in
decreased SNR.
The ADS1283 provides a chop feature that reduces the PGA 1/f noise. See the Programmable Gain Amplifier
(PGA) section for more information about chopping. Table 1 summarizes the SNR and input noise voltage with
the CHOP bit enabled. Disabling the CHOP bit results in increased low-frequency noise, particularly evident with
high PGA gains and lower sample rates. Table 2 summarizes SNR and input noise voltage with CHOP disabled.
Table 1. Signal-to-Noise Ratio (dB) and Input Noise (µV), CHOP Bit Enabled
(1)
PGA (SNR, dB) (1)
PGA (Input-Referred Noise, µV RMS)
DATA RATE
(SPS)
1
2
4
8
16
32
64
1
2
4
8
16
32
64
250
130
129
129
127
125
119
114
0.59
0.30
0.16
0.10
0.07
0.06
0.06
500
127
126
126
124
122
116
111
0.84
0.43
0.23
0.14
0.09
0.09
0.08
1000
124
123
123
121
119
113
108
1.19
0.60
0.32
0.20
0.13
0.12
0.11
2000
121
120
120
118
116
110
105
1.68
0.86
0.46
0.28
0.18
0.17
0.16
4000
117
117
117
115
113
107
102
2.40
1.22
0.66
0.40
0.26
0.25
0.23
Typical values at T = +25°C and VREF = 5 V. SNR values rounded to the nearest dB. Number of ADC conversions used in the analysis
varied to maintain measurement bandwidth = 0.1 Hz to 0.413 × data rate. Note that SNR and input noise data of ADS1283A applies to
PGA = 1, 4, and 16 only.
Table 2. Signal-to-Noise Ratio (dB) and Input Noise (µV), CHOP Bit Disabled
(1)
PGA (SNR, dB) (1)
PGA (Input-Referred Noise, µV RMS)
DATA RATE
(SPS)
1
2
4
8
16
32
64
1
2
4
8
16
32
64
250
129
128
125
120
116
110
104
0.63
0.37
0.26
0.21
0.18
0.17
0.18
500
126
125
123
119
114
108
103
0.87
0.47
0.31
0.25
0.21
0.21
0.20
1000
123
123
121
117
114
108
102
1.20
0.65
0.39
0.30
0.22
0.22
0.22
2000
120
120
119
116
112
107
101
1.69
0.91
0.51
0.37
0.26
0.25
0.25
4000
117
117
116
114
111
105
99
2.41
1.24
0.70
0.46
0.33
0.31
0.30
Typical values at T = +25°C and VREF = 5 V. SNR values rounded to the nearest dB. Number of ADC conversions used in the analysis
varied to maintain measurement bandwidth = 0.1 Hz to 0.413 × data rate. Note that SNR and input noise data of ADS1283A applies to
PGA = 1, 4, and 16 only.
Input-referred noise is related to SNR by Equation 1:
FSRRMS
SNR = 20log
NRMS
where
•
•
14
FSRRMS = Full-scale range RMS = VREF / (2 × √2 × PGA)
NRMS = Noise (RMS, input-referred)
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8 Detailed Description
8.1 Overview
The ADS1283 is a high-performance analog-to-digital converter (ADC) intended for energy exploration, seismic
monitoring, chromatography, and other exacting performance applications. The converter provides 31-bit
resolution in data rates from 250 SPS to 4000 SPS. See the Functional Block Diagram section for a block
diagram of the ADS1283.
The ADS1283A device is functionally equivalent to the ADS1283, except that the ADS1283A supports PGA
gains of 1, 4, and 16 only. The ADS1283A also relaxes the THD specification of these gains. See the Electrical
Characteristics section for more details. The ADS1283B provides equivalent performance to the ADS1283, but
provides two offset voltage options, 75 mV and 100 mV. See Offset for details.
The two-channel input mux allows five configurations:
1. Input 1
2. Input 2
3. Input 1 and input 2 shorted together
4. Input 1 and input 2 disconnected and PGA input internally shorted with two 400-Ω resistors
5. Input 1 and input 2 shorted to perform input common-mode test
See the Analog Inputs and Multiplexer section for more details.
The input mux is followed by a continuous-time PGA, featuring very low noise of 5 nV/√Hz. The PGA is
controlled by register settings, allowing gains from 1 to 64 for the ADS1283 and ADS1283B, and gains of 1, 4,
and 16 for the ADS1283A.
The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal
(VIN = AINP – AINN) against the differential reference (VREF = VREFP – VREFN). A digital output (MFLAG)
indicates that the modulator is in overload as a result of an overdrive condition. The modulator connects to the
on-chip digital filter that provides the output codes.
The digital filter consists of a variable decimation rate, fifth-order sinc filter, followed by a variable phase,
decimate-by-32, finite-impulse response (FIR) low-pass filter with programmable phase, and then by an
adjustable high-pass filter for dc removal of the output code. The output of the digital filter can be taken from the
sinc or the FIR low-pass, with the FIR option of the infinite impulse response (IIR) high-pass section.
Gain and offset registers scale the digital filter output to produce the final code value. The scaling feature can be
used for calibration and sensor gain matching.
The SYNC input resets the operation of both the digital filter and the modulator, allowing synchronization
conversions of multiple ADS1283 devices to an external event. The SYNC input supports a continuously-toggled
input mode that accepts an external data frame clock locked to the conversion rate.
The RESET input resets the register settings and also restarts the conversion process.
The PWDN input sets the device into a micro-power state. Note that register settings are not retained in PWDN
mode. Use the STANDBY command in its place if it is desired to retain register settings (the quiescent current in
standby mode is slightly higher).
Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) provide increased reliability in highnoise environments. The SPI™-compatible serial interface is used to read conversion data, in addition to reading
from and writing to the configuration registers.
The device allows either unipolar and bipolar analog power-supply operation. The analog supplies may be set to
+5 V for unipolar signals (with the inputs level shifted externally), or set to ±2.5 V to accept true bipolar input
signals (ground referenced). The digital supply is separate and accepts voltages from 1.8 V to 3.3 V,
independent of the analog power supplies used.
An internal subregulator is used to supply the digital core from DVDD. BYPAS (pin 28), is the subregulator output
and requires a 1-μF capacitor for noise reduction. Note that the regulated output voltage on BYPAS is not
available to drive external circuitry.
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VREFP
VREFN
AVDD
CAPN
CAPP
8.2 Functional Block Diagram
BYPAS
+1.8 V
(Digital core)
AINP2
AINN2
AINP1
AINN1
DVDD
CLK
LDO
Mux
300 :
PGA
4th-Order
û
Modulator
300 :
Calibration
CS
SCLK
DIN
Serial
Interface
DOUT
Overrange
Detection
400 Ÿ
400 Ÿ
Programmable
Digital Filter
DRDY
SYNC
Control
RESET
PWDN
AVDD + AVSS
2
AVSS
MFLAG
DGND
8.3 Feature Description
8.3.1 Analog Inputs and Multiplexer
A diagram of the input multiplexer is shown in Figure 25.
AVDD
S1
AINP1
ESD Diodes
S2
AINP2
400W
(+)
S3
S7
AVSS
To PGA
AVDD + AVSS
AVDD
2
400W
S4
S5
AINN1
ESD Diodes
AINN2
(-)
S6
AVSS
Figure 25. Analog Inputs and Multiplexer
ESD diodes protect the multiplexer inputs. If either input is taken below AVSS – 0.3 V, or above AVDD + 0.3 V,
the ESD protection diodes can turn on. If these conditions are possible, use external clamp diodes, series
resistors, or both to limit the input current to safe values (see the Absolute Maximum Ratings table).
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Feature Description (continued)
Also, overdriving one unused input can affect the conversions of the other input. If an overdriven input interacts
with the measured input, clamp the overdriven signal with external Schottky diodes.
The specified input operating range of the PGA is shown in Equation 2:
AVSS + 0.7V < (AINN or AINP) < AVDD - 1.25V
(2)
For best operation, maintain absolute input levels (input signal level and common-mode level) within these limits.
The multiplexer connects one of the two external differential inputs to the preamplifier inputs, in addition to
internal connections for various self-test modes. Table 3 summarizes the multiplexer configurations for Figure 25.
Table 3. Multiplexer Modes
MUX[2:0]
SWITCHES
000
S1, S5
AINP1 and AINN1 connected to preamplifier
DESCRIPTION
001
S2, S6
AINP2 and AINN2 connected to preamplifier
010
S3, S4
Preamplifier inputs shorted together through 400-Ω internal resistors
011
S1, S5, S2, S6
100
S6, S7
AINP1, AINN1 and AINP2, AINN2 connected together and to the preamplifier
External short, preamplifier inputs shorted to AINN2 (common-mode test)
The typical on-resistance (RON) of the multiplexer is 30 Ω (each switch). When the multiplexer is used to drive an
external load on one input by a signal generator on the other input, on-resistance and on-resistance amplitude
dependency can lead to measurement errors. Figure 26 shows THD versus load resistance and amplitude. THD
improves with high-impedance loads and with lower-amplitude drive signals. The data are measured with the
circuit from Figure 27 with MUX[2:0] = 011.
Total Harmonic Distortion (dB)
0
PGA = 1
PGA = 2
PGA = 4
PGA = 8
PGA = 16
PGA = 32
PGA = 64
-20
-40
-60
-80
-100
-120
-140
0.1k
1k
10k
100k
1M
10M
RLOAD (W)
Figure 26. THD vs External Load and Signal Magnitude (PGA); See Figure 27
500 Ÿ
Test Signal
500 :
RLOAD
Input 1
Input 2
Figure 27. Driving an External Load Through the Multiplexer
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8.3.2 Programmable Gain Amplifier (PGA)
The PGA of the ADS1283 is a low-noise, continuous-time, differential-in and differential-out CMOS amplifier. The
gain is set by register bits PGA[2:0], and is programmable from 1 to 64 for the ADS1283, or can be set to 1, 4,
and 16 for the ADS1283A. The PGA differentially drives the modulator through 300-Ω internal resistors. A C0G
capacitor (10-nF C0G or film dielectric) must be connected to CAPP and CAPN to filter modulator sampling
glitches. The external capacitor also serves as an antialias filter. The corner frequency is given in Equation 3:
1
fP =
6.3 ´ 600 ´ C
(3)
The ADS1283 PGA provides a chop feature. As shown in Figure 28, amplifiers A1 and A2 are chopper stabilized
to remove the offset, offset drift, and 1/f noise. Chopper stabilization (or chopping) moves the offset and noise to
fCLK / 1024 (4 kHz, fCLK = 4.096 MHz ), which is located safely out of the pass-band frequency. Chopping can be
disabled by setting the CHOP bit = 0. When chopping is disabled, the PGA input impedance increases (see
Differential Input Impedance parameter in the Electrical Characteristics). As shown in Figure 29, chopping
maintains flat noise density, leaving predominantly white noise. However, if chopping is disabled, the PGA input
noise results in a rising 1/f noise profile.
AVDD
MUX (+)
300W
A1
CAPP
CHOP
Gain Control
PGA[2:0] Bits
10nF
300W
CAPN
A2
(55kW, typ)
Modulator
Effective
Impedance
MUX (-)
Chopping Control CHOP Bit
AVSS
(1)
Modulator input impedance scales with clock rate.
Figure 28. PGA Block Diagram
PGA Noise (nV/¥+])
100
PGA CHOP Off
10
PGA CHOP On
1
1
10
100
Frequency (Hz)
1k
Figure 29. PGA Noise
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As a result of the stray capacitance of the input chopping switches, low-level transient currents flow through the
inputs when chopping is enabled. The average value of the transient currents versus the input voltage results in
an effective input impedance. The effective input impedance depends on the PGA gain, as shown in Table 4.
Despite the relatively high input impedance, carefully evaluate applications with high-impedance sensors or highimpedance termination resistors when chopping is enabled. Table 4 shows the PGA differential input impedance
with CHOP enabled.
Table 4. Differential Input Impedance (CHOP Enabled)
PGA
DIFFERENTIAL INPUT IMPEDANCE (GΩ)
1
7
2
7
4
4
8
3
16
2
32
1
64
0.5
The PGA has programmable gains from 1 to 64. Table 5 shows the register bit setting for the PGA and resulting
full-scale differential range.
Table 5. PGA Gain Settings
(1)
(2)
DIFFERENTIAL INPUT RANGE
(V) (2)
PGA[2:0]
GAIN (1)
000
1
±2.5
001
2
±1.25
010
4
±0.625
011
8
±0.312
100
16
±0.156
101
32
±0.078
110
64
±0.039
The ADS1283A supports gains of 1, 4, and 16 only.
VREF = 5 V. The input range scales with VREF.
The specified range of the PGA output is shown in Equation 4:
AVSS + 0.4V < (CAPN or CAPP) < AVDD - 0.4V
(4)
For best performance, maintain PGA output levels (signal + common-mode) within these limits.
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8.3.3 Analog-to-Digital Converter (ADC)
The ADC block of the ADS1283 is composed of two sections: a high-accuracy modulator and a programmable
digital filter.
8.3.3.1 Modulator
The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as Figure 30
shows. The modulator shifts the quantization noise to a higher frequency (out of the pass band), where the noise
can be easily removed by digital filtering. The modulator data can either be completely filtered by the on-chip
digital filter or partially filtered by the onboard sinc filter in conjunction with external, post-processing filters.
f MOD = fCLK/4
1st-Stage
(2nd-Order û )
Analog
Signal
Digital
Filter
Math
Block
2nd-Stage
(2nd-Order û )
Figure 30. Fourth-Order Modulator
The modulator performance is optimized for input signals over the dc to 2-kHz bandwidth. As Figure 31 shows,
the effect of PGA and modulator chop result in spectral artifacts at the chop frequency (4 kHz) and related oddorder harmonics to the chop frequency. When using the sinc filter mode in conjunction with an external postdecimation filter, design the external digital filter to suppress the modulator chopping artifacts.
0
±20
Amplitude (dB)
±40
±60
±80
±100
±120
±140
±160
±180
0
4000
8000 12000 16000 20000 24000 28000 32000
Frequency (Hz)
C001
Figure 31. Sinc Output FFT (64 kSPS)
8.3.3.1.1 Modulator Overrange
The ADS1283 modulator is inherently stable, and therefore, has predictable recovery behavior resulting from an
input overdrive condition. The modulator does not exhibit self-reset cycles, which often results in an unstable
output data stream. The ADS1283 modulator outputs a data stream with 90% duty cycle of ones-to-zeroes
density with the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the
input is overdriven past 90% modulation, but below 100% modulation (10% and 0% for negative overdrive,
respectively), the modulator remains stable and continues to output the 1s density data stream. The digital filter
may or may not clip the output codes to +FS or –FS, depending on the duration of the overdrive. When the input
returns to the normal range from a long-duration overdrive (worst case), the modulator returns immediately to the
normal range, but the group delay of the digital filter delays the return of the conversion result to within the linear
range (31 readings for linear phase FIR). An additional 31 readings (62 total) are required for completely-settled
data.
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If the inputs are sufficiently overdriven to drive the modulator to full duty cycle (that is, all 1s or all 0s), the
modulator enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on
the duration. A small-duration overdrive condition may not always clip the output code. When the input returns to
the normal range, the modulator requires up to 12 modulator clock cycles (fMOD) to exit saturation and return to
the linear region. The digital filter requires an additional 62 conversions for fully-settled data (linear-phase FIR).
In the extreme case of input overrange (where either overdriven input exceeds the voltage of the analog supply
voltage plus an internal ESD diode drop), the internal diodes begin to conduct, thus clipping the input signal.
When the input overdrive is removed, the diodes recover quickly. Make sure to limit the input current to 10 mA
(continuous duty) if an overvoltage condition is possible.
8.3.3.1.2 Modulator Input Impedance
The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The
charging of the input sampling capacitor draws a transient current from the PGA output. Use the average value
of the current to calculate an effective input impedance, as shown in Equation 5:
REFF = 1 / (fMOD × CS)
where
•
•
fMOD = Modulator sample frequency = CLK / 4
CS = Input sampling capacitor = 17 pF (typ)
(5)
The resulting modulator input impedance is 55 kΩ (CLK = 4.096 MHz). The modulator input impedance and the
internal PGA 300-Ω output resistors result in a systematic gain error of –1%. The modulator CS can vary ±20%
over production lots, affecting the nominal gain error.
8.3.3.1.3 Modulator Overrange Detection (MFLAG)
The ADS1283 has a fast-responding, overrange detection that indicates when the differential input exceeds
100% or –100% full-scale. The threshold tolerance is ±2.5%.The MFLAG output pin asserts high when in an
overrange condition. As Figure 32 and Figure 33 illustrate, the absolute differential input is compared to 100% of
range. The output of the comparator is sampled at the rate of fMOD / 2, yielding the MFLAG output. The minimum
detectable MFLAG pulse duration is fMOD / 2.
AINP
å
IABSI
P
100% FS
AINN
Q
MFLAG
Pin
fMOD/2
VIN (% of Full-Scale)
Figure 32. Modulator Overrange Block Diagram
+100
(AINP - AINN)
0
Time
-100
MFLAG
Pin
Figure 33. Modulator Overrange Flag Operation
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8.3.3.1.4 Offset
The ADC modulator can produce low-level idle tones that appear in the spectrum when there is no signal input or
when low-level signal inputs are present to the ADC. The ADC provides an optional dc offset voltage designed to
shift the idle tones to the stop band of digital filter response, where the idle tones are reduced. The internal offset
is applied to the modulator input; therefore, the offset voltage amplitude is independent of PGA gain. For all
ADS1283 versions, the offset option is 100 mV. For the ADS1283B, a second offset option is 75 mV. The 75-mV
offset optimally reduces idle tones under various gain, data rate, and chop mode settings.
The offset is enabled by the OFFSET1 and OFFSET0 bits (default is off). The offset voltage reduces the
available input range 4% (3% for the 75 mV value) before the onset of clipped codes. The offset voltage can be
calibrated by using the offset calibration register (OFC[2:0]). Use the offset calibration register to compensate the
offset voltage, thereby restoring the full input voltage range. See Offset and Full-Scale Calibration Registers and
Calibration Commands (OFSCAL and GANCAL) sections for more details.
8.3.3.1.5 Voltage Reference Inputs (VREFP, VREFN)
The voltage reference for the ADS1283 is the differential voltage between VREFP and VREFN:
VREF = VREFP – VREFN
(6)
The reference inputs use a structure similar to that of the analog inputs with the circuitry of the reference inputs
shown in Figure 34. The average load presented by the switched-capacitor reference input can be modeled with
an effective differential impedance of:
REFF = tSAMPLE / CIN (tSAMPLE = 1 / fMOD).
(7)
Note that the effective impedance of the reference inputs loads the external reference.
AVDD
fMOD = fCLK/4
ESD
Diodes
REFF =
VREFP
1
fMOD x 11.5 pF
REFF : 85 NŸ
11.5pF
VREFN
ESD
Diodes
AVSS
Figure 34. Simplified Reference Input Circuit
Place a 0.1-µF ceramic capacitor directly between the ADC VREFP and VREFN pins. Multiple ADC applications
can share a single voltage reference, but must have individual capacitors placed for each ADC.
The ADS1283 reference inputs are protected by ESD diodes. In order to prevent these diodes from turning on,
the voltage on either input must stay within the range shown in Equation 8:
AVSS - 300mV < (VREFP or VREFN) < AVDD + 300mV
(8)
The minimum valid input for VREFN is AVSS – 0.1 V, and the maximum valid input for VREFP is AVDD + 0.1 V.
To achieve the best performance from the ADS1283, use a high-quality 5-V reference voltage. A 4-V or 4.5-V
reference voltage can be used; however, this lower reference voltage reduces the signal input range with a
corresponding decrease of SNR. Noise and drift on the reference degrade overall system performance. To
achieve optimum performance, make sure to give special care to the circuitry generating the reference voltages.
See the Application Information section for reference recommendations.
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8.3.3.2 Digital Filter
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rate.
The digital filter is comprised of three cascaded filter stages: a variable-decimation, fifth-order sinc filter; a fixeddecimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter
(HPF), as shown in Figure 35.
Filter Mode
(Register Select)
Filter
MUX
From Modulator
Sinc Filter
(Decimate by
8 to 128)
Coefficient Filter
(FIR)
(Decimate by 32)
High-Pass Filter
(IIR)
To Output Register
Code
Clip
CAL
Block
Figure 35. Digital Filter and Output Code Processing
The output can be taken from one of the three filter blocks, as Figure 35 shows. For partial filtering by the
ADS1283, select the sinc filter output. For complete on-chip filtering, activate both the sinc + FIR stages. The
HPF can then be included to remove dc and low frequencies from the data. Table 6 shows the filter options.
Table 6. Digital Filter Selection
FILTR[1:0] BITS
DIGITAL FILTERS SELECTED
00
Reserved (not used)
01
Sinc
10
Sinc + FIR
11
Sinc + FIR + HPF
(low-pass and high-pass)
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8.3.3.2.1 Sinc Filter Stage (sinx / x)
The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter
from the modulator at the rate of fMOD (fCLK / 4). The sinc filter attenuates the high-frequency noise of the
modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of
the converter, and is set by the DR[2:0] register bits, as shown in Table 7.
Table 7. Sinc Filter Data Rates
DR[2:0] REGISTER
DECIMATION RATIO (N)
000
128
DATA RATE (SPS)
8,000
001
64
16,000
010
32
32,000
011
16
64,000
100
8
128,000
Equation 9 shows the scaled Z-domain transfer function of the sinc filter.
5
1 - Z-N
H(Z) =
-1
N(1 - Z )
where
•
N = decimation ratio
(9)
Equation 10 shows the frequency domain transfer function of the sinc filter.
5
sin
½H(f)½ =
N sin
pN ´ f
fMOD
p´f
fMOD
where
•
N = decimation ratio (see Table 7)
(10)
The sinc filter has notches (or zeros) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has zero gain. Figure 36 shows the frequency response of the sinc filter and Figure 37
shows the roll-off of the sinc filter.
0
0
-20
-0.5
-40
Gain (dB)
Gain (dB)
-1.0
-60
-80
-1.5
-2.0
-100
-2.5
-120
-140
-3.0
0
1
2
3
4
Normalized Frequency (fIN/fDATA)
5
0
Figure 36. Sinc Filter Frequency Response
(N = 32)
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0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA)
Figure 37. Sinc Filter Roll-Off
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8.3.3.2.2 FIR Stage
The second stage of the ADS1283 digital filter is an FIR low-pass filter. Data are supplied to this stage from the
sinc filter. The FIR stage is segmented into four substages, as shown in Figure 38.
FIR Stage 2
Decimate by 2
FIR Stage 1
Decimate by 2
Sinc
Filter
FIR Stage 3
Decimate by 4
FIR Stage 4
Decimate by 2
Output
Coefficients
Linear
Minimum
PHASE Select
Figure 38. FIR Filter Substages
The first two substages are half-band filters with decimation ratios of two. The third substage decimates by four,
and the fourth substage decimates by two. The overall decimation of the FIR stage is 32. Note that two
coefficient sets are used for the third and fourth sections, depending on the phase selection. Table 8 lists the
data rates and overall decimation ratio of the FIR stage. See Table 9 for the FIR filter coefficients.
Table 8. FIR Filter Data Rates
DR[2:0] REGISTER
DECIMATION RATIO (N)
FIR DATA RATE (SPS)
000
4096
250
001
2048
500
010
1024
1000
011
512
2000
100
256
4000
Table 9. FIR Stage Coefficients
SECTION 1
SECTION 2
SECTION 3
SECTION 4
LINEAR PHASE
SCALING =
1 / 8388608
SCALING = 1 / 134217728
SCALING = 1 / 134217728
COEFFICIENT
LINEAR PHASE
SCALING =
1 / 512
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
b0
3
–10944
0
819
–132
11767
b1
0
0
0
8211
–432
133882
b2
–25
103807
–73
44880
–75
769961
2940447
MINIMUM
PHASE
b3
0
0
–874
174712
2481
b4
150
–507903
–4648
536821
6692
8262605
b5
256
0
–16147
1372637
7419
17902757
b6
150
2512192
–41280
3012996
–266
30428735
b7
0
4194304
–80934
5788605
–10663
40215494
b8
–25
2512192
–120064
9852286
–8280
39260213
b9
0
0
–118690
14957445
10620
23325925
b10
3
–507903
–18203
20301435
22008
–1757787
b11
0
224751
24569234
348
–21028126
b12
103807
580196
26260385
–34123
–21293602
b13
0
893263
24247577
–25549
–3886901
b14
–10944
891396
18356231
33460
14396783
b15
293598
9668991
61387
16314388
b16
–987253
327749
–7546
1518875
b17
–2635779
–7171917
–94192
–12979500
b18
–3860322
–10926627
–50629
–11506007
b19
–3572512
–10379094
101135
2769794
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Table 9. FIR Stage Coefficients (continued)
SECTION 1
SECTION 3
SECTION 4
SCALING = 1 / 134217728
SCALING = 1 / 134217728
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
MINIMUM
PHASE
–822573
–6505618
134826
12195551
b21
4669054
–1333678
–56626
6103823
b22
12153698
2972773
–220104
–6709466
b23
19911100
5006366
–56082
–9882714
b24
25779390
4566808
263758
–353347
b25
27966862
2505652
231231
8629331
b26
25779390
126331
–215231
5597927
b27
19911100
–1496514
–430178
–4389168
b28
12153698
–1933830
34715
–7594158
b29
4669054
–1410695
580424
–428064
b30
–822573
–502731
283878
6566217
b31
–3572512
245330
–588382
4024593
b32
–3860322
565174
–693209
–3679749
b33
–2635779
492084
366118
–5572954
b34
–987253
231656
1084786
332589
b35
293598
–9196
132893
5136333
b36
891396
–125456
–1300087
2351253
b37
893263
–122207
–878642
–3357202
b38
580196
–61813
1162189
–3767666
b39
224751
–4445
1741565
1087392
b40
–18203
22484
–522533
3847821
b41
–118690
22245
–2490395
919792
b42
–120064
10775
–688945
–2918303
b43
–80934
940
2811738
–2193542
b44
–41280
–2953
2425494
1493873
b45
–16147
–2599
–2338095
2595051
b46
–4648
–1052
–4511116
–79991
b47
–874
–43
641555
–2260106
b48
–73
214
6661730
–963855
b49
0
132
2950811
1482337
b50
0
33
–8538057
1480417
b51
0
0
COEFFICIENT
LINEAR PHASE
SCALING =
1 / 512
b20
26
SECTION 2
LINEAR PHASE
SCALING =
1 / 8388608
–10537298
–586408
b52
9818477
–1497356
b53
41426374
–168417
b54
56835776
1166800
b55
41426374
644405
b56
9818477
–675082
b57
–10537298
–806095
b58
–8538057
211391
b59
2950811
740896
b60
6661730
141976
b61
641555
–527673
b62
–4511116
–327618
b63
–2338095
278227
b64
2425494
363809
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Table 9. FIR Stage Coefficients (continued)
SECTION 1
SECTION 3
SECTION 4
SCALING = 1 / 134217728
SCALING = 1 / 134217728
LINEAR
PHASE
LINEAR
PHASE
MINIMUM
PHASE
2811738
–70646
b66
–688945
–304819
b67
–2490395
–63159
b68
–522533
205798
b69
1741565
124363
b70
1162189
–107173
b71
–878642
–131357
b72
–1300087
31104
b73
132893
107182
b74
1084786
15644
b75
366118
–71728
b76
–693209
–36319
b77
–588382
38331
b78
283878
38783
b79
580424
–13557
b80
34715
–31453
b81
–430178
–1230
b82
–215231
20983
b83
231231
7729
b84
263758
–11463
b85
–56082
–8791
b86
–220104
4659
b87
–56626
7126
b88
134826
–732
b89
101135
–4687
b90
–50629
–976
b91
–94192
2551
b92
–7546
1339
b93
61387
–1103
b94
33460
–1085
b95
–25549
314
b96
–34123
681
b97
348
16
b98
22008
–349
COEFFICIENT
LINEAR PHASE
SCALING =
1 / 512
SECTION 2
LINEAR PHASE
SCALING =
1 / 8388608
MINIMUM
PHASE
b65
b99
10620
–96
b100
–8280
144
b101
–10663
78
b102
–266
–46
b103
7419
–42
b104
6692
9
b105
2481
16
b106
–75
0
b107
–432
–4
b108
–132
0
b109
0
0
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As shown in Figure 39, the FIR frequency response provides a flat pass band to 0.375 of the data rate
(±0.003 dB pass-band ripple). Figure 40 shows the transition from pass band to stop band.
20
1.5
0
1.0
-20
Magnitude (dB)
Magnitude (mdB)
2.0
0.5
0
-0.5
-1.0
-40
-60
-80
-100
-120
-1.5
-140
-2.0
-160
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0
0.1
Normalized Input Frequency (fIN/fDATA)
Figure 39. FIR Pass-Band Magnitude Response (fDATA =
500 Hz)
0.2 0.3 0.4 0.5 0.6 0.7 0.8
Normalized Input Frequency (fIN/fDATA)
0.9
1.0
Figure 40. FIR Transition Band Magnitude Response
Although not shown in Figure 40, the pass-band response repeats at multiples of the modulator frequency
(NfMOD – f0 and NfMOD + f0, where N = 1, 2, and so on, and f0 = pass band). These image frequencies, if present
in the signal and not externally filtered, fold back (or alias) into the pass band and cause errors. A low-pass
signal filter reduces the effect of aliasing. Often, the RC low-pass filter provided by the PGA output resistors and
the external capacitor connected to CAPP and CAPN provide sufficient signal attenuation.
8.3.3.2.3 Group Delay and Step Response
The FIR block is implemented as a multistage FIR structure with selectable linear or minimum phase response.
The pass band, transition band, and stop band responses of the filters are nearly identical but differ in the
respective phase responses.
8.3.3.2.3.1 Linear Phase Response
Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear
phase filters have the property that the time delay is constant from any instant of the input signal to the same
instant of the output data, and is independent of the signal nature. This filter behavior results in essentially zero
phase error when analyzing multitone signals. However, the group delay and settling time of the linear phase
filter are somewhat larger than the minimum phase filter, as shown in Figure 41.
1.4
Minimum Phase Filter
1.2
Amplitude (dB)
1.0
0.8
0.6
0.4
0.2
Linear Phase Filter
0
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA)
Figure 41. FIR Step Response
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8.3.3.2.3.2 Minimum Phase Response
The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the
relationship (phase) is not constant versus frequency, as shown in Figure 42. The filter phase is selected by the
PHS bit, as Table 10 shows.
35
Linear Phase Filter
Group Delay (1/fDATA)
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120
Frequency (Hz)
140 160 180
200
Figure 42. FIR Group Delay (fDATA = 500Hz)
Table 10. FIR Phase Selection
PHS BIT
FILTER PHASE
0
Linear
1
Minimum
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8.3.3.2.4 HPF Stage
The last stage of the ADS1283 filter block is a first-order HPF implemented as an IIR structure. This filter stage
blocks dc signals, and rolls off low-frequency components below the cutoff frequency. The transfer function for
the filter is shown in Equation 11:
-1
2-a
1-Z
´
HPF(Z) =
-1
1 - bZ
2
where
•
b=
b is calculated as shown in Equation 12
1 + (1 - a)
(11)
2
2
(12)
The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 13 is used to set
the high-pass corner frequency. Table 11 lists example values for the high-pass filter.
HPF[1:0] = 65,536 1 -
1-2
cos wN + sin wN - 1
cos wN
where
•
•
•
•
HPF = High-pass filter register value (converted to hexadecimal)
ωN = 2πfHP / fDATA (normalized frequency, radians)
fHP = High-pass corner frequency (Hz)
fDATA = Data rate (Hz)
(13)
Table 11. High-Pass Filter Value Examples
30
fHP (Hz)
DATA RATE (SPS)
HPF[1:0]
0.5
250
0337h
1.0
500
0337h
1.0
1000
019Ah
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The HPF causes a small gain error, in which case the magnitude of the error depends on the ratio of fHP / fDATA.
For many common values of (fHP / fDATA), the gain error is negligible. Figure 43 shows the gain error of the HPF.
0
Gain Error (dB)
-0.10
-0.20
-0.30
-0.40
-0.50
0.0001
0.001
0.01
0.1
Frequency Ratio (fHP/fDATA)
Figure 43. HPF Gain Error
The gain error factor is illustrated in Equation 14:
1+
1-2
cos wN + sin wN - 1
cos wN
HPF Gain =
2-
cos wN + sin wN - 1
cos wN
(14)
0
90
-7.5
75
-15.0
60
Amplitude
45
-22.5
Phase
-30.0
30
-37.5
15
-45.0
0.01
Phase (°)
Amplitude (dB)
Figure 44 shows the first-order amplitude and phase response of the HPF. In the case of applying step inputs or
synchronizing, make sure to take the settling time of the filter into account.
0
0.1
1
10
Normalized Frequency (f/fC)
100
Figure 44. HPF Amplitude and Phase Response
8.3.4 Master Clock Input (CLK)
The ADS1283 requires a clock for operation. The nominal clock frequency is 4.096 MHz. The clock is applied to
the CLK pin. The ADC data rates scale with CLK frequency, however there is no benefit in noise by reducing the
CLK frequency.
As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock
input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the source.
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8.4 Device Functional Modes
8.4.1 Synchronization (SYNC PIN and SYNC Command)
The ADS1283 can be synchronized to an external event, as well as to other ADS1283 devices if the
synchronization is applied simultaneously.
The ADS1283 has two sources for synchronization: the SYNC input pin and the SYNC command. The ADS1283
also has two synchronizing modes: pulse-sync and continuous-sync. In pulse-sync mode, the ADS1283
synchronizes to a single synchronization. In continuous-sync mode, either a single synchronization is used to
synchronize conversions, or a continuous clock is applied to the pin with a period equal to integer multiples of the
data rate. When the periods of the SYNC input and the DRDY output do not match, the ADS1283 resynchronizes
and conversions are restarted.
8.4.1.1 Pulse-Sync Mode
In pulse-sync mode, when a synchronization occurs (by pin or command), the ADS1283 unconditionally stops
and restarts the conversion process. When the ADC synchronizes, the device resets the internal filter memory,
DRDY goes high, and after the digital filter has settled, new conversion data are available as shown in Figure 45
and Table 12.
tCSDL
CLK
tDR
SYNC
tSPWH
tSPWL
New Data Ready
DRDY
(Pulse-sync mode)
DOUT
(Pulse-sync mode)
New Data Ready
DRDY
(Continuous-sync mode)
DOUT
(Continuous-sync mode)
Figure 45. Pulse-Sync and Continuous-Sync Timing With Single Synchronization
Table 12. Pulse-Sync Timing for Figure 45 and Figure 46
PARAMETER
tCSDL
CLK rising edge to SYNC rising edge (1)
tSYNC
(2)
tSPWH,
tDR
(1)
(2)
32
SYNC clock period
L
SYNC pulse width, high or low
MIN
MAX
UNIT
30
–30
ns
1
Infinite
2
Time for data ready (SINC filter)
n / fDATA
1 / fCLK
See Table 13
Time for data ready (FIR filter)
62.98046875 / fDATA + 468 / fCLK
CLK rising edge to SYNC rising edge timing must not occur within the specified time window.
Continuous-sync mode; a free-running clock applied to the SYNC input without causing resynchronization. See Figure 46
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Table 13. tDR Time for Data Ready (Sinc Filter)
(1)
fDATA (kSPS)
fCLK CYCLES (1)
128
440
64
616
32
968
16
1672
8
2824
For SYNC and WAKEUP commands, number of fCLK cycles from next rising CLK edge directly after
eighth rising SCLK edge to DRDY falling edge. For WAKEUP command only, subtract two fCLK cycles.
Table 13 is referenced by Table 12 and Table 15.
Observe the timing restriction of SYNC rising edge to CLK rising edge as shown in Figure 45 and Table 12.
Synchronization occurs on the next rising CLK edge after the rising edge of the SYNC, or after the eighth rising
SCLK edge when synchronized by command. To synchronize multiple ADCs, broadcast the command to the
ADCs simultaneously.
8.4.1.2 Continuous-Sync Mode
In continuous-sync mode, either a single synchronization pulse or a continuous clock may be applied. When a
single synchronization pulse is applied (rising edge), the device resynchronizes as it does in pulse-sync mode.
ADC resynchronization occurs only under the condition that the time from the previous rising edge of SYNC is
not a multiple of the conversion period. When resynchronization occurs in continuous-sync mode, DRDY
continues to toggle unaffected, and the DOUT output is held low until data are ready (63 DRDY periods later). At
the 63rd reading, conversion data are valid (when the conversion data are non-zero), as shown in Figure 45.
When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data
rate or the device resynchronizes. Note that synchronization results in the restarting of the digital filter and an
interruption of 63 readings (as shown in Table 12).
If a SYNC clock is applied to the ADC, the device resynchronizes only under the condition tSYNC ≠ N / fDATA,
where N = 1, 2, 3, and so on. DRDY continues to output, but DOUT is held low until the new data are ready. If a
SYNC clock is applied and the clock period matches an integral multiple of the output data rate, the device freely
runs without resynchronization. Note that the phase of the applied clock and output data rate (DRDY) are not
aligned because of the initial delay of DRDY after the SYNC clock is first applied. Figure 46 shows the timing for
continuous-sync mode.
tCSDL
CLK
SYNC
tSPWH
tSPWL
tSYNC
DRDY
1/fDATA
Figure 46. Continuous-Sync Timing With SYNC Clock
Apply a SYNC clock input after the continuous-sync mode is set. The first rising edge of SYNC then causes a
synchronization. Note that subsequent writes to any ADC register results in resynchronization at the time of the
register write operation. The resynchronization leads to loss of the SYNC-pin controlled synchronization
performed previously. Send the STANDBY command followed by the WAKEUP command to reestablish the
SYNC-pin synchronization. Resynchronization to the SYNC pin occurs as long as the time between the
STANDBY and WAKEUP commands is not a multiple integer of the conversion period by at least one clock
cycle.
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8.4.2 Reset (RESET Pin and Reset Command)
The ADS1283 can be reset in two ways: toggle the RESET pin low, or send a RESET command. When using
the RESET pin, take it low and hold for at least 2 / fCLK to force a reset. The ADS1283 is held in reset until the
pin is released. By command, reset takes effect on the next rising edge of fCLK after the eighth rising edge of
SCLK of the command. In order to make certain that the RESET command can function, the SPI interface may
need to be reset; see the Serial Interface section.
When the ADS1283 is reset, registers are set to default and the conversions are synchronized on the next rising
edge of CLK. New conversion data are available, as shown in Figure 47 and Table 14.
Settled
Data
DRDY
tDR
tCRHD
System Clock
(fCLK)
tRST
tRCSU
RESET Pin
or
RESET Command
Figure 47. Reset Timing
Table 14. Reset Timing for Figure 47
PARAMETER
MIN
UNIT
tCRHD
CLK to RESET hold time
10
ns
tRCSU
RESET to CLK setup time
10
ns
tRST
RESET low
2
1 / fCLK
tDR
Time for data ready
62.98046875 / fDATA + 468 / fCLK
s
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8.4.3 Power-Down (PWDN Pin and STANDBY Command)
There are two ways to power-down the ADS1283: take the PWDN pin low, or send a STANDBY command.
When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the
register settings are reset.
When in a power-down state, the device outputs remain active and the device inputs must not float. When the
STANDBY command is sent, the SPI port and the configuration registers are kept active. Figure 48 and Table 15
show the timing. Standby mode is cancelled when CS is taken high.
PWDN Pin
Wakeup
Command
DRDY
tDR
Figure 48. PWDN Pin and Wake-Up Command Timing
(Table 15 shows tDR)
Table 15. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data
PARAMETER
tDR
(1)
(2)
FILTER MODE
Time for data ready 216 CLK cycles after power-on;
and new data ready after PWDN pin or WAKEUP command
See Table 13
SINC (1)
62.98046875 / fDATA + 468 / fCLK
FIR
(2)
Supply power-on and PWDN pin default is 1000 SPS FIR.
Subtract two CLK cycles for the WAKEUP command. The WAKEUP command is timed from the next rising edge of CLK to after the
eighth rising edge of SCLK during command to DRDY falling.
8.4.4 Power-On Sequence
The ADS1283 has three power supplies: AVDD, AVSS, and DVDD. Figure 49 shows the power-on sequence of
the ADS1283. The power supplies can be sequenced in any order. The supplies [the difference of (AVDD –
AVSS) and DVDD] generate signals that are ANDed together for the internal reset. After the supplies have
crossed the minimum thresholds, 216 fCLK cycles are counted before releasing the internal reset. After the internal
reset is released, new conversion data are available, as shown in Figure 49 and Table 15.
3.5V nom
AVDD - AVSS
1V nom
DVDD
CLK
16
2
fCLK
Internal Reset
DRDY
tDR
Figure 49. Power-On Sequence
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8.4.5 DVDD Power Supply
The DVDD supply operates over the range of 1.65 V to 3.6 V. If operating DVDD at less than 2.25 V, connect the
DVDD pin to the BYPAS pin. Otherwise, do not connect these pins together. Figure 50 shows this connection.
1.65 V to 3.6 V
DVDD
1 µF
Connect DVDD to BYPAS if DVDD is < 2.25 V.
Otherwise, do not connect these pins together.
BYPAS
1 µF
Figure 50. DVDD Power
8.4.6 Serial Interface
A serial interface is used to read both the conversion data and to access the configuration registers. The
interface is SPI-compatible and consists of four signals: CS, SCLK, DIN, and DOUT. A minimum of 16 ADCs
converting at 4 kSPS can share a common serial bus when operating SCLK at 2 MHz.
8.4.6.1 Chip Select (CS)
Chip select (CS) is an active-low input that enables the ADC serial interface for data transfer. When CS is low,
the serial interface is enabled for communication. When CS is high, the serial interface is disabled. When the
serial interface is disabled, the DOUT (output data pin) is high impedance (tristate or Hi-Z). When CS is high,
SCLK activity is ignored, and data transfers or commands in progress are reset. CS must remain low for the
duration of the data transfer with the ADC. CS can be tied low, which permanently enables the ADC serial
interface. When CS goes high, the ADC idles (STANDBY) and stop read data continuous (SDATAC) modes are
cancelled. See the SDATAC Requirements section for more information about SDATAC mode.
8.4.6.2 Serial Clock (SCLK)
The serial clock (SCLK) is an input pin that is used to clock data into (DIN) and out of (DOUT) the ADC. SCLK is
a Schmitt-trigger input that has a high degree of noise immunity. However, keep SCLK as clean as possible to
prevent possible glitches from inadvertently shifting the data.
Data are shifted into DIN on the rising edge of SCLK and data are shifted out of DOUT on the falling edge of
SCLK. Keep SCLK low when not active. SCLK is ignored when CS is high.
8.4.6.3 Data Input (DIN)
The data input pin (DIN) is used to input register data and commands to the ADS1283. Keep DIN low when
reading conversion data in the read-data-continuous mode (except when issuing a SDATAC command). Data on
DIN are shifted into the converter on the rising edge of SCLK.
8.4.6.4 Data Output (DOUT)
The data output pin (DOUT) is used to output data from the ADS1283. Data are shifted out on the falling edge of
SCLK. When CS is high, the DOUT pin is in tristate.
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8.4.6.5 Serial Port Auto Timeout
The serial interface is reset each time CS is taken high. However, for applications that tie CS low, the serial port
cannot be reset by taking CS high; reset of the serial interface is no longer possible by using CS. The ADS1283
provides a feature that automatically recovers the interface when a transmission is stopped or interrupted, or if an
inadvertent glitch appears on SCLK. To reset the serial interface, hold SCLK low for 64 DRDY cycles. The reset
of the serial interface results in termination of data transfer or commands in progress. After serial port reset
occurs, the next SCLK pulse starts a new communication cycle. To prevent automatic reset from occurring, pulse
SCLK at least once for every 64 DRDY pulses.
8.4.6.6 Data Ready (DRDY)
DRDY is an output that is driven low when new conversion data are ready, as shown in Figure 51. When reading
data in continuous mode, the read operation must be completed before four CLK periods before the next falling
DRDY goes low again, or the data are overwritten with new conversion data. When reading data in command
mode, the read operation can overlap the occurrence of the next DRDY without data corruption.
DRDY
DOUT
Bit 31
Bit 30
Bit 29
SCLK
Figure 51. DRDY With Data Retrieval
DRDY resets high on the first falling edge of SCLK. Figure 51 and Figure 52 show the function of DRDY with and
without data readback, respectively.
If data are not retrieved (no SCLK provided), DRDY pulses high for four fCLK periods during the update time, as
shown in Figure 52.
DRDY remains active when CS is high.
4/fCLK
Data Updating
DRDY
Figure 52. DRDY With No Data Retrieval
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8.4.7 Data Format
The ADS1283 output data is 32-bits in binary twos complement format, as shown in Table 16. The LSB of the
data is a redundant sign bit: 0 for positive numbers and 1 for negative numbers. However, when the output is
clipped to +FS, the LSB = 1, and when the output is clipped to –FS, the LSB = 0. If desired, the data readback
can be stopped at 24 bits. Note that in sinc-filter mode, the output data are scaled by ½.
Table 16. Ideal Output Code Versus Input Signal
32-BIT IDEAL OUTPUT CODE(1)
INPUT SIGNAL VIN
(AINP – AINN)
FIR FILTER
VREF
>
2 x PGA
See note
7FFFFFFEh
3FFFFFFFh
00000002h
00000001h
00000000h
00000000h
FFFFFFFFh
FFFFFFFFh
80000001h
C0000000h
80000000h
See note
VREF
2PGA ´ (230 - 1)
0
-VREF
2PGA ´ (230 - 1)
230
-VREF
2PGA
<
(3)
7FFFFFFFh
2 x PGA
VREF
SINC FILTER(2)
´
30
2 -1
230
-VREF
2PGA
´
230 - 1
(3)
(1) Excludes effects of noise, linearity, offset, and gain errors.
(2) Due to the reduction in oversampling ratio (OSR) related to high data rates of the sinc filter, full resolution may not be available.
(3) In sinc-filter mode, the output does not clip at half-scale code when the full-scale range is exceeded.
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8.4.8 Reading Data
The ADS1283 provides two modes to read conversion data: read-data-continuous and read-data-by-command.
8.4.8.1 Read-Data-Continuous Mode
In the read-data-continuous mode, the conversion data are shifted out directly from the device without the need
for sending a read command. This mode is the default mode at power-on. This mode is also enabled by the
RDATAC command. When DRDY goes low, indicating that new data are available, the MSB of data appears on
DOUT, as shown in Figure 53. The data are normally read on the rising edge of SCLK, at the occurrence of the
first falling edge of SCLK, DRDY returns high. After 32 bits of data have been shifted out, further SCLK
transitions cause DOUT to go low. If desired, the read operation may be stopped at 24 bits. The data shift
operation must be completed within four CLK periods before DRDY falls again or the data may be corrupted.
When a SDATAC command is issued, the DRDY output is blocked but the ADS1283 continues conversions. In
stop continuous mode, the data can only be read by command.
CS(1)
DRDY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
25 26 27 28 29 30
31 32
SCLK
DOUT(2)
Data Byte 1 (MSB)
Data Byte 2 (MSB - 1)
Data Byte 4 (LSB)
tDDPD
DIN
(1)
DOUT is in tristate when CS is high. CS can be tied low. See Figure 1 for CS low to valid DOUT propagation time.
Figure 53. Read Data Continuous
Table 17. Timing Data for Figure 53
PARAMETER
(1)
MIN
TYP
DRDY to valid MSB on DOUT propagation delay (1)
tDDPD
MAX
UNIT
100
ns
DOUT is in tristate when CS is high. Load on DOUT = 20 pF || 100 kΩ.
8.4.8.2 Read-Data-By-Command Mode
Read-data-continuous mode is stopped by the SDATAC command and put into read-data-by-command mode. In
read-data-by-command mode, an RDATA command must be sent to the device for each data conversion (as
shown in Figure 54). When the read data command is received (on the eighth SCLK rising edge), data are
available to read only when DRDY goes low (tDR). When DRDY goes low, conversion data appear on DOUT. The
data may be read on the rising edge of SCLK.
CS(1)
DRDY
tDR
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
33 34 35 36 37 38
39 40
SCLK
DOUT(2)
DIN
(1)
Don't Care
Data Byte 1 (MSB)
Date Byte 4 (LSB)
tDDPD
Command Byte (0001 0010)
DOUT is in tristate when CS is high.CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.
Figure 54. Read Data By Command, RDATA (tDDPD timing is given in Table 17)
Table 18. Read Data Timing for Figure 54
PARAMETER
tDR
DESCRIPTION
Time for new data after data read command
MIN
0
TYP
MAX
UNIT
1
fDATA
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8.4.9 One-Shot Operation
The ADS1283 can perform very power-efficient, one-shot conversions using the STANDBY command while
under software control. Figure 55 shows this sequence. First, issue the STANDBY command to set the standby
mode.
When ready to make a measurement, issue the WAKEUP command. When DRDY goes low, the fully-settled
conversion data are ready and can be read directly in read-data-continuous mode. Afterwards, issue another
STANDBY command. When ready for the next measurement, repeat the cycle starting with another WAKEUP
command.
ADC Status
Standby
Standby
Performing One-Shot Conversion
CS
DRDY
DIN
WAKEUP
STANDBY
(1)
STANDBY
DOUT
Settled
Data
See Figure 48 and Table 15 for time to new data.
Figure 55. One-Shot Conversions Using the STANDBY Command
8.4.10 Offset and Full-Scale Calibration Registers
The conversion data can be scaled for offset and gain before yielding the final output code. As shown in
Figure 56, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the
full-scale register (FSC). Equation 15 shows the scaling:
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(15)
The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically
by the calibration commands.
The offset and full-scale calibrations apply to specific PGA settings. When the PGA is changed, these registers
generally require recalculation. Calibration is bypassed in the sinc filter mode.
AINP
Modulator
AINN
Digital
Filter
+
S
´
OFC
Register
FSC Register
400000h
-
Output Data
Clipped to 32 Bits
Final Output
Figure 56. Calibration Block Diagram
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8.4.10.1 OFC[2:0] Registers
The 24-bit offset calibration word is composed of three 8-bit registers, as shown in Table 19. The offset register
is left-justified to align with the 32 bits of conversion data. The offset is in twos complement format with a
maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from
the conversion data. A register value of 00000h has no offset correction (default value).
Table 19. Offset Calibration Word
REGISTER
BYTE
OFC0
LSB
B7
B6
B5
B4
BIT ORDER
B3
B2
B1
OFC1
MID
B15
B14
B13
B12
B11
B10
B9
B8
OFC2
MSB
B23 (MSB)
B22
B21
B20
B19
B18
B17
B16
B0 (LSB)
Although the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 20),
in order to avoid input overload, do not exceed the maximum input voltage range of 106% FSR (including
calibration).
Table 20. Offset Calibration Values
OFC REGISTER
FINAL OUTPUT CODE(1)
7FFFFFh
80000000h
000001h
FFFFFF00h
000000h
00000000h
FFFFFFh
00000100h
800000h
7FFFFF00h
(1) Full 32-bit final output code with zero code input.
8.4.10.2 FSC[2:0] Registers
The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 21. The full-scale
calibration value is 24-bit, straight offset binary, normalized to 1.0 at code 400000h.
Table 21. Full-Scale Calibration Word
REGISTER
BYTE
FSC0
LSB
B7
B6
B5
B4
BIT ORDER
B3
B2
B1
FSC1
MID
B15
B14
B13
B12
B11
B10
B9
B8
FSC2
MSB
B23 (MSB)
B22
B21
B20
B19
B18
B17
B16
B0 (LSB)
Table 22 summarizes the scaling of the full-scale register. A register value of 400000h (default value) has no
gain correction (gain = 1). Although the full-scale calibration register value corrects gain errors above one (gain
correction < 1), the full-scale range of the analog inputs must not exceed 106% FSR (including calibration) in
order to avoid input overload.
Table 22. Full-Scale Calibration Register Values
FSC REGISTER
GAIN CORRECTION
800000h
2.0
400000h
1.0
200000h
0.5
000000h
0
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8.4.11 Calibration Commands (OFSCAL and GANCAL)
Use the calibration commands (OFSCAL or GANCAL) to calibrate the conversion data. The values of the offset
and gain calibration registers are internally written to perform calibration. The appropriate input signals must be
applied to the ADS1283 inputs before sending the commands. Use slower data rates to achieve more consistent
calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if calibrating at
power-on, be sure the reference voltage is fully settled.
Figure 57 shows the calibration command sequence. After the analog input voltage (and reference) have
stabilized, send the SDATAC command, followed by the SYNC and RDATAC commands. DRDY goes low after
64 data periods. After DRDY goes low, send the SDATAC command, then the calibrate command (OFSCAL or
GANCAL), followed by the RDATAC command. After 16 data periods, calibration is complete and conversion
data can be read at this time. The SYNC input must remain high during the calibration sequence.
VIN
Fully stable input and reference voltage.
Commands
SDATAC
DRDY
SYNC
RDATAC
SDATAC
OFSCAL or
GANCAL
RDATAC
16 Data
Periods
64 Data Periods
Calibration
Complete
SYNC
Figure 57. Offset and Gain Calibration Timing
The calibration commands apply to specific PGA settings. If the PGA is changed, recalibration is necessary.
Calibration is bypassed in the sinc filter mode.
8.4.11.1 OFSCAL Command
The OFSCAL command performs an offset calibration. Before sending the OFSCAL command sequence
(Figure 57), a zero input signal must be applied to the ADS1283 and the inputs allowed to stabilize. When the
command sequence (Figure 57) is sent, the ADS1283 averages 16 readings, and then writes this value to the
OFC register. The contents of the OFC register can be subsequently read or written. During offset calibration, the
full-scale correction is bypassed. Use the OFSCAL command to calibrate the optional 100-mV offset.
8.4.11.2 GANCAL Command
The GANCAL command performs a gain calibration. Before sending the GANCAL command sequence
(Figure 57), a dc input must be applied (typically full-scale input, but not to exceed 106% full-scale). After the
signal has stabilized, the command sequence can be sent. The ADS1283 averages 16 readings, then computes
a gain value that scales the applied calibration voltage to full-scale. The gain value is written to the FSC register,
where the contents are subsequently read or written.
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8.4.12 User Calibration
System calibration of the ADS1283 can be performed without using the calibration commands. This procedure
requires the calibration values to be externally calculated and then written to the calibration registers. The steps
for this procedure are:
1. Set the OFSCAL[2:0] register = 0h, and GANCAL[2:0] = 400000h. These values set the offset and gain
registers to 0 and 1, respectively.
2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average the
output readings. Higher numbers of averaged readings result in more consistent calibration. Write the
averaged value to the OFC register.
3. Apply a differential dc signal, or an ac signal (typically full-scale, but do not exceed 106% FSR). Wait for the
system to settle and then average the output readings.
The value written to the FSC registers is calculated by Equation 16 or Equation 17.
DC-signal calibration is shown in Equation 16. The expected output code is based on 31-bit output data.
FSC[2:0] = 400000h ´
Expected Output Code
Actual Output Code
(16)
For ac-signal calibration, use an RMS value of collected data, as shown in Equation 17:
Expected RMS Value
FSC[2:0] = 400000h ´
Actual RMS Value
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8.5 Programming
8.5.1 Commands
The commands listed in Table 23 control the operation of the ADS1283. Most commands are stand-alone (that
is, one byte in length); the register read and write commands are two bytes long in addition to the actual register
data bytes.
Table 23. Command Descriptions
COMMAND
TYPE
1st COMMAND BYTE (1) (2)
DESCRIPTION
WAKEUP
Control
Wake-up from standby mode
0000 000X (00h or 01h)
STANDBY
Control
Enter standby mode
0000 001X (02h or 03h)
SYNC
Control
Synchronize the analog-to-digital conversion
0000 010X (04h or 5h)
RESET
Control
Reset registers to default values
0000 011X (06h or 07h)
RDATAC
Control
Enter read data continuous mode
0001 0000 (10h)
SDATAC
Control
Stop read data continuous mode
0001 0001 (11h)
Read data by command (4)
2nd COMMAND BYTE (3)
RDATA
Data
RREG
Register
Read nnnnn register(s) at address rrrrr (4)
001r rrrr (20h + 000r rrrr)
000n nnnn (00h + n nnnn)
Register
Write nnnnn register(s) at address rrrrr
010r rrrr (40h + 000r rrrr)
000n nnnn (00h + n nnnn)
WREG
0001 0010 (12h)
OFSCAL
Calibration
Offset calibration
0110 0000 (60h)
GANCAL
Calibration
Gain calibration
0110 0001 (61h)
(1)
(2)
(3)
(4)
X = don't care.
rrrrr = starting address for register read and write commands.
nnnnn = number of registers to be read from or written to – 1. For example, to read from or write to three registers, set nnnnn = 2
(00010).
Required to cancel read-data-continuous mode before sending a command.
CS must remain low for duration of the command-byte sequence. A delay of 24 fCLK cycles between commands
and between bytes within a command is required, starting from the last SCLK rising edge of one command to the
first SCLK rising edge of the following command. The required delay is shown in Figure 58.
CS
DIN
Command
Byte
Command
Byte
SCLK
tSCLKDLY(1)
(1)
tSCLKDLY(1)
tSCLKDLY = 24 / fCLK (min).
Figure 58. Consecutive Commands
8.5.1.1 SDATAC Requirements
In read-data-continuous mode, the ADS1283 places conversion data on the DOUT pin as SCLK is applied. As a
result of the potential conflict between conversion data and register data placed on DOUT resulting from a RREG
or RDATA operation, it is necessary to send a stop-read-data-continuous (SDATAC) command before a RREG
or RDATA command. The SDATAC command disables the direct output of conversion data on the DOUT pin.
CS = 1 cancels SDATAC mode; therefore, keep CS held low after sending the SDATAC command to the next
RREG or RDATA command.
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8.5.1.2 WAKEUP: Wake-Up From Standby Mode
The WAKEUP command is used to exit the standby mode. After sending this command, the time for the first data
to be ready is illustrated in Figure 48 and Table 16. Sending this command during normal operation has no
effect; for example, reading data by the read-data-continuous mode with DIN held low.
8.5.1.3 STANDBY: Standby Mode
The STANDBY command places the ADS1283 into standby mode. In standby, the device enters a reduced
power state where a low quiescent current remains to keep the register settings and serial interface active. The
ADC remains in standby mode until CS is taken high or the WAKEUP command is sent. For complete device
shutdown, take the PWDN pin low (register settings are not saved). The operation of standby mode is shown in
Figure 59.
0000 001X
(STANDBY)
DIN
0000 000X
(WAKEUP)
SCLK
Operating
Standby Mode
Operating
Figure 59. STANDBY Command Sequence
8.5.1.4 SYNC: Synchronize the Analog-to-Digital Conversion
The SYNC command synchronizes the analog-to-digital conversion. Upon receiving the command, the reading in
progress is cancelled and the conversion process is restarted. In order to synchronize multiple ADS1283s, the
command must be sent simultaneously to all devices. The SYNC pin must be held high during this command.
8.5.1.5 RESET: Reset the Device
The RESET command resets the registers to default values, enables read-data-continuous mode, and restarts
the conversion process. The RESET command is functionally equivalent to taking the RESET pin low. See
Figure 47 for the RESET command timing.
8.5.1.6 RDATAC: Read Data Continuous
The RDATAC command enables read-data-continuous mode (default mode). In this mode, conversion data is
read from the device directly without the need to supply a data read command. Each time DRDY falls low, new
data are available to read. See the Read-Data-Continuous Mode section for more details.
8.5.1.7 SDATAC: Stop Read Data Continuous
The SDATAC command stops read-data-continuous mode. Exit read-data-continuous mode before sending
register and data read commands. The SDATAC command suppresses the DRDY output, but the ADS1283
continues conversions. Take CS high to cancel SDATAC mode.
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8.5.1.8 RDATA: Read Data by Command
The RDATA command reads the conversion data. See the Read-Data-By-Command Mode section for more
details.
8.5.1.9 RREG: Read Register Data
The RREG command is used to read single- or multiple-register data. The command consists of a two-byte
opcode argument, followed by the output of register data. The first byte of the opcode includes the starting
address, and the second byte specifies the number of registers to read minus one.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers to read minus one.
Starting with the 16th falling edge of SCLK, the register data appear on DOUT. Read the data on the 17th SCLK
rising edge.
The RREG command is illustrated in Figure 60.
A delay of 24 fCLK cycles is required between each byte transaction.
CS(1)
tDLY
1
2
3
4
5
6
7
8
9
tDLY
10 11 12 13 14 15 16
tDLY
17 18 19 20 21 22 23 24
25 26
SCLK
DIN
Command Byte 1
DOUT(2)
Command Byte 2
Don't Care
Register Data 5
Register Data 6
Example: Read six registers, starting at register 05h (OFC0)
Command Byte 1 = 0010 0101
Command Byte 2 = 0000 0101
(1)
DOUT is in tristate when CS is high. CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.
Figure 60. Read Register Data (Table 24 shows tDLY)
Table 24. tDRY Value
46
PARAMETER
MIN
tDLY
24 / fCLK
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8.5.1.10 WREG: Write to Register
The WREG command writes single- or multiple-register data. The command consists of a two-byte op-code
argument followed by the input of register data. The first byte of the op-code contains the starting address and
the second byte specifies the number of registers to write minus one.
First command byte: 010r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers to write minus one.
Data byte(s): one or more register data bytes, depending on the number of registers specified.
Figure 61 illustrates the WREG command.
A delay of 24 fCLK cycles is required between each byte transaction.
CS(1)
tDLY
1
2
3
4
5
6
7
8
9
tDLY
10 11 12 13 14 15 16
tDLY
17 18 19 20 21 22 23 24
25 26
SCLK
DIN
Command Byte 1
Command Byte 2
Register Data 5
Register Data 6
Example: Write six registers, starting at register 05h (OFC0)
Command Byte 1 = 0100 0101
Command Byte 2 = 0000 0101
(1)
CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.
Figure 61. Write Register Data (Table 24 shows tDLY)
8.5.1.11 OFSCAL: Offset Calibration
The OFSCAL command performs an offset calibration. The inputs to the converter (or the inputs to the external
preamplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration
register updates after this operation. See the Calibration Commands section for more details.
8.5.1.12 GANCAL: Gain Calibration
The GANCAL command performs a gain calibration. The inputs to the converter should have a stable dc input
(typically full-scale, but not to exceed 106% full-scale). The gain calibration register updates after this operation.
See the Calibration Commands section for more details.
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8.6 Register Maps
Collectively, the registers contain all the information needed to configure the device, such as data rate, filter
selection, calibration, and more. The registers are accessed by the RREG and WREG commands. The registers
can be accessed individually or as a block of registers by sending or receiving consecutive bytes. After a register
write operation, the ADC resets, resulting in an interruption of 63 readings.
Table 25. Register Map
ADDRESS
REGISTER
RESET
VALUE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
ID_CFG
X0h
ID3
ID2
ID1
ID0
0
0
OFFSET1
OFFSET0
01h
CONFIG0
52h
SYNC
1
DR2
DR1
DR0
PHASE
FILTR1
FILTR0
02h
CONFIG1
08h
0
MUX2
MUX1
MUX0
CHOP
PGA2
PGA1
PGA0
03h
HPF0
32h
HPF07
HPF06
HPF05
HPF04
HPF03
HPF02
HPF01
HPF00
04h
HPF1
03h
HPF15
HPF14
HPF13
HPF12
HPF11
HPF10
HPF09
HPF08
05h
OFC0
00h
OFC07
OFC06
OFC05
OFC04
OFC03
OFC02
OFC01
OFC00
06h
OFC1
00h
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC09
OFC08
07h
OFC2
00h
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
08h
FSC0
00h
FSC07
FSC06
FSC05
FSC04
FSC03
FSC02
FSC01
FSC00
09h
FSC1
00h
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC09
FSC08
0Ah
FSC2
40h
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
8.6.1 Register Descriptions
8.6.1.1 ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]
Figure 62. ID_CFG Register
7
ID3
R-xh
6
ID2
R-xh
5
ID1
R-xh
4
ID0
R-xh
3
0
R/W-0h
2
0
R/W-0h
1
OFFSET1
R/W-0h
0
OFFSET0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit[7:4]
ID[3:0]
Factory-programmed identification bits (read-only). The ID bits are subject to change
without notification.
Bit[3:2]
Reserved
Always write 00
Bit[1:0]
OFFSET[1:0] (see Offset section)
00: Disables offset (default)
01: Reserved
10: Offset = 100/PGA mV (all ADS1283 versions)
11: Offset = 75/PGA mV (ADS1283B only)
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8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
Figure 63. CONFIG0 Register
7
SYNC
R/W-0h
6
1
R/W-1h
5
DR2
R/W-0h
4
DR1
R/W-1h
3
DR0
R/W-0h
2
PHASE
R/W-0h
1
FILTR1
R/W -1h
0
FILTR0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit[7]
SYNC
Synchronization mode bit.
0: Pulse-sync mode (default)
1: Continuous-sync mode
Bit[6]
RESERVED
Always write 1
Bit[5:3]
DR[2:0]
Data rate select bits.
000: 250 SPS
001: 500 SPS
010: 1000 SPS (default)
011: 2000 SPS
100: 4000 SPS
Bit[2]
PHASE
FIR phase response bit.
0: Linear phase (default)
1: Minimum phase
Bit[1:0]
FILTR[1:0]
Digital filter configuration bits.
00: Reserved
01: Sinc filter block only
10: Sinc + LPF filter blocks (default)
11: Sinc + LPF + HPF filter blocks
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8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
Figure 64. CONFIG1 Register
7
0
R/W-0h
6
MUX2
R/W-0h
5
MUX1
R/W-0h
4
MUX0
R/W-0h
3
CHOP
R/W-1h
2
PGA2
R/W-0h
1
PGA1
R/W-0h
0
PGA0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit[7]
Reserved
Always write 0
Bit[6:4]
MUX[2:0]
MUX select bits.
000: AINP1 and AINN1 (default)
001: AINP2 and AINN2
010: Internal short through 400-Ω resistor
011: AINP1 and AINN1 connected to AINP2 and AINN2
100: External short to AINN2
Bit[3]
CHOP
PGA chopping enable bit.
0: PGA chopping disabled
1: PGA chopping enabled (default)
Bit[2:0]
PGA[2:0]
PGA gain select bits. Note that ADS1283A supports PGA gains of 1, 4, and 16 only.
000: G
001: G
010: G
011: G
100: G
101: G
110: G
=
=
=
=
=
=
=
1 (default)
2 (ADS1283 and ADS1283B only)
4
8 (ADS1283 and ADS1283B only)
16
32 (ADS1283 and ADS1283B only)
64 (ADS1283 and ADS1283B only)
8.6.1.4 HPF0 and HPF1 Registers
These two bytes (high-byte and low-byte, respectively) set the corner frequency of the high-pass filter.
8.6.1.4.1 HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]
Figure 65. HPF0 Register
7
HPF07
R/W-0h
6
HPF06
R/W-0h
5
HPF05
R/W-1h
4
HPF04
R/W-1h
3
HPF03
R/W-0h
2
HPF02
R/W-0h
1
HPF01
R/W-1h
0
HPF00
R/W-0h
1
HPF09
R/W-1h
0
HPF08
1R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.4.2 HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]
Figure 66. HPF1 Register
7
HPF15
R/W-0h
6
HPF14
R/W-0h
5
HPF13
R/W-0h
4
HPF12
R/W-0h
3
HPF11
R/W-0h
2
HPF10
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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8.6.1.5 OFC0, OFC1, OFC2 Registers
These three bytes set the offset calibration value.
8.6.1.5.1 OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]
Figure 67. OFC0 Register
7
OFC07
R/W-0h
6
OFC06
R/W-0h
5
OFC05
R/W-0h
4
OFC04
R/W-0h
3
OFC03
R/W-0h
2
OFC02
R/W-0h
1
OFC01
R/W-0h
0
OFC00
R/W-0h
2
OFC10
R/W-0h
1
OFC09
R/W-0h
0
OFC08
R/W-0h
2
OFC18
R/W-0h
1
OFC17
R/W-0h
0
OFC16
R/W-0h
2
FSC02
R/W-0h
1
FSC01
R/W-0h
0
FSC00
R/W-0h
2
FSC10
R/W-0h
1
FSC09
R/W-0h
0
FSC08
R/W-0h
1
FSC17
R/W-0h
0
FSC16
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.5.2 OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]
Figure 68. OFC1 Register
7
OFC15
R/W-0h
6
OFC14
R/W-0h
5
OFC13
R/W-0h
4
OFC12
R/W-0h
3
OFC11
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.5.3 OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]
Figure 69. OFC2 Register
7
OFC23
R/W-0h
6
OFC22
R/W-0h
5
OFC21
R/W-0h
4
OFC20
R/W-0h
3
OFC19
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.6 FSC0, FSC1, FSC2 Registers
These three bytes set the full-scale calibration value.
8.6.1.6.1 FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]
Figure 70. FSC0 Register
7
FSC07
R/W-0h
6
FSC06
R/W-0h
5
FSC05
R/W-0h
4
FSC04
R/W-0h
3
FSC03
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.6.2 FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]
Figure 71. FSC1 Register
7
FSC15
R/W-0h
6
FSC14
R/W-0h
5
FSC13
R/W-0h
4
FSC12
R/W-0h
3
FSC11
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.6.3 FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]
Figure 72. FSC2 Register
7
FSC23
R/W-0h
6
FSC22
R/W-1h
5
FSC21
R/W-0h
4
FSC20
R/W-0h
3
FSC19
R/W-0h
2
FSC18
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1283 is a very high-resolution ADC. Optimal performance requires giving special attention to the
support circuitry and printed circuit board (PCB) design. Locate noisy digital components (such as
microcontrollers, oscillators, and so on) in an area of the PCB away from the converter and front-end
components. Keep the digital current path short and separate from sensitive analog components by placing the
digital components close to the power-entry point.
9.2 Typical Applications
9.2.1 Geophone Interface
A typical geophone front-end application is shown in Figure 73. The application diagram shows the ADS1283
operation with dual ±2.5-V analog supplies. The ADS1283 can also operate with a single 5-V analog supply.
+2.5V
2.5V
1 PF
AVDD
AVSS
AINP2
Test
Signal
+2.5V
(1)
R1
100 Ÿ
AINN2
R3
100 Ÿ
AINP1
R5
20 kŸ
C2
1 nF, C0G
R2
R6
20 kŸ 100 Ÿ
R4
C3
1 nF, C0G 100 Ÿ
Geophone
C4
10nF
C0G
AINN1
ADC
-2.5V
C6
10 nF
C0G
+3.3V
R7
1 kŸ
1 PF
CAPN
(2)
VREFP
REF5050
NR
+
1 PF
CAPP
1 PF
C5
100 PF
C7
0.1 PF
VREFN
DGND
2.5V
(1)
Optional external diode clamps.
(2)
Optional reference noise filter.
Figure 73. Geophone Interface Application
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Typical Applications (continued)
The geophone input signal is filtered by both a differential filter (components C4 and R1 to R4) and by commonmode filters (components C2, C3 and R1, R2). The differential filter removes high-frequency normal-mode
components from the input signal. The common-mode filters remove high-frequency components that are
common to both input leads. The input filters are not required for all applications; check the system requirements
for each application.
Resistors R5 and R6 bias the signal input to the midsupply point (ground). For single-supply operation, set the
bias to a low impedance midsupply point (AVDD / 2 = 2.5 V).
Optional diode clamps protect the ADS1283 inputs from high-level voltage transients and overloads. The diodes
provide additional protection if possible high-level input transients and surges exceed the ADC internal ESD
diode rating.
The REF5050 5-V reference provides the reference to the ADC. An optional filter network (R7 and C5) reduces
the in-band reference noise for improved dynamic performance. However, the RC filter network increases the
filter settling-time (from seconds to possibly minutes) depending on the dielectric absorption properties of
capacitor C5. Capacitor C7 is mandatory and provides high-frequency bypassing of the reference inputs; place C7
as close as possible to the ADS1283 pins. Resistor R7 (1 kΩ) results in a 1% systematic gain error. Multiple
ADCs can share a single reference, but if shared, use independent reference filters for each ADC.
As an alternative, the REF5045 (4.5 V) reference can be used. The REF5045 reference has the advantage of
operating directly from the 5-V (total) power supply; however, the 4.5-V reference reduces signal range by 10%
and results in a 1-dB loss of SNR.
Capacitor C6 (10 nF) filters the PGA output glitches caused by sampling of the modulator. This capacitor also
forms an antialias filter with a low-pass cutoff frequency of 26 kHz.
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Typical Applications (continued)
9.2.2 Digital Interface
Figure 74 shows the digital connection to a controller (field programmable gate array or microcontroller). In this
example, two ADCs are shown connected to one controller. The ADCs share the same serial interface (SCLK,
DIN, and DOUT). The ADC is selected for communication by strobing each CS low. The DRDY output from both
ADCs can be used; however, when the devices are synchronized, the DRDY output from only one device is
sufficient.
Clock
ADC #1
+3.3V
(1)
CLK
DVDD
1 µF
RESET
SYNC
47 Ÿ
CS
SCLK
CLK (input)
RESET (output)
47 Ÿ
47 Ÿ
BYPAS
1 µF
Controller
47 Ÿ
47 Ÿ
SYNC (output)
SS1 (output)
SCLK (output)
47 Ÿ
MOSI (output)
DIN
DOUT
DGND
MFLAG
(1)
DVDD
47 Ÿ
47 Ÿ
ADC #2
+3.3V
47 Ÿ
47 Ÿ
CLK
47 Ÿ
RESET
1 µF
MISO (input)
MFLAG1 (input)
MFLAG2 (input)
SS2 (output)
DRDY (input)
SYNC
BYPAS
CS
SCLK
1 µF
DIN
DOUT
MFLAG
DRDY
DGND
(1)
For DVDD < 2.25 V, tie DVDD and BYPASS together. see the DVDD Power Supply section.
Figure 74. Controller Interface with Dual ADCs
The modulator overrange flag (MFLAG) from each device ties to the controller input. For synchronization,
connect all ADCs to the same SYNC signal. For reset, either connect all ADCs to the same RESET signal or
connect the ADCs to individual RESET signals.
Avoid ringing on the digital inputs to the ADCs. Place 47-Ω resistors in series with the digital traces to help
reduce ringing by controlling impedances. Place the resistors at the source (driver) end of the trace. Do not float
unused digital inputs; tie them to DVDD or GND.
54
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9.3 Initialization Set Up
After reset or power-on, configure the registers using the following procedure:
1. Reset the serial interface. Before using the serial interface, it may be necessary to recover the serial
interface (undefined I/O power-up sequencing may cause a false SCLK to occur). To reset the interface,
toggle the CS pin high then low, or toggle the RESET pin high then low, or when in read-data-continuous
mode, hold SCLK low for 64 DRDY periods.
2. Configure the registers. The registers are configured by either writing to them individually or as a group,
and can be configured in either mode. To cancel read-data-continuous mode, send the SDATAC command
before register read and write operations .
3. Verify register data. For verification of device communications, read back the register.
4. Set the data mode. After register configuration, configure the device for read-data-continuous mode by
executing the RDATAC command, or configure for read-data-by-command mode (set in step 2, by the
SDATAC command).
5. Synchronize readings. Whenever SYNC is high, the ADS1283 freely runs the data conversions. To
resynchronize the conversions in pulse-sync mode, take SYNC low and then high. In continuous-sync mode,
apply the synchronizing clock to the SYNC pin with a clock period equal to multiples of the ADC conversion
period.
6. Read data. If read-data-continuous mode is active, the data are read directly after DRDY falls by applying
SCLK pulses. If the read-data-continuous mode is inactive, the data can only be read by executing the
RDATA command. The RDATA command must be sent in this mode to read each conversion result.
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.3 Trademarks
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
56
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58
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1283BIRHFR
ACTIVE
VQFN
RHF
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS
1283B
ADS1283BIRHFT
ACTIVE
VQFN
RHF
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS
1283B
ADS1283IRHFR
ACTIVE
VQFN
RHF
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS
1283
ADS1283IRHFT
ACTIVE
VQFN
RHF
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS
1283
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS1283BIRHFR
VQFN
RHF
24
ADS1283BIRHFT
VQFN
RHF
ADS1283IRHFR
VQFN
RHF
ADS1283IRHFT
VQFN
RHF
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
24
250
180.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
24
3000
330.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
24
250
180.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1283BIRHFR
VQFN
RHF
24
3000
367.0
367.0
35.0
ADS1283BIRHFT
VQFN
RHF
24
250
210.0
185.0
35.0
ADS1283IRHFR
VQFN
RHF
24
3000
367.0
367.0
35.0
ADS1283IRHFT
VQFN
RHF
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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