Texas Instruments | ADS7028 Small, 8-Channel, 12-Bit ADC With SPI Interface, GPIOs, and CRC | Datasheet | Texas Instruments ADS7028 Small, 8-Channel, 12-Bit ADC With SPI Interface, GPIOs, and CRC Datasheet

Texas Instruments ADS7028 Small, 8-Channel, 12-Bit ADC With SPI Interface, GPIOs, and CRC Datasheet
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ADS7028
SBAS978 – JUNE 2019
ADS7028 Small, 8-Channel, 12-Bit ADC With SPI Interface, GPIOs, and CRC
1 Features
2 Applications
•
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•
•
•
•
•
•
•
•
•
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•
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•
Small package size:
– WQFN 3 mm × 3 mm
8 channels configurable as any combination of:
– Up to 8 analog inputs, digital inputs, or digital
outputs
GPIOs for I/O expansion:
– Open-drain, push-pull digital outputs
Analog watchdog:
– Programmable thresholds per channel
– Event counter for transient rejection
Wide operating ranges:
– AVDD: 2.35 V to 5.5 V
– DVDD: 1.65 V to 5.5 V
– –40°C to +85°C temperature range
Enhanced-SPI digital interface:
– High-speed, 60-MHz interface
– Achieve full throughput with >13.5-MHz SPI
CRC for read/write operation:
– CRC on data read/write
– CRC on power-up configuration
Programmable averaging filters
Root-mean-square module:
– 16-bit true RMS output
– Programmable RMS time window
Zero-crossing-detect module:
– ZCD output corresponding to analog input
– Built-in transient rejection and hysteresis
– Digitally adjustable detection threshold
Supervisory functions
Portable instrumentation
Appliances
Telecommunication infrastructure
Power-supply monitoring
3 Description
The ADS7028 is an easy-to-use, 8-channel,
multiplexed,
12-bit,
1-MSPS,
successive
approximation register analog-to-digital converter
(SAR ADC). The eight channels can be
independently configured as either analog inputs,
digital inputs, or digital outputs. The device has an
internal oscillator for the ADC conversion process.
The ADS7028 communicates via an SPI-compatible
interface and operates in either autonomous or
single-shot conversion mode. The ADS7028
implements the analog watchdog function by eventtriggered interrupts per channel using a digital
window comparator with programmable high and low
thresholds, hysteresis, and an event counter. The
ADS7028 has a built-in cyclic redundancy check
(CRC) for data read/write operations and the powerup configuration. The ADS7028 features a root-meansquare (RMS) module that computes a 16-bit true
RMS result for any analog input channel. The
integrated zero-crossing-detect (ZCD) module allows
for transient rejection and hysteresis near the
configurable threshold crossings.
Device Information(1)
PART NUMBER
ADS7028
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
ADS7028 Block Diagram and Applications
Device Block Diagram
Example System Architecture
DECAP
AVDD
VCC
DVDD
Digital Window
Comparator
AIN0 / GPIO0
AIN1 / GPIO1
ADC
LOAD
AVDD
High/Low Threshold
± Hysteresis
OVP
Programmable
Averaging Filters
AIN2 / GPIO2
MUX
AIN3 / GPIO3
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
CS
MUX
SPI Interface
and
CRC
Verification
Sequencer
Pin CFG
GPO Write
RMS Module
GPI Read
ZCD Module
SCLK
ADC
GPIO
OCP
SDI
SDO
GND
OVP: Over voltage protection
OCP: Over current protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
ADS7028
SBAS978 – JUNE 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
8.4 Device Functional Modes........................................ 21
8.5 ADS7028 Registers................................................. 25
9
Application and Implementation ........................ 69
9.1 Application Information............................................ 69
9.2 Typical Applications ................................................ 69
10 Power Supply Recommendations ..................... 71
10.1 AVDD and DVDD Supply Recommendations....... 71
11 Layout................................................................... 72
11.1 Layout Guidelines ................................................. 72
11.2 Layout Example .................................................... 72
12 Device and Documentation Support ................. 73
12.1
12.2
12.3
12.4
12.5
Detailed Description .............................................. 9
ADVANCE INFORMATION
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
73
73
73
73
73
13 Mechanical, Packaging, and Orderable
Information ........................................................... 73
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
June 2019
*
Initial release.
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5 Device Comparison Table
PART
NUMBER
DESCRIPTION
ADS7028
ADS7038
8-channel, 12-bit ADC with SPI
interface and GPIOs
ZERO-CROSSING-DETECT
(ZCD) MODULE
ROOT-MEAN-SQUARE
(RMS) MODULE
Yes
Yes
Yes
Yes
No
No
Yes
No
No
ADVANCE INFORMATION
ADS7038-Q1
CRC MODULE
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6 Pin Configuration and Functions
12
SDO
11
CS
10
DVDD
AIN1/GPIO1
AIN0/GPIO0
SDI
SCLK
15
14
13
9
ADVANCE INFORMATION
8
4
DECAP
AIN5/GPIO5
Pad
7
3
AVDD
AIN4/GPIO4
Thermal
6
2
AIN7/GPIO7
AIN3/GPIO3
5
1
AIN6/GPIO6
AIN2/GPIO2
16
RTE Package
16-Pin WQFN
Top View
GND
Not to scale
Pin Functions
PIN
NAME
NO.
FUNCTION (1)
DESCRIPTION
AIN0/GPIO0
15
AI, DI, DO
Channel 0; can be configured as either an analog input (default), digital input, or digital output.
AIN1/GPIO1
16
AI, DI, DO
Channel 1; can be configured as either an analog input (default), digital input, or digital output.
AIN2/GPIO2
1
AI, DI, DO
Channel 2; can be configured as either an analog input (default), digital input, or digital output.
AIN3/GPIO3
2
AI, DI, DO
Channel 3; can be configured as either an analog input (default), digital input, or digital output.
AIN4/GPIO4
3
AI, DI, DO
Channel 4; can be configured as either an analog input (default), digital input, or digital output.
AIN5/GPIO5
4
AI, DI, DO
Channel 5; can be configured as either an analog input (default), digital input, or digital output.
AIN6/GPIO6
5
AI, DI, DO
Channel 6; can be configured as either an analog input (default), digital input, or digital output.
AIN7/GPIO7
6
AI, DI, DO
Channel 7; can be configured as either an analog input (default), digital input, or digital output.
AVDD
7
Supply
CS
11
DI
DECAP
8
Supply
Connect a decoupling capacitor to this pin for the internal power supply.
DVDD
10
Supply
Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND.
GND
9
Supply
Ground for the power supply; all analog and digital signals are referred to this pin voltage.
SCLK
13
DI
Serial clock for the SPI interface.
SDI
14
DI
Serial data in for the device.
SDO
12
DO
Serial data out for the device.
(1)
4
Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF
decoupling capacitor to GND.
Chip-select input pin; active low. The device takes control of the data bus when CS is low.
The device starts converting the active input channel on the rising edge of CS. SDO goes hi-Z
when CS is high.
AI = analog input, DI = digital input, and DO = digital output.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
DVDD to GND
AVDD to GND
MIN
MAX
–0.3
5.5
UNIT
V
–0.3
5.5
V
AINx / GPOx (2) to GND
GND – 0.3 AVDD + 0.3
V
Digital input to GND
GND – 0.3
5.5
V
Current through any pin except supply pins
(3)
–10
10
mA
Junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–60
150
°C
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AINx / GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16.
Pin current must be limited to 10mA or less.
ADVANCE INFORMATION
(1)
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
Analog supply voltage
2.35
3.3
5.5
V
DVDD
Digital supply voltage
1.65
3.3
5.5
V
ANALOG INPUTS
FSR
Full-scale input range
AINX - GND
0
AVDD
V
VIN
Absolute input voltage
AINX - GND
–0.1
AVDD + 0.1
V
85
℃
TEMPERATURE RANGE
TA
(1)
Ambient temperature
–40
25
AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
7.4 Thermal Information
ADS7028
THERMAL METRIC
(1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
49.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.4
°C/W
RθJB
Junction-to-board thermal resistance
24.7
°C/W
ΨJT
Junction-to-top characterization parameter
1.3
°C/W
ΨJB
Junction-to-board characterization parameter
24.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
CSH
Sampling capacitance
12
pF
DC PERFORMANCE
Resolution
No missing codes
DNL
Differential nonlinearity
INL
Integral nonlinearity
V(OS)
Input offset error
Post offset calibration
Input offset thermal drift
Post offset calibration
GE
Gain error
12
bits
–0.9
±0.2
0.9
LSB
–2
±0.5
2
LSB
–2
±0.3
2
±5
–0.1
±0.05
Gain error thermal drift
LSB
ppm/°C
0.1
±5
%FSR
ppm/°C
AC PERFORMANCE
ADVANCE INFORMATION
SINAD
Signal-to-noise + distortion ratio
SNR
Signal-to-noise ratio
Isolation crosstalk
AVDD = 5 V, fIN = 2 kHz
68.5
71.5
AVDD = 3 V, fIN = 2 kHz
67.5
70.5
AVDD = 5 V, fIN = 2 kHz
69
72
AVDD = 3 V, fIN = 2 kHz
68
71
fIN = 100 kHz
dB
dB
–100
dB
1
µF
DECAP Pin
Decoupling capacitor on DECAP
pin
0.1
SPI INTERFACE (CS, SCLK, SDI, SDO)
VIH
Input high logic level
VIL
Input low logic level
VOH
VOL
Output high logic level
Output low logic level
0.7 x DVDD
5.5
V
V
–0.3
0.3 x DVDD
Source current = 2 mA,
DVDD > 2 V
0.8 x DVDD
DVDD
Source current = 2 mA,
DVDD ≤ 2 V
0.7 x DVDD
DVDD
Sink current = 2 mA, DVDD > 2 V
0
0.4
Sink current = 2 mA, DVDD ≤ 2 V
0
0.2 x DVDD
0.7 x AVDD
AVDD + 0.3
V
V
GPIOs
VIH
Input high logic level
VIL
Input low logic level
–0.3
V
0.3 x AVDD
V
100
nA
0.8 x AVDD
AVDD
V
0
0.2 x AVDD
Input leakge current
GPIO configured as input
10
VOH
Output high logic level
GPO_DRIVE_CFG = push-pull,
ISOURCE = 2 mA
VOL
Output low logic level
ISINK = 2 mA
IOH
Output high source current
VOH > 0.7 x AVDD
5
mA
IOL
Output low sink current
VOL < 0.3 x AVDD
5
mA
V
POWER-SUPPLY CURRENTS
IAVDD
Analog supply current
Full throughput, AVDD = 5 V
2.66
Full throughput, AVDD = 3 V
1.56
No conversion, AVDD = 5 V
0.03
mA
0.05
7.6 Timing Requirements
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
MIN
MAX
UNIT
CONVERSION CYCLE
6
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Timing Requirements (continued)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
MIN
fCYCLE
Sampling frequency
tCYCLE
ADC cycle-time period
tACQ
Acquisition time
tQT_ACQ
MAX
UNIT
1000
kSPS
1 / fCYCLE
s
300
ns
Quiet acquisition time
10
ns
tD_CNVCAP
Quiet conversion time
10
ns
tWH_CSZ
Pulse duration: CS high
10
ns
tWL_CSZ
Pulse duration: CS low
10
ns
SPI INTERFACE TIMINGS
fCLK
Maximum SCLK frequency
tCLK
Minimum SCLK time period
60
MHz
tPH_CK
SCLK high time
0.45
0.55
tCLK
tPL_CK
SCLK low time
tSU_CSCK
Setup time: CS falling to the first SCLK capture edge
0.45
5
0.55
tCLK
ns
tSU_CKDI
Setup time: SDI data valid to the SCLK capture edge
1.2
ns
tHT_CKDI
Hold time: SCLK capture edge to data valid on SDI
0.65
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
5
ns
ns
7.7 Switching Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
PARAMETER
Test Conditions
MIN
MAX
UNIT
600
ns
CONVERSION CYCLE
tCONV
ADC conversion time
tACQ
Acquisition time
400
ns
RESET and ALERT
AVDD ≥ 2.35 V,
CDECAP = 1 µF
tPU
Power-up time for device
tRST
Delay time; RST bit = 1b to device reset
complete (1)
tALERT_HI
ALERT high period
ALERT_LOGIC[1:0]
= 1x
tALERT_LO
ALERT low period
ALERT_LOGIC[1:0]
= 1x
5
ms
5
ms
85
105
ns
85
105
ns
SPI INTERFACE TIMINGS
tDEN_CSDO
Delay time: CS falling to data enable
15
ns
tDZ_CSDO
Delay time: CS rising to SDO going Hi-Z
15
ns
tD_CKDO
Delay time: SCLK launch edge to (next)
data valid on SDO
15
ns
(1)
RST bit is automatically reset to 0b after tRST.
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Sample
S
Sample
S+1
CS
tcycle
tconv_max
tconv
tacq
tconv_min
ADCST (Internal)
CNV (S)
ACQ (S + 1)
Figure 1. Conversion Cycle Timing
ADVANCE INFORMATION
tCLK
tPH_CK
CS
tPL_CK
SCLK(1)
tSU_CKDI
tSU_CSCK
tD_CKCS
SCLK(1)
SDI
tDEN_CSDO
tDZ_CSDO
SDO
(1)
tHT_CKDI
tD_CKDO
SDO
The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 2. SPI-Compatible Serial Interface Timing
8
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8 Detailed Description
8.1 Overview
The ADS7028 is a small, eight-channel, multiplexed, 12-bit, 1-MSPS, analog-to-digital converter (ADC) with an
enhanced-SPI serial interface. The eight channels of the ADS7028 can be individually configured as either
analog inputs, digital inputs, or digital outputs. The device includes a digital comparator which can be used to
interrupt the host when a programmed high or low threshold is crossed on any input channel. The device uses an
internal oscillator for conversion. The ADC can be used in manual mode for reading ADC data over the SPI
interface or in autonomous mode for monitoring the analog inputs without an active SPI interface.
The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution. The
root-mean-square (RMS) module computes a 16-bit true RMS result of any analog input channel over a
configurable time window. The zero-crossing-detect (ZCD) module can be used to generate a digital output
corresponding to the programmable threshold crossings of any analog input channel.
8.2 Functional Block Diagram
High/Low Threshold
± Hysteresis
ADVANCE INFORMATION
DECAP
AVDD
DVDD
Digital Window
Comparator
AIN0 / GPIO0
AIN1 / GPIO1
ADC
Averager
1 to 128
AIN2 / GPIO2
AIN3 / GPIO3
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
CS
MUX
Sequencer
SPI Interface
SCLK
SDI
Pin CFG
GPO Write
RMS Module
GPI Read
ZCD Module
SDO
CRC (optional)
GND
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8.3 Feature Description
8.3.1 Multiplexer and ADC
The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose
inputs/outputs (GPIOs). Figure 3 shows that each input pin has ESD protection diodes to AVDD and GND. On
power-up or after device reset, all eight multiplexer channels are configured as analog inputs.
Figure 3 shows an equivalent circuit for pins configured as analog inputs. The ADC sampling switch is
represented by ideal switch (SW) in series with the resistor RSW (typically 150 Ω) and the sampling capacitor,
CSH (typically 12 pF).
AVDD
Pin CFG
GPIO0
AIN0 / GPIO0
RSW
SW
ADVANCE INFORMATION
MUX
CSH
AVDD
ADC
GPIO7
AIN7 / GPIO7
Multiplexer
Figure 3. Analog Inputs, GPIOs, and ADC Connections
During acquisition, the SW switch is closed to allow the signal on the selected analog input channel to charge the
internal sampling capacitor. During conversion, the SW switch is opened to disconnect the analog input channel
from the sampling capacitor.
The multiplexer channels can be configured as GPIOs in the PIN_CFG register. The direction of a GPIO (either
as an input or an output) can be set in the GPIO_CFG register. The logic level on the channels configured as
digital inputs can be read from the GPI_VALUE register. The digital outputs can be accessed by writing to the
GPO_OUTPUT_VALUE register. The digital outputs can be configured as either open-drain or push-pull in the
GPO_DRIVE_CFG register.
8.3.2 Reference
The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process.
TI recommends connecting a 1-µF, low-equivalent series resistance (ESR) ceramic decoupling capacitor
between the AVDD and GND pins.
8.3.3 ADC Transfer Function
The ADC output is in straight binary format. Equation 1 computes the ADC resolution:
1 LSB = VREF / 2N
where:
•
•
10
VREF = AVDD
N = 12
(1)
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Feature Description (continued)
Figure 4 and Table 1 detail the transfer characteristics for the device.
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
AVDD/2 (AVDD/2 + 1 LSB)
(AVDD ± 1 LSB)
Figure 4. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE FOR SINGLE-ENDED INPUT
CODE
DESCRIPTION
IDEAL OUTPUT
CODE
≤1 LSB
NFSC
Negative full-scale code
000
1 LSB to 2 LSBs
NFSC + 1
—
001
(AVDD / 2) to (AVDD / 2) + 1 LSB
MC
Mid code
800
(AVDD / 2) + 1 LSB to (AVDD / 2) + 2 LSB
MC + 1
—
801
≥ AVDD – 1 LSB
PFSC
Positive full-scale code
FFF
8.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the
CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit
to check the ADC offset calibration completion status.
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8.3.5 Programmable Averaging Filter
The ADS7028 features a built-in oversampling (OSR) function that can be used to average several samples. The
averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging filter
configuration is common to all analog input channels. Figure 5 shows that the averaging filter module output is
16 bits long. In manual conversion mode and auto-sequence mode, only the first conversion for the selected
analog input channel must be initiated by the host; see the Manual Mode and Auto-Sequence Mode sections. As
shown in Figure 5, any remaining conversions for the selected averaging factor are generated internally. The
time required to complete the averaging operation is determined by the sampling speed and number of samples
to be averaged. As shown in Figure 5, the 16-bit result can be read out after the averaging operation completes.
Sample
AINx
(start of averaging)
Sample
AINx
Sample
AINx
CS
N ± 1 conversions triggered
internally
tAVG = N samples x t CYCLE
ADVANCE INFORMATION
SCLK
SDO
[15:0] Data
16 clocks
Figure 5. Averaging Example
In autonomous mode of operation, samples from analog input channels that are enabled in the
AUTO_SEQ_CH_SEL register are averaged sequentially. The digital window comparator compares the top 12
bits of the 16-bit average result with the thresholds.
Equation 2 provides the LSB value of the 16-bit average result.
AVDD
1 LSB
216
(2)
8.3.6 CRC on Data Interface
The ADS7028 features a cyclic redundancy check (CRC) module for checking the integrity of the data bits
exchanged over the SPI interface. The CRC module is bidirectional, which appends an 8-bit CRC to every byte
read from the device and also evaluates the CRC of every incoming byte over the SPI interface. The CRC
module uses the CRC-8-CCITT polynomial (x8 + x2 + x + 1) for CRC computation.
To enable the CRC module, set the CRC_EN bit in the GENERAL_CFG register. Table 2 shows the different
ways that a CRC error that occurs when configuring the ADS7028 can be detected.
Table 2. Configuring Notifications when CRC Error is Detected
CRC ERROR NOTIFICATION
CONFIGURATION
DESCRIPTION
ALERT
ALERT_CRCIN = 1b
ALERT (internal signal) is asserted if a CRC error is detected
Status flags
APPEND_STATUS = 10b
4-bit status flags are appended to the ADC data. See the Output Data
Format section for details.
Register read
—
Read the CRCERR_IN bit to check if a CRC error was detected.
12
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When the ADS7028 detects a CRC error on the SPI interface, the erroneous data are ignored and the
CRCERR_IN bit is set. Additional notifications can be enabled as described in Table 2. Further register writes are
disabled until the CRCERR_IN bit is cleared by writing 1b to this bit. When using autonomous conversion mode,
further conversions can be disabled on a CRC error on the SPI interface by setting CONV_ON_ERR = 1b.
8.3.7 General-Purpose I/Os
The eight channels of the ADS7028 can be independently configured as analog inputs, digital inputs, or digital
outputs. Table 3 shows how the PIN_CFG and GPIO_CFG registers can be used to configure the device
channels.
PIN_CFG[7:0]
GPIO_CFG[7:0]
GPO_DRIVE_CFG[7:0]
CHANNEL CONFIGURATION
0
x
x
Analog input (default)
1
0
x
Digital input
1
1
0
Digital output; open-drain driver
1
1
1
Digital output; push-pull driver
Digital outputs can be configured to logic 1 or 0 by writing to the GPO_OUTPUT_VALUE register. Reading the
GPI_VALUE register returns the logic level for all channels configured as digital inputs or digital outputs. The
GPI_VALUE register can be read to detect a failure in external components, such as a floating pullup resistor or
a low-impedance pulldown resistor, that prevents digital outputs being set to the desired logic level.
8.3.8 Oscillator and Timing Control
The device uses an internal oscillator for conversion. When using the averaging module, the host initiates the
first conversion and subsequent conversions are generated internally by the device. Also, in autonomous mode
of operation, the start of the conversion signal is generated by the device. Table 4 describes how the sampling
rate can be controlled by the OSC_SEL and CLK_DIV[3:0] register fields when the device generates the start of
the conversion.
Table 4. Configuring Sampling Rate for Internal Conversion Start Control
OSC_SEL = 0
CLK_DIV[3:0]
SAMPLING FREQUENCY, fCYCLE
(kSPS)
OSC_SEL = 1
CYCLE TIME,
tCYCLE (µs)
SAMPLING FREQUENCY,
fCYCLE (kSPS)
CYCLE TIME, tCYCLE
(µs)
0000b
1000
1
31.25
32
0001b
666.7
1.5
20.83
48
0010b
500
2
15.63
64
0011b
333.3
3
10.42
96
0100b
250
4
7.81
128
0101b
166.7
6
5.21
192
0110b
125
8
3.91
256
0111b
83
12
2.60
384
1000b
62.5
16
1.95
512
1001b
41.7
24
1.3
768
1010b
31.3
32
0.98
1024
1011b
20.8
48
0.65
1536
1100b
15.6
64
0.49
2048
1101b
10.4
96
0.33
3072
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Table 3. Configuring Channels as Analog Inputs or GPIOs
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The conversion time of the device, given by tCONV in the Switching Characteristics table, is independent of the
OSC_SEL and CLK_DIV[3:0] configuration.
8.3.9 Output Data Format
Figure 6 shows various SPI frames for reading data. The data output is MSB aligned. If averaging is enabled the
output data from the ADC are 16 bits long, otherwise the output data are 12 bits long. Optionally, a 4-bit channel
ID or status flags can be appended at the end of the output data by configuring the APPEND_STATUS[1:0] field.
CS
SCLK
1
12
2
13
14
15
16
17
18
19
20
Data output when averaging is disabled
OSR[2:0] = 00b
12 SCLKs minimum. Remaining clocks optional.
SDO
LSB
MSB
Channel ID / Status Flags
ADVANCE INFORMATION
12 bit ADC data
4 bits optional
Data output when averaging is enabled
OSR[2:0] > 00b
16 SCLKs minimum. Remaining clocks optional.
SDO
LSB
MSB
Channel ID / Status Flags
16 bit averaged ADC data
4 bits optional
Figure 6. SPI Frames for Reading Data
8.3.10 Zero-Crossing-Detect Module
The zero-crossing-detect (ZCD) module generates a digital output corresponding to the designated analog input
signal crossing a configured threshold. Figure 7 shows the digital output corresponding to the threshold crossings
of an analog input. In order to detect the threshold crossings on a particular analog input, configure the 4-bit
channel ID in the ZCD_CHID register. The threshold crossing to be detected can be configured in the
corresponding HIGH_TH register. The output of the ZCD module can be connected to any digital output by
configuring the ZCD_TRIG_EN and GPO_VALUE_ZCD registers.
Transient rejection
Analog input
High threshold
AIN0
AIN1
High threshold
AIN2
MUX
ADC
ZCD Module
Programmable
Averaging Filters
AIN3
Sequencer
Configurable
GPO4
transient rejection time
GPO5
GPO6
Transient
Rejection
Channel ID
Digital Output
Logic
GPO7
Digital output
Figure 7. ZCD Module Operation and Block Diagram
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The ADC conversion result of the selected analog input channel is compared with the digital threshold that then
sets the digital output accordingly. Transients near zero crossings can be rejected, as calculated in Equation 3,
by configuring the ZCD_BLANKING register.
1
transient rejection time = MULT_EN × ZCD_BLANKING>6: 0? ×
seconds
sampling rate for ZCD channel
(3)
8.3.11 Digital Window Comparator
The internal digital window comparator (DWC) is available in both conversion modes (manual and autonomous).
The DWC outputs an internal ALERT signal. The internal ALERT signal can be output on any one of the digital
output channels by configuring the ALERT_PIN register. Figure 8 provides a block diagram for the digital window
comparator.
EVENT_RGN[0]
Digital input CH0
ALERT
(internal)
ADC
High threshold Hysteresis
Averager
1 to 128
EVENT_HIGH_FLAG[0]
MUX
Event
Counter
Low threshold +
Hysteresis
EVENT_LOW_FLAG[0]
ALERT_CH_SEL[0]
PIN_CFG[0]
GPIO_CFG[0]
All registers are
specific for individual
analog input
channels
Figure 8. Digital Window Comparator Block Diagram
The low-side threshold, high-side threshold, event counter, and hysteresis parameters are independently
programmable for each input channel. Figure 9 illustrates that the window comparator can monitor events for
every analog input channel.
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12-bit ADC data
or
[15:4] Average result
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High threshold Hysteresis
0xFFF
High threshold Hysteresis
Digital code
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Signal above limit
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Digital code
0xFFF
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Low threshold +
Hysteresis
0x000
0x000
Low threshold +
Hysteresis
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Signal below limit
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Samples
0x000
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Signal out of band
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High threshold Hysteresis
DWC_CH_POL = 0
Low threshold +
Hysteresis
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Signal out of band
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0xFFF
High threshold Hysteresis
Digital code
ADVANCE INFORMATION
Digital code
0xFFF
Samples
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Signal in band
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Low threshold +
Hysteresis
DWC_CH_POL = 1
0x000
Samples
Samples
Figure 9. Event Monitoring With the Window Comparator
To enable the digital window comparator, set the DWC_EN bit in the GENERAL_CFG register. By default,
hysteresis = 0, high threshold = 0xFFF, and low threshold = 0x000. For detecting when a signal is in-band, the
EVENT_RGN register must be configured. In each of the cases shown in Figure 9, either or both
ALERT_HIGH_FLAG and ALERT_LOW_FLAG can be set. The programmable event counter counts consecutive
threshold violations before alert flags are set. The event count can be set to a higher value to avoid transients in
the input signal setting the alert flags.
In order to assert the ALERT signal (internal) when the alert flag is set for a particular analog input channel, set
the corresponding bit in the DWC_CH_SEL register. Alert flags are set, irrespective of the DWC_CH_SEL
configuration, if DWC_EN = 1 and high or low thresholds are exceeded.
8.3.11.1 Interrupts From Digital Inputs
Table 5 shows that rising edge or falling edge events can be detected on channels configured as digital inputs.
Table 5. Configuring Interrupts From Digital Inputs
PIN_CFG[7:0]
16
GPIO_CFG[7:0]
EVENT_RGN[7:0]
EVENT DESCRIPTION
1
0
0
ALERT_HIGH_FLAG is set on the rising edge on the digital input
channel
1
0
1
ALERT_LOW_FLAG is set on the falling edge on the digital input
channel
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8.3.11.2 Triggering Digital Outputs With Alert and ZCD
Figure 10 shows that digital outputs can be updated in response to alerts from individual channels or
synchronous to the zero-crossing-detect signal.
Digital output 7
Digital output 0
Select alerts on which channels
should be enabled as triggers
CH [7:0]
trigger
GPO_TRIGGER_UPDATE_EN
[0]
Enable the triggers
GPO_OUTPUT_VALUE [0]
ADVANCE INFORMATION
GPO_ZCD_UPDATE_
EN [0]
GPO0_VALUE_ON_ZCD_CFG_
CH0 [1:0]
0
00
Logic 0
01
ZCD
10
ZCD
11
Logic 1
1
0
1
GPO_VALUE_ON_TRIGGER [0]
Figure 10. Block Diagram of the Digital Output Logic
8.3.11.2.1 Triggering Digital Outputs on Alerts
Any given digital output can be updated in response to an alert condition on one or more analog inputs and
digital inputs. To update the digital output in response to alert conditions, configure the trigger and the value to
be launched when the trigger occurs.
8.3.11.2.1.1 Trigger
The following events can act as triggers for updating the value on the digital output:
• An alert on one or more analog input channels. The digital window comparator must be enabled for these
channels.
• An alert on one or more digital input channels. The digital window comparator must be enabled for these
channels.
Configure the GPOx_TRIG_EVENT_SEL register to select which channels, analog inputs, or digital inputs can
trigger an update on the digital output pin. After configuring the triggers for updating a digital output, the logic can
be enabled by configuring the corresponding bit in the GPO_TRIGGER_UPDATE_EN register.
8.3.11.2.1.2 Output Value
The digital outputs can be set to logic 1 or logic 0 in response to triggers. The value to be updated on the digital
output when a trigger event occurs can be configured in the GPO_VALUE_ON_TRIGGER register.
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8.3.11.2.2 Changing Digital Outputs Synchronous to ZCD
Individual digital outputs can be set to either logic 0, logic 1, ZCD, or ZCD synchronous to the zero-crossingdetect signal. This function can be enabled for individual digital outputs by configuring the
GPO_VALUE_ON_ZCD_CFG_CHx field and setting the corresponding bit in the GPO_ZCD_UPDATE_EN [7:0]
register. See the Zero-Crossing-Detect Module section for details about the operation of ZCD module and
Figure 10 for a block diagram detailing controlling the digital outputs with the ZCD signal.
8.3.12 Root-Mean-Square Module
In the ADS7028, any one analog input channel can be selected for computing the RMS result. The RMS result is
computed over a block of samples from the selected channel and result can be read from the
RMS_RESULT_LSB and RMS_RESULT_MSB registers. As shown in Equation 4, compute the RMS result with
the 16-bit square root mean of the accumulated result of the squares of the ADC conversion data.
4/5 = ¨F
&1 2 + &2 2 + &3 2 + ® + &0 2
&1 + &2 + &3 + ® + &0 2
p .5$
GF>×l
0
0
ADVANCE INFORMATION
AC component
DC component
(4)
In Equation 4, D is the data corresponding to the analog input channel selected for RMS measurement and N is
the number of samples over which RMS is computed. The DC offset must be subtracted from the AC component
because the analog input signal to the ADC is unipolar. DC subtraction can be enabled or disabled, given by b in
Equation 4, by configuring the DC_SUB field. The size of a 1-LSB RMS result is given in Equation 5 and the
RMS result is 16 bits long.
1 LSB = AVDD / 216
(5)
The procedure for using the RMS module is outlined in the steps below:
1. Select the channel for RMS computation using the RMS_CHID field in the RMS_CFG register.
2. Define the time over which RMS is to be computed by configuring the RMS_SAMPLES field.
3. Start RMS computation by setting RMS_EN = 1 in the GENERAL_CFG register.
4. The RMS result is ready when the sample size defined by RMS_SAMPLES has been converted on the
analog input channel selected for RMS computation.
5. To monitor for completion of the RMS computation, poll the RMS_DONE bit in the SYSTEM_STATUS
register. The ALERT pin can also be used for requesting an interrupt by configuring the ALERT_RMS bit in
the ALERT_MAP register.
6. For starting a new RMS measurement, write 1 to the RMS_EN bit in the GENERAL_CFG register.
8.3.13 Minimum, Maximum, and Latest Data Registers
The ADS7028 can record the minimum, maximum, and latest code (statistics registers) for every analog input
channel. To enable or re-enable recording statistics, set the STATS_EN bit in the GENERAL_CFG register.
Writing 1 to the STATS_EN bit reinitializes the statistics module. Afterwards, results from new conversions are
recorded in the statistics registers.. Previous values can be read from the statistics registers until a new
conversion result is available. Before reading the statistics registers, set STATS_EN = 0 to prevent any updates
to this block of registers.
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8.3.14 Device Programming
8.3.14.1 Enhanced-SPI Interface
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds
and still achieve full throughput. As described in Table 6, the host controller can use any of the four SPIcompatible protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device.
PROTOCOL
SCLK POLARITY
(At the CS Falling Edge)
SCLK PHASE
(Capture Edge)
CPOL_CPHA[1:0]
DIAGRAM
SPI-00
SPI-01
Low
Rising
00b
Figure 11
Low
Falling
01b
Figure 12
SPI-10
High
Falling
10b
Figure 11
SPI-11
High
Rising
11b
Figure 12
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data
read and data write operations. To select a different SPI-compatible protocol, program the CPOL_CPHA[1:0]
field. This first write operation must adhere to the SPI-00 protocol. Any subsequent data transfer frames must
adhere to the newly-selected protocol.
CS
CS
CPOL = 0
CPOL = 0
SCLK
SCLK
CPOL = 1
CPOL = 1
SDO
MSB
MSB-1
MSB-2
LSB+1
LSB
SDO
0
Figure 11. Standard SPI Timing Protocol
(CPHA = 0)
MSB
MSB-1
LSB+1
LSB
Figure 12. Standard SPI Timing Protocol
(CPHA = 1)
8.3.14.2 Register Read/Write Operation
The device supports the commands listed in Table 7 to access the internal configuration registers.
Table 7. Opcodes for Commands
OPCODE
COMMAND DESCRIPTION
0000 0000b
No operation
0001 0000b
Single register read
0000 1000b
Single register write
0001 1000b
Set bit
0010 0000b
Clear bit
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Table 6. SPI Protocols for Configuring the Device
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8.3.14.2.1 Register Write
A 24-bit SPI frame is required for writing data to configuration registers. The 24-bit data on SDI, as shown in
Figure 13. consists of an 8-bit write command (0000 1000b), an 8-bit register address, and 8-bit data. The write
command is decoded on the CS rising edge and the specified register is updated with the 8-bit data specified
during the register write operation.
CS
SCLK
1
2
8
9
0000 1000b
(WR_REG)
SDI
10
16
18
17
8-bit Address
24
8-bit Data
Figure 13. Register Write Operation
ADVANCE INFORMATION
8.3.14.2.2 Register Read
Register read operation consists of two SPI frames: the first SPI frame initiates a register read and the second
SPI frame reads data from the register address provided in the first frame. As shown in Figure 14, the 8-bit
register address and the 8-bit dummy data are sent over the SDI pin during the first 24-bit frame with the read
command (0001 0000b). On the rising edge of CS, the read command is decoded and the requested register
data are available for reading during the next frame. During the second frame, the first eight bits on SDO
correspond to the requested register read. During the second frame, SDI can be used to initiate another
operation or can be set to 0.
CS
SCLK
SDI
1
2
0001 0000b
(RD_REG)
8
9
10
8-bit Address
16
17
18
0000 0000b
24
1
2
8
9
Command
10
16
8-bit Address
17
18
24
8-bit Data
Optional; can set SDI = 0
SDO
8-bit Register Data
Figure 14. Register Read Operation
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8.4 Device Functional Modes
Table 8 lists the functional modes supported by the ADS7028.
Table 8. Functional Modes
FUNCTIONAL
MODE
CONVERSION CONTROL
MUX CONTROL
CONV_MODE[1:0]
SEQ_MODE[1:0]
Manual
CS rising edge
Register write to MANUAL_CHID
00b
00b
On-the-fly
CS rising edge
First 5 bits after the CS falling edge
00b
10b
Auto-sequence
CS rising edge
Channel sequencer
00b
01b
Autonomous
Internal to the device
Channel sequencer
01b
01b
The device powers up in manual mode and can be configured into either of these modes by writing the
configuration registers for the desired mode.
8.4.1 Device Power-Up and Reset
8.4.2 Manual Mode
Manual mode allows the external host processor to directly select the analog input channel. Figure 15 shows the
steps for operating the device in manual mode.
Idle
SEQ_MODE = 0
CONV_MODE = 0
Configure channels as AIN/GPIO using PIN_CFG
Select Manual mode
(CONV_MODE = 00b, SEQ_MODE = 00b)
Configure desired Channel ID in MANUAL_CHID field
Host starts conversion and reads conversion result
No
Same
Channel ID?
Yes
Figure 15. Device Operation in Manual Mode
In manual mode, the command to switch to a new channel (indicated by cycle N in Figure 16) is decoded by the
device on the CS rising edge. The CS rising edge is also the start of the conversion signal, and therefore the
device samples the previously selected MUX channel in cycle N+1. The newly selected analog input channel
data are available in cycle N+2. For switching the analog input channel, a register write to the MANUAL_CHID
field requires 24 clocks; see the Register Write section for more details. After a channel is selected, the number
of clocks required for reading the output data depends on the device output data frame size; see the Output Data
Format section for more details.
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On power-up, the BOR bit is set indicating a power-cycle or reset event. The device can be reset by setting the
RST bit or by recycling the power on the AVDD pin.
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Sample
AINx
Sample
AINx
Sample
AINy
tCONV
Sample
AINz
tCYCLE
CS
SCLK
SDI
SDO
ADVANCE INFORMATION
100-ns
Switch to AINy
Switch to AINz
Switch to AINx
Data AINx
Data AINx
Data AINy
24 clocks
MUX OUT = AINx
MUX
Cycle N
MUX OUT = AINy
MUX OUT = AINz
Cycle (N + 1)
Cycle (N + 2)
Figure 16. Starting Conversions and Reading Data in Manual Mode
8.4.3 On-the-Fly Mode
In the on-the-fly mode of operation, the analog input channel is selected, as shown in Figure 17, using the first
five bits on SDI without waiting for the CS rising edge. Thus, the ADC samples the newly selected channel on
the CS edge and there is no latency between the channel selection and the ADC output data.
Sample
AINx
Sample
AINx
Sample
AINy
tCONV
Sample
AINz
tCYCLE
CS
SCLK
1
24
1
2
3
4
5
12
1
2
3
4
5
12
5 clocks
SEQ_MODE =
10b
SDI
SDO
1
4-bit AINy ID
Data AINx
1
4-bit AINz ID
12 clocks
12 clocks
Data AINx
Data AINy
24 clocks
MUX
MUX OUT = AINx
100-ns
MUX OUT = AINy
MUX OUT = AINx
MUX OUT = AINz
No Cycle Latency
Figure 17. Starting Conversions and Reading Data in On-the-Fly Mode
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The number of clocks required for reading the output data depends on the device output data frame size; see the
Output Data Format section for more details.
8.4.4 Auto-Sequence Mode
In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input
channel after every conversion. The desired analog input channels can be configured for sequencing in the
AUTO_SEQ_CHSEL register. To enable the channel sequencer, set SEQ_START = 1b. After every conversion,
the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel
sequencer from selecting channels, set SEQ_START = 0b.
In the example shown in Figure 18, AIN2 and AIN6 are enabled for sequencing in AUTO_SEQ_CHSEL. The
channel sequencer loops through AIN2 and AIN6 and repeats until SEQ_START is set to 0b. The number of
clocks required for reading the output data depends on the device output data frame size; see the Output Data
Format section for more details.
Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN2
Sample
AIN6
tCYCLE
ADVANCE INFORMATION
CS
SCLK
SDI
SDO
MUX
SEQ_START
Data AINx
Data AINx
24 clocks
12 clocks
MUX OUT = AINx
MUX OUT = AIN2
Data AIN2
Data AIN6
Data AIN2
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AIN6
Scan channels AIN2 and AIN6 and repeat
Figure 18. Starting Conversions and Reading Data in Auto-Sequence Mode
8.4.5 Autonomous Mode
In autonomous mode, the device can be programmed to monitor the voltage applied on the analog input pins of
the device and generate an ALERT signal internal to the device when the programmable high or low threshold
values are crossed. The internal ALERT signal can be mapped to any one digital output channel by configuring
the channel ID in the ALERT_PIN[3:0] register field. In autonomous mode, the device generates the start of
conversion using the internal oscillator. The first start of conversion must be provided by the host and the device
generates the subsequent start of conversions.
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Figure 19 shows the steps for configuring the functional mode to autonomous mode. Abort the on-going
sequence by setting the SEQ_START to 0b before changing the functional mode or configuration of device.
Idle
SEQ_MODE = 0
CONV_MODE = 0
Configure channels as AIN/GPIO using GPIO_CFG
Channel
selection
Enable analog inputs for sequencing (AUTO_SEQ_CHSEL)
Select Auto-sequence mode (SEQ_MODE = 01b)
Configure alert condition using HIGH_THRESHOLD_CHx,
LOW_THRESHOLD_CHx,EVENT_COUNT, HYSTERESIS_CHx, and
EVENT_REGION_CHx fields
Enable analog inputs to trigger ALERT pin using ALERT_CH_SEL
ADVANCE INFORMATION
Configuration
Threshold & Alert
configuration
Configure ALERT pin behavior using ALERT_DRIVE and ALERT_LOGIC
Configure sampling rate of analog inputs using OSC_SEL and CLK_DIV
Set mode to autonomous monitoring (CONV_MODE = 01b)
Sampling rate
configuration
(optional) Enable averaging and min/max recording (OSR[2:0] and STATS_EN)
Enable threshold comparison (DWC_EN = 1)
Enable autonomous monitoring (SEQ_START = 1)
Active Operation
(Host can sleep)
No
ALERT?
(optional) read conversion results in
MIN_VALUE_CHx, MAX_VALUE_CHx, and
LAST_VALUE_CHx registers
Yes
Stop autonomous monitoring (SEQ_START = 0)
Disable threshold comparison (DWC_EN = 0)
ALERT Detected
Read alert flags ± EVENT_FLAG, EVENT_HIGH_FLAG, EVENT_LOW_FLAG
Clear alert flags ± EVENT_HIGH_FLAG, EVENT_LOW_FLAG
Figure 19. Configuring the Device in Autonomous Mode
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8.5 ADS7028 Registers
Table 9 lists the ADS7028 registers. All register offset addresses not listed in Table 9 should be considered as
reserved locations and the register contents should not be modified.
Table 9. ADS7028 Registers
Acronym
0x0
SYSTEM_STATUS
0x1
GENERAL_CFG
0x2
DATA_CFG
0x3
OSR_CFG
0x4
OPMODE_CFG
0x5
PIN_CFG
0x7
GPIO_CFG
0x9
GPO_DRIVE_CFG
0xB
GPO_OUTPUT_VALUE
0xD
GPI_VALUE
0xF
ZCD_BLANKING_CFG
0x10
SEQUENCE_CFG
0x11
CHANNEL_SEL
0x12
AUTO_SEQ_CH_SEL
0x14
ALERT_CH_SEL
0x16
ALERT_MAP
0x17
ALERT_PIN_CFG
0x18
EVENT_FLAG
Register
Name
Section
SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
DATA_CFG Register (Address = 0x2) [reset = 0x0]
OSR_CFG Register (Address = 0x3) [reset = 0x0]
OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
PIN_CFG Register (Address = 0x5) [reset = 0x0]
GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
GPI_VALUE Register (Address = 0xD) [reset = 0x0]
ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0]
SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0]
ALERT_MAP Register (Address = 0x16) [reset = 0x0]
ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0]
EVENT_FLAG Register (Address = 0x18) [reset = 0x0]
0x1A
EVENT_HIGH_FLAG
EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0]
0x1C
EVENT_LOW_FLAG
EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0]
0x1E
EVENT_RGN
0x20
HYSTERESIS_CH0
0x21
HIGH_TH_CH0
0x22
EVENT_COUNT_CH0
0x23
LOW_TH_CH0
0x24
HYSTERESIS_CH1
0x25
HIGH_TH_CH1
0x26
EVENT_COUNT_CH1
0x27
LOW_TH_CH1
0x28
HYSTERESIS_CH2
0x29
HIGH_TH_CH2
0x2A
EVENT_COUNT_CH2
0x2B
LOW_TH_CH2
0x2C
HYSTERESIS_CH3
0x2D
HIGH_TH_CH3
0x2E
EVENT_COUNT_CH3
0x2F
LOW_TH_CH3
0x30
HYSTERESIS_CH4
0x31
HIGH_TH_CH4
0x32
EVENT_COUNT_CH4
0x33
LOW_TH_CH4
0x34
HYSTERESIS_CH5
0x35
HIGH_TH_CH5
ADVANCE INFORMATION
Address
EVENT_RGN Register (Address = 0x1E) [reset = 0x0]
HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0]
HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF]
EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0]
LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0]
HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0]
HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF]
EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0]
LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0]
HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0]
HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF]
EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0]
LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0]
HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0]
HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF]
EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0]
LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0]
HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0]
HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF]
EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0]
LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0]
HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0]
HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF]
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Table 9. ADS7028 Registers (continued)
Address
ADVANCE INFORMATION
26
Acronym
0x36
EVENT_COUNT_CH5
0x37
LOW_TH_CH5
0x38
HYSTERESIS_CH6
Register
Name
Section
EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0]
LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0]
HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0]
0x39
HIGH_TH_CH6
0x3A
EVENT_COUNT_CH6
HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF]
0x3B
LOW_TH_CH6
0x3C
HYSTERESIS_CH7
0x3D
HIGH_TH_CH7
0x3E
EVENT_COUNT_CH7
0x3F
LOW_TH_CH7
0x60
MAX_CH0_LSB
MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0]
0x61
MAX_CH0_MSB
MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0]
0x62
MAX_CH1_LSB
MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0]
0x63
MAX_CH1_MSB
MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0]
0x64
MAX_CH2_LSB
MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0]
0x65
MAX_CH2_MSB
MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0]
0x66
MAX_CH3_LSB
MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0]
0x67
MAX_CH3_MSB
MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0]
0x68
MAX_CH4_LSB
MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0]
0x69
MAX_CH4_MSB
MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0]
0x6A
MAX_CH5_LSB
MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0]
0x6B
MAX_CH5_MSB
MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0]
0x6C
MAX_CH6_LSB
MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0]
0x6D
MAX_CH6_MSB
MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0]
0x6E
MAX_CH7_LSB
MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0]
0x6F
MAX_CH7_MSB
MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0]
0x80
MIN_CH0_LSB
MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF]
0x81
MIN_CH0_MSB
MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF]
0x82
MIN_CH1_LSB
MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF]
0x83
MIN_CH1_MSB
MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF]
0x84
MIN_CH2_LSB
MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF]
0x85
MIN_CH2_MSB
MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF]
0x86
MIN_CH3_LSB
MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF]
0x87
MIN_CH3_MSB
MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF]
0x88
MIN_CH4_LSB
MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF]
0x89
MIN_CH4_MSB
MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF]
0x8A
MIN_CH5_LSB
MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF]
0x8B
MIN_CH5_MSB
MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF]
0x8C
MIN_CH6_LSB
MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF]
0x8D
MIN_CH6_MSB
MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF]
0x8E
MIN_CH7_LSB
MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF]
0x8F
MIN_CH7_MSB
MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF]
0xA0
RECENT_CH0_LSB
RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0]
0xA1
RECENT_CH0_MSB
RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0]
0xA2
RECENT_CH1_LSB
RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0]
0xA3
RECENT_CH1_MSB
RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0]
0xA4
RECENT_CH2_LSB
RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0]
EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0]
LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0]
HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0]
HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF]
EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0]
LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0]
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Table 9. ADS7028 Registers (continued)
Acronym
Register
Name
Section
0xA5
RECENT_CH2_MSB
0xA6
RECENT_CH3_LSB
RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0]
RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0]
0xA7
RECENT_CH3_MSB
RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0]
0xA8
RECENT_CH4_LSB
RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0]
0xA9
RECENT_CH4_MSB
RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0]
0xAA
RECENT_CH5_LSB
RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0]
RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0]
0xAB
RECENT_CH5_MSB
0xAC
RECENT_CH6_LSB
RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0]
0xAD
RECENT_CH6_MSB
RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0]
0xAE
RECENT_CH7_LSB
RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0]
0xAF
RECENT_CH7_MSB
RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0]
0xC0
RMS_CFG
RMS_CFG Register (Address = 0xC0) [reset = 0x0]
0xC1
RMS_LSB
RMS_LSB Register (Address = 0xC1) [reset = 0x0]
0xC2
RMS_MSB
0xC3
GPO0_TRIG_EVENT_SEL
GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2]
0xC5
GPO1_TRIG_EVENT_SEL
GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x1]
0xC7
GPO2_TRIG_EVENT_SEL
GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x8]
0xC9
GPO3_TRIG_EVENT_SEL
GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x4]
0xCB
GPO4_TRIG_EVENT_SEL
GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset =
0x20]
0xCD
GPO5_TRIG_EVENT_SEL
GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset =
0x10]
0xCF
GPO6_TRIG_EVENT_SEL
GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x80]
0xD1
GPO7_TRIG_EVENT_SEL
GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x40]
0xE3
GPO_VALUE_ZCD_CFG_CH0_CH3
GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3)
[reset = 0x0]
0xE4
GPO_VALUE_ZCD_CFG_CH4_CH7
GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4)
[reset = 0x0]
0xE7
GPO_ZCD_UPDATE_EN
0xE9
GPO_TRIGGER_CFG
0xEB
GPO_VALUE_TRIG
RMS_MSB Register (Address = 0xC2) [reset = 0x0]
GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0]
GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0]
GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0]
Complex bit access types are encoded to fit into small table cells. Table 10 shows the codes that are used for
access types in this section.
Table 10. ADS7028 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
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Address
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Table 10. ADS7028 Access Type Codes (continued)
Access Type
Code
Description
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
8.5.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
SYSTEM_STATUS is shown in Figure 20 and described in Table 11.
Return to the Summary Table.
ADVANCE INFORMATION
Figure 20. SYSTEM_STATUS Register
7
RSVD
6
SEQ_STATUS
5
RESERVED
4
RMS_DONE
3
OSR_DONE
R-1b
R-0b
R-0b
R/W-0b
R/W-0b
2
CRC_ERR_FU
SE
R-0b
1
CRC_ERR_IN
0
BOR
R/W-0b
R/W-1b
Table 11. SYSTEM_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
1b
Reads return 1b.
6
SEQ_STATUS
R
0b
Status of the channel sequencer.
0b = Sequence stopped.
1b = Sequence in progress.
5
RESERVED
R
0b
Reserved. Reads return 0.
4
RMS_DONE
R/W
0b
RMS computation status. Clear this bit by writing 1b to this bit.
0b = RMS operation in progress or not started; RMS result not
ready.
1b = RMS computation complete; RMS result ready.
3
OSR_DONE
R/W
0b
Averaging status. Clear this bit by writing 1b to this bit.
0b = Averaging in progress or not started; average result is not
ready.
1b = Averaging complete; average result is ready.
2
CRC_ERR_FUSE
R
0b
Device power-up configuration CRC check status. To re-evaluate
this bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration.
1b = Device configuration not loaded correctly.
1
CRC_ERR_IN
R/W
0b
Status of CRC check on incoming data. Write 1b to clear this error
flag.
0b = No CRC error.
1b = CRC error detected. All register writes, except to addresses
0x00 and 0x01, are blocked.
0
BOR
R/W
1b
Brown out reset indicator. This bit is set if brown out condition occurs
or device is power cycled. Write 1b to this bit to clear the flag.
0b = No brown out from the last time this bit was cleared.
1b = Brown out condition detected or device power cycled.
28
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8.5.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
GENERAL_CFG is shown in Figure 21 and described in Table 12.
Return to the Summary Table.
Figure 21. GENERAL_CFG Register
7
RMS_EN
R/W-0b
6
CRC_EN
R/W-0b
5
STATS_EN
R/W-0b
4
DWC_EN
R/W-0b
3
RESERVED
R-0b
2
CH_RST
R/W-0b
1
CAL
R/W-0b
0
RST
W-0b
Table 12. GENERAL_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RMS_EN
R/W
0b
Enable or disable the RMS module.
0b = RMS module disabled.
1b = RMS module enabled; writing 1b to this bit clears
RMS_RESULT registers and initiates new RMS computation.
6
CRC_EN
R/W
0b
Enable or disable CRC on device interface.
1b = CRC appended to data output. CRC check is enabled on
incoming data.
5
STATS_EN
R/W
0b
Enable or disable the statistics module to update minimu, maximum,
and latest output code registers.
0b = Statistics registers are not updated.
1b = Clear statistics registers and conitnue updating with new
conversion results.
4
DWC_EN
R/W
0b
Enable or disable the digital window comparator.
0b = Reset or disable digital window comparator.
1b = Enable digital window comparator.
3
RESERVED
R
0b
Reserved. Reads return 0.
2
CH_RST
R/W
0b
Force all channels to be analog inputs.
0b = Normal operation.
1b = All channels are set as analog inputs irrespective of
configuration in other registers.
1
CAL
R/W
0b
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is
set to 0b.
0
RST
W
0b
Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and
BOR bit is set to 1b.
8.5.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]
DATA_CFG is shown in Figure 22 and described in Table 13.
Return to the Summary Table.
Figure 22. DATA_CFG Register
7
FIX_PAT
R/W-0b
6
RESERVED
R-0b
5
4
APPEND_STATUS[1:0]
R/W-0b
3
2
RESERVED
R-0b
1
0
CPOL_CPHA[1:0]
R/W-0b
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0b = CRC module disabled.
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Table 13. DATA_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
FIX_PAT
R/W
0b
Device outputs fixed data bits, which can be helpful for debugging
communication with the device.
0b = Normal operation.
1b = Device outputs fixed code 0xA5A repetitively when reading
ADC data.
6
5-4
RESERVED
R
0b
Reserved. Reads return 0.
APPEND_STATUS[1:0]
R/W
0b
Append 4-bit channel ID or status flags to output data.
0b = Channel ID and status flags are not appended to ADC data.
1b = 4-bit channel ID is appended to ADC data.
10b = 4-bit status flags are appended to ADC data.
11b = Reserved.
3-2
RESERVED
R
0b
Reserved. Reads return 0.
1-0
CPOL_CPHA[1:0]
R/W
0b
This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0.
1b = CPOL = 0, CPHA = 1.
ADVANCE INFORMATION
10b = CPOL = 1, CPHA = 0.
11b = CPOL = 1, CPHA = 1.
8.5.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 23 and described in Table 14.
Return to the Summary Table.
Figure 23. OSR_CFG Register
7
6
5
RESERVED
R-0b
4
3
2
1
OSR[2:0]
R/W-0b
0
Table 14. OSR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0b
Reserved. Reads return 0.
2-0
OSR[2:0]
R/W
0b
Selects the number of ADC output samples to average.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples
8.5.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
OPMODE_CFG is shown in Figure 24 and described in Table 15.
Return to the Summary Table.
Figure 24. OPMODE_CFG Register
7
CONV_ON_ER
R
R/W-0b
30
6
5
CONV_MODE[1:0]
4
OSC_SEL
R/W-0b
R/W-0b
3
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2
1
0
CLK_DIV[3:0]
R/W-0b
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Table 15. OPMODE_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
CONV_ON_ERR
R/W
0b
Control continuation of autonomous modes if CRC error is detected
on communication interface.
0b = If CRC error is detected, device continues channel sequencing
and pin configuration is retained. See the CRC_ERR_IN bit for more
details.
1b = If CRC error is detected, device changes all channels to analog
inputs and channel sequencing is paused until CRC_ERR_IN bit is
set to 0b. After clearing CRC_ERR_IN flag, device resumes channel
sequencing and pin confguration is restored.
6-5
CONV_MODE[1:0]
R/W
0b
These bits set the mode of conversion of the ADC.
0b = Manual mode; conversions are initiated by the host.
1b = Autonomous mode; conversions are initiated by the internal
state machine.
4
OSC_SEL
R/W
0b
Selects the oscillator for internal timing generation.
0b = High-speed oscillator.
1b = Low-power oscillator.
CLK_DIV[3:0]
R/W
0b
Sampling speed control in autonomous monitoring mode
(CONV_MODE = 01b). See the section on oscillator and timing
control for details.
ADVANCE INFORMATION
3-0
8.5.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]
PIN_CFG is shown in Figure 25 and described in Table 16.
Return to the Summary Table.
Figure 25. PIN_CFG Register
7
6
5
4
3
2
1
0
PIN_CFG[7:0]
R/W-0b
Table 16. PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PIN_CFG[7:0]
R/W
0b
Configure device channels AIN / GPIO [7:0] as analog inputs or
GPIOs.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.
8.5.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPIO_CFG is shown in Figure 26 and described in Table 17.
Return to the Summary Table.
Figure 26. GPIO_CFG Register
7
6
5
4
3
2
1
0
GPIO_CFG[7:0]
R/W-0b
Table 17. GPIO_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPIO_CFG[7:0]
R/W
0b
Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input.
1b = GPIO is configured as digital output.
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8.5.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_DRIVE_CFG is shown in Figure 27 and described in Table 18.
Return to the Summary Table.
Figure 27. GPO_DRIVE_CFG Register
7
6
5
4
3
GPO_DRIVE_CFG[7:0]
R/W-0b
2
1
0
Table 18. GPO_DRIVE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_DRIVE_CFG[7:0]
R/W
0b
Configure digital outputs GPO[7:0] as open-drain or push-pull
outputs.
0b = Digital output is open-drain; connect external pullup resistor.
1b = Push-pull driver is used for digital output.
8.5.9 GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
ADVANCE INFORMATION
GPO_OUTPUT_VALUE is shown in Figure 28 and described in Table 19.
Return to the Summary Table.
Figure 28. GPO_OUTPUT_VALUE Register
7
6
5
4
3
GPO_OUTPUT_VALUE[7:0]
R/W-0b
2
1
0
Table 19. GPO_OUTPUT_VALUE Register Field Descriptions
Bit
Field
Type
7-0
GPO_OUTPUT_VALUE[7: R/W
0]
Reset
Description
0b
Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.
8.5.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]
GPI_VALUE is shown in Figure 29 and described in Table 20.
Return to the Summary Table.
Figure 29. GPI_VALUE Register
7
6
5
4
3
GPI_VALUE[7:0]
R-0b
2
1
0
Table 20. GPI_VALUE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPI_VALUE[7:0]
R
0b
Readback the logic level on GPIO[7:0].
0b = GPIO is at logic 0.
1b = GPIO is at logic 1.
8.5.11 ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0]
ZCD_BLANKING_CFG is shown in Figure 30 and described in Table 21.
Return to the Summary Table.
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Figure 30. ZCD_BLANKING_CFG Register
7
MULT_EN
R/W-0b
6
5
4
3
ZCD_BLANKING[6:0]
R/W-0b
2
1
0
Table 21. ZCD_BLANKING_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
MULT_EN
R/W
0b
Multiplier enable bit for the ZCD_BLANKING field.
0b = Blanking count = ZCD_BLANKING
1b = Blanking count = ZCD_BLANKING x 8
6-0
ZCD_BLANKING[6:0]
R/W
0b
This field defines the number of analog conversions, of the ZCD
channel, which must be ignored before generating next ZCD event.
The counting starts from ZCD event detection.
8.5.12 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
SEQUENCE_CFG is shown in Figure 31 and described in Table 22.
Figure 31. SEQUENCE_CFG Register
7
6
RESERVED
R-0b
5
4
SEQ_START
R/W-0b
3
2
1
0
SEQ_MODE[1:0]
R/W-0b
RESERVED
R-0b
Table 22. SEQUENCE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0b
Reserved. Reads return 0.
4
SEQ_START
R/W
0b
Control for start of channel sequence when using channel sequencer
(SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels
enabled in AUTO_SEQ_CHSEL register.
3-2
RESERVED
R
0b
Reserved. Reads return 0.
1-0
SEQ_MODE[1:0]
R/W
0b
Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID
field.
1b = Auto sequence mode; channel selected by internal channel
sequencer.
10b = On-the-fly sequence mode.
11b = Reserved.
8.5.13 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
CHANNEL_SEL is shown in Figure 32 and described in Table 23.
Return to the Summary Table.
Figure 32. CHANNEL_SEL Register
7
6
5
4
3
ZCD_CHID[3:0]
R/W-0b
2
1
MANUAL_CHID[3:0]
R/W-0b
0
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ADVANCE INFORMATION
Return to the Summary Table.
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Table 23. CHANNEL_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
ZCD_CHID[3:0]
R/W
0b
Input channel to treat as ZCD input. If the selected channel is
configured as an analog input, internally generated ZCD signal is
used (setup thresholds accordingly). If the selected channel is a
digital input, the digital signal on this channel is directly used as ZCD
signal.
3-0
MANUAL_CHID[3:0]
R/W
0b
In manual mode (SEQ_MODE = 00b), this field contains the 4-bit
channel ID of the analog input channel for next ADC conversion. For
valid ADC data, the selected channel must not be configured as
GPIO in PIN_CFG register.
0b = AIN0
1b = AIN1
10b = AIN2
11b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
ADVANCE INFORMATION
1000b = Reserved.
8.5.14 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
AUTO_SEQ_CH_SEL is shown in Figure 33 and described in Table 24.
Return to the Summary Table.
Figure 33. AUTO_SEQ_CH_SEL Register
7
6
5
4
3
AUTO_SEQ_CH_SEL[7:0]
R/W-0b
2
1
0
Table 24. AUTO_SEQ_CH_SEL Register Field Descriptions
Bit
Field
Type
7-0
AUTO_SEQ_CH_SEL[7:0] R/W
Reset
Description
0b
Select analog input channels AIN[7:0] in for auto sequencing mode.
0b = Analog input channel is not enabled in scanning sequence.
1b = Analog input channel is enabled in scanning sequence.
8.5.15 ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0]
ALERT_CH_SEL is shown in Figure 34 and described in Table 25.
Return to the Summary Table.
Figure 34. ALERT_CH_SEL Register
7
6
5
4
3
ALERT_CH_SEL[7:0]
R/W-0b
2
1
0
Table 25. ALERT_CH_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ALERT_CH_SEL[7:0]
R/W
0b
Select channels for which the alert flags can assert the ALERT
signal.
0b = Alert flags for this channel do not assert the ALERT signal.
1b = Alert flags for this channel assert the ALERT signal.
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8.5.16 ALERT_MAP Register (Address = 0x16) [reset = 0x0]
ALERT_MAP is shown in Figure 35 and described in Table 26.
Return to the Summary Table.
Figure 35. ALERT_MAP Register
7
6
5
4
3
2
1
ALERT_RMS
R/W-0b
RESERVED
R-0b
0
ALERT_CRCIN
R/W-0b
Table 26. ALERT_MAP Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0b
Reserved. Reads return 0.
1
ALERT_RMS
R/W
0b
Enable or disable asserting ALERT signal based on RMS
computation status (RMS_DONE = 1b).
0b = ALERT signal is not asserted when RMS_DONE =1b.
0
ALERT_CRCIN
R/W
0b
Enable or disable the alert notification for CRC error on input data
(CRCERR_IN = 1b).
0b = ALERT signal is not asserted when CRCERR_IN = 1b.
1b = ALERT signal is asserted when CRCERR_IN = 1b. Clear
CRCERR_IN for deasserting the ALERT signal.
8.5.17 ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0]
ALERT_PIN_CFG is shown in Figure 36 and described in Table 27.
Return to the Summary Table.
Figure 36. ALERT_PIN_CFG Register
7
6
5
ALERT_PIN[3:0]
R/W-0b
4
3
2
1
0
ALERT_LOGIC[1:0]
R/W-0b
RESERVED
R-0b
Table 27. ALERT_PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
ALERT_PIN[3:0]
R/W
0b
Internal ALERT output of the digital window comparator will be
output on this channel. This channel must be configured as digital
output.
3-2
RESERVED
R
0b
Reserved. Reads return 0.
1-0
ALERT_LOGIC[1:0]
R/W
0b
Configure how ALERT signal is asserted.
0b = Active low.
1b = Active high.
10b = Pulsed low (one logic low pulse once per alert flag).
11b = Pulsed high (one logic high pulse once per alert flag).
8.5.18 EVENT_FLAG Register (Address = 0x18) [reset = 0x0]
EVENT_FLAG is shown in Figure 37 and described in Table 28.
Return to the Summary Table.
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ADVANCE INFORMATION
1b = ALERT signal is asserted when RMS_DONE = 1b. Clear
RMS_DONE flag to deassert the ALERT signal.
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Figure 37. EVENT_FLAG Register
7
6
5
4
3
EVENT_FLAG[7:0]
R-0b
2
1
0
Table 28. EVENT_FLAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_FLAG[7:0]
R
0b
Alert flags indicating digital window comparator status for
AIN/GPIO[7:0]. Write 0b to individual bits of EVENT_HIGH and
EVENT_LOW flag registers to clear alert flag.
0b = Event condition not detected.
1b = Event condition detected.
8.5.19 EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0]
EVENT_HIGH_FLAG is shown in Figure 38 and described in Table 29.
Return to the Summary Table.
ADVANCE INFORMATION
Figure 38. EVENT_HIGH_FLAG Register
7
6
5
4
3
EVENT_HIGH_FLAG[7:0]
R/W-0b
2
1
0
Table 29. EVENT_HIGH_FLAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_HIGH_FLAG[7:0]
R/W
0b
Alert flag corresponding to high threshold of analog input or rising
edge of digital input on CH[7:0]. Write 1b to clear this flag.
0b = No alert condition detected.
1b = Either high threshold was exceeded (analog input) or rising
edge was detected (digital input).
8.5.20 EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0]
EVENT_LOW_FLAG is shown in Figure 39 and described in Table 30.
Return to the Summary Table.
Figure 39. EVENT_LOW_FLAG Register
7
6
5
4
3
EVENT_LOW_FLAG[7:0]
R/W-0b
2
1
0
Table 30. EVENT_LOW_FLAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_LOW_FLAG[7:0]
R/W
0b
Alert flag corresponding to low threshold of analog input or falling
edge of digital input on CH[7:0]. Write 1b to clear this flag.
0b = No Event condition detected.
1b = Either low threshold was exceeded (analog input) or falling
edge was detected (digital input).
8.5.21 EVENT_RGN Register (Address = 0x1E) [reset = 0x0]
EVENT_RGN is shown in Figure 40 and described in Table 31.
Return to the Summary Table.
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Figure 40. EVENT_RGN Register
7
6
5
4
3
EVENT_RGN[7:0]
R/W-0b
2
1
0
Table 31. EVENT_RGN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_RGN[7:0]
R/W
0b
Choice of region used in monitoring analog/digital inputs CH[7:0].
0b = Alert flag is set if: (conversion result andlt low threshold) or
(conversion result andgt high threshold). For digital inputs, rising
edge sets the alert flag.
1b = Alert flag is set if: (low threshold andgt conversion result andlt
high threshold). For digital inputs, falling edge sets the alert flag.
8.5.22 HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0]
HYSTERESIS_CH0 is shown in Figure 41 and described in Table 32.
Figure 41. HYSTERESIS_CH0 Register
7
6
5
HIGH_THRESHOLD_CH0_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH0[3:0]
R/W-0b
0
Table 32. HYSTERESIS_CH0 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH0 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH0[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.23 HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF]
HIGH_TH_CH0 is shown in Figure 42 and described in Table 33.
Return to the Summary Table.
Figure 42. HIGH_TH_CH0 Register
7
6
5
4
3
HIGH_THRESHOLD_CH0_MSB[7:0]
R/W-11111111b
2
1
0
Table 33. HIGH_TH_CH0 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH0 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.24 EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0]
EVENT_COUNT_CH0 is shown in Figure 43 and described in Table 34.
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ADVANCE INFORMATION
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Figure 43. EVENT_COUNT_CH0 Register
7
6
5
LOW_THRESHOLD_CH0_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH0[3:0]
R/W-0b
0
Table 34. EVENT_COUNT_CH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH0
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH0[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.25 LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0]
LOW_TH_CH0 is shown in Figure 44 and described in Table 35.
Return to the Summary Table.
Figure 44. LOW_TH_CH0 Register
ADVANCE INFORMATION
7
6
5
4
3
LOW_THRESHOLD_CH0_MSB[7:0]
R/W-0b
2
1
0
Table 35. LOW_TH_CH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH0
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.26 HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0]
HYSTERESIS_CH1 is shown in Figure 45 and described in Table 36.
Return to the Summary Table.
Figure 45. HYSTERESIS_CH1 Register
7
6
5
HIGH_THRESHOLD_CH1_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH1[3:0]
R/W-0b
0
Table 36. HYSTERESIS_CH1 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH1 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH1[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.27 HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF]
HIGH_TH_CH1 is shown in Figure 46 and described in Table 37.
Return to the Summary Table.
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Figure 46. HIGH_TH_CH1 Register
7
6
5
4
3
HIGH_THRESHOLD_CH1_MSB[7:0]
R/W-11111111b
2
1
0
Table 37. HIGH_TH_CH1 Register Field Descriptions
Bit
Field
Type
7-0
HIGH_THRESHOLD_CH1 R/W
_MSB[7:0]
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.28 EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0]
EVENT_COUNT_CH1 is shown in Figure 47 and described in Table 38.
Return to the Summary Table.
Figure 47. EVENT_COUNT_CH1 Register
6
5
LOW_THRESHOLD_CH1_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH1[3:0]
R/W-0b
0
ADVANCE INFORMATION
7
Table 38. EVENT_COUNT_CH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH1
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH1[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.29 LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0]
LOW_TH_CH1 is shown in Figure 48 and described in Table 39.
Return to the Summary Table.
Figure 48. LOW_TH_CH1 Register
7
6
5
4
3
LOW_THRESHOLD_CH1_MSB[7:0]
R/W-0b
2
1
0
Table 39. LOW_TH_CH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH1
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.30 HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0]
HYSTERESIS_CH2 is shown in Figure 49 and described in Table 40.
Return to the Summary Table.
Figure 49. HYSTERESIS_CH2 Register
7
6
5
HIGH_THRESHOLD_CH2_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH2[3:0]
R/W-0b
0
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Table 40. HYSTERESIS_CH2 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH2 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH2[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.31 HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF]
HIGH_TH_CH2 is shown in Figure 50 and described in Table 41.
Return to the Summary Table.
Figure 50. HIGH_TH_CH2 Register
7
6
5
4
3
HIGH_THRESHOLD_CH2_MSB[7:0]
R/W-11111111b
2
1
0
ADVANCE INFORMATION
Table 41. HIGH_TH_CH2 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH2 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.32 EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0]
EVENT_COUNT_CH2 is shown in Figure 51 and described in Table 42.
Return to the Summary Table.
Figure 51. EVENT_COUNT_CH2 Register
7
6
5
LOW_THRESHOLD_CH2_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH2[3:0]
R/W-0b
0
Table 42. EVENT_COUNT_CH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH2
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH2[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.33 LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0]
LOW_TH_CH2 is shown in Figure 52 and described in Table 43.
Return to the Summary Table.
Figure 52. LOW_TH_CH2 Register
7
40
6
5
4
3
LOW_THRESHOLD_CH2_MSB[7:0]
R/W-0b
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Table 43. LOW_TH_CH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH2
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.34 HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0]
HYSTERESIS_CH3 is shown in Figure 53 and described in Table 44.
Return to the Summary Table.
Figure 53. HYSTERESIS_CH3 Register
7
6
5
HIGH_THRESHOLD_CH3_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH3[3:0]
R/W-0b
0
Bit
Field
7-4
3-0
Type
Reset
Description
HIGH_THRESHOLD_CH3 R/W
_LSB[3:0]
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
HYSTERESIS_CH3[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.35 HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF]
HIGH_TH_CH3 is shown in Figure 54 and described in Table 45.
Return to the Summary Table.
Figure 54. HIGH_TH_CH3 Register
7
6
5
4
3
HIGH_THRESHOLD_CH3_MSB[7:0]
R/W-11111111b
2
1
0
Table 45. HIGH_TH_CH3 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH3 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.36 EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0]
EVENT_COUNT_CH3 is shown in Figure 55 and described in Table 46.
Return to the Summary Table.
Figure 55. EVENT_COUNT_CH3 Register
7
6
5
LOW_THRESHOLD_CH3_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH3[3:0]
R/W-0b
0
Table 46. EVENT_COUNT_CH3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH3
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
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ADVANCE INFORMATION
Table 44. HYSTERESIS_CH3 Register Field Descriptions
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Table 46. EVENT_COUNT_CH3 Register Field Descriptions (continued)
Bit
Field
3-0
EVENT_COUNT_CH3[3:0 R/W
]
Type
Reset
Description
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.37 LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0]
LOW_TH_CH3 is shown in Figure 56 and described in Table 47.
Return to the Summary Table.
Figure 56. LOW_TH_CH3 Register
7
6
5
4
3
LOW_THRESHOLD_CH3_MSB[7:0]
R/W-0b
2
1
0
Table 47. LOW_TH_CH3 Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH3
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.38 HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0]
HYSTERESIS_CH4 is shown in Figure 57 and described in Table 48.
Return to the Summary Table.
Figure 57. HYSTERESIS_CH4 Register
7
6
5
HIGH_THRESHOLD_CH4_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH4[3:0]
R/W-0b
0
Table 48. HYSTERESIS_CH4 Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
HIGH_THRESHOLD_CH4 R/W
_LSB[3:0]
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
HYSTERESIS_CH4[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.39 HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF]
HIGH_TH_CH4 is shown in Figure 58 and described in Table 49.
Return to the Summary Table.
Figure 58. HIGH_TH_CH4 Register
7
6
5
4
3
HIGH_THRESHOLD_CH4_MSB[7:0]
R/W-11111111b
2
1
0
Table 49. HIGH_TH_CH4 Register Field Descriptions
42
Bit
Field
7-0
HIGH_THRESHOLD_CH4 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
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8.5.40 EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0]
EVENT_COUNT_CH4 is shown in Figure 59 and described in Table 50.
Return to the Summary Table.
Figure 59. EVENT_COUNT_CH4 Register
7
6
5
LOW_THRESHOLD_CH4_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH4[3:0]
R/W-0b
0
Table 50. EVENT_COUNT_CH4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH4
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH4[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.41 LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0]
ADVANCE INFORMATION
LOW_TH_CH4 is shown in Figure 60 and described in Table 51.
Return to the Summary Table.
Figure 60. LOW_TH_CH4 Register
7
6
5
4
3
LOW_THRESHOLD_CH4_MSB[7:0]
R/W-0b
2
1
0
Table 51. LOW_TH_CH4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH4
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.42 HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0]
HYSTERESIS_CH5 is shown in Figure 61 and described in Table 52.
Return to the Summary Table.
Figure 61. HYSTERESIS_CH5 Register
7
6
5
HIGH_THRESHOLD_CH5_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH5[3:0]
R/W-0b
0
Table 52. HYSTERESIS_CH5 Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
HIGH_THRESHOLD_CH5 R/W
_LSB[3:0]
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
HYSTERESIS_CH5[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.43 HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF]
HIGH_TH_CH5 is shown in Figure 62 and described in Table 53.
Return to the Summary Table.
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Figure 62. HIGH_TH_CH5 Register
7
6
5
4
3
HIGH_THRESHOLD_CH5_MSB[7:0]
R/W-11111111b
2
1
0
Table 53. HIGH_TH_CH5 Register Field Descriptions
Bit
Field
Type
7-0
HIGH_THRESHOLD_CH5 R/W
_MSB[7:0]
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.44 EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0]
EVENT_COUNT_CH5 is shown in Figure 63 and described in Table 54.
Return to the Summary Table.
Figure 63. EVENT_COUNT_CH5 Register
7
ADVANCE INFORMATION
6
5
LOW_THRESHOLD_CH5_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH5[3:0]
R/W-0b
0
Table 54. EVENT_COUNT_CH5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH5
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH5[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.45 LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0]
LOW_TH_CH5 is shown in Figure 64 and described in Table 55.
Return to the Summary Table.
Figure 64. LOW_TH_CH5 Register
7
6
5
4
3
LOW_THRESHOLD_CH5_MSB[7:0]
R/W-0b
2
1
0
Table 55. LOW_TH_CH5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH5
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.46 HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0]
HYSTERESIS_CH6 is shown in Figure 65 and described in Table 56.
Return to the Summary Table.
Figure 65. HYSTERESIS_CH6 Register
7
44
6
5
HIGH_THRESHOLD_CH6_LSB[3:0]
R/W-1111b
4
3
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2
1
HYSTERESIS_CH6[3:0]
R/W-0b
0
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Table 56. HYSTERESIS_CH6 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH6 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH6[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.47 HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF]
HIGH_TH_CH6 is shown in Figure 66 and described in Table 57.
Return to the Summary Table.
Figure 66. HIGH_TH_CH6 Register
6
5
4
3
HIGH_THRESHOLD_CH6_MSB[7:0]
R/W-11111111b
2
1
0
ADVANCE INFORMATION
7
Table 57. HIGH_TH_CH6 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH6 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.48 EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0]
EVENT_COUNT_CH6 is shown in Figure 67 and described in Table 58.
Return to the Summary Table.
Figure 67. EVENT_COUNT_CH6 Register
7
6
5
LOW_THRESHOLD_CH6_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH6[3:0]
R/W-0b
0
Table 58. EVENT_COUNT_CH6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH6
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH6[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.49 LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0]
LOW_TH_CH6 is shown in Figure 68 and described in Table 59.
Return to the Summary Table.
Figure 68. LOW_TH_CH6 Register
7
6
5
4
3
LOW_THRESHOLD_CH6_MSB[7:0]
R/W-0b
2
1
0
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Table 59. LOW_TH_CH6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH6
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.50 HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0]
HYSTERESIS_CH7 is shown in Figure 69 and described in Table 60.
Return to the Summary Table.
Figure 69. HYSTERESIS_CH7 Register
7
6
5
HIGH_THRESHOLD_CH7_LSB[3:0]
R/W-1111b
4
3
2
1
HYSTERESIS_CH7[3:0]
R/W-0b
0
Table 60. HYSTERESIS_CH7 Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
7-4
3-0
Type
Reset
Description
HIGH_THRESHOLD_CH7 R/W
_LSB[3:0]
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
HYSTERESIS_CH7[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.51 HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF]
HIGH_TH_CH7 is shown in Figure 70 and described in Table 61.
Return to the Summary Table.
Figure 70. HIGH_TH_CH7 Register
7
6
5
4
3
HIGH_THRESHOLD_CH7_MSB[7:0]
R/W-11111111b
2
1
0
Table 61. HIGH_TH_CH7 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH7 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.52 EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0]
EVENT_COUNT_CH7 is shown in Figure 71 and described in Table 62.
Return to the Summary Table.
Figure 71. EVENT_COUNT_CH7 Register
7
6
5
LOW_THRESHOLD_CH7_LSB[3:0]
R/W-0b
4
3
2
1
EVENT_COUNT_CH7[3:0]
R/W-0b
0
Table 62. EVENT_COUNT_CH7 Register Field Descriptions
46
Bit
Field
Type
Reset
Description
7-4
LOW_THRESHOLD_CH7
_LSB[3:0]
R/W
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
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Table 62. EVENT_COUNT_CH7 Register Field Descriptions (continued)
Bit
Field
3-0
EVENT_COUNT_CH7[3:0 R/W
]
Type
Reset
Description
0b
Configuration for checking 'n+1' consecutive samples exceeding
either high or low threshold before setting alert flag.
8.5.53 LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0]
LOW_TH_CH7 is shown in Figure 72 and described in Table 63.
Return to the Summary Table.
Figure 72. LOW_TH_CH7 Register
7
6
5
4
3
LOW_THRESHOLD_CH7_MSB[7:0]
R/W-0b
2
1
0
Bit
Field
Type
Reset
Description
7-0
LOW_THRESHOLD_CH7
_MSB[7:0]
R/W
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
ADVANCE INFORMATION
Table 63. LOW_TH_CH7 Register Field Descriptions
8.5.54 MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0]
MAX_CH0_LSB is shown in Figure 73 and described in Table 64.
Return to the Summary Table.
Figure 73. MAX_CH0_LSB Register
7
6
5
4
3
MAX_VALUE_CH0_LSB[7:0]
R-0b
2
1
0
Table 64. MAX_CH0_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH0_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.55 MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0]
MAX_CH0_MSB is shown in Figure 74 and described in Table 65.
Return to the Summary Table.
Figure 74. MAX_CH0_MSB Register
7
6
5
4
3
MAX_VALUE_CH0_MSB[7:0]
R-0b
2
1
0
Table 65. MAX_CH0_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH0_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
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8.5.56 MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0]
MAX_CH1_LSB is shown in Figure 75 and described in Table 66.
Return to the Summary Table.
Figure 75. MAX_CH1_LSB Register
7
6
5
4
3
MAX_VALUE_CH1_LSB[7:0]
R-0b
2
1
0
Table 66. MAX_CH1_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH1_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.57 MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0]
MAX_CH1_MSB is shown in Figure 76 and described in Table 67.
ADVANCE INFORMATION
Return to the Summary Table.
Figure 76. MAX_CH1_MSB Register
7
6
5
4
3
MAX_VALUE_CH1_MSB[7:0]
R-0b
2
1
0
Table 67. MAX_CH1_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH1_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.58 MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0]
MAX_CH2_LSB is shown in Figure 77 and described in Table 68.
Return to the Summary Table.
Figure 77. MAX_CH2_LSB Register
7
6
5
4
3
MAX_VALUE_CH2_LSB[7:0]
R-0b
2
1
0
Table 68. MAX_CH2_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH2_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.59 MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0]
MAX_CH2_MSB is shown in Figure 78 and described in Table 69.
Return to the Summary Table.
48
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Figure 78. MAX_CH2_MSB Register
7
6
5
4
3
MAX_VALUE_CH2_MSB[7:0]
R-0b
2
1
0
Table 69. MAX_CH2_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH2_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.60 MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0]
MAX_CH3_LSB is shown in Figure 79 and described in Table 70.
Return to the Summary Table.
Figure 79. MAX_CH3_LSB Register
6
5
4
3
MAX_VALUE_CH3_LSB[7:0]
R-0b
2
1
0
ADVANCE INFORMATION
7
Table 70. MAX_CH3_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH3_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.61 MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0]
MAX_CH3_MSB is shown in Figure 80 and described in Table 71.
Return to the Summary Table.
Figure 80. MAX_CH3_MSB Register
7
6
5
4
3
MAX_VALUE_CH3_MSB[7:0]
R-0b
2
1
0
Table 71. MAX_CH3_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH3_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.62 MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0]
MAX_CH4_LSB is shown in Figure 81 and described in Table 72.
Return to the Summary Table.
Figure 81. MAX_CH4_LSB Register
7
6
5
4
3
MAX_VALUE_CH4_LSB[7:0]
R-0b
2
1
0
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Table 72. MAX_CH4_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH4_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.63 MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0]
MAX_CH4_MSB is shown in Figure 82 and described in Table 73.
Return to the Summary Table.
Figure 82. MAX_CH4_MSB Register
7
6
5
4
3
MAX_VALUE_CH4_MSB[7:0]
R-0b
2
1
0
Table 73. MAX_CH4_MSB Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH4_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.64 MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0]
MAX_CH5_LSB is shown in Figure 83 and described in Table 74.
Return to the Summary Table.
Figure 83. MAX_CH5_LSB Register
7
6
5
4
3
MAX_VALUE_CH5_LSB[7:0]
R-0b
2
1
0
Table 74. MAX_CH5_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH5_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.65 MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0]
MAX_CH5_MSB is shown in Figure 84 and described in Table 75.
Return to the Summary Table.
Figure 84. MAX_CH5_MSB Register
7
6
5
4
3
MAX_VALUE_CH5_MSB[7:0]
R-0b
2
1
0
Table 75. MAX_CH5_MSB Register Field Descriptions
50
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH5_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
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8.5.66 MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0]
MAX_CH6_LSB is shown in Figure 85 and described in Table 76.
Return to the Summary Table.
Figure 85. MAX_CH6_LSB Register
7
6
5
4
3
MAX_VALUE_CH6_LSB[7:0]
R-0b
2
1
0
Table 76. MAX_CH6_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH6_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.67 MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0]
ADVANCE INFORMATION
MAX_CH6_MSB is shown in Figure 86 and described in Table 77.
Return to the Summary Table.
Figure 86. MAX_CH6_MSB Register
7
6
5
4
3
MAX_VALUE_CH6_MSB[7:0]
R-0b
2
1
0
Table 77. MAX_CH6_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH6_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.68 MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0]
MAX_CH7_LSB is shown in Figure 87 and described in Table 78.
Return to the Summary Table.
Figure 87. MAX_CH7_LSB Register
7
6
5
4
3
MAX_VALUE_CH7_LSB[7:0]
R-0b
2
1
0
Table 78. MAX_CH7_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH7_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.69 MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0]
MAX_CH7_MSB is shown in Figure 88 and described in Table 79.
Return to the Summary Table.
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Figure 88. MAX_CH7_MSB Register
7
6
5
4
3
MAX_VALUE_CH7_MSB[7:0]
R-0b
2
1
0
Table 79. MAX_CH7_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MAX_VALUE_CH7_MSB[
7:0]
R
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.70 MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF]
MIN_CH0_LSB is shown in Figure 89 and described in Table 80.
Return to the Summary Table.
Figure 89. MIN_CH0_LSB Register
7
6
5
ADVANCE INFORMATION
4
3
MIN_VALUE_CH0_LSB[7:0]
R-11111111b
2
1
0
Table 80. MIN_CH0_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH0_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.71 MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF]
MIN_CH0_MSB is shown in Figure 90 and described in Table 81.
Return to the Summary Table.
Figure 90. MIN_CH0_MSB Register
7
6
5
4
3
MIN_VALUE_CH0_MSB[7:0]
R-11111111b
2
1
0
Table 81. MIN_CH0_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH0_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.72 MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF]
MIN_CH1_LSB is shown in Figure 91 and described in Table 82.
Return to the Summary Table.
Figure 91. MIN_CH1_LSB Register
7
52
6
5
4
3
MIN_VALUE_CH1_LSB[7:0]
R-11111111b
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1
0
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Table 82. MIN_CH1_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH1_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.73 MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF]
MIN_CH1_MSB is shown in Figure 92 and described in Table 83.
Return to the Summary Table.
Figure 92. MIN_CH1_MSB Register
7
6
5
4
3
MIN_VALUE_CH1_MSB[7:0]
R-11111111b
2
1
0
Bit
Field
7-0
MIN_VALUE_CH1_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
ADVANCE INFORMATION
Table 83. MIN_CH1_MSB Register Field Descriptions
8.5.74 MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF]
MIN_CH2_LSB is shown in Figure 93 and described in Table 84.
Return to the Summary Table.
Figure 93. MIN_CH2_LSB Register
7
6
5
4
3
MIN_VALUE_CH2_LSB[7:0]
R-11111111b
2
1
0
Table 84. MIN_CH2_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH2_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.75 MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF]
MIN_CH2_MSB is shown in Figure 94 and described in Table 85.
Return to the Summary Table.
Figure 94. MIN_CH2_MSB Register
7
6
5
4
3
MIN_VALUE_CH2_MSB[7:0]
R-11111111b
2
1
0
Table 85. MIN_CH2_MSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH2_MSB[7 R
:0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
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8.5.76 MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF]
MIN_CH3_LSB is shown in Figure 95 and described in Table 86.
Return to the Summary Table.
Figure 95. MIN_CH3_LSB Register
7
6
5
4
3
MIN_VALUE_CH3_LSB[7:0]
R-11111111b
2
1
0
Table 86. MIN_CH3_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH3_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.77 MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF]
MIN_CH3_MSB is shown in Figure 96 and described in Table 87.
ADVANCE INFORMATION
Return to the Summary Table.
Figure 96. MIN_CH3_MSB Register
7
6
5
4
3
MIN_VALUE_CH3_MSB[7:0]
R-11111111b
2
1
0
Table 87. MIN_CH3_MSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH3_MSB[7 R
:0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.78 MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF]
MIN_CH4_LSB is shown in Figure 97 and described in Table 88.
Return to the Summary Table.
Figure 97. MIN_CH4_LSB Register
7
6
5
4
3
MIN_VALUE_CH4_LSB[7:0]
R-11111111b
2
1
0
Table 88. MIN_CH4_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH4_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.79 MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF]
MIN_CH4_MSB is shown in Figure 98 and described in Table 89.
Return to the Summary Table.
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Figure 98. MIN_CH4_MSB Register
7
6
5
4
3
MIN_VALUE_CH4_MSB[7:0]
R-11111111b
2
1
0
Table 89. MIN_CH4_MSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH4_MSB[7 R
:0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.80 MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF]
MIN_CH5_LSB is shown in Figure 99 and described in Table 90.
Return to the Summary Table.
Figure 99. MIN_CH5_LSB Register
6
5
4
3
MIN_VALUE_CH5_LSB[7:0]
R-11111111b
2
1
0
ADVANCE INFORMATION
7
Table 90. MIN_CH5_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH5_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.81 MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF]
MIN_CH5_MSB is shown in Figure 100 and described in Table 91.
Return to the Summary Table.
Figure 100. MIN_CH5_MSB Register
7
6
5
4
3
MIN_VALUE_CH5_MSB[7:0]
R-11111111b
2
1
0
Table 91. MIN_CH5_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH5_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.82 MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF]
MIN_CH6_LSB is shown in Figure 101 and described in Table 92.
Return to the Summary Table.
Figure 101. MIN_CH6_LSB Register
7
6
5
4
3
MIN_VALUE_CH6_LSB[7:0]
R-11111111b
2
1
0
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Table 92. MIN_CH6_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH6_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.83 MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF]
MIN_CH6_MSB is shown in Figure 102 and described in Table 93.
Return to the Summary Table.
Figure 102. MIN_CH6_MSB Register
7
6
5
4
3
MIN_VALUE_CH6_MSB[7:0]
R-11111111b
2
1
0
Table 93. MIN_CH6_MSB Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
7-0
MIN_VALUE_CH6_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.84 MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF]
MIN_CH7_LSB is shown in Figure 103 and described in Table 94.
Return to the Summary Table.
Figure 103. MIN_CH7_LSB Register
7
6
5
4
3
MIN_VALUE_CH7_LSB[7:0]
R-11111111b
2
1
0
Table 94. MIN_CH7_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH7_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.85 MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF]
MIN_CH7_MSB is shown in Figure 104 and described in Table 95.
Return to the Summary Table.
Figure 104. MIN_CH7_MSB Register
7
6
5
4
3
MIN_VALUE_CH7_MSB[7:0]
R-11111111b
2
1
0
Table 95. MIN_CH7_MSB Register Field Descriptions
56
Bit
Field
Type
7-0
MIN_VALUE_CH7_MSB[7 R
:0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
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8.5.86 RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0]
RECENT_CH0_LSB is shown in Figure 105 and described in Table 96.
Return to the Summary Table.
Figure 105. RECENT_CH0_LSB Register
7
6
5
4
3
LAST_VALUE_CH0_LSB[7:0]
R-0b
2
1
0
Table 96. RECENT_CH0_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH0_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.87 RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0]
RECENT_CH0_MSB is shown in Figure 106 and described in Table 97.
ADVANCE INFORMATION
Return to the Summary Table.
Figure 106. RECENT_CH0_MSB Register
7
6
5
4
3
LAST_VALUE_CH0_MSB[7:0]
R-0b
2
1
0
Table 97. RECENT_CH0_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH0_MSB R
[7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.88 RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0]
RECENT_CH1_LSB is shown in Figure 107 and described in Table 98.
Return to the Summary Table.
Figure 107. RECENT_CH1_LSB Register
7
6
5
4
3
LAST_VALUE_CH1_LSB[7:0]
R-0b
2
1
0
Table 98. RECENT_CH1_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH1_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.89 RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0]
RECENT_CH1_MSB is shown in Figure 108 and described in Table 99.
Return to the Summary Table.
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Figure 108. RECENT_CH1_MSB Register
7
6
5
4
3
LAST_VALUE_CH1_MSB[7:0]
R-0b
2
1
0
Table 99. RECENT_CH1_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH1_MSB R
[7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.90 RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0]
RECENT_CH2_LSB is shown in Figure 109 and described in Table 100.
Return to the Summary Table.
Figure 109. RECENT_CH2_LSB Register
7
6
5
ADVANCE INFORMATION
4
3
LAST_VALUE_CH2_LSB[7:0]
R-0b
2
1
0
Table 100. RECENT_CH2_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH2_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.91 RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0]
RECENT_CH2_MSB is shown in Figure 110 and described in Table 101.
Return to the Summary Table.
Figure 110. RECENT_CH2_MSB Register
7
6
5
4
3
LAST_VALUE_CH2_MSB[7:0]
R-0b
2
1
0
Table 101. RECENT_CH2_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH2_MSB R
[7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.92 RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0]
RECENT_CH3_LSB is shown in Figure 111 and described in Table 102.
Return to the Summary Table.
Figure 111. RECENT_CH3_LSB Register
7
58
6
5
4
3
LAST_VALUE_CH3_LSB[7:0]
R-0b
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2
1
0
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Table 102. RECENT_CH3_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH3_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.93 RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0]
RECENT_CH3_MSB is shown in Figure 112 and described in Table 103.
Return to the Summary Table.
Figure 112. RECENT_CH3_MSB Register
7
6
5
4
3
LAST_VALUE_CH3_MSB[7:0]
R-0b
2
1
0
Bit
Field
Type
7-0
LAST_VALUE_CH3_MSB R
[7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
ADVANCE INFORMATION
Table 103. RECENT_CH3_MSB Register Field Descriptions
8.5.94 RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0]
RECENT_CH4_LSB is shown in Figure 113 and described in Table 104.
Return to the Summary Table.
Figure 113. RECENT_CH4_LSB Register
7
6
5
4
3
LAST_VALUE_CH4_LSB[7:0]
R-0b
2
1
0
Table 104. RECENT_CH4_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH4_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.95 RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0]
RECENT_CH4_MSB is shown in Figure 114 and described in Table 105.
Return to the Summary Table.
Figure 114. RECENT_CH4_MSB Register
7
6
5
4
3
LAST_VALUE_CH4_MSB[7:0]
R-0b
2
1
0
Table 105. RECENT_CH4_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH4_MSB R
[7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
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8.5.96 RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0]
RECENT_CH5_LSB is shown in Figure 115 and described in Table 106.
Return to the Summary Table.
Figure 115. RECENT_CH5_LSB Register
7
6
5
4
3
LAST_VALUE_CH5_LSB[7:0]
R-0b
2
1
0
Table 106. RECENT_CH5_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH5_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.97 RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0]
RECENT_CH5_MSB is shown in Figure 116 and described in Table 107.
ADVANCE INFORMATION
Return to the Summary Table.
Figure 116. RECENT_CH5_MSB Register
7
6
5
4
3
LAST_VALUE_CH5_MSB[7:0]
R-0b
2
1
0
Table 107. RECENT_CH5_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH5_MSB R
[7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.98 RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0]
RECENT_CH6_LSB is shown in Figure 117 and described in Table 108.
Return to the Summary Table.
Figure 117. RECENT_CH6_LSB Register
7
6
5
4
3
LAST_VALUE_CH6_LSB[7:0]
R-0b
2
1
0
Table 108. RECENT_CH6_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH6_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.99 RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0]
RECENT_CH6_MSB is shown in Figure 118 and described in Table 109.
Return to the Summary Table.
60
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Figure 118. RECENT_CH6_MSB Register
7
6
5
4
3
LAST_VALUE_CH6_MSB[7:0]
R-0b
2
1
0
Table 109. RECENT_CH6_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH6_MSB R
[7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.100 RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0]
RECENT_CH7_LSB is shown in Figure 119 and described in Table 110.
Return to the Summary Table.
Figure 119. RECENT_CH7_LSB Register
6
5
4
3
LAST_VALUE_CH7_LSB[7:0]
R-0b
2
1
0
ADVANCE INFORMATION
7
Table 110. RECENT_CH7_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH7_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.101 RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0]
RECENT_CH7_MSB is shown in Figure 120 and described in Table 111.
Return to the Summary Table.
Figure 120. RECENT_CH7_MSB Register
7
6
5
4
3
LAST_VALUE_CH7_MSB[7:0]
R-0b
2
1
0
Table 111. RECENT_CH7_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH7_MSB R
[7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.102 RMS_CFG Register (Address = 0xC0) [reset = 0x0]
RMS_CFG is shown in Figure 121 and described in Table 112.
Return to the Summary Table.
Figure 121. RMS_CFG Register
7
6
5
RMS_CHID[3:0]
R/W-0b
4
3
RESERVED
R-0b
2
RMS_DC_SUB
R/W-0b
1
0
RMS_SAMPLES[1:0]
R/W-0b
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Table 112. RMS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RMS_CHID[3:0]
R/W
0b
Select analog input channel for RMS computation.
3
RESERVED
R
0b
Reserved. Reads return 0.
2
RMS_DC_SUB
R/W
0b
Subtract DC component from the RMS result.
0b = Do not subtract DC component.
1b = Subtract DC component.
1-0
RMS_SAMPLES[1:0]
R/W
0b
Number of samples for computing RMS result.
0b = 1024
1b = 4096
10b = 16384
11b = 65536
8.5.103 RMS_LSB Register (Address = 0xC1) [reset = 0x0]
RMS_LSB is shown in Figure 122 and described in Table 113.
Return to the Summary Table.
ADVANCE INFORMATION
Figure 122. RMS_LSB Register
7
6
5
4
3
RMS_RESULT_LSB[7:0]
R-0b
2
1
0
1
0
1
0
Table 113. RMS_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RMS_RESULT_LSB[7:0]
R
0b
Lower 8-bits of RMS computation result.
8.5.104 RMS_MSB Register (Address = 0xC2) [reset = 0x0]
RMS_MSB is shown in Figure 123 and described in Table 114.
Return to the Summary Table.
Figure 123. RMS_MSB Register
7
6
5
4
3
RMS_RESULT_MSB[7:0]
R-0b
2
Table 114. RMS_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RMS_RESULT_MSB[7:0]
R
0b
Upper 8-bits of RMS result.
8.5.105 GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2]
GPO0_TRIG_EVENT_SEL is shown in Figure 124 and described in Table 115.
Return to the Summary Table.
Figure 124. GPO0_TRIG_EVENT_SEL Register
7
62
6
5
4
3
GPO0_TRIG_EVENT_SEL[7:0]
R/W-10b
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Table 115. GPO0_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO0_TRIG_EVENT_SE
L[7:0]
R/W
10b
Select the inputs AIN/GPIO[7:0] which can trigger an event based
update on GPO0.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO0 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO0 output.
8.5.106 GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x1]
GPO1_TRIG_EVENT_SEL is shown in Figure 125 and described in Table 116.
Return to the Summary Table.
Figure 125. GPO1_TRIG_EVENT_SEL Register
6
5
4
3
GPO1_TRIG_EVENT_SEL[7:0]
R/W-1b
2
1
0
Table 116. GPO1_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO1_TRIG_EVENT_SE
L[7:0]
R/W
1b
Select the inputs AIN/GPIO[7:0] which can trigger an event based
update on GPO1.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO1 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit ttrigger
GPO1 output.
8.5.107 GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x8]
GPO2_TRIG_EVENT_SEL is shown in Figure 126 and described in Table 117.
Return to the Summary Table.
Figure 126. GPO2_TRIG_EVENT_SEL Register
7
6
5
4
3
GPO2_TRIG_EVENT_SEL[7:0]
R/W-1000b
2
1
0
Table 117. GPO2_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO2_TRIG_EVENT_SE
L[7:0]
R/W
1000b
Select the inputs AIN/GPIO[7:0] which can trigger an event based
update on GPO2.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO2 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO2 output.
8.5.108 GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x4]
GPO3_TRIG_EVENT_SEL is shown in Figure 127 and described in Table 118.
Return to the Summary Table.
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Figure 127. GPO3_TRIG_EVENT_SEL Register
7
6
5
4
3
GPO3_TRIG_EVENT_SEL[7:0]
R/W-100b
2
1
0
Table 118. GPO3_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO3_TRIG_EVENT_SE
L[7:0]
R/W
100b
Select the inputs AIN/GPIO[7:0] which can trigger an event based
update on GPO3.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO3 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO3 output.
8.5.109 GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset = 0x20]
GPO4_TRIG_EVENT_SEL is shown in Figure 128 and described in Table 119.
Return to the Summary Table.
ADVANCE INFORMATION
Figure 128. GPO4_TRIG_EVENT_SEL Register
7
6
5
4
3
GPO4_TRIG_EVENT_SEL[7:0]
R/W-100000b
2
1
0
Table 119. GPO4_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO4_TRIG_EVENT_SE
L[7:0]
R/W
100000b
Select the inputs AIN/GPIO[7:0] which can trigger an Event based
update on GPO4.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO4 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO4 output.
8.5.110 GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset = 0x10]
GPO5_TRIG_EVENT_SEL is shown in Figure 129 and described in Table 120.
Return to the Summary Table.
Figure 129. GPO5_TRIG_EVENT_SEL Register
7
6
5
4
3
GPO5_TRIG_EVENT_SEL[7:0]
R/W-10000b
2
1
0
Table 120. GPO5_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO5_TRIG_EVENT_SE
L[7:0]
R/W
10000b
Select the inputs AIN/GPIO[7:0] which can trigger an Event based
update on GPO5.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO5 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO5 output.
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8.5.111 GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x80]
GPO6_TRIG_EVENT_SEL is shown in Figure 130 and described in Table 121.
Return to the Summary Table.
Figure 130. GPO6_TRIG_EVENT_SEL Register
7
6
5
4
3
GPO6_TRIG_EVENT_SEL[7:0]
R/W-10000000b
2
1
0
Table 121. GPO6_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO6_TRIG_EVENT_SE
L[7:0]
R/W
10000000b
Select the inputs AIN/GPIO[7:0] which can trigger an Event based
update on GPO6.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO6 output.
8.5.112 GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x40]
GPO7_TRIG_EVENT_SEL is shown in Figure 131 and described in Table 122.
Return to the Summary Table.
Figure 131. GPO7_TRIG_EVENT_SEL Register
7
6
5
4
3
GPO7_TRIG_EVENT_SEL[7:0]
R/W-1000000b
2
1
0
Table 122. GPO7_TRIG_EVENT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO7_TRIG_EVENT_SE
L[7:0]
R/W
1000000b
Select the inputs AIN/GPIO[7:0] which can trigger an Event based
update on GPO7.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not
trigger GPO7 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO7 output.
8.5.113 GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3) [reset = 0x0]
GPO_VALUE_ZCD_CFG_CH0_CH3 is shown in Figure 132 and described in Table 123.
Return to the Summary Table.
Figure 132. GPO_VALUE_ZCD_CFG_CH0_CH3 Register
7
6
GPO_VALUE_ZCD_CFG_CH3[1
:0]
R/W-0b
5
4
GPO_VALUE_ZCD_CFG_CH2[1
:0]
R/W-0b
3
2
GPO_VALUE_ZCD_CFG_CH1[1
:0]
R/W-0b
1
0
GPO_VALUE_ZCD_CFG_CH0[1
:0]
R/W-0b
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1b = Alert flags for the AIN/GPIO corresponding to this bit trigger
GPO6 output.
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Table 123. GPO_VALUE_ZCD_CFG_CH0_CH3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GPO_VALUE_ZCD_CFG
_CH3[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
5-4
GPO_VALUE_ZCD_CFG
_CH2[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
3-2
GPO_VALUE_ZCD_CFG
_CH1[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
ADVANCE INFORMATION
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
1-0
GPO_VALUE_ZCD_CFG
_CH0[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
8.5.114 GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4) [reset = 0x0]
GPO_VALUE_ZCD_CFG_CH4_CH7 is shown in Figure 133 and described in Table 124.
Return to the Summary Table.
Figure 133. GPO_VALUE_ZCD_CFG_CH4_CH7 Register
7
6
GPO_VALUE_ZCD_CFG_CH7[1
:0]
R/W-0b
5
4
GPO_VALUE_ZCD_CFG_CH6[1
:0]
R/W-0b
3
2
GPO_VALUE_ZCD_CFG_CH5[1
:0]
R/W-0b
1
0
GPO_VALUE_ZCD_CFG_CH4[1
:0]
R/W-0b
Table 124. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GPO_VALUE_ZCD_CFG
_CH7[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
5-4
GPO_VALUE_ZCD_CFG
_CH6[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
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Table 124. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-2
GPO_VALUE_ZCD_CFG
_CH5[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
1-0
GPO_VALUE_ZCD_CFG
_CH4[1:0]
R/W
0b
Define the GPO value to be launched on ZCD rising and falling
edges.
0b = Rising (0) and falling (0) -> logic 0 on both edges
1b = Rising (0) and falling (1) -> ZCD_bar
10b = Rising (1) and falling (0) -> ZCD
11b = Rising (1) and falling (1) -> logic 1 on both edges
8.5.115 GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0]
Return to the Summary Table.
Figure 134. GPO_ZCD_UPDATE_EN Register
7
6
5
4
3
GPO_ZCD_UPDATE_EN[7:0]
R/W-0b
2
1
0
Table 125. GPO_ZCD_UPDATE_EN Register Field Descriptions
Bit
Field
7-0
GPO_ZCD_UPDATE_EN[ R/W
7:0]
Type
Reset
Description
0b
Update digital outputs GPO[7:0] synchronous to ZCD.
0b = Digital output not updated synchronous to ZCD.
1b = Digital output updated synchronous to ZCD. Configure
GPO_VALUE_ON_ZCD_CFG register.
8.5.116 GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0]
GPO_TRIGGER_CFG is shown in Figure 135 and described in Table 126.
Return to the Summary Table.
Figure 135. GPO_TRIGGER_CFG Register
7
6
5
4
3
GPO_TRIGGER_UPDATE_EN[7:0]
R/W-0b
2
1
0
Table 126. GPO_TRIGGER_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_TRIGGER_UPDAT
E_EN[7:0]
R/W
0b
Update digital outputs GPO[7:0] when corresponding trigger is set. .
0b = Digital output is not updated in response to alert flags.
1b = Digital output is updated when corresponding alert flags are set.
Configure GPOx_TRIG_EVENT_SEL register to select which alert
flags can trigger an update on the desired GPO.
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GPO_ZCD_UPDATE_EN is shown in Figure 134 and described in Table 125.
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8.5.117 GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0]
GPO_VALUE_TRIG is shown in Figure 136 and described in Table 127.
Return to the Summary Table.
Figure 136. GPO_VALUE_TRIG Register
7
6
5
4
3
GPO_VALUE_ON_TRIGGER[7:0]
R/W-0b
2
1
0
Table 127. GPO_VALUE_TRIG Register Field Descriptions
Bit
Field
7-0
GPO_VALUE_ON_TRIGG R/W
ER[7:0]
Type
Reset
Description
0b
Value to be set on digital outputs GPO[7:0] when corresponding
trigger occurs. GPO update on alert flags must be enabled in
corresponding bit in GPO_TRIGGER_CFG register.
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.
ADVANCE INFORMATION
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register analog-to-digital converter (SAR ADC) are the input driver and the reference driver circuits. This section
details some general principles for designing the input driver circuit, reference driver circuit, and provides some
application circuits designed for the ADS7028.
9.2 Typical Applications
Digital Output (open-drain)
Digital Output (push-pull)
Analog Input
Analog Input
Analog Input
Analog Input
AVDD (VREF)
SPI
Device
Controller
Digital Input
Digital Input
Figure 137. DAQ Circuit: Single-Supply DAQ
9.2.1.1 Design Requirements
The goal of this application is to configure some channels of the ADS7028 as digital inputs, open-drain digital
outputs, and push-pull digital outputs.
9.2.1.2 Detailed Design Procedure
The ADS7028 can support GPIO functionality at each input pin. Any analog input pin can be independently
configured as a digital input, a digital open-drain output, or a digital push-pull output though the PIN_CFG and
GPIO_CFG registers; see Table 3.
9.2.1.2.1 Digital Input
The digital input functionality can be used to monitor a signal within the system. Figure 138 illustrates that the
state of the digital input can be read from the GPI_VALUE register.
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9.2.1 Mixed-Channel Configuration
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Typical Applications (continued)
ADC
From input device
AVDD
GPIx
SW
GPIx
Figure 138. Digital Input
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9.2.1.2.2 Digital Open-Drain Output
The channels of the ADS7028 can be configured as digital open-drain outputs supporting an output voltage up to
5.5 V. An open-drain output, as shown in Figure 139, consists of an internal FET (Q) connected to ground. The
output is idle when not driven by the device, which means Q is off and the pullup resistor, RPULL_UP, connects the
GPOx node to the desired output voltage. The output voltage can range anywhere up to 5.5 V, depending on the
external voltage that the GPIOx is pulled up to. When the device is driving the output, Q turns on, thus
connecting the pullup resistor to ground and bringing the node voltage at GPOx low.
VPULL_UP
Receiving Device
ADC
RPULL_UP
GPOx
ILOAD
Q
Figure 139. Digital Open-Drain Output
The minimum value of the pullup resistor, as calculated in Equation 6, is given by the ratio of VPULL_UP and the
maximum current supported by the device digital output (5 mA).
RMIN = (VPULL_UP / 5 mA)
(6)
The maximum value of the pullup resistor, as calculated in Equation 7, depends on the minimum input current
requirement, ILOAD, of the receiving device driven by this GPIO.
RMAX = (VPULL_UP / ILOAD)
(7)
Select RPULL_UP such that RMIN < RPULL_UP < RMAX.
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Typical Applications (continued)
9.2.2 Digital Push-Pull Output Configuration
The channels of the ADS7028 can be configured as digital push-pull outputs supporting an output voltage up to
AVDD. As shown in Figure 140, a push-pull output consists of two mirrored opposite bipolar transistors, Q1 and
Q2. The device can both source and sink current because only one transistor is on at a time (either Q2 is on and
pulls the output low, or Q1 is on and sets the output high). A push-pull configuration always drives the line
opposed to an open-drain output where the line is left floating.
ADC
AVDD
Q1
GPOx
Digital
output
Figure 140. Digital Push-Pull Output
10 Power Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The ADS7028 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. For supplies greater than 2.35 V, AVDD and DVDD can be shorted externally if
single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device.
Decouple the AVDD and DVDD pins individually, as shown in Figure 141, with 1-µF ceramic decoupling
capacitors. The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If
both supplies are powered from the same source, a minimum capacitor value of 220 nF is required for
decoupling.
AVDD
AVDD
1 PF
GND
1 PF
DVDD
DVDD
Figure 141. Power-Supply Decoupling
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11 Layout
11.1 Layout Guidelines
Figure 142 shows a board layout example for the ADS7028. Avoid crossing digital lines with the analog signal
path and keep the analog input signals and the AVDD supply away from noise sources.
Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply
pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to
the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference
voltage for the ADS7028. Place the decoupling capacitor (CREF) for AVDD close to the device AVDD and GND
pins and connect CREF to the device pins with thick copper tracks.
GND
DVDD
SDO
ADVANCE INFORMATION
CS
11.2 Layout Example
DECAP
SCLK
AVDD
SDI
AIN/GPIO
Figure 142. Example Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7028IRTER
PREVIEW
WQFN
RTE
16
3000
TBD
Call TI
Call TI
-40 to 85
ADS7028IRTET
PREVIEW
WQFN
RTE
16
250
TBD
Call TI
Call TI
-40 to 85
XADS7028IRTER
ACTIVE
WQFN
RTE
16
3000
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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