Texas Instruments | TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs | Datasheet | Texas Instruments TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs Datasheet

Texas Instruments TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs Datasheet
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TLA2528
SBAS961 – MAY 2019
TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
Small package size:
– 3-mm × 3-mm WQFN
8 channels configurable as any combination of:
– Up to 8 analog inputs, digital inputs, or digital
outputs
GPIOs for I/O expansion:
– Open-drain, push-pull digital outputs
Wide operating ranges:
– AVDD: 2.35 V to 5.5 V
– DVDD: 1.65 V to 5.5 V
– –40°C to +85°C temperature range
I2C interface:
– Up to 3.4 MHz (high speed)
– 8 configurable I2C addresses
Programmable averaging filters:
– Programmable sample size for averaging
– Averaging with internal conversions
– 16-bit resolution for average output
Supervisory functions
Portable instrumentation
Telecommunication infrastructure
Power-supply monitoring
3 Description
The TLA2528 is an easy-to-use, 8-channel,
multiplexed, 12-bit, successive approximation register
analog-to-digital converter (SAR ADC). The eight
channels can be independently configured as either
analog inputs, digital inputs, or digital outputs. The
device has an internal oscillator for ADC conversion
processes.
The TLA2528 communicates via an I2C-compatible
interface and supports standard-mode (100 kHz),
fast-mode (400 kHz), fast-mode plus (1 MHz), and
high-speed mode (3.4 MHz). Up to eight I2C
addresses can be selected for the TLA2528 by
connecting a resistor on the ADDR pin.
Device Information(1)
PART NAME
TLA2528
PACKAGE
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
TLA2528 Block Diagram and Applications
Example Applications
Device Block Diagram
AVDD (VREF)
AIN / GPIO
DECAP
AVDD
AIN / GPIO
DVDD
AIN0 / GPIO0
ADDR
AIN1 / GPIO1
ADC
Programmable
Averaging Filter
I2C Interface
AIN2 / GPIO2
SDA
SCL
AIN / GPIO
AIN / GPIO
AIN / GPIO
AIN / GPIO
I2C
TLA2528
Controller
AIN / GPIO
AIN / GPIO
AIN3 / GPIO3
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
MUX
VSIGNAL + noise
Sequencer
Pin CFG
GND
Reduced
noise
R1
GPO Write
GPI Read
TLA2528
TLA2528
Controller
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
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SBAS961 – MAY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Timing Requirements..........................................
Timing Requirements ................................................
I2C Switching Characteristics....................................
Switching Characteristics ..........................................
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 16
7.6 TLA2528 Registers ................................................. 19
8
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9
Power Supply Recommendations...................... 28
9.1 AVDD and DVDD Supply Recommendations......... 28
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
Detailed Description .............................................. 8
ADVANCE INFORMATION
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
May 2019
*
Initial release.
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5 Pin Configuration and Functions
12
NC
11
ADDR
10
DVDD
9
GND
ADVANCE INFORMATION
AIN1 / GPIO1
AIN0 / GPIO0
SDA
SCL
15
14
13
8
4
DECAP
AIN5 / GPIO5
7
3
AVDD
AIN4 / GPIO4
Thermal
Pad
6
2
AIN7 / GPIO7
AIN3 / GPIO3
5
1
AIN6 / GPIO6
AIN2 / GPIO2
16
RTE Package
16-Pin WQFN
Top View
Pin Functions
PIN
NAME
NO.
FUNCTION (1)
DESCRIPTION
AIN0/GPIO0
15
AI, DI, DO
Channel 0; configurable as either an analog input (default) or a general-purpose
input/output (GPIO)
AIN1/GPIO1
16
AI, DI, DO
Channel 1; configurable as either an analog input (default) or a GPIO
AIN2/GPIO2
1
AI, DI, DO
Channel 2; configurable as either an analog input (default) or a GPIO
AIN3/GPIO3
2
AI, DI, DO
Channel 3; configurable as either an analog input (default) or a GPIO
AIN4/GPIO4
3
AI, DI, DO
Channel 4; configurable as either an analog input (default) or a GPIO
AIN5/GPIO5
4
AI, DI, DO
Channel 5; configurable as either an analog input (default) or a GPIO
AIN6/GPIO6
5
AI, DI, DO
Channel 6; configurable as either an analog input (default) or a GPIO
AIN7/GPIO7
6
AI, DI, DO
Channel 7; configurable as either an analog input (default) or a GPIO
ADDR
11
AI
Input for selecting the device I2C address.
Connect a resistor to this pin from DECAP pin or GND to select one of the eight
addresses.
AVDD
7
Supply
Analog supply input, also used as the reference voltage to the ADC; connect a
1-µF decoupling capacitor to GND
DECAP
8
Supply
Connect a decoupling capacitor to this pin for the internal power supply
DVDD
10
Supply
Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND
GND
9
Supply
Ground for the power supply; all analog and digital signals are referred to this
pin voltage
NC
No connection
SDA
14
DI, DO
SCL
13
DI
(1)
This pin must be left floating with no external connection
Serial data input or output for the I2C interface
Serial clock for the I2C interface
AI = analog input, DI = digital input, and DO = digital output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
DVDD to GND
AVDD to GND
MIN
MAX
–0.3
5.5
UNIT
V
–0.3
5.5
V
AINx/GPOx (2)
GND – 0.3 AVDD + 0.3
V
ADDR
GND – 0.3
2.1
V
Digital inputs
GND – 0.3
5.5
V
Current through any pin except supply pins (3)
–10
10
mA
Junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–60
150
°C
(1)
ADVANCE INFORMATION
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AINx/GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16.
Pin current must be limited to 10mA or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
Analog supply voltage
2.35
3.3
5.5
V
DVDD
Digital supply voltage
1.65
3.3
5.5
V
0
AVDD
V
–0.1
AVDD + 0.1
V
85
℃
ANALOG INPUTS
FSR
Full-scale input range
AINX (1) - GND
VIN
Absolute input voltage
AINX - GND
TEMPERATURE RANGE
TA
(1)
Ambient temperature
–40
25
AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
6.4 Thermal Information
TLA2528
THERMAL METRIC
(1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
49.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.4
°C/W
RθJB
Junction-to-board thermal resistance
24.7
°C/W
ΨJT
Junction-to-top characterization parameter
1.3
°C/W
ΨJB
Junction-to-board characterization parameter
24.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
CSH
Sampling capacitance
12
pF
DC PERFORMANCE
Resolution
No missing codes
12
bits
±0.3
LSB
±0.5
LSB
DNL
Differential nonlinearity
INL
Integral nonlinearity
V(OS)
Input offset error
Post offset calibration
±0.5
Input offset thermal drift
Post offset calibration
±5
GE
Gain error
Gain error thermal drift
LSB
ppm/°C
±0.05
%FSR
±5
ppm/°C
AC PERFORMANCE
Signal-to-noise + distortion ratio
AVDD = 5 V, fIN = 2 kHz
71.5
AVDD = 3 V, fIN = 2 kHz
70.5
dB
ADVANCE INFORMATION
SINAD
DECAP Pin
Decoupling capacitor on DECAP
pin
0.22
1
µF
DIGITAL INPUT/OUTPUT (SCL, SDA)
VIH
VIL
VOL
IOL
Input high logic level
Input low logic level
Output low logic level
Low-level output current (sink)
All I2C modes
2
All I C modes
0.7 x DVDD
5.5
V
V
–0.3
0.3 x DVDD
Sink current = 2 mA, DVDD > 2 V
0
0.4
Sink current = 2 mA, DVDD ≤ 2 V
0
0.2 x DVDD
VOL = 0.4 V, standard and fast
mode
3
VOL = 0.6 V, fast mode
6
VOL = 0.4 V, fast mode plus
V
mA
20
GPIOs
VIH
Input high logic level
VIL
Input low logic level
0.7 x AVDD
AVDD + 0.3
V
–0.3
0.3 x AVDD
V
VOH
Output high logic level
GPO_DRIVE_CFG = push-pull,
ISOURCE = 2 mA
0.8 x AVDD
AVDD
V
VOL
Output low logic level
ISINK = 2 mA
IOH
Output high source current
VOH > 0.7 x AVDD
0
0.2 x AVDD
5
mA
IOL
Output low sink current
VOL < 0.3 x AVDD
5
mA
V
POWER SUPPLY CURRENTS
I2C high-speed mode, AVDD = 5 V
2
IAVDD
Analog supply current
260
I C fast mode plus, AVDD = 5 V
83
I2C fast mode, AVDD = 5 V
35
I2C standard mode, AVDD = 5 V
10
No conversion, AVDD = 5 V
5
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5
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6.6 I2C Timing Requirements
MODE
FAST MODE
MIN
HIGH SPEED MODE
MAX
MIN
UNIT
MAX
fSCL
SCL clock frequency (1)
tSUSTA
START condition setup time for repeated start
260
160
ns
tHDSTA
Start condition hold time
260
160
ns
tLOW
Clock low period
500
160
ns
tHIGH
Clock high period
260
60
ns
tSUDAT
Data in setup time
50
10
ns
tHDDAT
Data in hold time
0
0
ns
tR
SCL rise time
120
80
ns
tF
SCL fall time
120
80
ns
tSUSTO
STOP condition hold time
260
60
ns
tBUF
Bus free time before new transmission
500
300
ns
(1)
1
3.4
MHz
Bus load (CB) consideration; CB ≤ 400 pF for fSCL ≤ 1 MHz; CB < 100 pF for fSCL = 3.4 MHz.
ADVANCE INFORMATION
6.7 Timing Requirements
at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and
maximum values at TA = –40°C to +85°C; typical values at TA = 25°C.
MIN
tACQ
Acquisition time
MAX
UNIT
300
ns
6.8 I2C Switching Characteristics
MODE
FAST MODE
MIN
HIGH-SPEED MODE
MAX
MIN
UNIT
MAX
tVDDATA
SCL low to SDA data out valid
450
200
ns
tVDACK
SCL low to SDA acknowledge time
450
200
ns
tSTRETCH
Clock stretch time in one-shot conversion mode; during ADC
conversion
1200
950
ns
tSP
Noise supression time constant on SDA and SCL
50
10
ns
6
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6.9 Switching Characteristics
at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and
maximum values at TA = –40°C to +85°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
CONVERSION CYCLE
tCONV
ADC conversion time
tSTRETCH
ns
5
ms
5
ms
RESET
AVDD ≥ 2.35 V
tPU
Power-up time for device
tRST
Delay time; RST bit = 1b to device reset
complete (1)
(1)
RST bit is automatically reset to 0b after tRST.
9th clock
tLOW
tHIGH
tR
tSUDAT
tF
tSUSTO
tSTRETCH
tHDSTA tHDDAT
ADVANCE INFORMATION
SCL
tSUSTA
tSP
SDA
tBUF
P
tVDDAT
tVDACK
Sr
S
P
NOTE: S = start, Sr = repeated start, and P = stop.
Figure 1. I2C Timing Diagram
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7 Detailed Description
7.1 Overview
The TLA2528 is a small, eight-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2Ccompatible serial interface. The eight channels of the TLA2528 can be individually configured as either analog
inputs, digital inputs, or digital outputs. The device uses an internal oscillator for conversion. The analog input
channel selection can be auto-sequenced to simplify the digital interface with the host.
The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution.
The I2C serial interface supports standard-mode, fast-mode, fast-mode plus, and high-speed mode.
7.2 Functional Block Diagram
DECAP
AVDD
DVDD
ADVANCE INFORMATION
AIN0 / GPIO0
ADDR
AIN1 / GPIO1
ADC
Programmable
Averaging Filter
2
I C Interface
AIN2 / GPIO2
SDA
SCL
AIN3 / GPIO3
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
8
MUX
Sequencer
Pin CFG
GND
GPO Write
GPI Read
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7.3 Feature Description
7.3.1 Multiplexer and ADC
The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose
inputs/outputs (GPIOs). Figure 2 shows that each input pin has electrostatic discharge (ESD) protection diodes
to AVDD and GND. On power-up or after device reset, all eight multiplexer channels are configured as analog
inputs.
Figure 2 shows an equivalent circuit for pins configured as analog inputs. The ADC sampling switch is
represented by an ideal switch (SW) in series with the resistor, RSW (typically 150 Ω), and the sampling capacitor,
CSH (typically 12 pF).
AVDD
Pin CFG
GPIO0
AIN0 / GPIO0
SW
MUX
CSH
AVDD
ADC
GPIO7
AIN7 / GPIO7
Multiplexer
Figure 2. Analog Inputs, GPIOs, and ADC Connections
During acquisition, the SW switch is closed to allow the signal on the selected analog input channel to charge the
internal sampling capacitor. During conversion, the SW switch is opened to disconnect the analog input channel
from the sampling capacitor.
The multiplexer channels can be configured as GPIOs in the PIN_CFG register. The direction of a GPIO (either
as an input or an output) can be set in the GPIO_CFG register. The logic level on the channels configured as
digital inputs can be read from the GPI_VALUE register. The digital outputs can be accessed by writing to the
GPO_OUTPUT_VALUE register. The digital outputs can be configured as either open-drain or push-pull in the
GPO_DRIVE_CFG register.
7.3.2 Reference
The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process.
TI recommends connecting a 1-µF, low-equivalent series resistance (ESR) ceramic decoupling capacitor
between the AVDD and GND pins.
7.3.3 ADC Transfer Function
The ADC output is in straight binary format. Equation 1 computes the ADC resolution:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD
N = 12
(1)
Figure 3 and Table 1 detail the transfer characteristics for the device.
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Feature Description (continued)
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
1 LSB
AVDD/2 (AVDD/2 + 1 LSB)
(AVDD ± 1 LSB)
ADVANCE INFORMATION
Figure 3. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE
CODE
DESCRIPTION
IDEAL OUTPUT CODE
≤1 LSB
NFSC
Negative full-scale code
000
1 LSB to 2 LSBs
NFSC + 1
—
001
(AVDD / 2) to (AVDD / 2) + 1 LSB
MC
Mid code
800
(AVDD / 2) + 1 LSB to (AVDD / 2) + 2 LSB
MC + 1
—
801
≥ AVDD – 1 LSB
PFSC
Positive full-scale code
FFF
7.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the
CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit
to check the ADC offset calibration completion status.
7.3.5 I2C Address Selector
The I2C address for the device is determined by connecting external resistors on the ADDR pin. The device
address is determined at power-up based on the resistor values. The device retains this address until the next
power-up event, until the next device reset, or until the device receives a command to program its own address.
Figure 4 shows a connection diagram for the ADDR pin and Table 2 lists the resistor values for selecting different
addresses of the device.
DECAP Pin
R1
ADDR
R2
Figure 4. External Resistor Connection Diagram for the ADDR Pin
10
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Table 2. I2C Address Selection
RESISTORS
R2 (1)
0Ω
DNP (2)
001 0111b (17h)
11 kΩ
DNP (2)
001 0110b (16h)
33 kΩ
DNP (2)
001 0101b (15h)
100 kΩ
DNP (2)
DNP
(2)
001 0100b (14h)
0 Ω or DNP
(2)
001 0000b (10h)
DNP (2)
11 kΩ
001 0001b (11h)
DNP (2)
33 kΩ
001 0010b (12h)
100 kΩ
001 0011b (13h)
DNP
(1)
(2)
ADDRESS
R1 (1)
(2)
Tolerance for R1, R2 ≤ ±5%.
DNP = Do not populate.
The ADS7138 features a built-in oversampling (OSR) function that can be used to average several samples. The
averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging filter
configuration is common to all analog input channels. Figure 5 shows that the averaging filter module output is
16 bits long. In the manual conversion mode and auto-sequence mode, only the first conversion for the selected
analog input channel must be initiated by the host; see the Manual Mode and Auto-Sequence Mode sections. As
shown in Figure 5, any remaining conversions for the selected averaging factor are generated internally. The
time required to complete the averaging operation is determined by the sampling speed and number of samples
to be averaged. As shown in Figure 5, the 16-bit result can be read out after the averaging operation completes.
Sample AINX
S
7-bit ADDR
R
Sample AINX
A
Sample AINX
Sample AINX
OSR_DONE = 1
Bus idle or Poll OSR_DONE bit
DATA[15:8]
A
DATA[7:0]
A
OSR_DONE = 0
OSR_CFG[2:0] = 2
Time = tCONV x OSR_CFG[2:0]
Data from host to device
Data from device to host
Figure 5. Averaging Example
In Figure 5, SCL is stretched by the device after the start of conversions until the averaging operation is
complete.
If SCL stretching is not required during averaging, enable the statistics registers by setting STATS_EN to 1b and
initiate conversions by writing 1b to the CNVST bit. The OSR_DONE bit in the SYSTEM_STATUS register can
be polled to check the averaging completion status. When using the CNVST bit to initiate conversion, the result
can be read in the RECENT_CHx_LSB and RECENT_CHx_MSB registers.
Equation 2 provides the LSB value of the 16-bit average result.
AVDD
1 LSB
216
(2)
7.3.7 General-Purpose I/Os (GPIOs)
The eight channels of the TLA2528 can be independently configured as analog inputs, digital inputs, or digital
outputs. Table 3 describes how the PIN_CFG and GPIO_CFG registers can be used to configure the channels.
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7.3.6 Programmable Averaging Filter
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Table 3. Configuring Channels as Analog Inputs or GPIOs
PIN_CFG[7:0]
GPIO_CFG[7:0]
GPO_DRIVE_CF
G[7:0]
CHANNEL CONFIGURATION
0
x
x
Analog input (default)
1
0
x
Digital input
1
1
0
Digital output; open-drain driver
1
1
1
Digital output; push-pull driver
The digital outputs can be configured to logic 1 or 0 by writing to the GPO_OUTPUT_VALUE register. Reading
the GPI_VALUE register returns the logic level for all channels configured as digital inputs.
7.3.8 Oscillator and Timing Control
The device uses an internal oscillator for conversions. When using the averaging module, the host initiates the
first conversion and all subsequent conversions are generated internally by the device. However, in the
autonomous mode of operation, the start of the conversion signal is generated by the device. Table 4 shows that
when the device generates the start of the conversion, the sampling rate is controlled by the OSC_SEL and
CLK_DIV[3:0] register fields.
ADVANCE INFORMATION
Table 4. Configuring Sampling Rate for Internal Conversion Start Control
OSC_SEL = 0
CLK_DIV[3:0]
SAMPLING FREQUENCY,
fCYCLE (kSPS)
OSC_SEL = 1
CYCLE TIME,
tCYCLE (µs)
SAMPLING FREQUENCY, fCYCLE
(kSPS)
CYCLE TIME, tCYCLE
(µs)
0000b
1000
1
31.25
32
0001b
666.7
1.5
20.83
48
0010b
500
2
15.63
64
0011b
333.3
3
10.42
96
0100b
250
4
7.81
128
0101b
166.7
6
5.21
192
0110b
125
8
3.91
256
0111b
83
12
2.60
384
1000b
62.5
16
1.95
512
1001b
41.7
24
1.3
768
1010b
31.3
32
0.98
1024
1011b
20.8
48
0.65
1536
1100b
15.6
64
0.49
2048
1101b
10.4
96
0.33
3072
The conversion time of the device (see tCONV in the Switching Characteristics table) is independent of the
OSC_SEL and CLK_DIV[3:0] configuration.
7.3.9 Output Data Format
Figure 6 illustrates various I2C frames for reading data.
• Read the ADC conversion result: Two 8-bit I2C packets are required (frame A).
• Read the averaged conversion result: Two 8-bit I2C packets are required (frame B).
• Read data with the channel ID or status flags appended: The 4-bit channel ID or status flags can be
appended to the 12-bit ADC result by configuring the APPEND_STATUS field in the GENERAL_CFG
register. The status flags can be used to detect if a CRC error is detected and if an alert condition is detected
by the digital window comparator. When the channel ID is or status flags are appended to the 12-bit ADC
data, two I2C packets are required (frame C). If the channel ID is or status flags are appended to the 16-bit
average result, three I2C frames are required (frame D).
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Sample A
S
7-bit Slave Address
R
A
Sample A + 1
D11
D10
D9
D8
D7
D6
D5
D4
A
D3
D2
D1
D0
0
0
0
0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
D1
D0
Frame A : Reading ADC data
S
7-bit Slave Address
R
A
D15
D14
D13
D12
D11
D10
D9
D8
A
Frame B : Reading ADC data with averaging enabled
S
7-bit Slave Address
R
A
D11
D10
D9
D8
D7
D6
D5
D4
A
D3
D2
4-bit Channel ID
A
Frame C : Reading ADC data with channel ID appended
7-bit Slave Address
R
A
D15
D14
D8
A
D7
D6
D0
A
4-bit Channel ID
0
0
0
0
A
Frame D : Reading ADC data with averaging enabled &
channel ID appended
Clock stretching for conversion time
Data from host to device
Data from device to host
Figure 6. Data Frames for Reading Data
7.3.10 I2C Protocol Features
7.3.10.1 General Call
On receiving a general call (00h), the device provides an acknowledge (ACK).
7.3.10.2 General Call With Software Reset
On receiving a general call (00h) followed by a software reset (06h), the device resets itself.
7.3.10.3 General Call With a Software Write to the Programmable Part of the Slave Address
On receiving a general call (00h) followed by 04h, the device reevaluates its own I2C address configured by the
ADDR pin. During this operation, the device does not respond to other I2C commands except the general-call
command.
7.3.10.4 Configuring the Device for High-Speed I2C Mode
The device can be configured in high-speed I2C mode by providing an I2C frame with one of these codes: 0x09,
0x0B, 0x0D, or 0x0F.
After receiving one of these codes, the device sets the I2C_HIGH_SPEED bit in the SYSTEM_STATUS register
and remains in high-speed I2C mode until a STOP condition is received in an I2C frame.
7.4 Device Functional Modes
Table 5 lists the functional modes supported by the TLA2528.
Table 5. Functional Modes
FUNCTIONAL
MODE
CONVERSION CONTROL
MUX CONTROL
SEQ_MODE[1:0]
Manual
9th falling edge of SCL (ACK)
Register write to MANUAL_CHID
00b
Auto-sequence
9th falling edge of SCL (ACK)
Channel sequencer
01b
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The device powers up in manual mode (see the Manual Mode section) and can be configured into any mode
listed in Table 5 by writing the configuration registers for the desired mode.
7.4.1 Device Power-Up and Reset
On power-up, the device calculates the address from the resistors connected on the ADDR pin and the BOR bit
is set, thus indicating a power-cycle or reset event.
The device can be reset by an I2C general call (00h) followed by a software reset (06h), by setting the RST bit, or
by recycling the power on the AVDD pin.
7.4.2 Manual Mode
Manual mode allows the external host processor to directly select the analog input channel. Figure 7 lists the
steps for operating the device in manual mode.
Idle
SEQ_MODE = 0
Configure channels as AIN/GPIO using PIN_CFG
ADVANCE INFORMATION
Select Manual mode
(SEQ_MODE = 00b)
Configure desired Channel ID in MANUAL_CHID field
Host provides Conversion Start Frame on I2C Bus
Host provides Conversion Read Frame on I2C Bus
No
Yes
Same
Channel ID?
Manual mode with channel selection using register write
Figure 7. Device Operation in Manual Mode
Provide an I2C start or restart frame to initiate a conversion, as shown in the conversion start frame of Figure 8,
after configuring the device registers. ADC data can be read in subsequent I2C frames. The number of I2C
frames required to read conversion data depends on the output data frame size; see the Output Data Format
section for more details. A new conversion is initiated on the ninth falling edge of SCL (ACK bit) when the last
byte of output data is read.
Sample A + 1
Sample A
S
7-bit Slave Address
R
A
Clock stretching for conversion time
8 bit I2C frame
A
8 bit I2C frame
A
8 bit I2C frame
A
8 bit I2C frame
A
Clock stretching for conversion time
Data from host to device
Data from device to host
Figure 8. Starting a Conversion and Reading Data in Manual Mode
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7.4.3 Auto-Sequence Mode
In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input
channel after every conversion. The desired analog input channels can be configured for sequencing in the
AUTO_SEQ_CHSEL register. To enable the channel sequencer, set SEQ_START to 1b. After every conversion,
the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel
sequencer from selecting channels, set SEQ_START to 0b. Figure 9 lists the conversion start and read frames
for auto-sequence mode.
Idle
SEQ_MODE = 0
Configure channels as AIN/GPIO using PIN_CFG
Enable analog inputs for sequencing (AUTO_SEQ_CHSEL)
Select Auto-sequence mode (SEQ_MODE = 01b)
ADVANCE INFORMATION
(optional) Configure alert conditions
(optional) Append Channel ID to data using APPEND_STATUS
Enable channel sequencing SEQ_START = 1
Host provides Conversion Start Frame on I2C Bus
Host provides Conversion Read Frame on I2C Bus
Device selects next channel according to AUTO_SEQ_CHSEL
Continue?
Yes
No
Disable channel sequencing SEQ_START = 0
Idle
Figure 9. Device Operation in Auto-Sequence Mode
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7.5 Programming
Table 6 provides the acronyms for different conditions in an I2C frame. Table 7 lists the various command
opcodes.
Table 6. I2C Frame Acronyms
SYMBOL
DESCRIPTION
S
Start condition for the I2C frame
Sr
Restart condition for the I2C frame
P
Stop condition for the I2C frame
A
ACK (low)
N
NACK (high)
R
Read bit (high)
W
Write bit (low)
Table 7. Opcodes for Commands
ADVANCE INFORMATION
OPCODE
COMMAND DESCRIPTION
0001 0000b
Single register read
0000 1000b
Single register write
0001 1000b
Set bit
0010 0000b
Clear bit
0011 0000b
Reading a continuous block of registers
0010 1000b
Writing a continuous block of registers
7.5.1 Reading Registers
The I2C master can either read a single register or a continuous block registers from the device, as described in
the Single Register Read and Reading a Continuous Block of Registers sections.
7.5.1.1 Single Register Read
To read a single register from the device, the I2C master must provide an I2C command with three frames to set
the register address for reading data. Table 7 lists the opcodes for different commands. After this command is
provided, the I2C master must provide another I2C frame (as shown in Figure 10) containing the device address
and the read bit. After this frame, the device provides the register data. The device provides the same register
data even if the host provides more clocks. To end the register read command, the master must provide a STOP
or a RESTART condition in the I2C frame.
S
7-bit Slave Address
W
A
0001 0000b
A
Register
Address
Data from host to device
A
P/Sr
S
7-bit Slave Address
R
A
Register Data
A
P/Sr
Data from device to host
NOTE: S = start, Sr = repeated start, and P = stop.
Figure 10. Reading Register Data
16
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7.5.1.2 Reading a Continuous Block of Registers
To read a continuous block of registers, the I2C master must provide an I2C command to set the register
address. The register address is the address of the first register in the block that must be read. After this
command is provided, the I2C master must provide another I2C frame, as shown in Figure 11, containing the
device address and the read bit. After this frame, the device provides the register data. The device provides data
for the next register when more clocks are provided. When data are read from addresses that do not exist in the
register map of the device, the device returns zeros. If the device does not have any further registers to provide
data on, the device provide zeros. To end the register read command, the master must provide a STOP or a
RESTART condition in the I2C frame.
S
7-bit Slave Address
W
A
0011 0000b
A
1st Reg Address
in the Block
A
Data from host to device
P/Sr
S
7-bit Slave Address
R
A
Register Data
A
P/Sr
Data from device to host
NOTE: S = start, Sr = repeated start, and P = stop.
7.5.2 Writing Registers
The I2C master can either write a single register or a continuous block of registers to the device, set a few bits in
a register, or clear a few bits in a register.
7.5.2.1 Single Register Write
To write a single register from the device, as shown in Figure 12, the I2C master must provide an I2C command
with four frames. The register address is the address of the register that must be written and the register data is
the value that must be written. Table 7 lists the opcodes for different commands. To end the register write
command, the master must provide a STOP or a RESTART condition in the I2C frame.
S
7-bit Slave Address
W
A
0000 1000b
Data from host to device
A
Register
Address
A
Register Data
A
P/Sr
Data from device to host
NOTE: S = start, Sr = repeated start, and P = stop.
Figure 12. Writing a Single Register
7.5.2.2 Set Bit
The I2C master must provide an I2C command with four frames, as shown in Figure 12, to set bits in a register
without changing the other bits. The register address is the address of the register that the bits must set and the
register data is the value representing the bits that must be set. Bits with a value of 1 in the register data are set
and bits with a value of 0 in the register data are not changed. Table 7 lists the opcodes for different commands.
To end this command, the master must provide a STOP or RESTART condition in the I2C frame.
7.5.2.3 Clear Bit
The I2C master must provide an I2C command with four frames, as shown in Figure 12, to clear bits in a register
without changing the other bits. The register address is the address of the register that the bits must clear and
the register data is the value representing the bits that must be cleared. Bits with a value of 1 in the register data
are cleared and bits with a value of 0 in the register data are not changed. Table 7 lists the opcodes for different
commands. To end this command, the master must provide a STOP or a RESTART condition in the I2C frame.
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Figure 11. Reading a Continuous Block of Registers
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7.5.2.4 Writing a Continuous Block of Registers
The I2C master must provide an I2C command, as shown in Figure 13, to write a continuous block of registers.
The register address is the address of the first register in the block that must be written. The I2C master must
provide data for registers in subsequent I2C frames in an ascending order of register addresses. Writing data to
addresses that do not exist in the register map of the device have no effect. Table 7 lists the opcodes for
different commands. If the data provided by the I2C master exceeds the address space of the device, the device
ignores the data beyond the address space. To end the register write command, the master must provide a
STOP or a RESTART condition in the I2C frame.
S
7-bit Slave Address
W
A
0010 1000b
A
1st Reg Address
in the block
Data from host to device
A
Register Data
A
P/Sr
Data from device to host
NOTE: S = start, Sr = repeated start, and P = stop.
Figure 13. Writing a Continuous Block of Registers
ADVANCE INFORMATION
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7.6 TLA2528 Registers
Table 8 lists the TLA2528 registers. All register offset addresses not listed in Table 8 should be considered as
reserved locations and the register contents should not be modified.
Table 8. TLA2528 Registers
Acronym
0x0
SYSTEM_STATUS
0x1
GENERAL_CFG
0x2
DATA_CFG
0x3
OSR_CFG
0x4
OPMODE_CFG
0x5
PIN_CFG
0x7
GPIO_CFG
0x9
GPO_DRIVE_CFG
Register
Name
Section
SYSTEM_STATUS Register (Address = 0x0) [reset = 0x80]
GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
DATA_CFG Register (Address = 0x2) [reset = 0x0]
OSR_CFG Register (Address = 0x3) [reset = 0x0]
OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
PIN_CFG Register (Address = 0x5) [reset = 0x0]
GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
0xB
GPO_OUTPUT_VALUE
0xD
GPI_VALUE_LSB
GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
GPI_VALUE_LSB Register (Address = 0xD) [reset = 0x0]
0x10
SEQUENCE_CFG
SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
0x11
CHANNEL_SEL
0x12
AUTO_SEQ_CHSEL
CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
AUTO_SEQ_CHSEL Register (Address = 0x12) [reset = 0x0]
Complex bit access types are encoded to fit into small table cells. Table 9 shows the codes that are used for
access types in this section.
Table 9. TLA2528 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
7.6.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x80]
SYSTEM_STATUS is shown in Figure 14 and described in Table 10.
Return to the Summary Table.
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Address
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Figure 14. SYSTEM_STATUS Register
7
RSVD
6
SEQ_STATUS
5
I2C_SPEED
4
RESERVED
3
OSR_DONE
R-1b
R-0b
R-0b
R-0b
R/W-0b
2
CRC_ERR_FU
SE
R-0b
1
RESERVED
0
BOR
R-0b
R/W-0b
Table 10. SYSTEM_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
1b
This bit must read 1b.
6
SEQ_STATUS
R
0b
Sequencer Status
0b = Sequence stopped
1b = Sequence in progress
2
5
I C_SPEED
R
I2C high-speed status
0b
0b = Device is not in high speed mode
1b = Device is in high speed mode
4
RESERVED
R
0b
Reserved. Reads return 0b.
3
OSR_DONE
R/W
0b
OSR status. Clear this bit by writing 1b to this bit.
ADVANCE INFORMATION
0b = OSR in progress; data not ready.
1b = OSR complete; data ready.
2
CRC_ERR_FUSE
R
0b
Device fuse CRC check status. To re-evaluate this bit, software reset
the device or power cycle AVDD.
0b = Configuration is good.
1b = Device configuration not loaded correctly.
1
RESERVED
R
0b
Reserved. Reads return 0b.
0
BOR
R/W
0b
Brown out reset indicator. This bit is set if brown out condition occurs
or device is power cycled. Write 1 to this bit to clear the flag.
0b = No brown out from last time this bit was cleared.
1b = Brown out condition detected or device power cycled.
7.6.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
GENERAL_CFG is shown in Figure 15 and described in Table 11.
Return to the Summary Table.
Figure 15. GENERAL_CFG Register
7
6
5
4
RESERVED
R-0b
3
CNVST
W-0b
2
CH_RST
R/W-0b
1
CAL
R/W-0b
0
RST
W-0b
Table 11. GENERAL_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0b
Reserved. Reads return 0b.
CNVST
W
0b
Intiate start of conversion. Readback of this bit will return 0.
3
0b = Normal operation.
1b = Initiate start of conversion.
2
CH_RST
R/W
0b
Force all channels to be analog inputs.
0b = Normal operation.
1b = All channels will be set as analog inputs irrespective of
configuration in other registers.
1
CAL
R/W
0b
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset will be calibrated. After calibration is complete, this
bit will be set to 0.
20
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Table 11. GENERAL_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
RST
W
0b
Software reset all registers to default values.
0b = Normal operation.
1b = Device will be reset. After reset is complete, this bit will be set
to 0.
7.6.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]
DATA_CFG is shown in Figure 16 and described in Table 12.
Return to the Summary Table.
Figure 16. DATA_CFG Register
6
RESERVED
R-0b
5
4
APPEND_STATUS[1:0]
R/W-0b
3
2
1
0
RESERVED
R-0b
Table 12. DATA_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
FIX_PAT
R/W
0b
Device outputs fixed data bits. Helpful for debugging device
communication.
0b = Normal operation.
1b = Device outputs a fixed code 0xA5A repeatitively when reading
ADC data.
6
5-4
RESERVED
R
0b
Reserved. Reads return 0b.
APPEND_STATUS[1:0]
R/W
0b
Append 4-bit channel ID to output data.
0b = Flag is not appended to ADC data.
1b = Channel ID is appended to ADC data.
3-0
RESERVED
R
0b
Reserved. Reads return 0b.
7.6.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 17 and described in Table 13.
Return to the Summary Table.
Figure 17. OSR_CFG Register
7
6
5
RESERVED
R-0b
4
3
2
1
OSR[2:0]
R/W-0b
0
Table 13. OSR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0b
Reserved. Reads return 0b.
2-0
OSR[2:0]
R/W
0b
Selects the oversampling ratio for ADC conversion result.
0b = OSR = 0.
1b = OSR = 2.
10b = OSR = 4.
11b = OSR = 8.
100b = OSR = 16.
101b = OSR = 32.
110b = OSR = 64.
111b = OSR = 128.
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FIX_PAT
R/W-0b
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7.6.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
OPMODE_CFG is shown in Figure 18 and described in Table 14.
Return to the Summary Table.
Figure 18. OPMODE_CFG Register
7
6
RESERVED
R-0b
5
4
OSC_SEL
R/W-0b
3
2
1
0
CLK_DIV[3:0]
R/W-0b
Table 14. OPMODE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0b
Reserved. Reads return 0b.
OSC_SEL
R/W
0b
Selects the oscillator for internal timing generation.
4
0b = High speed oscillator.
1b = Low power oscillator.
3-0
CLK_DIV[3:0]
R/W
0b
Sampling speed control. Refer to section on Oscillator and Timing
Control for details.
ADVANCE INFORMATION
7.6.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]
PIN_CFG is shown in Figure 19 and described in Table 15.
Return to the Summary Table.
Figure 19. PIN_CFG Register
7
6
5
4
3
2
1
0
PIN_CFG[7:0]
R/W-0b
Table 15. PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PIN_CFG[7:0]
R/W
0b
Configure device channels CH7 through CH0 as analog input or
GPIO.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.
7.6.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPIO_CFG is shown in Figure 20 and described in Table 16.
Return to the Summary Table.
Figure 20. GPIO_CFG Register
7
6
5
4
3
2
1
0
GPIO_CFG[7:0]
R/W-0b
Table 16. GPIO_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPIO_CFG[7:0]
R/W
0b
Configure GPIO7 through GPIO0 as either digital input or digital
output.
0b = GPIO is digital input.
1b = GPIO is digital output.
22
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7.6.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_DRIVE_CFG is shown in Figure 21 and described in Table 17.
Return to the Summary Table.
Figure 21. GPO_DRIVE_CFG Register
7
6
5
4
3
GPO_DRIVE_CFG[7:0]
R/W-0b
2
1
0
Table 17. GPO_DRIVE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_DRIVE_CFG[7:0]
R/W
0b
Configure digital outputs GPO7 through GPO0 as open-drain or
push-pull output.
0b = Digital output is open-drain. Connect external pullup.
1b = Digital output is push-pull.
ADVANCE INFORMATION
7.6.9 GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
GPO_OUTPUT_VALUE is shown in Figure 22 and described in Table 18.
Return to the Summary Table.
Figure 22. GPO_OUTPUT_VALUE Register
7
6
5
4
3
GPO_OUTPUT_VALUE[7:0]
R/W-0b
2
1
0
Table 18. GPO_OUTPUT_VALUE Register Field Descriptions
Bit
Field
Type
7-0
GPO_OUTPUT_VALUE[7: R/W
0]
Reset
Description
0b
Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.
7.6.10 GPI_VALUE_LSB Register (Address = 0xD) [reset = 0x0]
GPI_VALUE_LSB is shown in Figure 23 and described in Table 19.
Return to the Summary Table.
Figure 23. GPI_VALUE_LSB Register
7
6
5
4
3
GPI_VALUE[7:0]
R-0b
2
1
0
Table 19. GPI_VALUE_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPI_VALUE[7:0]
R
0b
Readback the logic level on digital input.
0b = Digital input is at logic 0.
1b = Digital input is at logic 1.
7.6.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
SEQUENCE_CFG is shown in Figure 24 and described in Table 20.
Return to the Summary Table.
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Figure 24. SEQUENCE_CFG Register
7
6
RESERVED
R-0b
5
4
SEQ_START
R/W-0b
3
2
RESERVED
R-0b
1
0
SEQ_MODE[1:0]
R/W-0b
Table 20. SEQUENCE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0b
Reserved. Reads return 0b.
4
SEQ_START
R/W
0b
Sequence start control when using auto sequence mode.
0b = Stop auto sequencing.
1b = Start auto sequencing from first enabled analog input channel
starting from channel ID = 0 (ascending order).
3-2
RESERVED
R
0b
Reserved. Reads return 0b.
1-0
SEQ_MODE[1:0]
R/W
0b
Selects the mode of scanning analog input channels.
0b = Manual sequence mode.
1b = Auto sequence mode.
10b = Reserved.
ADVANCE INFORMATION
11b = Reserved.
7.6.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
CHANNEL_SEL is shown in Figure 25 and described in Table 21.
Return to the Summary Table.
Figure 25. CHANNEL_SEL Register
7
6
5
4
3
RESERVED
R-0b
2
1
MANUAL_CHID[3:0]
R/W-0b
0
Table 21. CHANNEL_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0b
Reserved. Reads return 0b.
3-0
MANUAL_CHID[3:0]
R/W
0b
In manual mode, this field contains the 4-bit channel ID of the analog
input channel for next ADC conversion. For valid ADC data, the
channel ID must not be configured as GPIO.
0b = CH0
1b = CH5
10b = CH6
11b = CH3
100b = CH4
111b = CH7
1000b = Reserved.
7.6.13 AUTO_SEQ_CHSEL Register (Address = 0x12) [reset = 0x0]
AUTO_SEQ_CHSEL is shown in Figure 26 and described in Table 22.
Return to the Summary Table.
Figure 26. AUTO_SEQ_CHSEL Register
7
24
6
5
4
3
AUTO_SEQ_CHSEL[7:0]
R/W-0b
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2
1
0
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Table 22. AUTO_SEQ_CHSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
AUTO_SEQ_CHSEL[7:0]
R/W
0b
Enable analog input channels AIN7 through AIN0 in auto sequencing
mode.
0b = Analog input channel is not enabled in scanning sequence.
ADVANCE INFORMATION
1b = Analog input channel is enabled in scanning sequence.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing the input driver circuit, reference driver circuit, and provides
some application circuits designed for the TLA2528.
8.2 Typical Applications
8.2.1 Mixed-Channel Configuration
ADVANCE INFORMATION
Digital Output (open-drain)
Digital Output (push-pull)
Analog Input
Analog Input
Analog Input
Analog Input
AVDD (VREF)
I2C
Device
Controller
Digital Input
Digital Input
Figure 27. DAQ Circuit: Single-Supply DAQ
8.2.1.1 Design Requirements
The goal of this application is to configure some channels of the TLA2528 as digital inputs, open-drain digital
outputs, and push-pull digital outputs.
8.2.1.2 Detailed Design Procedure
The TLA2528 can support GPIO functionality at each input pin. Any analog input pin can be independently
configured as a digital input, a digital open-drain output, or a digital push-pull output though the PIN_CFG and
GPIO_CFG registers; see Table 3.
8.2.1.2.1 Digital Input
The digital input functionality can be used to monitor a signal within the system. Figure 28 illustrates that the
state of the digital input can be read from the GPI_VALUE register.
26
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Typical Applications (continued)
ADC
From input device
AVDD
GPIx
SW
GPIx
8.2.1.2.2 Digital Open-Drain Output
The channels of the TLA2528 can be configured as digital open-drain outputs supporting an output voltage up to
5.5 V. An open-drain output, as shown in Figure 29, consists of an internal FET (Q) connected to ground. The
output is idle when not driven by the device, which means Q is off and the pull-up resistor, RPULL_UP, connects
the GPOx node to the desired output voltage. The output voltage can range anywhere up to 5.5 V, depending on
the external voltage that the GPIOx is pulled up to. When the device is driving the output, Q turns on, thus
connecting the pull-up resistor to ground and bringing the node voltage at GPOx low.
VPULL_UP
Receiving Device
ADC
RPULL_UP
GPOx
ILOAD
Q
Figure 29. Digital Open-Drain Output
The minimum value of the pullup resistor, as calculated in Equation 3, is given by the ratio of VPULL_UP and the
maximum current supported by the device digital output (5 mA).
RMIN = (VPULL_UP / 5 mA)
(3)
The maximum value of the pullup resistor, as calculated in Equation 4, depends on the minimum input current
requirement, ILOAD, of the receiving device driven by this GPIO.
RMAX = (VPULL_UP / ILOAD)
(4)
Select RPULL_UP such that RMIN < RPULL_UP < RMAX.
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ADVANCE INFORMATION
Figure 28. Digital Input
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Typical Applications (continued)
8.2.1.3 Digital Push-Pull Output
The channels of the TLA2528 can be configured as digital push-pull outputs supporting an output voltage up to
AVDD. As shown in Figure 30, a push-pull output consists of two mirrored opposite bipolar transistors, Q1 and
Q2. The device can both source and sink current because only one transistor is on at a time (either Q2 is on and
pulls the output low, or Q1 is on and sets the output high). A push-pull configuration always drives the line
opposed to an open-drain output where the line is left floating.
ADC
AVDD
Q1
GPOx
Digital
output
Q2
ADVANCE INFORMATION
Figure 30. Digital Push-Pull Output
9 Power Supply Recommendations
9.1 AVDD and DVDD Supply Recommendations
The TLA2528 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. For supplies greater than 2.35 V, AVDD and DVDD can be shorted externally if
single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device.
Decouple the AVDD and DVDD pins individually, as shown in Figure 31, with 1-µF ceramic decoupling
capacitors. The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If
both supplies are powered from the same source, a minimum capacitor value of 220 nF is required for
decoupling.
AVDD
AVDD
1 PF
GND
1 PF
DVDD
DVDD
Figure 31. Power-Supply Decoupling
28
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10 Layout
10.1 Layout Guidelines
Figure 32 shows a board layout example for the TLA2528. Avoid crossing digital lines with the analog signal path
and keep the analog input signals and the AVDD supply away from noise sources.
Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply
pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to
the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference
voltage for the TLA2528. Place the decoupling capacitor (CREF) for AVDD close to the device AVDD and GND
pins and connect CREF to the device pins with thick copper tracks.
ADVANCE INFORMATION
DVDD
GND
ADDR
NC
10.2 Layout Example
SCL
DECAP
SDA
AVDD
AIN/GPIO
Figure 32. Example Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
ADVANCE INFORMATION
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
ADVANCE INFORMATION
3.1
2.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
1.68 0.07
(0.1) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
16
SYMM
16X
13
0.30
0.18
0.1
0.05
C A B
0.5
0.3
4219117/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
17
ADVANCE INFORMATION
(2.8)
(0.58)
TYP
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219117/A 09/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.55)
16
13
16X (0.6)
1
ADVANCE INFORMATION
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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29-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLA2528IRTER
PREVIEW
WQFN
RTE
16
3000
TBD
Call TI
Call TI
-40 to 85
TLA2528IRTET
PREVIEW
WQFN
RTE
16
250
TBD
Call TI
Call TI
-40 to 85
XTLA2528IRTER
ACTIVE
WQFN
RTE
16
3000
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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