Texas Instruments | ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) | Datasheet | Texas Instruments ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) Datasheet

Texas Instruments ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) Datasheet
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ADC12DJ5200RF
SLVSEN9 – APRIL 2019
1 Features
3 Description
•
The ADC12DJ5200RF device is an RF-sampling,
giga-sample, analog-to-digital converter (ADC) that
can directly sample input frequencies from DC to
above 10 GHz. ADC12DJ5200RF can be configured
as a dual-channel, 5.2 GSPS ADC or single-channel,
10.4 GSPS ADC. These operating modes allow
programmable tradeoffs in channel count and Nyquist
bandwidth allows for flexible hardware that meets the
needs of multiple applications. Useable input
frequency range of up to 10 GHz enables direct RF
sampling of L-band, S-band, C-band, and X-band for
frequency agile systems.
1
•
•
•
•
•
•
•
•
ADC core:
– 12-bit resolution
– Up to 10.4 GSPS in single-channel mode
– Up to 5.2 GSPS in dual-channel mode
Performance specifications:
– Noise floor (–20 dBFS, VFS = 1.0 VPP-DIFF):
– Dual-channel mode: –151.8 dBFS/Hz
– Single-channel mode: –154.4 dBFS/Hz
– ENOB (dual channel, FIN = 2.4 GHz): 8.6 Bits
Buffered analog inputs with VCMI of 0 V:
– Analog input bandwidth (–3 dB): 8.0 GHz
– Usable input frequency range: > 10 GHz
– Full-scale input voltage (VFS, default): 0.8 VPP
Noiseless aperture delay (TAD) adjustment:
– Precise sampling control: 19-fs Step
– Simplifies synchronization and interleaving
– Temperature and voltage invariant delays
Easy-to-use synchronization features:
– Automatic SYSREF timing calibration
– Timestamp for sample marking
JESD204C serial data interface:
– Maximum lane rate: 17.16 Gbps
– Support for 64B/66B and 8B/10B encoding
– 8B/10B modes are JESD204B compatible
Optional digital down-converters (DDC):
– 4x and 8x complex decimation
– Four independent 32-Bit NCOs per DDC
Power consumption: 4.0 W
Power supplies: 1.1 V, 1.9 V
The ADC12DJ5200RF uses a high-speed JESD204C
output interface with up to 16 serialized lanes
supporting up to 17.16 Gbps line rate. Deterministic
latency and multi-device synchronization is supported
through JESD204C subclass-1. The JESD204C
interface can be configured to trade-off line rate and
number of lanes. Both 8B/10B and 64B/66B data
encoding schemes are supported. 64b/66b encoding
supports forward error correction (FEC) for improved
bit error rates. The interface is backwards compatible
with JESD204B receivers when using 8B/10B
encoding modes.
Innovative
synchronization
features,
including
noiseless aperture delay (TAD) adjustment and
SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters
(DDCs) are available to provide digital conversion to
baseband and to reduce the interface rate.
Device Information(1)
PART NUMBER
PACKAGE
ADC12DJ5200RF
BODY SIZE (NOM)
FCBGA (144) 10.00 mm × 10.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
ADC12DJ5200RF Block Diagram
2 Applications
NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD
•
•
•
•
•
•
Oscilloscopes and wideband digitizers
Communications testers (802.11ad, 5G)
Electronic warfare (SIGINT, ELINT)
Satellite communications (SATCOM)
RF-sampling software-defined radio (SDR)
Spectrometry
SCLK
SDI
SDO
SCS\
SPI Registers and
Device Control
TMSTP+
INA+
DA0+
DA0-
Crossbar MUX
or Interleaving
TMSTPInput
MUX
JESD204C
Link A
ADC A
INA-
DA7+
DA7-
Digital Down
Converter (DDC)
Block
Overrange
SYNCSE\
DDC Options:
DDC Bypass
Decimate-by-4
Decimate-by-8
INB+
DB0+
DB0-
INBInput
MUX
JESD204C
Link B
ADC B
DB7+
DB7-
Aperture
Delay Adjust
CLK+
Clock Distribution
and Synchronization
CLK-
SYSREF+
SYSREF-
JMODE
Status
Indicators
SYSREF
Windowing
TDIODE+
ORA0
ORA1
ORB0
ORB1
CALSTAT
TDIODE-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel,
12-bit, RF-Sampling Analog-to-Digital Converter (ADC)
ADC12DJ5200RF
SLVSEN9 – APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.5 Programming........................................................... 79
7.6 SPI_Register_Map Registers.................................. 81
1
1
1
2
3
8
8
8.1 Application Information.......................................... 127
8.2 Typical Applications ............................................. 127
8.3 Initialization Set Up .............................................. 131
9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
ADVANCE INFORMATION
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 9
Thermal Information .................................................. 9
Electrical Characteristics: DC Specifications .......... 10
Electrical Characteristics: Power Consumption ...... 12
Electrical Characteristics: AC Specifications (DualChannel Mode) ........................................................ 13
6.8 Electrical Characteristics: AC Specifications (SingleChannel Mode) ........................................................ 18
6.9 Timing Requirements .............................................. 24
6.10 Switching Characteristics ...................................... 26
7
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Power Supply Recommendations.................... 131
9.1 Power Sequencing ................................................ 133
10 Layout................................................................. 133
10.1 Layout Guidelines ............................................... 133
10.2 Layout Example .................................................. 135
11 Device and Documentation Support ............... 138
11.1 Device Support ..................................................
11.2 Documentation Support ......................................
11.3 Receiving Notification of Documentation
Updates..................................................................
11.4 Community Resources........................................
11.5 Trademarks .........................................................
11.6 Electrostatic Discharge Caution ..........................
11.7 Glossary ..............................................................
Detailed Description ............................................ 30
7.1
7.2
7.3
7.4
Application and Implementation ...................... 127
30
31
32
60
138
138
139
139
139
139
139
12 Mechanical, Packaging, and Orderable
Information ......................................................... 139
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
April 2019
*
Initial release.
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SLVSEN9 – APRIL 2019
5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
A
AGND
AGND
AGND
INA+
INA±
AGND
AGND
DA3+
DA3±
DA2+
DA2±
DGND
B
TMSTP+
AGND
AGND
AGND
AGND
AGND
AGND
DA7+
DA7±
DA6+
DA6±
DGND
C
TMSTP±
SYNCSE
BG
VA19
VA11
AGND
NCOA0
ORA0
VD11
VD11
DA5+
DA1+
D
AGND
VA11
VA11
VA19
VA11
AGND
NCOA1
ORA1
DGND
DGND
DA5±
DA1±
E
AGND
VA19
VA19
VA19
VA11
AGND
CALTRIG
SCS
VD11
VD11
DA4+
DA0+
F
CLK+
AGND
AGND
VA19
VA11
AGND
CALSTAT
SCLK
DGND
DGND
DA4±
DA0±
G
CLK±
AGND
AGND
VA19
VA11
AGND
VD11
SDI
DGND
DGND
DB4±
DB0±
H
AGND
VA19
VA19
VA19
VA11
AGND
VD11
SDO
VD11
VD11
DB4+
DB0+
J
AGND
VA11
VA11
VA19
VA11
AGND
NCOB1
ORB1
DGND
DGND
DB5±
DB1±
K
SYSREF+
TDIODE+
TDIODE±
VA19
VA11
PD
NCOB0
ORB0
VD11
VD11
DB5+
DB1+
L
SYSREF±
AGND
AGND
AGND
AGND
AGND
AGND
DB7+
DB7±
DB6+
DB6±
DGND
M
AGND
AGND
AGND
INB+
INB±
AGND
AGND
DB3+
DB3±
DB2+
DB2±
DGND
ADVANCE INFORMATION
AAV Package
144-Ball Flip Chip BGA
Top View
Not to scale
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3
ADC12DJ5200RF
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Pin Functions
PIN
I/O
DESCRIPTION
ADVANCE INFORMATION
NAME
NO.
AGND
A1, A2, A3,
A6, A7, B2,
B3, B4, B5,
B6, B7, C6,
D1, D6, E1,
E6, F2, F3,
F6, G2, G3,
G6, H1, H6,
J1, J6, L2, L3,
L4, L5, L6, L7,
M1, M2, M3,
M6, M7
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
BG
C3
O
Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited
capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be
left disconnected if not used.
CALSTAT
F7
O
Foreground calibration status output or device alarm output. Functionality is programmed through
CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALTRIG
E7
I
Foreground calibration trigger input. This pin is only used if hardware calibration triggering is
selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG.
Tie this pin to GND if not used.
CLK+
F1
I
Device (sampling) clock positive input. The clock signal is strongly recommended to be ACcoupled to this input for best performance. In single-channel mode, the analog input signal is
sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled
on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination
and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN
is set to 0.
CLK–
G1
I
Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best
performance.
DA0+
E12
O
High-speed serialized data output for channel A, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA0–
F12
O
High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left
disconnected if not used.
DA1+
C12
O
High-speed serialized data output for channel A, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA1–
D12
O
High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left
disconnected if not used.
DA2+
A10
O
High-speed serialized-data output for channel A, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA2–
A11
O
High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left
disconnected if not used.
DA3+
A8
O
High-speed serialized-data output for channel A, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA3–
A9
O
High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left
disconnected if not used.
DA4+
E11
O
High-speed serialized data output for channel A, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA4–
F11
O
High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left
disconnected if not used.
DA5+
C11
O
High-speed serialized data output for channel A, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA5–
D11
O
High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left
disconnected if not used.
4
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Pin Functions (continued)
I/O
DESCRIPTION
NO.
DA6+
B10
O
High-speed serialized data output for channel A, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA6–
B11
O
High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left
disconnected if not used.
DA7+
B8
O
High-speed serialized data output for channel A, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DA7–
B9
O
High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left
disconnected if not used.
DB0+
H12
O
High-speed serialized data output for channel B, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB0–
G12
O
High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left
disconnected if not used.
DB1+
K12
O
High-speed serialized data output for channel B, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB1–
J12
O
High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left
disconnected if not used.
DB2+
M10
O
High-speed serialized data output for channel B, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB2–
M11
O
High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left
disconnected if not used.
DB3+
M8
O
High-speed serialized data output for channel B, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB3–
M9
O
High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left
disconnected if not used.
DB4+
H11
O
High-speed serialized data output for channel B, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB4–
G11
O
High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left
disconnected if not used.
DB5+
K11
O
High-speed serialized data output for channel B, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB5–
J11
O
High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left
disconnected if not used.
DB6+
L10
O
High-speed serialized data output for channel B, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB6–
L11
O
High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left
disconnected if not used.
DB7+
L8
O
High-speed serialized data output for channel B, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used.
DB7–
L9
O
High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left
disconnected if not used.
DGND
A12, B12, D9,
D10, F9, F10,
G9, G10, J9,
J10, L12, M12
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
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ADVANCE INFORMATION
PIN
NAME
5
ADC12DJ5200RF
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
INA+
A4
I
Channel A analog input positive connection. INA± is recommended for use in single channel
mode for optimal performance. The differential full-scale input voltage is determined by the
FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is
terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is
typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used.
INA–
A5
I
Channel A analog input negative connection. INA± is recommended for use in single channel
mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated
to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
INB+
M4
I
Channel B analog input positive connection. INA± is recommended for use in single channel
mode for optimal performance. The differential full-scale input voltage is determined by the
FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is
terminated to ground through a 50-Ω termination resistor. The input common-mode voltage must
typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used.
INB–
M5
I
Channel B analog input negative connection. INA± is recommended for use in single channel
mode for optimal performance. See INB+ for detailed description. This input is terminated to
ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
ADVANCE INFORMATION
NCOA0
C7
I
LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible
four NCOs, is used for digital mixing when using a complex output JMODE. The remaining
unselected NCOs continue to run to maintain phase coherency and can be swapped in by
changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous
input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more
information. Tie this pin to GND if not used.
NCOA1
D7
I
MSB of NCO selection control for DDC A. Tie this pin to GND if not used.
NCOB0
K7
I
LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible
four NCOs, is used for digital mixing when using a complex output JMODE. The remaining
unselected NCOs continue to run to maintain phase coherency and can be swapped in by
changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous
input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more
information. Tie this pin to GND if not used.
NCOB1
J7
I
MSB of NCO selection control for DDC B. Tie this pin to GND if not used.
O
Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
O
Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
O
Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
ORA0
ORA1
ORB0
C8
D8
K8
ORB1
J8
O
Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
PD
K6
I
This pin disables all analog circuits and serializer outputs when set high for temperature diode
calibration or to reduce power consumption when the device is not being used. Tie this pin to
GND if not used.
SCLK
F8
I
Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial
programming data in and out. The Using the Serial Interface section describes the serial interface
in more detail. Supports 1.1-V and 1.8-V CMOS levels.
SCS
E8
I
Serial interface chip select active low input. The Using the Serial Interface section describes the
serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ
pullup resistor to VD11.
SDI
G8
I
Serial interface data input. The Using the Serial Interface section describes the serial interface in
more detail. Supports 1.1-V and 1.8-V CMOS levels.
6
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Pin Functions (continued)
NO.
SDO
H8
SYNCSE
C2
I/O
DESCRIPTION
O
Serial interface data output. The Using the Serial Interface section describes the serial interface
in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V
CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
I
Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize
the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do
not use the SYNC signal for initialization, however it may be used for NCO synchronization.
When toggled low in 8B/10B modes this input initiates code group synchronization (see the Code
Group Synchronization (CGS) section). After code group synchronization, this input must be
toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence
(ILAS) section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and
using TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is
used as the JESD204C SYNC signal.
SYSREF+
K1
I
The SYSREF positive input is used to achieve synchronization and deterministic latency across
the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal
untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is
set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination
changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled
when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when
SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode
voltage range provided in the Recommended Operating Conditions table.
SYSREF–
L1
I
SYSREF negative input
TDIODE+
K2
I
Temperature diode positive (anode) connection. An external temperature sensor can be
connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin
can be left disconnected if not used.
TDIODE–
K3
I
Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
TMSTP+
B1
I
Timestamp input positive connection or differential JESD204C SYNC positive connection. This
input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1.
This differential input is used as the JESD204C SYNC signal input when SYNC_SEL is set 1.
This input can be used as both a timestamp and differential SYNC input at the same time,
allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low
signaling when used as a JESD204C SYNC. For additional usage information, see the
Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to
TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when
TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin
(TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin
is not self-biased and therefore must be externally biased for both AC- and DC-coupled
configurations. The common-mode voltage must be within the range provided in the
Recommended Operating Conditions table when both AC and DC coupled. This pin can be left
disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC
and timestamp is not required.
TMSTP–
C1
I
Timestamp input positive connection or differential JESD204C SYNC negative connection. This
pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for
JESD204C SYNC and timestamp is not required.
VA11
C5, D2, D3,
D5, E5, F5,
G5, H5, J2,
J3, J5, K5
I
1.1-V analog supply
VA19
C4, D4, E2,
E3, E4, F4,
G4, H2, H3,
H4, J4, K4
I
1.9-V analog supply
VD11
C9, C10, E9,
E10, G7, H7,
H9, H10, K9,
K10
I
1.1-V digital supply
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ADVANCE INFORMATION
PIN
NAME
7
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage range
VGND
Voltage between AGND and DGND
MIN
MAX
VA19 (2)
–0.3
2.35
VA11 (2)
–0.3
1.32
VD11 (3)
–0.3
1.32
–1.32
1.32
Voltage between VD11 and VA11
VPIN
Pin voltage range
–0.1
0.1
DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–,
TMSTP+, TMSTP– (3)
–0.5
VD11 +
0.5 (4)
CLK+, CLK–, SYSREF+, SYSREF– (2)
–0.5
VA11 +
0.5 (5)
BG, TDIODE+, TDIODE– (2)
–0.5
VA19 +
0.5 (6)
–1
1
–0.5
VA19 +
0.5 (6)
INA+, INA–, INB+, INB– (2)
ADVANCE INFORMATION
CALSTAT, CALTRIG, NCOA0, NCOA1,
NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1,
PD, SCLK, SCS, SDI, SDO, SYNCSE (2)
UNIT
V
V
V
IMAX(ANY)
Peak input current (any input except INA+, INA–, INB+, INB–)
–25
25
mA
IMAX(INx)
Peak input current (INA+, INA–, INB+, INB–)
–50
50
mA
16.4
dBm
100
mA
150
°C
150
°C
Single-ended with ZS-SE = 50 Ω or differential
with ZS-DIFF = 100 Ω
PMAX(INx)
Peak RF input power (INA+, INA–, INB+, INB–)
IMAX(ALL)
Peak total input current (sum of absolute value of all currents forced in or out, not including powersupply current)
Tj
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
(6)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured to AGND.
Measured to DGND.
Maximum voltage not to exceed VD11 absolute maximum rating.
Maximum voltage not to exceed VA11 absolute maximum rating.
Maximum voltage not to exceed VA19 absolute maximum rating.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
8
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
VCMI
Input common-mode voltage
VID
Input voltage, peak-to-peak differential
NOM
MAX
1.8
1.9
2.0
VA11, analog 1.1-V supply (1)
1.05
1.1
1.15
VD11, digital 1.1-V supply (2)
1.05
1.1
1.15
INA+, INA–, INB+, INB– (1)
–50
0
100
CLK+, CLK–, SYSREF+, SYSREF– (1) (3)
0
0.3
0.55
TMSTP+, TMSTP– (2) (4)
0
0.3
0.55
0.4
1.0
2.0
CLK+ to CLK–, SYSREF+ to SYSREF–,
TMSTP+ to TMSTP–
High-level input voltage
CALTRIG, NCOA0, NCOA1, NCOB0,
NCOB1, PD, SCLK, SCS, SDI, SYNCSE (1)
VIL
Low-level input voltage
CALTRIG, NCOA0, NCOA1, NCOB0,
NCOB1, PD, SCLK, SCS, SDI, SYNCSE (1)
IC_TD
Temperature diode input current
TDIODE+ to TDIODE–
CL
BG maximum load capacitance
IO
BG maximum output current
DC
Input clock duty cycle
TA
Operating free-air temperature
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
(6)
V
mV
V
VPP-DIFF
1.0 (5)
INA+ to INA–, INB+ to INB–
VIH
UNIT
0.7
V
0.45
V
100
30%
50%
–40
–65
µA
50
pF
100
µA
70%
85
°C
125 (6)
°C
150
°C
Measured to AGND.
Measured to DGND.
TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input
common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which case,
the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN =
0 or DC-coupled with TMSTP_LVPECL_EN= 1.
The ADC output code saturates when VID for INA± or INB± exceeds the programmed full-scale voltage(VFS) set by FS_RANGE_A for
INA± or FS_RANGE_B for INB±.
Prolonged use above junction temperature of 105°C may increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADC12DJ5200RF
THERMAL METRIC (1)
AAV (FCBGA)
UNIT
144 PINS
RθJA
Junction-to-ambient thermal resistance
23.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.8
°C/W
RθJB
Junction-to-board thermal resistance
8.4
°C/W
ψJT
Junction-to-top characterization parameter
0.23
°C/W
ψJB
Junction-to-board characterization parameter
8.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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9
ADVANCE INFORMATION
VDD
MIN
VA19, analog 1.9-V supply (1)
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SLVSEN9 – APRIL 2019
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6.5 Electrical Characteristics: DC Specifications
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
DNL
Differential nonlinearity
INL
Integral nonlinearity
Resolution with no missing codes
12
Maximum positive excursion from ideal step size
0.7
Maximum negative excursion from ideal step size
–0.3
Bits
LSB
Maximum positive excursion from ideal transfer
function
2.0
LSB
Maximum negative excursion from ideal transfer
function
–2.0
LSB
CAL_OS = 0
±2.0
mV
CAL_OS = 1
±0.3
mV
±55
mV
ANALOG INPUTS (INA+, INA–, INB+, INB–)
ADVANCE INFORMATION
VOFF
Offset error
VOFF_ADJ
Input offset voltage adjustment
range
Available offset correction range (see OS_CAL or
OADJ_x_INx)
VOFF_DRIFT
Offset drift
Foreground calibration at nominal temperature
only
23
Foreground calibration at each temperature
Default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000)
Analog differential input full-scale
range
VFS
Maximum full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xFFFF)
750
800
1000
1040
Minimum full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0x2000)
VFS_DRIFT
Analog differential input full-scale
range drift
480
Default FS_RANGE_A and FS_RANGE_B setting,
foreground calibration at nominal temperature
only, inputs driven by a 50-Ω source, includes
effect of RIN drift
–0.01
Default FS_RANGE_A and FS_RANGE_B setting,
foreground calibration at each temperature, inputs
driven by a 50-Ω source, includes effect of RIN drift
0.03
VFS_MATCH
Analog differential input full-scale
range matching
Matching between INA± and INB±, default setting,
dual-channel mode
RIN
Single-ended input resistance to
AGND
Each input pin is terminated to AGND, measured
at TA = 25°C
RIN_TEMPCO
Input termination linear
temperature coefficient
CIN
Single-ended input capacitance
µV/°C
0
850
mVPP
500
%/°C
0.625%
48
50
17.6
Single-channel mode measured at DC
0.4
Dual-channel mode measured at DC
0.4
52
Ω
mΩ/°C
pF
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
ΔVBE
10
Temperature diode voltage slope
Forced forward current of 100 µA. Offset voltage
(approximately 0.792 V at 0°C) varies with process
and must be measured for each part. Offset
measurement must be done with the device
unpowered or with the PD pin asserted to
minimize device self-heating.
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–1.6
mV/°C
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Electrical Characteristics: DC Specifications (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BAND-GAP VOLTAGE OUTPUT (BG)
VBG
Reference output voltage
IL ≤ 100 µA
1.1
V
VBG_DRIFT
Reference output temperature drift
IL ≤ 100 µA
–64
µV/°C
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
VCM
Internal termination
Input common-mode voltage, selfbiased
100
Ω
Single-ended termination to GND (per pin) with
DEVCLK_LVPECL_EN = 0,
SYSREF_LVPECL_EN = 0, and
TMSTP_LVPECL_EN = 0
50
Self-biasing common-mode voltage for CLK± when
AC-coupled (DEVCLK_LVPECL_EN must be set
to 0)
0.3
Self-biasing common-mode voltage for SYSREF±
when AC-coupled (SYSREF_LVPECL_EN must
be set to 0) and with receiver enabled
(SYSREF_RECV_EN = 1)
0.3
Self-biasing common-mode voltage for SYSREF±
when AC-coupled (SYSREF_LVPECL_EN must
be set to 0) and with receiver disabled
(SYSREF_RECV_EN = 0)
VA11
V
CL_DIFF
Differential input capacitance
Between positive and negative differential input
pins
0.1
pF
CL_SE
Single-ended input capacitance
Each input to ground
0.5
pF
SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
VOD
Differential output voltage, peakto-peak
100-Ω load
VCM
Output common-mode voltage
AC coupled
ZDIFF
Differential output impedance
550
600
650
mVPP-DIFF
120
Ω
VD11 / 2
80
100
V
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
IIH
High-level input current
IIL
Low-level input current
40
CI
Input capacitance
VOH
High-level output voltage
ILOAD = –400 µA
VOL
Low-level output voltage
ILOAD = 400 µA
–40
µA
2
pF
1.65
V
150
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µA
mV
11
ADVANCE INFORMATION
ZT
Differential termination with
DEVCLK_LVPECL_EN = 0,
SYSREF_LVPECL_EN = 0, and
TMSTP_LVPECL_EN = 0
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SLVSEN9 – APRIL 2019
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6.6 Electrical Characteristics: Power Consumption
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADVANCE INFORMATION
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
4.11
W
IVA19
1.9-V analog supply current
935
mA
IVA11
1.1-V analog supply current
837
mA
IVD11
1.1-V digital supply current
1195
mA
PDIS
Power dissipation
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
5.13
W
IVA19
1.9-V analog supply current
936
mA
IVA11
1.1-V analog supply current
845
mA
IVD11
1.1-V digital supply current
2672
mA
PDIS
Power dissipation
5.65
W
IVA19
1.9-V analog supply current
1014
mA
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
12
Power mode 1: JMODE 1 (single-channel
mode, 16 lanes, 8B/10B encoding, DDC
bypassed), foreground calibration
Power mode 2: JMODE 30 (singlechannel mode, 8 lanes, 64B/66B
encoding, DDC bypassed), foreground
calibration
Power mode 3: JMODE 1 (single-channel
mode, 16 lanes, 8B/10B encoding, DDC
bypassed), background calibration
Power mode 4: JMODE 3 (dual-channel
mode, 16 lanes, 8B/10B encoding, DDC
bypassed), background calibration
Power mode 5: JMODE 22 (singlechannel mode, 8 lanes, 8B/10B encoding,
4x decimation), foreground calibration
Power mode 6: JMODE 11 (dual-channel
mode, 8 lanes, 8B/10B encoding, 4x
decimation), foreground calibration
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934
mA
838
mA
1281
mA
4.01
W
1242
mA
1013
mA
1386
mA
5.0
W
1320
mA
1013
mA
1368
mA
845
mA
2563
mA
5.67
W
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 3, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
FPBW
Full-power input bandwidth
(–3 dB) (1)
XTALK
Channel-to-channel
crosstalk
TEST CONDITIONS
MIN
TYP
Foreground calibration
8.1
Background calibration
8.1
Aggressor = 1 GHz, –1 dBFS
–87
Aggressor = 3 GHz, –1 dBFS
–76
Aggressor = 6 GHz, –1 dBFS
–62
Code error rate
Maximum CER, does not include JESD204C interface BER
NOISEDC
DC input noise standard
deviation
No input, foreground calibration, excludes DC offset, includes fixed
interleaving spur (fS / 2 spur)
Noise spectral density,
excludes fixed interleaving
spur (fS / 2 spur)
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
–151.8
NSD
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
–150.3
NF
Noise figure, ZS = 100 Ω
SNR
Signal-to-noise ratio,
excluding DC, HD2 to
HD9, fS / 2, fS / 2 – fIN,
23.2
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
22.7
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
(1)
GHz
dB
Errors/
sample
2.3
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
fIN = 997 MHz
UNIT
10–18
CER
fIN = 347 MHz
MAX
AIN = –1 dBFS
55.1
AIN = –3 dBFS
55.6
AIN = –12 dBFS
56.1
AIN = –3 dBFS, VFS = 1.0 VPP
56.5
AIN = –1 dBFS
54.9
AIN = –3 dBFS
55.4
AIN = –12 dBFS
56.1
AIN = –1 dBFS
54.1
AIN = –3 dBFS
54.8
AIN = –12 dBFS
56.0
AIN = –3 dBFS, VFS = 1.0 VPP
55.8
AIN = –1 dBFS
52.4
AIN = –3 dBFS
53.5
AIN = –12 dBFS
55.7
AIN = –1 dBFS
50.4
AIN = –3 dBFS
51.8
AIN = –12 dBFS
55.3
AIN = –1 dBFS
48.6
AIN = –3 dBFS
50.3
AIN = –12 dBFS
54.8
LSB
dBFS/Hz
dB
ADVANCE INFORMATION
PARAMETER
dBFS
Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB
below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input
bandwidth.
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Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 3, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
SINAD
Signal-to-noise and
distortion ratio, excluding
DC and fS / 2 fixed spurs
fIN = 2397 MHz
ADVANCE INFORMATION
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fIN = 347 MHz
fIN = 997 MHz
ENOB
Effective number of bits,
excluding DC and fS / 2
fixed spurs
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
14
MIN
TYP
AIN = –1 dBFS
54.4
AIN = –3 dBFS
55.3
AIN = –12 dBFS
56.0
AIN = –3 dBFS, VFS = 1.0 VPP
56.0
AIN = –1 dBFS
54.2
AIN = –3 dBFS
54.8
AIN = –12 dBFS
55.8
AIN = –1 dBFS
53.4
AIN = –3 dBFS
54.3
AIN = –12 dBFS
55.9
AIN = –3 dBFS, VFS = 1.0 VPP
55.1
AIN = –1 dBFS
51.3
AIN = –3 dBFS
52.7
AIN = –12 dBFS
55.5
AIN = –1 dBFS
48.6
AIN = –3 dBFS
51.0
AIN = –12 dBFS
55.2
AIN = –1 dBFS
46.2
AIN = –3 dBFS
48.9
AIN = –12 dBFS
54.7
AIN = –1 dBFS
8.7
AIN = –3 dBFS
8.9
AIN = –12 dBFS
9.0
AIN = –3 dBFS, VFS = 1.0 VPP
9.0
AIN = –1 dBFS
8.7
AIN = –3 dBFS
8.8
AIN = -12 dBFS
9.0
AIN = –1 dBFS
8.6
AIN = –3 dBFS
8.7
AIN = –12 dBFS
9.0
AIN = –3 dBFS, VFS = 1.0 VPP
8.9
AIN = –1 dBFS
8.2
AIN = –3 dBFS
8.5
AIN = –12 dBFS
8.9
AIN = –1 dBFS
7.8
AIN = –3 dBFS
8.2
AIN = –12 dBFS
8.9
AIN = –1 dBFS
7.4
AIN = –3 dBFS
7.8
AIN = –12 dBFS
8.8
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MAX
UNIT
dBFS
bits
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Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 3, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
SFDR
Spurious-free dynamic
range, excluding DC and fS /
2 fixed spurs
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
HD2
2nd-order harmonic
distortion
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
MIN
TYP
AIN = –1 dBFS
68
AIN = –3 dBFS
73
AIN = –12 dBFS
76
AIN = –3 dBFS, VFS = 1.0 VPP
71
AIN = –1 dBFS
68
AIN = –3 dBFS
72
AIN = –12 dBFS
73
AIN = –1 dBFS
67
AIN = –3 dBFS
69
AIN = –12 dBFS
74
AIN = –3 dBFS, VFS = 1.0 VPP
71
AIN = –1 dBFS
63
AIN = –3 dBFS
67
AIN = –12 dBFS
72
AIN = –1 dBFS
55
AIN = –3 dBFS
63
AIN = –12 dBFS
76
AIN = –1 dBFS
53
AIN = –3 dBFS
58
AIN = –12 dBFS
74
AIN = –1 dBFS
–76
AIN = –3 dBFS
–76
AIN = –12 dBFS
–82
AIN = –3 dBFS, VFS = 1.0 VPP
–78
AIN = –1 dBFS
–76
AIN = –3 dBFS
–76
AIN = –12 dBFS
–84
AIN = –1 dBFS
–71
AIN = –3 dBFS
–73
AIN = –12 dBFS
–81
AIN = –3 dBFS, VFS = 1.0 VPP
–73
AIN = –1 dBFS
–63
AIN = –3 dBFS
–67
AIN = –12 dBFS
–81
AIN = –1 dBFS
–63
AIN = –3 dBFS
–66
AIN = –12 dBFS
–78
AIN = –1 dBFS
–54
AIN = –3 dBFS
–58
AIN = –12 dBFS
–75
MAX
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Copyright © 2019, Texas Instruments Incorporated
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UNIT
dBFS
ADVANCE INFORMATION
PARAMETER
dBFS
15
ADC12DJ5200RF
SLVSEN9 – APRIL 2019
www.ti.com
Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 3, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
3rd-order harmonic
distortion
HD3
ADVANCE INFORMATION
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
fS / 2 – fIN
fS / 2 – fIN input signal
dependent interleaving spur
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fS / 2
16
fS / 2 fixed interleaving spur,
independent of input signal
MIN
TYP
AIN = –1 dBFS
–68
AIN = –3 dBFS
–77
AIN = –12 dBFS
–88
AIN = –3 dBFS, VFS = 1.0 VPP
–72
AIN = –1 dBFS
–68
AIN = –3 dBFS
–73
AIN = –12 dBFS
–83
AIN = –1 dBFS
–67
AIN = –3 dBFS
–76
AIN = –12 dBFS
–90
AIN = –3 dBFS, VFS = 1.0 VPP
–71
AIN = –1 dBFS
–65
AIN = –3 dBFS
–69
AIN = –12 dBFS
–84
AIN = –1 dBFS
–55
AIN = –3 dBFS
–63
AIN = –12 dBFS
–88
AIN = –1 dBFS
–53
AIN = –3 dBFS
–59
AIN = –12 dBFS
–84
AIN = –1 dBFS
–71
AIN = –3 dBFS
–73
AIN = –12 dBFS
–76
AIN = –3 dBFS, VFS = 1.0 VPP
–71
AIN = –1 dBFS
–70
AIN = –3 dBFS
–72
AIN = –12 dBFS
–73
AIN = –1 dBFS
–69
AIN = –3 dBFS
–69
AIN = –12 dBFS
–74
AIN = –3 dBFS, VFS = 1.0 VPP
–71
AIN = –1 dBFS
–66
AIN = –3 dBFS
–68
AIN = –12 dBFS
–72
AIN = –1 dBFS
–69
AIN = –3 dBFS
–70
AIN = –12 dBFS
–76
AIN = –1 dBFS
–69
AIN = –3 dBFS
–71
AIN = –12 dBFS
–74
AIN = –20 dBFS
Submit Documentation Feedback
–71
MAX
UNIT
dBFS
dBFS
dBFS
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: ADC12DJ5200RF
ADC12DJ5200RF
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SLVSEN9 – APRIL 2019
Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 3, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
SPUR
Worst spur, excluding DC,
HD2, HD3, fS / 2 and fS / 2 fIN spurs
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
f1 = 343 MHz,
f2 = 353 MHz
f1 = 993 MHz,
f2 = 1003 MHz
IMD3
3rd-order intermodulation
distortion
f1 = 2393 MHz,
f2 = 2403 MHz
f1 = 4193 MHz,
f2 = 4203 MHz
f1 = 5993 MHz,
f2 = 6003 MHz
f1 = 7993 MHz,
f2 = 8003 MHz
MIN
TYP
AIN = –1 dBFS
–75
AIN = –3 dBFS
–76
AIN = –12 dBFS
–81
AIN = –3 dBFS, VFS = 1.0 VPP
–76
AIN = –1 dBFS
–74
AIN = –3 dBFS
–74
AIN = –12 dBFS
–80
AIN = –1 dBFS
–73
AIN = –3 dBFS
–75
AIN = –12 dBFS
–79
AIN = –3 dBFS, VFS = 1.0 VPP
–76
AIN = –1 dBFS
–73
AIN = –3 dBFS
–74
AIN = –12 dBFS
–80
AIN = –1 dBFS
–71
AIN = –3 dBFS
–73
AIN = –12 dBFS
–81
AIN = –1 dBFS
–70
AIN = –3 dBFS
–73
AIN = –12 dBFS
–79
AIN = –7 dBFS per tone
–80
AIN = –9 dBFS per tone
–85
AIN = –18 dBFS per tone
–94
AIN = –9 dBFS per tone, VFS = 1.0 VPP
–84
AIN = –7 dBFS per tone
–78
AIN = –9 dBFS per tone
–83
AIN = –18 dBFS per tone
–85
AIN = –7 dBFS per tone
–75
AIN = –9 dBFS per tone
–81
AIN = –18 dBFS per tone
–92
AIN = –9 dBFS per tone, VFS = 1.0 VPP
–79
AIN = –7 dBFS per tone
–70
AIN = –9 dBFS per tone
–77
AIN = –18 dBFS per tone
–91
AIN = –7 dBFS per tone
–63
AIN = –9 dBFS per tone
–69
AIN = –18 dBFS per tone
–92
AIN = –7 dBFS per tone
–50
AIN = –9 dBFS per tone
–57
AIN = –18 dBFS per tone
–87
MAX
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Product Folder Links: ADC12DJ5200RF
UNIT
dBFS
ADVANCE INFORMATION
PARAMETER
dBFS
17
ADC12DJ5200RF
SLVSEN9 – APRIL 2019
www.ti.com
6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), input signal
applied to INA±, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background
calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating
free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
FPBW
Full-power input bandwidth
(–3 dB) (1)
Foreground calibration
7.9
Background calibration
7.9
CER
Code error rate
Maximum CER, does not include JESD204C interface BER
NOISEDC
DC input noise standard
deviation
No input, foreground calibration, excludes DC offset, includes fixed
interleaving spurs (fS / 2 and fS / 4 spurs), OS_CAL enabled
Noise spectral density,
excludes fixed interleaving
spurs (fS / 2 and fS / 4 spur)
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
–154.4
NSD
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
–152.8
NF
Noise figure, ZS = 100 Ω
20.6
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS
20.3
ADVANCE INFORMATION
fIN = 997 MHz
SNR
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
(1)
18
2.7
Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS
fIN = 347 MHz
Signal-to-noise ratio,
excluding DC, HD2 to
HD9, fS / 2, fS / 4, fS / 2 –
fIN, fS / 4 ± fIN
10–18
AIN = –1 dBFS
55.1
AIN = –3 dBFS
55.6
AIN = –12 dBFS
56.2
AIN = –3 dBFS, VFS = 1.0 VPP
56.7
AIN = –1 dBFS
55.0
AIN = –3 dBFS
55.6
AIN = –12 dBFS
56.2
AIN = –1 dBFS
54.1
AIN = –3 dBFS
54.9
AIN = –12 dBFS
56.1
AIN = –3 dBFS, VFS = 1.0 VPP
55.8
AIN = –1 dBFS
52.4
AIN = –3 dBFS
53.6
AIN = –12 dBFS
55.8
AIN = –1 dBFS
50.5
AIN = –3 dBFS
51.9
AIN = –12 dBFS
55.5
AIN = –1 dBFS
48.6
AIN = –3 dBFS
50.3
AIN = –12 dBFS
55.0
MAX
UNIT
GHz
Errors/
sample
LSB
dBFS/Hz
dB
dBFS
Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB
below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input
bandwidth.
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SLVSEN9 – APRIL 2019
Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), input signal
applied to INA±, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background
calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating
free-air temperature range provided in the Recommended Operating Conditions table
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
SINAD
Signal-to-noise and
distortion ratio, excluding
DC and fS / 2 fixed spurs
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fIN = 347 MHz
fIN = 997 MHz
ENOB
Effective number of bits,
excluding DC and fS / 2
fixed spurs
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
MIN
TYP
AIN = –1 dBFS
53.9
AIN = –3 dBFS
54.8
AIN = –12 dBFS
55.6
AIN = –3 dBFS, VFS = 1.0 VPP
55.5
AIN = –1 dBFS
53.5
AIN = –3 dBFS
54.2
AIN = –12 dBFS
55.5
AIN = –1 dBFS
51.7
AIN = –3 dBFS
53.0
AIN = –12 dBFS
55.3
AIN = –3 dBFS, VFS = 1.0 VPP
54.1
AIN = –1 dBFS
49.4
AIN = –3 dBFS
51.1
AIN = –12 dBFS
54.6
AIN = –1 dBFS
47.6
AIN = –3 dBFS
50.2
AIN = –12 dBFS
54.6
AIN = –1 dBFS
45.0
AIN = –3 dBFS
47.6
AIN = –12 dBFS
53.7
AIN = –1 dBFS
8.7
AIN = –3 dBFS
8.8
AIN = –12 dBFS
8.9
AIN = –3 dBFS, VFS = 1.0 VPP
8.9
AIN = –1 dBFS
8.6
AIN = –3 dBFS
8.7
AIN = –12 dBFS
8.9
AIN = –1 dBFS
8.3
AIN = –3 dBFS
8.5
AIN = –12 dBFS
8.9
AIN = –3 dBFS, VFS = 1.0 VPP
8.7
AIN = –1 dBFS
7.9
AIN = –3 dBFS
8.2
AIN = –12 dBFS
8.8
AIN = –1 dBFS
7.6
AIN = –3 dBFS
8.0
AIN = –12 dBFS
8.8
AIN = –1 dBFS
7.2
AIN = –3 dBFS
7.6
AIN = –12 dBFS
8.6
MAX
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Product Folder Links: ADC12DJ5200RF
UNIT
dBFS
ADVANCE INFORMATION
PARAMETER
bits
19
ADC12DJ5200RF
SLVSEN9 – APRIL 2019
www.ti.com
Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), input signal
applied to INA±, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background
calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating
free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
SFDR
Spurious free dynamic
range, excluding DC, fS / 4
and fS / 2 fixed spurs
fIN = 2397 MHz
ADVANCE INFORMATION
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
HD2
2nd-order harmonic
distortion
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
20
MIN
TYP
AIN = –1 dBFS
68
AIN = –3 dBFS
70
AIN = –12 dBFS
78
AIN = –3 dBFS, VFS = 1.0 VPP
70
AIN = –1 dBFS
63
AIN = –3 dBFS
65
AIN = –12 dBFS
74
AIN = –1 dBFS
60
AIN = –3 dBFS
62
AIN = –12 dBFS
71
AIN = –3 dBFS, VFS = 1.0 VPP
62
AIN = –1 dBFS
57
AIN = –3 dBFS
59
AIN = –12 dBFS
67
AIN = –1 dBFS
55
AIN = –3 dBFS
58
AIN = –12 dBFS
67
AIN = –1 dBFS
52
AIN = –3 dBFS
54
AIN = –12 dBFS
64
AIN = –1 dBFS
–77
AIN = –3 dBFS
–78
AIN = –12 dBFS
–86
AIN = –3 dBFS, VFS = 1.0 VPP
–79
AIN = –1 dBFS
–81
AIN = –3 dBFS
–78
AIN = –12 dBFS
–84
AIN = –1 dBFS
–70
AIN = –3 dBFS
–73
AIN = –12 dBFS
–84
AIN = –3 dBFS, VFS = 1.0 VPP
–73
AIN = –1 dBFS
–63
AIN = –3 dBFS
–67
AIN = –12 dBFS
–87
AIN = –1 dBFS
–70
AIN = –3 dBFS
–74
AIN = –12 dBFS
–85
AIN = –1 dBFS
–56
AIN = –3 dBFS
–61
AIN = –12 dBFS
–78
Submit Documentation Feedback
MAX
UNIT
dBFS
dBFS
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: ADC12DJ5200RF
ADC12DJ5200RF
www.ti.com
SLVSEN9 – APRIL 2019
Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), input signal
applied to INA±, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background
calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating
free-air temperature range provided in the Recommended Operating Conditions table
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
HD3
3rd-order harmonic
distortion
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
fS / 2 – fIN
fS / 2 – fIN input signal
dependent interleaving spur
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
MIN
TYP
AIN = –1 dBFS
–68
AIN = –3 dBFS
–77
AIN = –12 dBFS
–89
AIN = –3 dBFS, VFS = 1.0 VPP
–72
AIN = –1 dBFS
–68
AIN = –3 dBFS
–77
AIN = –12 dBFS
–85
AIN = –1 dBFS
–67
AIN = –3 dBFS
–75
AIN = –12 dBFS
–95
AIN = –3 dBFS, VFS = 1.0 VPP
–71
AIN = –1 dBFS
–65
AIN = –3 dBFS
–69
AIN = –12 dBFS
–81
AIN = –1 dBFS
–55
AIN = –3 dBFS
–63
AIN = –12 dBFS
–88
AIN = –1 dBFS
–53
AIN = –3 dBFS
–59
AIN = –12 dBFS
–83
AIN = –1 dBFS
–68
AIN = –3 dBFS
–70
AIN = –12 dBFS
–78
AIN = –3 dBFS, VFS = 1.0 VPP
–70
AIN = –1 dBFS
–63
AIN = –3 dBFS
–65
AIN = –12 dBFS
–74
AIN = –1 dBFS
–60
AIN = –3 dBFS
–62
AIN = –12 dBFS
–71
AIN = –3 dBFS, VFS = 1.0 VPP
–62
AIN = –1 dBFS
–57
AIN = –3 dBFS
–59
AIN = –12 dBFS
–67
AIN = –1 dBFS
–55
AIN = –3 dBFS
–58
AIN = –12 dBFS
–67
AIN = –1 dBFS
–52
AIN = –3 dBFS
–54
AIN = –12 dBFS
–64
MAX
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Product Folder Links: ADC12DJ5200RF
UNIT
dBFS
ADVANCE INFORMATION
PARAMETER
dBFS
21
ADC12DJ5200RF
SLVSEN9 – APRIL 2019
www.ti.com
Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), input signal
applied to INA±, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background
calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating
free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
fIN = 347 MHz
fIN = 997 MHz
fIN = 2397 MHz
fS / 4 ± fIN
fS / 4 ± fIN input signal
dependent interleaving spur
ADVANCE INFORMATION
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
fS / 2
fS / 2 fixed interleaving spur,
independent of input signal
fS / 4
fS / 4 fixed interleaving spur,
independent of input signal
AIN = –3 dBFS
–75
AIN = –12 dBFS
–78
AIN = –3 dBFS, VFS = 1.0 VPP
–73
AIN = –1 dBFS
–76
AIN = –3 dBFS
–76
AIN = –12 dBFS
–78
AIN = –1 dBFS
–70
AIN = –3 dBFS
–71
AIN = –12 dBFS
–77
AIN = –3 dBFS, VFS = 1.0 VPP
–71
AIN = –1 dBFS
–68
AIN = –3 dBFS
–69
AIN = –12 dBFS
–76
AIN = –1 dBFS
–71
AIN = –3 dBFS
–72
AIN = –12 dBFS
–77
AIN = –1 dBFS
–68
AIN = –3 dBFS
–70
AIN = –12 dBFS
–77
–69
–70
AIN = –20 dBFS
–67
fIN = 2397 MHz
fIN = 4197 MHz
fIN = 5997 MHz
fIN = 7997 MHz
22
–72
AIN = –20 dBFS, OS_CAL enabled
fIN = 997 MHz
SPUR
TYP
AIN = –20 dBFS, OS_CAL disabled
fIN = 347 MHz
Worst spur, excluding DC,
HD2, HD3, fS / 2, fS / 4, fS /
2 - fIN, and fS / 4 ± fIN
MIN
AIN = –1 dBFS
AIN = –1 dBFS
–76
AIN = –3 dBFS
–75
AIN = –12 dBFS
–80
AIN = –3 dBFS, VFS = 1.0 VPP
–76
AIN = –1 dBFS
–74
AIN = –3 dBFS
–75
AIN = –12 dBFS
–81
AIN = –1 dBFS
–73
AIN = –3 dBFS
–75
AIN = –12 dBFS
–79
AIN = –3 dBFS, VFS = 1.0 VPP
–76
AIN = –1 dBFS
–73
AIN = –3 dBFS
–74
AIN = –12 dBFS
–81
AIN = –1 dBFS
–69
AIN = –3 dBFS
–72
AIN = –12 dBFS
–79
AIN = –1 dBFS
–62
AIN = –3 dBFS
–66
AIN = –12 dBFS
–78
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MAX
UNIT
dBFS
dBFS
dBFS
dBFS
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: ADC12DJ5200RF
ADC12DJ5200RF
www.ti.com
SLVSEN9 – APRIL 2019
Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), input signal
applied to INA±, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background
calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating
free-air temperature range provided in the Recommended Operating Conditions table
TEST CONDITIONS
f1 = 343 MHz,
f2 = 353 MHz
f1 = 993 MHz,
f2 = 1003 MHz
IMD3
3rd-order intermodulation
distortion
f1 = 2393 MHz,
f2 = 2403 MHz
f1 = 4193 MHz,
f2 = 4203 MHz
f1 = 5993 MHz,
f2 = 6003 MHz
f1 = 7993 MHz,
f2 = 8003 MHz
MIN
TYP
AIN = –7 dBFS per tone
–80
AIN = –9 dBFS per tone
–86
AIN = –18 dBFS per tone
–95
AIN = –9 dBFS per tone, VFS = 1.0 VPP
–84
AIN = –7 dBFS per tone
–78
AIN = –9 dBFS per tone
–82
AIN = –18 dBFS per tone
–85
AIN = –7 dBFS per tone
–75
AIN = –9 dBFS per tone
–81
AIN = –18 dBFS per tone
–94
AIN = –9 dBFS per tone, VFS = 1.0 VPP
–79
AIN = –7 dBFS per tone
–70
AIN = –9 dBFS per tone
–77
AIN = –18 dBFS per tone
–91
AIN = –7 dBFS per tone
–63
AIN = –9 dBFS per tone
–70
AIN = –18 dBFS per tone
–93
AIN = –7 dBFS per tone
–50
AIN = –9 dBFS per tone
–57
AIN = –18 dBFS per tone
–86
MAX
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Product Folder Links: ADC12DJ5200RF
UNIT
dBFS
ADVANCE INFORMATION
PARAMETER
23
ADC12DJ5200RF
SLVSEN9 – APRIL 2019
www.ti.com
6.9 Timing Requirements
MIN
NOM
MAX
UNIT
800
5200
MHz
192.3
1250
ps
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
fCLK
Input clock frequency (CLK±), both single-channel and dual-channel modes (1)
tCLK
Input clock period (CLK±), both single-channel and dual-channel modes (1)
SYSREF (SYSREF+, SYSREF–)
tINV(SYSREF)
Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time
violation, as measured by SYSREF_POS status register (2)
48
ps
tINV(TEMP)
Drift of invalid SYSREF capture region over temperature, positive number indicates a
shift toward MSB of SYSREF_POS register
0
ps/°C
tINV(VA11)
Drift of invalid SYSREF capture region over VA11 supply voltage, positive number
indicates a shift toward MSB of SYSREF_POS register
0.36
ps/mV
tSTEP(SP)
Delay of SYSREF_POS LSB
t(PH_SYS)
Minimum SYSREF± assertion duration after SYSREF± rising edge event
4
ns
t(PL_SYS)
Minimum SYSREF± de-assertion duration after SYSREF± falling edge event
1
ns
SYSREF_ZOOM = 0
77
SYSREF_ZOOM = 1
24
ps
JESD204B SYNC TIMING (SYNCSE OR TMSTP±)
ADVANCE INFORMATION
tH(SYNCSE)
(1)
(2)
(3)
24
Minimum hold time from multiframe or extended
multiblock boundary (SYSREF rising edge captured high)
to de-assertion of JESD204B SYNC signal (SYNCSE if
SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO
synchronization (NCO_SYNC_ILA = 1) (3)
JMODE = 0
21
JMODE = 1
17
JMODE = 2
21
JMODE = 3
17
JMODE = 5
9
JMODE = 7
9
JMODE = 10
18
JMODE = 11
9
JMODE = 13
22
JMODE = 14
9
JMODE = 19
9
JMODE = 20
9
JMODE = 21
18
JMODE = 22
9
JMODE = 23
18
JMODE = 24
9
JMODE = 36
16
JMODE = 37
16
JMODE = 38
16
JMODE = 39
20
tCLK cycles
Unless functionally limited to a smaller range in the ADC12DJ5200RF Operating Modes table based on programmed JMODE.
Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and
Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by
tINV(SYSREF), indicates the portion of the CLK± period(tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation.
Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to
find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS,
otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.
This parameter only applies to JMODE settings that use 8B/10B encoding or settings that use 64B/66B encoding and 4x or 8x
decimation. SYNC is not used for 64B/66B encoding modes unless the DDC block and NCOs are used and require synchronization.
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Timing Requirements (continued)
MIN
tSU(SYNCSE)
t(SYNCSE)
Minimum setup time from de-assertion of JESD204B
SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if
SYNC_SEL = 1) to multiframe or extended multiblock
boundary (SYSREF rising edge captured high) for NCO
synchronization (NCO_SYNC_ILA = 1) (3)
NOM
MAX
UNIT
–4
JMODE = 1
0
JMODE = 2
–4
JMODE = 3
0
JMODE = 5
8
JMODE = 7
8
JMODE = 10
–1
JMODE = 11
8
JMODE = 13
–5
JMODE = 14
8
JMODE = 19
8
JMODE = 20
8
JMODE = 21
–1
JMODE = 22
8
JMODE = 23
–1
JMODE = 24
8
JMODE = 36
1
JMODE = 37
1
JMODE = 38
1
JMODE = 39
–3
SYNCSE minimum assertion time to trigger link resynchronization
tCLK cycles
4
Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK)
Serial clock frequency
t(PH)
Serial clock high value pulse duration
32
0
15.625
ns
t(PL)
Serial clock low value pulse duration
32
ns
tSU(SCS)
Setup time from SCS to rising edge of SCLK
25
ns
tH(SCS)
Hold time from rising edge of SCLK to SCS
3
ns
tSU(SDI)
Setup time from SDI to rising edge of SCLK
25
ns
tH(SDI)
Hold time from rising edge of SCLK to SDI
3
ns
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MHz
25
ADVANCE INFORMATION
JMODE = 0
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6.10 Switching Characteristics
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
tAD
Sampling (aperture) delay from the CLK±
rising edge (dual-channel mode) or rising
and falling edge (single-channel mode) to
sampling instant
tTAD(MAX)
Coarse adjustment (TAD_COARSE =
Maximum tAD adjust programmable delay,
0xFF)
not including clock inversion (TAD_INV = 0)
Fine adjustment (TAD_FINE = 0xFF)
tTAD(STEP)
ADVANCE INFORMATION
tAJ
TAD_COARSE = 0x00, TAD_FINE =
0x00, and TAD_INV = 0
Aperture jitter, rms
ps
289
ps
4.9
ps
1.13
ps
Fine adjustment (TAD_FINE)
19
fs
Minimum tAD adjust coarse setting
(TAD_COARSE = 0x00, TAD_INV = 0),
dither disabled (ADC_DITH_EN = 0)
50
fs
Minimum tAD adjust coarse setting
(TAD_COARSE = 0x00, TAD_INV = 0),
dither enabled (ADC_DITH_EN = 1)
70
Coarse adjustment (TAD_COARSE)
tAD adjust programmable delay step size
360
Maximum tAD adjust coarse setting
(TAD_COARSE = 0xFF) excluding
TAD_INV (TAD_INV = 0), dither
disabled (ADC_DITH_EN = 0)
70 (1)
Maximum tAD adjust coarse setting
(TAD_COARSE = 0xFF) excluding
TAD_INV (TAD_INV = 0), dither
enabled (ADC_DITH_EN = 1)
80 (1)
fs
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
fSERDES
Serialized output bit rate
UI
Serialized output unit interval
tTLH
Low-to-high transition time (differential)
20% to 80%, 8H8L test pattern, 21.12
Gbps
tTHL
High-to-low transition time (differential)
20% to 80%, 8H8L test pattern, 21.12
Gbps
DDJ
Data dependent jitter, peak-to-peak
DCD
EBUJ
RJ
TJ
(1)
26
Even-odd jitter, peak-to-peak
Effective bounded uncorrelated jitter, peakto-peak
Unbounded random jitter, RMS
Total jitter, peak-to-peak, with unbounded
random jitter portion defined with respect to
a BER = 1e-15 (Q = 7.94)
1
17.16
Gbps
58.2
1000
ps
20
ps
20
ps
PRBS-7 test pattern, JMODE = 19, 12.8
Gbps
6.04
PRBS-9 test pattern, JMODE = 30,
17.16 Gbps
8.86
PRBS-7 test pattern, JMODE = 19, 12.8
Gbps
TBD
PRBS-9 test pattern, JMODE = 30,
17.16 Gbps
TBD
PRBS-7 test pattern, JMODE = 19, 12.8
Gbps
TBD
PRBS-9 test pattern, JMODE = 30,
17.16 Gbps
TBD
8H8L test pattern, JMODE = 19, 12.8
Gbps
0.98
PRBS-9 test pattern, JMODE = 30,
17.16 Gbps
1.19
PRBS-7 test pattern, JMODE = 19, 12.8
Gbps
21.4
PRBS-9 test pattern, JMODE = 30,
17.16 Gbps
27.6
ps
ps
ps
ps
ps
tAJ increases because of additional attenuation on the internal clock path.
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Switching Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tADC
(2)
Deterministic delay from the CLK± edge
that samples the reference sample to the
CLK± edge that samples SYSREF going
high (2)
JMODE = 0
2.5
JMODE = 1
–9.5
JMODE = 2
2
JMODE = 3
–10
JMODE = 5
–9.5
JMODE = 7
–10
JMODE = 10
179
JMODE = 11
167
JMODE = 13
364
JMODE = 14
356
JMODE = 19
–9.5
JMODE = 20
–10
JMODE = 21
144
JMODE = 22
138
JMODE = 23
215
JMODE = 24
211
JMODE = 30
2.5
JMODE = 31
2
JMODE = 32
2.5
JMODE = 33
2
JMODE = 34
6.5
JMODE = 35
6
JMODE = 36
144
JMODE = 37
179
JMODE = 38
215
JMODE = 39
364
tCLK cycles
tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high
capture point, in which case the total latency is smaller than the delay given by tTX.
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ADVANCE INFORMATION
ADC CORE LATENCY
ADC12DJ5200RF
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Switching Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 347
MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless
otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature
range provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
JESD204C AND SERIALIZER LATENCY
ADVANCE INFORMATION
Delay from the CLK± rising edge that
samples SYSREF high to the first bit of the
multiframe (8B/10B encoding) or extended
multiblock (64B/66B encoding) on the
JESD204C serial output lane
corresponding to the reference sample of
tADC (3)
tTX
JMODE = 0
92
111
JMODE = 1
159
189
JMODE = 2
93
112
JMODE = 3
159
189
JMODE = 5
143
172
JMODE = 7
143
172
JMODE = 10
85
102
JMODE = 11
143
172
JMODE = 13
85
102
JMODE = 14
143
170
JMODE = 19
143
168
JMODE = 20
143
168
JMODE = 21
84
102
JMODE = 22
143
172
JMODE = 23
84
102
JMODE = 24
143
170
JMODE = 30
114
134
JMODE = 31
115
134
JMODE = 32
102
120
JMODE = 33
103
120
JMODE = 34
102
120
JMODE = 35
103
120
JMODE = 36
102
120
JMODE = 37
103
120
JMODE = 38
102
120
JMODE = 39
103
120
tCLK cycles
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD)
Delay from the falling edge of the 16th SCLK cycle during read operation for SDO
transition from tri-state to valid data
t(ODZ)
Delay from the SCS rising edge for SDO transition from valid data to tri-state
t(OD)
Delay from the falling edge of SCLK during read operation to SDO valid
(3)
28
1
1
ns
10
ns
10
ns
The values given for tTX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will vary.
JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver
RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe
clock (LMFC) cycle.
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S1
S2
S0
tAD
tADC
tCLK
CLK+
CLK±
SYSREF+
SYSREF±
tSU(SYSREF)
tH(SYSREF)
tTX
Start of Multi-Frame (8B/10B) or Extended Multiblock (64B/66B)
S0(2)
DA0+/±(1)
(1)
(2)
S1
S2
Only serdes lane DA0+/- is shown, but it is representative of all lanes. The number of output lanes used and bit-packing format is dependent on the
programmed JMODE value.
Samples only shown for ease of understanding. The samples are packed into frames according to the selected JMODE and output as octets from Dxx+/±.
ADVANCE INFORMATION
Figure 1. ADC Timing Diagram
CLK+
CLK±
SYSREF+
SYSREF±
LMFC/LEMC(1)
(Internal)
One multi-frame (8B/10B) or extended
multiblock (64B/66B)
NCO one-time sync event
tH(SYNCSE)
tSU(SYNCSE)
SYNCSE
(SYNC_SEL=0)
TMSTP+/±
(SYNC_SEL=1)
Start of ILAS (8B/10B) or
extended multiblock (64B/66B)
tTX
DA0+/±(2)
(1)
(2)
/R
It is assumed that the internal LMFC/LEMC is aligned with the rising edge of CLK+/- that captures SYSREF+/- high value.
Only serdes lane DA0+/- is shown, but it is representative of all lanes. All lanes will output the ILAS (8B/10B) or the start of the extended multiblock (64B/66B)
at approximately the same point in time. Number of lanes is dependent on the programmed JMODE value.
Figure 2. SYNCSE and TMSTP± Timing Diagram for NCO Synchronization
1st clock
16th clock
24th clock
SCLK
tH(SCS)
tSU(SCS)
t(PH)
t(PL)
tH(SCS)
tSU(SCS)
t(PH) + t(PL) = t(P) = 1 / ¦CLK(SCLK)
SCS
tSU(SDI)
tSU(SDI) tH(SDI)
SDI
D7
D0
Write Command
COMMAND FIELD
SDO
D1
tH(SDI)
t(OD)
Hi-Z
D7
t(OZD)
D1
D0
Read Command
Hi-Z
t(ODZ)
Figure 3. Serial Interface Timing
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7 Detailed Description
7.1 Overview
ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly
sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ5200RF can sample
up to 5.2 GSPS and up to 10.4 GSPS in single-channel mode. Programmable tradeoffs in channel count (dualchannel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets
the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input
bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and singlechannel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes and subclass-1
compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to
17.16 Gbps and can be configured to trade-off bit rate and number of lanes. Both 8B/10B and 64B/66B data
encoding schemes are supported. The 64B/66B encoding schemes support forward error correction (FEC) for
improved bit error rates. The JESD204C interface is backwards compatible with JESD204B receivers when using
8B/10B encoding modes.
ADVANCE INFORMATION
A number of synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF
windowing, simplify system design for multi-channel systems. Aperture delay adjustment can be used to simplify
SYSREF capture, to align the sampling instance between multiple ADCs or to sample an ideal location of a frontend track and hold (T&H) amplifier output. SYSREF windowing offers a simplistic way to measure invalid timing
regions of SYSREF relative to the device clock and then choose an optimal sampling location. Dual-edge
sampling (DES) is implemented in single-channel mode to reduce the maximum clock rate applied to the ADC to
support a wide range of clock sources and relax setup and hold timing for SYSREF capture.
Optional digital down converters (DDCs) are available in both single-channel mode and dual-channel mode to
allow a reduction in interface rate (decimation) and digital mixing of the signal to baseband. Single-channel mode
supports a single DDC while dual-channel mode supports one DDC per channel. The DDC block supports data
decimation of 4x or 8x and alias-free complex output bandwidths of 80% of the effective output data rate.
ADC12DJ5200RF provides foreground and background calibration options for gain, offset and static linearity
errors. Foreground calibration is run at system startup or at specified times during which the ADC is offline and
not sending data to the logic device. Background calibration allows the ADC to run continually while the cores
are calibrated in the background so that the system does not experience downtime. The calibration routine is
also used to match the gain and offset between sub-ADC cores to minimize spurious artifacts from time
interleaving.
30
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7.2 Functional Block Diagram
NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD
SCLK
SDI
SDO
SCS\
SPI Registers and
Device Control
TMSTP+
Input
MUX
JESD204C
Link A
ADC A
INA-
DA7+
DA7-
Digital Down
Converter (DDC)
Block
Overrange
SYNCSE\
DDC Options:
DDC Bypass
Decimate-by-4
Decimate-by-8
INB+
DB0+
DB0-
INBInput
MUX
JESD204C
Link B
ADC B
DB7+
DB7-
Aperture
Delay Adjust
CLK+
Clock Distribution
and Synchronization
CLK-
SYSREF+
SYSREF-
JMODE
Status
Indicators
SYSREF
Windowing
TDIODE+
ORA0
ORA1
ORB0
ORB1
CALSTAT
TDIODE-
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ADVANCE INFORMATION
INA+
DA0+
DA0-
Crossbar MUX
or Interleaving
TMSTP-
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7.3 Feature Description
7.3.1 Device Comparison
The devices listed in Table 1 are part of a pin-to-pin compatible, high-speed, wide-bandwidth ADC family. The
family is offered to provide a scalable family of devices for varying resolution, sampling rate and signal
bandwidth.
Table 1. Device Family Comparison
MAXIMUM
SAMPLING RATE
RESOLUTION
DUAL CHANNEL
DECIMATION
SINGLE CHANNEL
DECIMATION
INTERFACE
(MAX LINERATE)
ADC12DJ5200RF
Single 10.4 GSPS
Dual 5.2 GSPS
12-bit
Complex: 4x, 8x
Complex: 4x, 8x
JESD204B /
JESD204C
(17.16 Gbps)
ADC12DJ3200
Single 6.4 GSPS
Dual 3.2 GSPS
12-bit
Real: 2x
Complex: 4x, 8x, 16x
None
JESD204B
(12.8 Gbps)
ADC08DJ3200
Single 6.4 GSPS
Dual 3.2 GSPS
8-bit
None
None
JESD204B
(12.8 Gbps)
ADC12DJ2700
Single 5.4 GSPS
Dual 2.7 GSPS
12-bit
Real: 2x
Complex: 4x, 8x, 16x
None
JESD204B
(12.8 Gbps)
PART NUMBER
ADVANCE INFORMATION
7.3.2 Analog Inputs
The analog inputs of the ADC12DJ5200RF have internal buffers to enable high input bandwidth and to isolate
sampling capacitor glitch noise from the input circuit. Analog inputs must be driven differentially because
operation with a single-ended signal results in degraded performance. Both AC-coupling and DC-coupling of the
analog inputs is supported. The analog inputs are designed for an input common-mode voltage (VCMI) of 0 V,
which is terminated internally through single-ended, 50-Ω resistors to ground (GND) on each input pin. DCcoupled input signals must have a common-mode voltage that meets the device input common-mode
requirements specified as VCMI in the Recommended Operating Conditions table. The 0-V input common-mode
voltage simplifies the interface to split-supply, fully-differential amplifiers and to a variety of transformers and
baluns. The ADC12DJ5200RF includes internal analog input protection to protect the ADC inputs during
overranged input conditions; see the Analog Input Protection section. Figure 4 provides a simplified analog input
model.
AGND
Analog Input
Protection
Diodes
50
INA+, INB+
ADC
INA±, INB±
Input Buffer
50
Figure 4. ADC12DJ5200RF Analog Input Internal Termination and Protection Diagram
There is minimal degradation in analog input bandwidth when using single-channel mode versus dual-channel
mode. Either analog input (INA+ and INA– or INB+ and INB–) can be used in single-channel mode. The desired
input can be chosen using SINGLE_INPUT in the input mux control register.
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7.3.2.1 Analog Input Protection
The analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of
sourcing or sinking input currents during overrange conditions, see the voltage and current limits in the Absolute
Maximum Ratings table. The overrange protection is also defined for a peak RF input power in the Absolute
Maximum Ratings table, which is frequency independent. Operation above the maximum conditions listed in the
Recommended Operating Conditions table results in an increase in failure-in-time (FIT) rate, so the system must
correct the overdrive condition as quickly as possible. Figure 4 shows the analog input protection diodes.
7.3.2.2 Full-Scale Voltage (VFS) Adjustment
Input full-scale voltage (VFS) adjustment is available, in fine increments, for each analog input through the
FS_RANGE_A register setting (see the INA full-scale range adjust register) and FS_RANGE_B register setting
(see the INB full-scale range adjust register) for INA± and INB±, respectively. The available adjustment range is
specified in the Electrical Characteristics: DC Specifications table. Larger full-scale voltages improve SNR and
noise floor (in dBFS/Hz) performance, but can degrade harmonic distortion. The full-scale voltage adjustment is
useful for matching the full-scale range of multiple ADCs when developing a multi-converter system or for
external interleaving of multiple ADC12DJ5200RFs to achieve higher sampling rates.
The input offset voltage for each input and for each ADC core can be adjusted through SPI registers. The
OADJ_A_FG0_VINx and OADJ_A_FG90_VINx registers (registers 0x344 to 0x34A) are used to adjust ADC core
A's offset voltage when sampling analog input x (where x is A for INA± or B for INB±) where the FG0 register is
used for dual channel mode and FG90 is used for single channel mode. OADJ_B_FG0_VINx is used to adjust
ADC core B's offset voltage when sampling input x. OADJ_B_FG0_VINx applies to both single channel mode
and dual channel mode. To adjust the offset voltage in dual channel mode simply adjust the offset for the ADC
core sampling the desired input. In single channel mode, both ADC core A's offset and ADC core B's offset must
be adjusted together. The difference in the two core's offsets in single channel mode will result in a spur at fS/2
that is independent of the input. These registers can be used to compensate the fS/2 spur in single channel
mode. See the Calibration Modes and Trimming section for more information.
7.3.3 ADC Core
The ADC12DJ5200RF consists of a total of six ADC cores. The cores are interleaved for higher sampling rates
and swapped on-the-fly for calibration as required by the operating mode. This section highlights the theory and
key features of the ADC cores.
7.3.3.1 ADC Theory of Operation
The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or by
the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC converts
the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the voltage on
INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a negative 2's
complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–, respectively, then
the digital output is a positive 2's complement value. Equation 1 can calculate the differential voltage at the input
pins from the digital output.
Code
VIN
V FS
2N
where
•
•
•
Code is the signed decimation output code (for example, –2048 to +2047)
N is the ADC resolution
and VFS is the full-scale input voltage of the ADC as specified in the Recommended Operating Conditions
table, including any adjustment performed by programming FS_RANGE_A or FS_RANGE_B
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33
ADVANCE INFORMATION
7.3.2.3 Analog Input Offset Adjust
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7.3.3.2 ADC Core Calibration
ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be
repeated when operating conditions change significantly, namely temperature, in order to maintain optimal
performance. The ADC12DJ5200RF has a built-in calibration routine that can be run as a foreground operation
or a background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling
the input signal, to complete the process. Background calibration can be used to overcome this limitation and
allow constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on
each mode.
7.3.3.3 Analog Reference Voltage
The reference voltage for the ADC12DJ5200RF is derived from an internal band-gap reference. A buffered
version of the reference voltage is available at the BG pin for user convenience. This output has an outputcurrent capability of ±100 µA. The BG output must be buffered if more current is required. No provision exists for
the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scalerange register settings.
7.3.3.4 ADC Overrange Detection
ADVANCE INFORMATION
To ensure that system gain management has the quickest possible response time, a low-latency configurable
overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the
ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of
the upper 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1.
These thresholds apply to both channel A and channel B in dual-channel mode. Table 2 lists how an ADC
sample is converted to an absolute value for a comparison of the thresholds.
Table 2. Conversion of ADC Sample for Overrange Comparison
ADC SAMPLE
(Offset Binary)
ADC SAMPLE
(2's Complement)
ABSOLUTE VALUE
UPPER 8 BITS USED FOR
COMPARISON
1111 1111 1111 (4095)
0111 1111 1111 (+2047)
111 1111 1111 (2047)
1111 1111 (255)
1000 0000 0000 (2048)
0000 0000 0000 (0)
000 0000 0000 (0)
0000 0000 (0)
0000 0001 0000 (16)
1000 0001 0000 (–2032)
111 1111 0000 (2032)
1111 1110 (254)
0000 0000 0000 (0)
1000 0000 0000 (–2048)
111 1111 1111 (2047)
1111 1111 (255)
If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the
monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is
0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and
the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1
corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold
is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by
monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be
OR'd together to determine whether an overrange condition occurred. OVR_N can be used to set the output
pulse duration from the last overrange event. Table 3 lists the overrange pulse lengths for the various OVR_N
settings (see the overrange configuration register). In decimation modes (only in the JMODEs where CS = 1 in
Table 22), the overrange status is also embedded into the output data samples where the OVR_T0 threshold
status is embedded as the LSB along with the upper 15 bits of every complex I sample and the OVR_T1
threshold status is embedded as the LSB along with the upper 15 bits of every complex Q sample. Table 4 lists
the outputs, related data samples, threshold settings, and the monitoring period equation. The embedded
overrange bit goes high if the associated channel exceeds the associated overrange threshold within the
monitoring period set by OVR_N. Use Table 4 to calculate the monitoring period.
34
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Table 3. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs
OVR_N
OVERRANGE PULSE LENGTH SINCE LAST OVERRANGE
EVENT (DEVCLK Cycles)
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
1024
(1)
OVERRANGE
INDICATOR
ASSOCIATED
THRESHOLD
DECIMATION TYPE
OVERRANGE STATUS
EMBEDDED IN
MONITORING PERIOD
(ADC Samples)
ORA0
OVR_T0
Complex down-conversion
Channel A in-phase (I)
samples
2OVR_N (1)
ORA1
OVR_T1
Complex down-conversion
Channel A quadrature
(Q) samples
2OVR_N (1)
ORB0
OVR_T0
Complex down-conversion
Channel B in-phase (I)
samples
2OVR_N (1)
ORB1
OVR_T1
Complex down-conversion
Channel B quadrature
(Q) samples
2OVR_N (1)
OVR_N is the monitoring period register setting.
Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is
triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set
much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input
signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never
tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of
time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of
the signal is above −12 dBFS).
7.3.3.5 Code Error Rate (CER)
ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle
codes, resulting from metastability caused by non-ideal comparator limitations. The ADC12DJ5200RF uses a
unique ADC architecture that inherently allows significant code error rate improvements from traditional pipelined
flash or successive approximation register (SAR) ADCs. The code error rate of the ADC12DJ5200RF is multiple
orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates
providing significant signal reliability improvements.
7.3.4 Temperature Monitoring Diode
A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE– pins. This diode facilitates
temperature monitoring and characterization of the device in higher ambient temperature environments. Although
the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline
measurement (offset) at a known ambient or board temperature and creating a linear equation with the diode
voltage slope provided in the Electrical Characteristics: DC Specifications table. Perform offset measurement
with the device unpowered or with the PD pin asserted to minimize device self-heating. Recommended
monitoring devices include the LM95233 device and similar remote-diode temperature monitoring products from
Texas Instruments.
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ADVANCE INFORMATION
Table 4. Threshold and Monitoring Period for Embedded Overrange Indicators in Dual-Channel
Decimation Modes
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7.3.5 Timestamp
The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample based
on the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (see the LSB control
bit output register) must be set in order to use the timestamp feature and output the timestamp data. When
enabled, the LSB of the 12-bit ADC digital output reports the status of the TMSTP± input. In effect, the 12-bit
output sample consists of the upper 11-bits of the 12-bit converter and the LSB of the 12-bit output sample is the
output of a parallel 1-bit converter (TMSTP±) with the same latency as the ADC core. In the 8-bit operating
modes, the LSB of the 8-bit output sample is used to output the timestamp status. The trigger must be applied to
the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling clock and is
sampled at approximately the same time as the analog input. Timestamp cannot be used when a JMODE with
decimation is selected and instead SYSREF must be used to achieve synchronization through the JESD204C
subclass-1 method for achieving deterministic latency.
7.3.6 Clocking
The clocking subsystem of the ADC12DJ5200RF has two input signals, device clock (CLK+, CLK–) and SYSREF
(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD
adjust), a clock duty cycle corrector and a SYSREF capture block. Figure 5 describes the clocking subsystem.
ADVANCE INFORMATION
Duty Cycle
Correction
tAD Adjust
Clock Distribution
and Synchronization
(ADC cores, digital,
JESD204C, etc.)
CLK+
E
IN
D_
F
TA
TA
D_
CO
AR
S
TA
D_
I
NV
E
CLK-
SYSREF Capture
SYSREF+
SYSREF Windowing
SYSREF-
SYSREF_POS
SYSREF_SEL
Automatic
SYSREF
Calibration
SRC_EN
Figure 5. ADC12DJ5200RF Clocking Subsystem
The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing
and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within
the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the
device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture
the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment
(tAD adjust) allows the user to shift the sampling instance of the ADC in fine steps in order to synchronize multiple
ADC12DJ5200RFs or to fine-tune system latency. Duty cycle correction is implemented in the ADC12DJ5200RF
to ease the requirements on the external device clock while maintaining high performance. Table 5 summarizes
the device clock interface in dual-channel mode and single-channel mode.
Table 5. Device Clock vs Mode of Operation
36
MODE OF OPERATION
SAMPLING RATE VS fCLK
Dual-channel mode
1 × fCLK
Rising edge
Single-channel mode
2 × fCLK
Rising and falling edge
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SYSREF is a system timing reference used for JESD204C subclass-1 implementations of deterministic latency.
SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be
captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The
ADC12DJ5200RF includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on
the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a
single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division
of, the local multiframe clock frequency in 8B/10B encoding modes or the local extended multiblock clock
frequency in 64B/66B encoding modes. Equation 2 is used to calculate valid SYSREF frequencies in 8B/10B
encoding modes. In 64B/66B modes, the denominator changes to 66 × 32 × E × n, where E is the number of
multiblocks in an extended multiblock.
f SYSREF
R u f CLK
10 u F u K u n
where
R and F are set by the JMODE setting (see Table 22)
fCLK is the device clock frequency (CLK±)
K is the programmed multiframe length (see Table 22 for valid K settings)
and n is any positive integer
(2)
7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
The ADC12DJ5200RF contains a delay adjustment on the device clock (sampling clock) input path, called tAD
adjust, that can be used to shift the sampling instance within the device in order to align sampling instances
among multiple devices or for external interleaving of multiple ADC12DJ5200RFs. Further, tAD adjust can be
used for automatic SYSREF calibration to simplify synchronization; see the Automatic SYSREF Calibration
section. Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path,
however a slight degradation in aperture jitter (tAJ) is possible at large values of TAD_COARSE because of
internal clock path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high
input frequencies (see tAJ in the Switching Characteristics table). This feature is programmed using TAD_INV,
TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the
input clock resulting in a delay equal to half the clock period. Table 6 summarizes the step sizes and ranges of
the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be
used in conjunction. All clocks within the device are shifted by the programmed tAD adjust amount, which results
in a shift of the timing of the JESD204C serialized outputs and affects the capture of SYSREF.
Table 6. tAD Adjust Adjustment Ranges
ADJUSTMENT PARAMETER
ADJUSTMENT STEP
DELAY SETTINGS
TAD_INV
1 / (fCLK × 2)
1
MAXIMUM DELAY
1 / (fCLK × 2)
TAD_COARSE
See tTAD(STEP) in the Switching
Characteristics table
256
See tTAD(MAX) in the Switching
Characteristics table
TAD_FINE
See tTAD(STEP) in the Switching
Characteristics table
256
See tTAD(MAX) in the Switching
Characteristics table
In order to maintain timing alignment between converters, stable and matched power-supply voltages and device
temperatures must be provided.
Aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to
the JESD204C data link. Use TAD_RAMP to reduce the probability of the JESD204C link losing synchronization;
see the Aperture Delay Ramp Control (TAD_RAMP) section.
7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
The ADC12DJ5200RF contains a function to gradually adjust the tAD adjust setting towards the newly written
TAD_COARSE value. This functionality allows the tAD adjust setting to be adjusted with minimal internal clock
circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 256
tCLK cycles) or faster ramp (four TAD_COARSE LSBs per 256 tCLK cycles) to be selected. The TAD_RAMP_EN
parameter enables the ramp feature and any subsequent writes to TAD_COARSE initiate a new cramp.
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ADVANCE INFORMATION
•
•
•
•
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7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic
latency. The ADC12DJ5200RF uses the JESD204C subclass-1 method to achieve deterministic latency and
synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic device clock (CLK±)
edge at each system power-on and at each device in the system. This requirement imposes setup and hold
constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all
system operating conditions. The ADC12DJ5200RF includes a number of features to simplify this
synchronization process and to relax system timing constraints:
• The ADC12DJ5200RF uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input
frequency by half and double the timing window for SYSREF (see Table 5)
• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid the user in
meeting setup and hold times over all conditions; see the SYSREF Position Detector and Sampling Position
Selection (SYSREF Windowing) section
• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (tAD adjust) to shift the ADC
sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the
ADC sampling instance); see the Automatic SYSREF Calibration section
7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
ADVANCE INFORMATION
The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge and
then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup and
hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet
timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However,
this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF
as operating conditions change or to remove system-to-system variation at production test by finding a unique
optimal value at nominal conditions for each system.
This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF
to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the
SYSREF_POS bits of the SYSREF capture position register. ADC12DJ5200RF must see at least 3 rising edges
of SYSREF before the SYSREF_POS output is valid. Each bit of SYSREF_POS represents a potential SYSREF
sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a
potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of
SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL in the
clock control register 0 to the value corresponding to that SYSREF_POS position. In general, the middle
sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and SYSREF_SEL
are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide
maximum margin for operating condition variations. This process can be performed at final test and the optimal
SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to
characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the
system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this
characterization can be used to track the optimal SYSREF sampling position as system operating conditions
change. In general, a single value can be found that meets timing over all conditions for well-matched systems,
such as those where CLK± and SYSREF± come from a single clocking device.
NOTE
SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the
Automatic SYSREF Calibration section.
The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When
SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are
finer. See the Switching Characteristics table for delay step sizes when SYSREF_ZOOM is enabled and
disabled. In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a
transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates.
Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient information to determine if
these settings are close to a timing violation, although the actual valid window can extend beyond these sampling
positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location
in SYSREF_POS. Table 7 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings.
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Although 24 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows
selection of the first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional
SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In
general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in
the fourth example a value of 15 provides additional margin and can be selected instead.
Table 7. Examples of SYSREF_POS Readings and SYSREF_SEL Selections
SYSREF_POS[23:0]
0x02D[7:0] (1)
0x02C[7:0] (1)
(Smallest Delay)
b10000000
b01100000
b00011001
b10011000
b00000000
b00110001
12
b10000000
b01100000
b00000001
6 or 7
b10000000
b00000011
b00000001
4 or 15
b10001100
b01100011
b00011001
6
8 or 9
Red coloration indicates the bits that are selected, as given in the last column of this table.
7.3.6.3.2 Automatic SYSREF Calibration
The ADC12DJ5200RF has an automatic SYSREF calibration feature to alleviate the often challenging setup and
hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF calibration
uses the tAD adjust feature to shift the device clock to maximize the SYSREF setup and hold times or to align the
sampling instance based on the SYSREF rising edge.
The ADC12DJ5200RF must have a proper device clock applied and be programmed for normal operation before
starting the automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous
SYSREF signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic
SYSREF calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable
register after configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN
high, the ADC12DJ5200RF searches for the optimal tAD adjust setting until the device clock falling edge is
internally aligned to the SYSREF rising edge. TAD_DONE in the SYSREF calibration status register can be
monitored to ensure that the SYSREF calibration has finished. By aligning the device clock falling edge with the
SYSREF rising edge, automatic SYSREF calibration maximizes the internal SYSREF setup and hold times
relative to the device clock and also sets the sampling instant based on the SYSREF rising edge. After the
automatic SYSREF calibration finishes, the rest of the startup procedure can be performed to finish bringing up
the system.
For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore
trace lengths must be matched from a common SYSREF source to each ADC12DJ5200RF. Any skew between
the SYSREF rising edge at each device results in additional error in the sampling instance between devices,
however repeatable deterministic latency from system startup to startup through each device must still be
achieved. No other design requirements are needed in order to achieve multi-device synchronization as long as
a proper elastic buffer release point is chosen in the JESD2048 receiver.
Figure 6 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times
are shown as tSU(OPT) and tH(OPT), respectively. Device clock and SYSREF are referred to as internal in this
diagram because the phase of the internal signals are aligned within the device and not to the external (applied)
phase of the device clock or SYSREF.
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(1)
OPTIMAL SYSREF_SEL
SETTING
0x02E[7:0]
(Largest Delay)
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Sampled Input Signal
Internal Unadjusted
Device Clock
Internal Calibrated
Device Clock
tTAD(SRC)
Internal SYSREF
tCAL(SRC)
ADVANCE INFORMATION
SRC_EN
(SPI register bit)
tH(OPT)
tSU(OPT)
Before calibration, device clock falling edge does
not align with SYSREF rising edge
Calibration
enabled
TAD_DONE
(SPI register bit)
After calibration, device clock falling edge
aligns with SYSREF rising edge
Calibration
finished
Figure 6. SYSREF Calibration Timing Diagram
When finished, the tAD adjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in
the SYSREF calibration status register. After calibration, the system continues to use the calibrated tAD adjust
setting for operation until the system is powered down. However, if desired, the user can then disable the
SYSREF calibration and fine-tune the tAD adjust setting according to the systems needs. Alternatively, the use of
the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal tAD adjust
setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and
TAD_FINE) upon system startup.
Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If
background calibration is the desired use case, disable the background calibration when the SYSREF calibration
is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock control
register 0 must be set to 0 when using SYSREF calibration.
SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted
clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the
clock path to reduce aperture jitter (tAJ).
7.3.7 Digital Down Converters (DDC)
After converting the analog voltage to a digital value, the digitized sample can either be sent directly to the
JESD204C interface block (DDC bypass) or sent to the digital down converter (DDC) block for frequency
conversion and decimation. The DDC block can be used in both dual channel mode and single channel mode.
Frequency conversion and decimation allows a specific frequency band to be selected and reduces the amount
of data sent over the data interface. The DDC first mixes the desired band to complex baseband (0 Hz) by
performing a complex mixing operating using the numerically-controlled oscillator (NCO) as the local oscillator
(LO). The DDC then low-pass filters the baseband signal to remove unwanted frequency images and any signals
that may potentially alias into the desired band. It finally decimates (down samples) the data to reduce the data
rate. Note that the filtering and decimation operations are actually performed as a single operation in
ADC12DJ5200RF. The DDC is designed with sufficient precision such that the digital processing does not
degrade the noise spectral density (NSD) performance of the ADC. Figure 7 illustrates the DDC block in
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ADC12DJ5200RF in dual channel mode while Figure 8 shows the DDC block of ADC12DJ5200RF in single
channel mode. In dual channel mode, the input data for each DDC can be selected to come from either ADC
channel A or ADC channel B by using the DIG_BIND_x SPI registers. Channel B has the same structure with the
input data selected by DIG_BIND_B and the NCO selection mux controlled by pins NCOB[1:0] or through
CSELB[1:0]. Only one DDC is available for use in single channel mode.
DDC A
NCO Bank A
NCOA[1:0]
or CSELA[1:0]
4
MUX
Complex
Mixer
Complex
15-bit @ Fs/N
2
DIG_BIND_A
D
Real
12-bit @ Fs
DDC Bypass
JESD204C
Link A
ADVANCE INFORMATION
Real
12-bit @ Fs
MUX
ADC
Channel A
MUX
MUX
D
DDC B
NCO Bank B
JMODE
NCOB[1:0]
or CSELB[1:0]
Real
12-bit @ Fs
4
Complex
15-bit @ Fs/N
MUX
Complex
Mixer
MUX
ADC
Channel B
MUX
MUX
2
DIG_BIND_B
D
Real
12-bit @ Fs
DDC Bypass
JESD204C
Link B
D
Figure 7. Digital Down Conversion Block in Dual Channel Mode
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DDC
NCO Bank A
ADC
Channel A
NCOA[1:0]
or CSELA[1:0]
JESD204C
Link A
Real
12-bit @ Fs
4
Complex
15-bit @ Fs/N
MUX
Complex
Mixer
MUX
Data
Interleave
MUX
2
D
Real
12-bit @ Fs
DDC Bypass
CLK
JMODE
D
ADC
Channel B
JESD204C
Link B
ADVANCE INFORMATION
Figure 8. Digital Down Conversion Block in Single Channel Mode
7.3.7.1 Numerically-Controlled Oscillator and Complex Mixer
The DDC contains a complex numerically-controlled oscillator (NCO) and a complex mixer. Equation 3 shows the
complex exponential sequence generated by the oscillator.
x[n] = ejωn
(3)
The frequency (ω) is specified by a 32-bit register setting (see the Basic NCO Frequency Setting Mode section
and the Rational NCO Frequency Setting Mode section). The complex exponential sequence is multiplied by the
real input from the ADC to mix the desired carrier to a frequency equal to fIN + fNCO, where fIN is the analog input
frequency after aliasing (in undersampling systems) and fNCO is the programmed NCO frequency.
7.3.7.1.1 NCO Fast Frequency Hopping (FFH)
Fast frequency hopping (FFH) is made possible by each DDC having four independent NCOs that can be
controlled by the NCOA0 and NCOA1 pins for DDC A and the NCOB0 and NCOB1 pins for DDC B. Each NCO
has independent frequency settings (see the Basic NCO Frequency Setting Mode section) and initial phase
settings (see the NCO Phase Offset Setting section) that can be set independently. Further, all NCOs have
independent phase accumulators that continue to run when the specific NCO is not selected, allowing the NCOs
to maintain their phase between selection so that downstream processing does not need to perform carrier
recovery after each hop, for instance.
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NCO hopping occurs when the NCO GPIO pins change state. The pins are controlled asynchronously and
therefore synchronous switching is not possible. Associated latencies are demonstrated in Figure 9, where tTX
and tADC are provided in the Switching Characteristics table. All latencies in Table 8 are approximations only.
NCO Bank
DDC Block
tGPIO-MIXER
tMIXER-TX
NCOx[1:0]
MUX
Dx0+/Dx1+/-
INx+
N
ADC
JESD204C
Dx2+/-
INxComplex
Mixer
Decimate-by-N
(based on JMODE)
Dx7+/-
Figure 9. NCO Fast Frequency Hopping Latency Diagram
Table 8. NCO Fast Frequency Hopping Latency Definitions
LATENCY PARAMETER
VALUE OR CALCULATION
UNITS
tGPIO-MIXER
~45 to ~68
tCLK cycles
tADC-MIXER
~37
tCLK cycles
tMIXER-TX
(tTX + tADC) – tADC-MIXER
tCLK cycles
7.3.7.1.2 NCO Selection
Within each channel DDC, four different frequency and phase settings are available for use. Each of the four
settings use a different phase accumulator within the NCO. Because all four phase accumulators are
independent and continuously running, rapid switching between different NCO frequencies is possible allowing
for phase coherent frequency hopping.
The specific frequency-phase pair used for each channel is selected through the NCOA[1:0] or NCOB[1:0] input
pins when CMODE is set to 1. Alternatively, the selected NCO can be chosen through SPI by CSELA for DDC A
and CSELB for DDC B by setting CMODE to 0 (default). The logic table for NCO selection is provided in Table 9
for both the GPIO and SPI selection options.
Table 9. Logic Table for NCO Selection Using GPIO or SPI
NCO SELECTION
CMODE
NCOx1
NCOx0
CSELx[1]
CSELx[0]
NCO 0 using GPIO
1
0
0
X
X
NCO 1 using GPIO
1
0
1
X
X
NCO 2 using GPIO
1
1
0
X
X
NCO 3 using GPIO
1
1
1
X
X
NCO 0 using SPI
0
X
X
0
0
NCO 1 using SPI
0
X
X
0
1
NCO 2 using SPI
0
X
X
1
0
NCO 3 using SPI
0
X
X
1
1
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The frequency for each phase accumulator is programmed independently through the FREQAx, FREQBx (x = 0
to 3) and, optionally, NCO_RDIV register settings. The phase offset for each accumulator is programmed
independently through the PHASEAx and PHASEBx (x = 0 to 3) register settings.
7.3.7.1.3 Basic NCO Frequency Setting Mode
In basic NCO frequency-setting mode (NCO_RDIV = 0x0000), the NCO frequency setting is set by the 32-bit
register value, FREQAx and FREQBx (x = 0 to 3). The NCO frequency for DDC A can be calculated using
Equation 4, where FREQAx can be replaced by FREQBx to calculate the NCO frequency for DDC B. FREQAx
and FREQBx can be considered either a 2's complement number (–2147483648 to 2147483647) or as an offset
binary number (0 to 4294967295).
ƒ(NCO) = FREQAx × 2–32 × ƒ(DEVCLK) (x = 0 – 3)
(4)
NOTE
Changing the FREQAx and FREQBx register settings during operation results in a nondeterministic NCO phase. If deterministic phase is required, the NCOs must be
resynchronized; see the NCO Phase Synchronization section.
7.3.7.1.4 Rational NCO Frequency Setting Mode
ADVANCE INFORMATION
In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized,
but sometimes an application requires very specific frequencies that fall between two frequency steps. For
example with ƒS equal to 2457.6 MHz and a desired ƒ(NCO) equal to 5.02 MHz, the value for FREQAx is
8773085.867. Truncating the fractional portion results in an ƒ(NCO) equal to 5.0199995 MHz, which is not the
desired frequency.
To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at
specific frequencies without error. First, select a frequency step size (ƒ(STEP)) that is appropriate for the NCO
frequency steps required. The typical value of ƒ(STEP) is 10 kHz. Next, use Equation 5 to program the NCO_RDIV
value.
NCO _ RDIV =
(¦DEVCLK
/ ¦ STEP )
64
(5)
The result of Equation 5 must be an integer value. If the value is not an integer, adjust either of the parameters
until the result is an integer value.
For example, select a value of 1920 for NCO_RDIV.
NOTE
NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are
not recommended.
Now use Equation 6 to calculate the FREQAx register value.
(
FREQAx = round 232 ´ ¦NCO / ¦DEVCLK
)
Alternatively, the following equations can be used:
¦(NCO)
N
¦(STEP)
(
FREQAx = round 2
44
26
´ N / NCO_RDIV
)
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(6)
(7)
(8)
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Table 10 lists common values for NCO_RDIV in 10-kHz frequency steps.
Table 10. Common NCO_RDIV Values (For 10-kHz Frequency Steps)
fCLK (MHz)
NCO_RDIV
2457.6
3840
1966.08
3072
1600
2500
1474.56
2304
1228.8
1920
7.3.7.1.5 NCO Phase Offset Setting
The NCO phase-offset setting for each NCO is set by the 16-bit register value PHASEAx and PHASEBx (where
x = 0 to 3). The value is left-justified into a 32-bit field and then added to the phase accumulator.
Use Equation 9 to calculate the phase offset in radians.
Φ(rad) = PHASEA/Bx × 2–16 × 2 × π (x = 0 to 3)
(9)
The NCOs must be synchronized after setting or changing the value of FREQAx or FREQBx. NCO
synchronization is performed when the JESD204C link is initialized or by SYSREF, based on the settings of
NCO_SYNC_ILA and NCO_SYNC_NEXT. The procedures are as follows for the JESD204C initialization
procedure and the SYSREF procedure for both DC-coupled and AC-coupled SYSREF signals.
NCO synchronization using the JESD204C SYNC signal (SYNCSE or TMSTP±). Although the 64B/66B encoding
modes do not use the SYNC signal to initialize the JESD204C link, it can still be used for NCO synchronization
with this method:
1. The device must be programmed for normal operation
2. Set NCO_SYNC_ILA to 1 to enable NCO synchronization using the SYNC signal
3. Set JESD_EN to 0
4. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings
5. In the JESD204C receiver (logic device), deassert the SYNC signal by setting SYNC high
6. Set JESD_EN to 1
7. Assert the SYNC signal by setting SYNC low in the JESD204C receiver. This start the code group
synchronization (CGS) process in 8B/10B encoding modes or arms the trigger in 64B/66B encoding modes.
8. After achieving CGS (or when ready to synchronize), deassert the SYNC signal by setting SYNC high at the
same time for all ADCs in order synchronize the NCOs in each ADC. The SYNC signal must meet the
required setup and hold times (as specified in the Timing Requirements table)
NCO synchronization using SYSREF (DC-coupled):
1. The device must be programmed for normal operation
2. Set JESD_EN to 1 to start the JESD204C link (the SYNC signal can respond as normal during the CGS
process)
3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings
4. Verify that SYSREF is disabled (held low)
5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1
6. Issue a single SYSREF pulse to all ADCs to synchronize NCOs within all devices
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7.3.7.1.6 NCO Phase Synchronization
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NCO synchronization using SYSREF (AC-coupled):
1. The device must be programmed for normal operation
2. Set JESD_EN to 1 to start the JESD204C link (the SYNC signal can respond as normal during the CGS
process)
3. Program FREQAx, FREQBx, PHASEAx, and PHASEBx to the desired settings
4. Run SYSREF continuously
5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1 at the same time at all ADCs by timing the
rising edge of SCLK for the last data bit (LSB) at the end of the SPI write so that the SCLK rising edge
occurs after a SYSREF rising edge and early enough before the next SYSREF rising edge so that the trigger
is armed before the next SYSREF rising edge (a long SYSREF period is recommended)
6. NCOs in all ADCs are synchronized by the next SYSREF rising edge
7.3.7.2 Decimation Filters
ADVANCE INFORMATION
The decimation filters are arranged to provide a programmable overall decimation of 4 or 8. All decimation filters
operate on complex data (from the complex digital mixer) and the outputs have a resolution of 15 bits. The
decimation filters are implemented as linear phase finite impulse response (FIR) filters. Table 11 lists the
effective output sample rates, available signal bandwidths, output formats, and stop-band attenuation for each
decimation mode.
Table 11. Output Sample Rates and Signal Bandwidths
DECIMATION
SETTING
ƒ(DEVCLK)
OUTPUT FORMAT
OUTPUT RATE
(MSPS)
MAX ALIAS PROTECTED SIGNAL
BANDWIDTH (MHz)
STOP-BAND
ATTENUATION
PASS-BAND
RIPPLE
No decimation (DDC
bypass)
ƒ(DEVCLK)
ƒ(DEVCLK) / 2
—
< ±0.001 dB
Real signal,
12-bit data
Decimate-by-4
ƒ(DEVCLK) / 4
0.8 × ƒ(DEVCLK) / 4
> 90 dB
< ±0.001 dB
Complex signal,
15-bit data
Decimate-by-8
ƒ(DEVCLK) / 8
0.8 × ƒ(DEVCLK) / 8
> 90 dB
< ±0.001 dB
Complex signal,
15-bit data
Figure 10 to Figure 13 provide the composite decimation filter responses. The black portion of the trace shows
the pass-band region, or alias-protected region, of the response. The red portion of the trace shows the transition
region of the response as well as any frequency regions that will alias into the transition region. The transition
region is not alias protected and therefore desired signals should only be placed in the pass-band region of the
filter response. The blue portion of the trace shows the frequency regions that will alias into the pass-band after
decimation and therefore define the stop-band region of the frequency response. The stop-band attenuation is
defined to sufficient filter any undesired images or signals to prevent them from aliasing into the desired passband. Use analog filtering before the analog inputs (INA± or INB±) for additional attenuation of signals that fall
within this band or to sufficiently reduce signals at the ADC inputs that may produce harmonics, interleaving
spurs or other undesired spurious signals that will alias into the desired signal band (before the complex mixing
and decimation operations).
46
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0
0.001
Passband
Transition Band
Aliasing Band
-20
Passband
Transition Band
Attenuation (dB)
Attenuation (dB)
0.0005
-40
-60
-80
0
-0.0005
-100
-120
-0.001
0
0.1
0.2
0.3
Normalized Frequency (Fs)
0.4
0.5
0
0.02
h4co
Figure 10. Decimate-by-4 Composite Response
0.04
0.06
0.08
Normalized Frequency (Fs)
0.1
0.12
h4co
Figure 11. Decimate-by-4 Composite Zoomed Pass-Band
Response
0
-20
Passband
Transition Band
Attenuation (dB)
Attenuation (dB)
0.0005
-40
-60
-80
0
-0.0005
-100
-120
-0.001
0
0.1
0.2
0.3
Normalized Frequency (Fs)
0.4
0.5
0
0.01
h8co
Figure 12. Decimate-by-8 Composite Response
0.02
0.03
0.04
Normalized Frequency (Fs)
0.05
0.06
h8co
Figure 13. Decimate-by-8 Composite Zoomed Pass-Band
Response
For maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each
decimation setting to achieve the composite responses illustrated in Figure 10 to Figure 13. Table 12 describes
the combination of filter blocks used for each decimation setting and Table 13 lists the coefficient details and
decimation factor of each filter block. The coefficients are symmetric with the center tap indicated by bold text.
Table 12. Decimation Mode Filter Usage
DECIMATION SETTING
FILTER BLOCKS USED (Listed in Order of Operation)
4
CS40, CS80
8
CS20, CS40, CS80
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0.001
Passband
Transition Band
Aliasing Band
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Table 13. Filter Coefficient Details
FILTER COEFFICIENT SET (Decimation Factor of Filter, Scale factor)
CS20 (2, 2-14)
CS40 (2, 2-17)
CS80 (2, 2-19)
109
109
–327
–327
–37
0
0
0
0
0
–37
0
–837
–837
2231
2231
118
118
0
0
0
0
0
0
4824
4824
–8881
–8881
–291
–291
8192
0
0
0
0
39742
39742
612
612
65536
0
0
–1159
–1159
0
0
2031
2031
0
0
–3356
–3356
0
0
5308
5308
ADVANCE INFORMATION
0
0
–8140
–8140
0
0
12284
12284
0
0
–18628
–18628
0
0
29455
29455
0
0
–53191
–53191
0
0
166059
166059
262144
7.3.7.3 Output Data Format
The DDC output data consists of 15-bit complex data plus the two overrange threshold-detection control
bits.Table 14 shows the data output format for the DDC modes.
Table 14. Complex Decimation Output Sample Format
I/Q
SAMPLE
16-BIT OUTPUT WORD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
DDC in-phase (I) 15-bit output data
OVR_T0
Q
DDC quadrature (Q) 15-bit output data
OVR_T1
7.3.7.4 Decimation Settings
7.3.7.4.1 Decimation Factor
The decimation setting is adjustable over the following settings and is set by the JMODE parameter. See
Table 22 for the available JMODE values and the corresponding decimation settings.
• DDC Bypass: No decimation, real output
• Decimate-by-4: Complex output
• Decimate-by-8: Complex output
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7.3.7.4.2 DDC Gain Boost
The DDC gain boost (see the DDC configuration register) provides additional gain through the DDC block.
Setting BOOST to 1 sets the total decimation filter chain gain to 6.02 dB. With a setting of 0, the total decimation
filter chain has a 0-dB gain. Only use this setting when the negative image of the input signal is filtered out by the
decimation filters, otherwise clipping may occur. There is no reduction in analog performance when gain boost is
enabled or disabled, but care must be taken to understand the reference output power for proper performance
calculations.
7.3.8 JESD204C Interface
The ADC12DJ5200RF uses a JESD204C high-speed serial interface for data converters to transfer data from the
ADC to the receiving logic device. Many of the available JESD204C output formats are backwards compatible
with existing JESD204B receivers, including many of the JESD204B modes in the ADC12DJ2700 and
ADC12DJ3200. The ADC12DJ5200RF serialized lanes are capable of operating with both 8B/10B encoding and
64B/66B encoding. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed-limited
logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which will be
described throughout this section. Figure 14 shows a simplified block diagram of the 8B/10B encoded JESD204C
interface and Figure 15 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.
ADC
TRANSPORT
LAYER
SCRAMBLER
(Optional)
8B/10B
LINK LAYER
SERDES
TX PHY
ANALOG
CHANNEL
Logic Device
JESD204B or JESD204C Block
APPLICATION
LAYER
TRANSPORT
LAYER
DESCRAMBLE
(Optional)
8B/10B
LINK LAYER
ADVANCE INFORMATION
ADC
JESD204C Block
SERDES
RX PHY
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Figure 14. Simplified 8B/10B Encoded JESD204C Interface Diagram
ADC
JESD204C Block
ADC
TRANSPORT
LAYER
SCRAMBLER
(Required)
64B/66B
LINK LAYER
SERDES
TX PHY
ANALOG
CHANNEL
Logic Device
JESD204C Block
APPLICATION
LAYER
TRANSPORT
LAYER
DESCRAMBLE
(Required)
64B/66B
LINK LAYER
SERDES
RX PHY
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Figure 15. Simplified 64B/66B Encoded JESD204C Interface Diagram
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The various signals used in the JESD204C interface and the associated ADC12DJ5200RF pin names are
summarized briefly in Table 15 for reference. Most of the signals are common between 8B/10B and 64B/66B
encoded JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B
encoding. The sync header encoded into the data stream is used for block synchronization instead of the SYNC
signal.
Table 15. Summary of JESD204C Signals
SIGNAL NAME
Data
SYNC
ADVANCE INFORMATION
Device clock
SYSREF
ADC12DJ5200RF PIN NAMES
DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
8B/10B
Yes
64B/66B
DESCRIPTION
Yes
High-speed serialized data
after 8B/10B or 64B/66B
encoding
SYNCSE, TMSTP+, TMSTP–
Yes
No
Link initialization signal
(handshake), toggles low to
start code group
synchronization (CGS)
process. Not used for
64B/66B encoding modes,
unless it is used for NCO
synchronization purposes.
CLK+, CLK–
Yes
Yes
ADC sampling clock, also
used for clocking digital logic
and output serializers
Yes
System timing reference
used to deterministically reset
the internal local multiframe
clock (LMFC) or local
extended multiblock clock
(LEMC) counters in each
JESD204C device
SYSREF+, SYSREF–
Yes
Not all optional features of JESD204C are supported by ADC12DJ5200RF. The list of features that are
supported and the features that are not supported is provided in Table 16.
Table 16. Declaration of Supported JESD204C Features
LETTER IDENTIFIER
REFERENCE
CLAUSE
a
b
50
FEATURE
SUPPORT IN ADC12DJ5200RF
clause 8
8B/10B link layer
Supported
clause 7
64B/66B link layer
Supported
c
clause 7
64B/80B link layer
Not supported
d
clause 7
The command channel when using the
64B/66B or 64B/80B link layer
Not supported
e
clause 7
Forward error correction (FEC) when using
the 64B/66B or 64B/80B link layer
Supported
f
clause 7
CRC3 when using the 64B/66B or 64B/80B
link layer
Not supported
g
clause 8
A physical SYNC pin when using the 8B/10B
link layer
Supported
h
clause 7, clause 8
Subclass 0
Not supported, but subclass 1 transmitter is
compatible with subclass 0 receiver
i
clause 7, clause 8
Subclass 1
Supported
j
clause 8
Subclass 2
Not supported
k
clause 7, clause 8
Lane alignment within a single link
Supported
l
clause 7, clause 8
Subclass 1 with support for a lane alignment
on a multipoint link by means of the
MULTIREF signal
Not supported
m
clause 8
SYNC interface timing is compatible with
JESD204A
Supported
n
clause 8
SYNC interface timing is compatible with
JESD204B
Supported
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7.3.8.1 Transport Layer
The transport layer takes samples from the ADC output (when decimation is bypassed) or from the DDC output
and maps the samples into octets inside of frames. The transport layer is common to both 8B/10B and 64B/66B
encoding modes. These frames are then mapped onto the available lanes. The mapping of octets into frames
and frames onto lanes is defined by the transport layer settings such as L, M, F, S, N and N'. An octet is 8 bits
(before 8B/10B or 64B/66B encoding), a frame consists of F octets and the frames are mapped onto L lanes.
Samples are N bits, but sent as N' bits across the link. The samples come from M converters and there are S
samples per converter per frame cycle. M is sometimes artificially increased in order to obtain a more desirable
mapping, for instance lower latency may be achieved with a larger M value for long frames.
There are a number of predefined transport layer modes in the ADC12DJ5200RF that are defined in Table 22.
The high level configuration parameters for the transport layer in the ADC12DJ5200RF are described in
Table 20. The transport layer mode is chosen by simply setting the JMODE register setting. For reference, the
various configuration parameters for JESD204C are defined in Table 21.
The link layer further maps the frames into multiframes when using 8B/10B encoding or blocks, multiblocks and
extended multiblocks when using 64B/66B encoding.
A data scrambler is available to scramble the data before transmission across the channel. Scrambling is used to
remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The scrambler is
optional for 8B/10B encoded modes, however it is mandatory for 64B/66B encoded modes in order to have
sufficient spectral content for clock recovery and adaptive equalization and to maintain DC balance to allow AC
coupling of the transmitter to the receiver. The scrambler operates on the data before encoding, such that the
8B/10B scrambler scrambles the 8-bit octets before 10-bit encoding and the 64B/66B scrambler scrambles the
64-bit block before the sync header insertion (66-bit encoding). The JESD204C receiver automatically
synchronizes its descrambler to the incoming scrambled data stream. For 8B/10B encoding, the initial lane
alignment sequence (ILA) is never scrambled. Scrambling can be enabled by setting SCR (in the JESD204C
control register) for 8B/10B encoding modes, but it is automatically enabled in 64B/66B modes. The scrambling
polynomial is different for 8B/10B encoding and 64B/66B encoding schemes as defined by the JESD204C
standard.
7.3.8.3 Link Layer
The link layer serves multiple purposes in JESD204C for both 8B/10B and 64B/66B encoding schemes, however
there are some differences in implementation for each encoding scheme. In general, the link layer's
responsibilities include scrambling of the data (see Scrambler), establishing the code (8B/10B) or block
(64B/66B) boundaries and the multiframe (8B/10B) or multiblock (64B/66B) boundaries, initializing the link,
encoding the data, and monitoring the health of the link. This section is split into an 8B/10B section (8B/10B Link
Layer) and a 64B/66B section (64B/66B Link Layer) in order to cover the specific implementation for each
encoding scheme.
7.3.8.4 8B/10B Link Layer
This section covers the link layer for the 8B/10B encoding operating modes including initialization of the
character, frame and multiframe boundaries, alignment of the lanes, 8B/10B encoding and monitoring of the
frame and multiframe alignment during operation.
7.3.8.4.1 Data Encoding (8B/10B)
The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across
the link using 8B/10B encoding. 8B/10B encoding ensures DC balance to allow use of AC-coupling between the
SerDes transmitter and receiver and guarantees a sufficient number of edge transitions for the receiver to reliably
recover the data clock. 8B/10B encoding also provides some error detection since a single bit error in a character
likely results in either not being able to find the 10-bit character in the 8B/10B decoder lookup table or an
incorrect character disparity.
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7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
The frames from the transport layer are combined into multiframes which are used in the process of achieving
deterministic latency in subclass 1 implementations. The length of a multiframe is set by the K parameter which
defines the number of frames in a multiframe. JESD204C increases the maximum allowed number of frames per
multiframe (K) from 32 in JESD204B to 256 in JESD204C to allow a longer multi-frame to ease deterministic
latency requirements. The total allowed range of K is defined by the inequality ceil(17/F) ≤ K ≤ min(256,
floor(1024/F)) where ceil() and floor() are the ceiling and floor function, respectively. The local multiframe clock
(LMFC) keeps track of the start and end of a multiframe for deterministic latency and data synchronization
purposes. The LMFC is reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver
in order to act as a timing reference for deterministic latency. The LMFC clock frequency is given in Equation 10
where fBIT is the serialized bit rate (line rate) of the SerDes interface and F and K are as defined above. The
frequency of SYSREF must equal to or an integer division of fLMFC when using 8B/10B encoding modes if
SYSREF is a continuous signal.
fLMFC = fBIT / (10 × F × K)
(10)
7.3.8.4.3 Code Group Synchronization (CGS)
ADVANCE INFORMATION
The first step in initializing the JESD204C link, after the LMFC is deterministically reset by SYSREF, is for the
receiver to find the boundaries of the encoded 10-bit characters sent across each SerDes lane. This process is
called code group synchronization (CGS). The receiver first asserts the SYNC signal (set to logic '0') when ready
to initialize the link. The transmitter responds to the request by sending a stream of K28.5 comma characters.
The receiver aligns its character clock to the K28.5 character sequence and CGS is achieved after successfully
receiving four consecutive K28.5 characters. The receiver deasserts SYNC (set to logic '1') on the next LMFC
edge after CGS is achieved and waits for the transmitter to start the initial lane alignment sequence (ILAS).
7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
After the transmitter detects the SYNC signal deassert (logic '0' to logic '1' transition), the transmitter waits until
its next LMFC edge to start sending the initial lane alignment sequence (ILAS). The ILAS consists of four
multiframes each containing a predetermined sequence. The receiver searches for the start of the ILAS to
determine the frame and multiframe boundaries. Each multiframe of the ILAS starts with a /R/ character (K28.0)
and ends with a /A/ character (K28.3) and either can be used to detect the boundary of a multiframe. Each lane
starts buffering its data in the elastic buffer once the ILAS reaches the receiver, starting with the /R/ character,
until all receivers have received the ILAS and subsequently release the ILAS from all lanes at the same time in
order to align the lanes. The elastic buffer release point is chosen to avoid ambiguity in the release of the data
caused by variation in the data delay (arrival of the ILAS at the receiver for each lane). The second multiframe of
the ILAS contains configuration parameters for the JESD204C link configuration that can be used by the receiver
to verify that the transmitter and receiver configurations match.
7.3.8.4.5 Frame and Multiframe Monitoring
The ADC12DJ5200RF supports frame and multiframe monitoring for verifying the health of the JESD204C link
when using 8B/10B encoding. The scheme changes depending on the use of scrambling. The implementation
when scrambling is disabled is covered first. If the last octet of the current frame matches the last octet of the
previous frame, then the last octet of the current frame is encoded as an /F/ (K28.7) character. If the current
frame is also the last frame of a multiframe, then an /A/ (K28.3) character is used instead. Neither an /F/ or /A/
character should occur in a normal data stream, except when replaced by the transmitter for alignment
monitoring. When the receiver detects an /F/ or /A/ character in the normal data stream the receiver checks to
see if the character occurs at the location expected to be the end of a frame or multiframe. If the character
occurs at a location other than the end of a frame or multiframe then either the transmitter or receiver has
become misaligned. The receiver replaces the alignment character with the appropriate data character upon
reception of a properly aligned /F/ or /A/ character. The appropriate data character is the last octet of the
previously received frame. This scheme increases the probability of an alignment character for non-scrambled
data streams.
The implementation when scrambling is enabled is slightly different since the octets will be randomized. If the last
octet of a frame is 0xFC (before 8B/10B encoding) then the transmitter encodes the octet as an /F/ (/K28.7/)
character. If the last octet of a multiframe is 0x7C (before 8B/10B encoding) then the transmitter encodes the
octet as an /A/ (/K28.3/) character. The location of the /A/ and /F/ characters is monitored to verify proper frame
and multiframe alignment. The receiver replaces the alignment characters by simply replacing an /F/ character
with the 0xFC octet and an /A/ character with the 0x7C octet.
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The receiver can report an error if multiple alignment characters occur in the incorrect location or do not occur
when expected. Upon detection of a frame or multiframe misalignment, the receiver should trigger a link
realignment by asserting SYNC. SYSREF should also be reissued to verify that the LMFC in the transmitter and
receiver have proper alignment before restarting the link.
7.3.8.5 64B/66B Link Layer
This section covers the link layer for the 64B/66B encoding operating modes which includes scrambling of the
data, addition of the sync headers (64B/66B encoding), the structure of the block and multiblock, the sync
header, cyclic redundancy checking (CRC), forward error correction (FEC) and link alignment.
7.3.8.5.1 64B/66B Encoding
The frames formed by the transport layer are packed into 8-octet long blocks (64 bits). This 64-bit block is
scrambled and then a 2-bit sync header (SH) is appended to form a 66-bit transmission block. The sync header
is used for block synchronization by marking the end of a block as well as allowing for cyclic redundancy
checking (CRC), forward error correction (FEC) or a command channel. The structure of a block is given in
Table 17 where SH represents the appended 2-bit sync header.
SH
OCTET0
OCTET1
OCTET2
OCTET3
OCTET4
OCTET5
OCTET6
OCTET7
[0:1]
[2:9]
[10:17]
[18:25]
[26:33]
[34:41]
[42:49]
[50:57]
[58:65]
7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
A multiblock is a 32 block container which consists of a concatenation of 32 blocks. An extended multiblock is a
concatenation of multiple multiblocks, where E defines the number of multiblocks in an extended multiblock. A
frame can be split between blocks and multiblocks, but there must be an integer number of frames in an
extended multiblock. An extended multiblock is only necessary when a multiblock does not have an integer
number of frames. If an extended multiblock is not used, because a multiblock contains an integer number of
frames, then the E parameter is equal to 1 to indicate that there is one multiblock in an extended multiblock.
Values of E greater than 1 are not supported in ADC12DJ5200RF.
An extended multiblock is analogous to a multiframe in the 8B/10B transport layer. The local extended mutiblock
clock (LEMC) keeps track of the start and end of a multiblock for deterministic latency and data synchronization
purposes in the same way the LMFC tracks the start and end of a multiframe in 8B/10B encoding. The LEMC is
reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver in order to act as a
timing reference for deterministic latency. The LEMC clock frequency is defined by Equation 11 where fBIT is the
serialized bit rate (line rate) of the SerDes interface. The frequency of SYSREF must equal to or an integer
division of fLMFC when using 64B/66B encoding modes if SYSREF is a continuous signal.
fLEMC = fBIT / (66 × 32 × E)
(11)
7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
The sync header contains two bits that are always opposite of each other (either 01 or 10). The JESD204C
receiver can find the block boundaries by looking for a 66-bit boundary that always contains a 0 to 1 or 1 to 0
transition. Although 0 to 1 and 1 to 0 transitions will occur at other locations in a block, it is impossible for the
sequence to appear at a fixed location, other than the proper sync header location, in successive blocks for a
long period of time. The sync header indicates the start of a block and can be used for block alignment
monitoring. If a 00 or a 11 bit sequence is seen at the assumed sync header location of a block, then block
alignment may have been lost. Multiple occurrences of incorrect sync header bits should trigger a search for the
sync header after sending SYSREF to all devices to reset LEMC alignment.
A sync header ([0:1]) of 01 corresponds to transmission of a 1 while a sync header of 10 corresponds to a
transmission of a 0. The transmitted bit from the sync header of each block of a multiblock are combined into a
32-bit word called the sync header stream. The sync header stream is used to transmit data in parallel with the
user data in order to synchronize the link by marking the borders of multiblocks and extended multiblocks. In
addition, the sync header stream provides one of either CRC, FEC or a command channel. ADC12DJ5200RF
supports CRC-12 and FEC and does not support CRC-3 or the command channel.
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Table 17. Structure of 64B/66B Block with Sync Header
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The 32-bit sync header stream always ends with a 00001 bit sequence, called the end-of-multiblock (EoMB)
signal, that indicates the end of a multiblock. For CRC and command channel modes, a 00001 sequence will
never occur in any other location in the sync header stream. For FEC mode, it is possible for a 00001 sequence
to appear in another location within the sync header stream, however it is improbable to see the 00001 sequence
in the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than
one multiblock to find the end of a multiblock. The end of an extended multiblock is found for all modes by
monitoring bit 22 of the sync header stream, the EoEMB bit, which indicates the end of an extended multiblock
when set to a 1. The EoMB (00001) and EoEMB signals, as well as fixed 1s in the sync header stream for CRC
and command channel modes, form the pilot signal of the sync header stream.
The defined format for each form of the sync header stream are defined in the following sections.
7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
ADVANCE INFORMATION
The cyclic redundancy check (CRC) mode is available to allow detection of potential bit errors during
transmission. Support for the 12-bit word CRC-12 mode is required by JESD204C, while a 3-bit word CRC-3
mode is optional. ADC12DJ5200RF does not support the CRC-3 mode and therefore this section is specific to
the CRC-12 mode only. The transmitter computes the CRC-12 parity bits from the scrambled data bits of the 32
blocks of a multiblock. The 12-bit CRC parity word is then transmitted in the sync header stream of the next
multiblock. The receiver computes the 12-bit parity word of the received multiblock and compares it against the
received 12-bit parity word of the next multiblock. A difference indicates that there is at least one error in the
received data bits or in the received 12-bit parity word. The minimum latency to the detection of a bit error in the
first data bit of a multiblock is 46 blocks.
The mapping of the sync header stream when using the CRC-12 mode is shown in Table 18. CRC[x]
corresponds to bit x of the 12-bit CRC word. Cmd[x] corresponds to bit x of the 7 bit command word, which are
always set to 0's in ADC12DJ5200RF. The 00001 bit sequence at the end of the sync header stream is the pilot
signal that is used to identify the end of a multiblock. The 1s that occur throughout the sync header guarantee
that the pilot signal will only be seen at the end of the sync header, allowing multiblock alignment after only a
single multiblock has been received. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last
multiblock of an extended multiblock.
Table 18. Sync Header Stream Bit Mapping for CRC-12 Mode
Bit
Function
Bit
Function
Bit
Function
Bit
Function
0
CRC[11]
8
CRC[5]
16
Cmd[6]
24
Cmd[2]
1
CRC[10]
9
CRC[4]
17
Cmd[5]
25
Cmd[1]
2
CRC[9]
10
CRC[3]
18
Cmd[4]
26
Cmd[0]
3
1
11
1
19
1
27
0
4
CRC[8]
12
CRC[2]
20
Cmd[3]
28
0
5
CRC[7]
13
CRC[1]
21
1
29
0
6
CRC[6]
14
CRC[0]
22
EoEMB
30
0
7
1
15
1
23
1
31
1
The CRC-12 encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 12-bit parity
word using the generator polynomial given by Equation 12. The polynomial is sufficient to detect all 2-bit errors in
a multiblock, spanning any distance, and burst error sequences of up to 12-bits in length. The probability of not
detecting a 3-bit error spanning any distance in a multiblock is approximately 0.004%.
0x987 == x12+x9+x8+x3+x2+x+1
(12)
The full parity bit generation for CRC-12 is shown in Figure 16. The input is a 2048 bit sequence, built from the
32 scrambled blocks of a multiblock (sync header is not included). The 12-bit parity word, CRC[11:0], is taken
from the Sx blocks after the full 2048 bit sequence is processed. The Sx blocks are initialized with 0's before
processing each multiblock. For more information on the CRC-12 parity word generation, refer to the JESD204C
standard.
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32-block input
(2048 bits)
1
x2
x
x3
S0
S1
S2
CRC[0]
CRC[1]
CRC[2]
x8
S3
S4
S5
S6
S7
CRC[3] CRC[4] CRC[5] CRC[6] CRC[7]
x9
S8
x12
S9
CRC[8]
S10
S11
CRC[9] CRC[10] CRC[11]
Figure 16. CRC-12 Parity Bit Generator
Forward error correction (FEC) is an optional feature in JESD204C and is supported by ADC12DJ5200RF.
Whereas CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors in order to
improve the bit error rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors,
however some applications, such as an oscilloscope, rely on long error-free measurements in order to detect a
certain response from the device under test (DUT). An error in these applications may result in a false-positive
detection of the response.
A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the 26-bit
parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then
calculates its own 26-bit parity word and calculates the difference between the locally generated and received
parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have
been received correctly, while any value other than 0 indicates at least one error in either the data bits or the
parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct
the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock
is 58 blocks.
The mapping of the sync header stream when using FEC mode is shown in Table 19. FEC[x] corresponds to bit
x of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is
used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within
the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location
within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find
the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of
an extended multiblock.
Table 19. Sync Header Stream Bit Mapping for FEC Mode
Bit
Function
Bit
Function
Bit
Function
Bit
Function
0
FEC[25]
8
FEC[17]
16
FEC[9]
24
FEC[2]
1
FEC[24]
9
FEC[16]
17
FEC[8]
25
FEC[1]
2
FEC[23]
10
FEC[15]
18
FEC[7]
26
FEC[0]
3
FEC[22]
11
FEC[14]
19
FEC[6]
27
0
4
FEC[21]
12
FEC[13]
20
FEC[5]
28
0
5
FEC[20]
13
FEC[12]
21
FEC[4]
29
0
6
FEC[19]
14
FEC[11]
22
EoEMB
30
0
7
FEC[18]
15
FEC[10]
23
FEC[3]
31
1
The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word
using the generator polynomial given by Equation 13. The 2048 scrambled input bits plus 26 parity bits forms a
shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire
code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.
g(x) = (x17+1)(x9+x4+1) == x26+x21+x17+x9+x4+1
(13)
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7.3.8.5.3.2 Forward Error Correction (FEC) Mode
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The full 26-bit FEC parity word generation is shown in Figure 17. The input is a 2048 bit sequence, built from the
32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken
from the Sx blocks after the full 2048 bit sequence is processed. The Sx blocks are initialized with 0's before
processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C
standard.
32-block input
(2048 bits)
x4
1
S0
S1
S2
S3
FEC[0] FEC[1] FEC[2] FEC[3]
x9
S4
...
S8
FEC[4] ... FEC[8]
x17
S9
S16
FEC[9] ... FEC[16]
x21
S17
S20
FEC[17] ... FEC[20]
S21
S24
S25
FEC[21] ... FEC[24] FEC[25]
Figure 17. FEC Parity Bit Generator
ADVANCE INFORMATION
FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction,
refer to the JESD204C standard.
7.3.8.5.4 Initial Lane Alignment
The 64B/66B link layer does not use an initial lane alignment sequence (ILAS) like the 8B/10B link layer.
Therefore, the receiver must use a different scheme to align lanes using the elastic buffer. In 8B/10B mode, the
ILAS triggers the elastic buffer to start buffering the data for each lane. After all lanes have started buffering the
data, the elastic buffers for each lane are released at a release point determined by the release buffer delay
(RBD) parameter and the phase of the LMFC. In 64B/66B mode, the process starts by having all lanes achieve
block, multiblock and extended multiblock alignment. Once all lanes have achieved alignment, the receiver can
begin buffering data in the elastic buffers at the start of the next extended multiblock on each lane. The data is
released at the next release point after all lanes have seen the start of an extended multiblock and have started
buffering the data. The release point is defined relative to the LEMC edge and the programmed RBD value, the
most intuitive of which is to release on the LEMC edge itself. The release point must be chosen to avoid the
region of the LEMC containing variation in the data delay on each lane from startup to startup.
7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
Synchronization of blocks, multiblocks and extended multiblocks by monitoring the sync header of each block
and EoMB and EoEMB bit of the sync header stream. A block will always begin with a 0 to 1 or 1 to 0 transition
(sync header). A single missed sync header can occur due to a bit error, however it there are a number of sync
header errors within a set number of blocks, then block synchronization has been lost and block synchronization
should be reinitialized. It is possible to still have block synchronization, but to lose multiblock or extended
multiblock synchronization. Multiblock synchronization is monitored by looking for the EoMB signal, 00001, at the
end of the sync header stream for each multiblock. If multiple EoMB signals are erroneous within a number of
blocks, multiblock synchronization has been lost and multiblock synchronization should be reinitialized. If an
erroneous EoEMB bit is received for multiple extended multiblocks within a number of extended multiblocks,
such as a 1 for a multiblock that is not the end of an extended multiblock or a 0 for a multiblock that is the end of
an extended multiblock, then multiblock synchronization is lost and extended multiblock synchronization should
be reinitialized. If multiblock or extended multiblock synchronizaton is lost, SYSREF should be applied to the
erroneous devices in order to reestablish the LEMC before the synchronization process begins.
7.3.8.6 Physical Layer
The JESD204C physical layer consists of a current mode logic (CML) output driver and receiver. The receiver
consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream
and can contain a continuous time linear equalizer (CTLE) and/or discrete feedback equalizer (DFE) to correct
for the low-pass response of the physical transmission channel. Likewise, the transmitter can contain preequalization to account for frequency dependent losses across the channel. The total reach of the SerDes links
depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error
performance. The SerDes lanes do not have to be matched in length because the receiver aligns the lanes
during the initial lane alignment sequence.
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7.3.8.6.1 SerDes Pre-Emphasis
The ADC12DJ5200RF high-speed output drivers can pre-equalize the transmitted data stream by using preemphasis in order to compensate for the low-pass response of the transmission channel. Configurable preemphasis settings allow the output drive waveform to be optimized for different PCB materials and signal
transmission distances. The pre-emphasis setting is adjusted through the serializer pre-emphasis setting
SER_PE (in the serializer pre-emphasis control register). Higher values increase the pre-emphasis to
compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram
analysis capability in the receiver. Adjust the pre-emphasis setting to optimize the eye-opening for the specific
hardware configuration and line rates needed.
7.3.8.7 JESD204C Enable
The JESD204C interface must be disabled through JESD_EN (in the JESD204C enable register) while any of
the other JESD204C parameters are being changed. When JESD_EN is set to 0 the block is held in reset and
the serializers are powered down. The clocks for this section are also gated off to further save power. When the
parameters are set as desired, the JESD204C block can be enabled (JESD_EN is set to 1).
JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices
achieve the same deterministic latency then they can be considered synchronized. This latency must be
achieved from system startup to startup to be deterministic. There are two key requirements to achieve
deterministic latency. The first is proper capture of SYSREF for which the ADC12DJ5200RF provides a number
of features to simplify this requirement at giga-sample clock rates (see the SYSREF Capture for Multi-Device
Synchronization and Deterministic Latency section for more information). SYSREF resets either the LMFC in
8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC and LEMC are analogous between
the two modes and will now be referred to as LMFC/LEMC.
The second requirement is to choose a proper elastic buffer release point in the receiver. Because the
ADC12DJ5200RF is an ADC, the ADC12DJ5200RF is the transmitter (TX) in the JESD204C link and the logic
device is the receiver (RX). The elastic buffer is the key block for achieving deterministic latency, and does so by
absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to
the receiver. A proper release point is one that provides sufficient margin against delay variations. An incorrect
release point results in a latency variation of one LMFC/LEMC period. Choosing a proper release point requires
knowing the average arrival time of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total
expected delay variation for all devices. With this information the region of invalid release points within the
LMFC/LEMC period can be defined, which stretches from the minimum to maximum delay for all lanes.
Essentially, the designer must ensure that the data for all lanes arrives at all devices after the previous release
point occurs and before the next release point occurs.
Figure 18 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is
shown. The second ADC has a longer routing distance (tPCB) and results in a longer link delay. First, the invalid
region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the
release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate
number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the
LMFC/LEMC cycle. In the case of Figure 18, the LMFC/LEMC edge (RBD = 0) is a good choice for the release
point because there is sufficient margin on each side of the valid region.
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7.3.8.8 Multi-Device Synchronization and Deterministic Latency
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Nominal Link Delay
(Arrival at Elastic Buffer)
ADC 1 Data
Propagation
tTX
ADC 2 Data
Propagation
tTX
tPCB
Link Delay
Variation
tRX-DESER
tPCB
tRX-DESER
Release point
margin
Choose LMFC/LEMC
edge as release point
(RBD = 0)
TX LMFC/LEMC
RX LMFC/LEMC
Time
Invalid Region
of LMFC/LEMC
Valid Region of
LMFC/LEMC
Figure 18. LMFC/LEMC Valid Region Definition for Elastic Buffer Release Point Selection
ADVANCE INFORMATION
The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is
important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within
every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay
can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the
requirements for more information.
7.3.8.9 Operation in Subclass 0 Systems
ADC12DJ5200RF can operate with subclass 0 compatibility provided that multi-ADC synchronization and
deterministic latency are not required. With these limitations, the device can operate without the application of
SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as
normal to initiate the CGS and ILAS in 8B/10B mode.
7.3.9 Alarm Monitoring
A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are
detected by this feature:
1. Serializer FIFO alarm (FIFO overflow or underflow)
2. Serializer PLL is not locked
3. JESD204C link is enabled, but not transmitting data (not in the data transmission state)
4. SYSREF causes internal clocks to be realigned
5. An upset that impacts the NCO phase
6. An upset that impacts the internal DDC or JESD204C clocks
When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the
host system writes a 1 to clear the alarm. If the alarm type is not masked (see the alarm mask register), then the
alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output
that goes high when an alarm occurs; see the CAL_STATUS_SEL bit in the calibration pin configuration register.
7.3.9.1 NCO Upset Detection
The NCO_ALM register bit indicates if the NCO in channel A or B has been upset. The NCO phase accumulators
in channel A are continuously compared to channel B. If the accumulators differ for even one clock cycle, the
NCO_ALM register bit is set and remains set until cleared by the host system by writing a 1. This feature
requires the phase and frequency words for each NCO accumulator in DDC A (PHASEAx, FREQAx) to be set to
the same values as the NCO accumulators in DDC B (PHASEBx, FREQBx). For example, PHASEA0 must be
the same as PHASEB0 and FREQA0 must be the same as FREQB0, however, PHASEA1 can be set to a
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different value than PHASEA0. This requirement ultimately reduces the number of NCO frequencies available for
phase coherent frequency hopping from four to two for each DDC. DDC B can use a different NCO frequency
than DDC A by setting the NCOB[1:0] pins to a different value than NCOA[1:0]. This detection is only valid after
the NCOs are synchronized by either SYSREF or the start of the ILA sequence (as determined by the NCO
synchronization register). For the NCO upset detection to work properly, follow these steps:
Program JESD_EN = 0
Ensure the device is configured to use both channels (PD_ACH = 0, PD_BCH = 0)
Select a JMODE that uses the NCO
Program all NCO frequencies and phases to be the same for channel A and B (for example, FREQA0 =
FREQB0, FREQA1 = FREQB1, FREQA2 = FREQB2, and FREQA3 = FREQB3)
5. If desired, use the CMODE and CSEL registers or the NCOA[1:0] and NCOB[1:0] pins to choose a unique
frequency for channel A and channel B
6. Program JESD_EN = 1
7. Synchronize the NCOs (using SYNC or using SYSREF); see the NCO synchronization register
8. Write a 1 to the NCO_ALM register bit to clear it
9. Monitor the NCO_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
10. If the frequency or phase registers are changed while the NCO is enabled, the NCOs can get out of
synchronization
11. Repeat steps 7-9
12. If the device enters and exits global power down, repeat steps 7-9
7.3.9.2 Clock Upset Detection
The CLK_ALM register bit indicates if the internal clocks have been upset. The clocks in channel A are
continuously compared to channel B. If the clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register
bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to function
properly, follow these steps:
1.
2.
3.
4.
5.
6.
Program JESD_EN = 0
Ensure the part is configured to use both channels (PD_ACH = 0, PD_BCH = 0)
Program JESD_EN = 1
Write CLK_ALM = 1 to clear CLK_ALM
Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and must be
cleared by writing a 1 to CLK_ALM
7.3.9.3 FIFO Upset Detection
The FIFO_ALM bit indicates if an underflow or overflow condition has occurred on any of the JESD204C
serializer lanes within the synchronizing FIFO between the digital logic block and serializer outputs. The
FIFO_LANE_ALM register bits can be used to determine which lane triggered the underflow or overflow condition
alarm. If the FIFO pointers are upset due to an undesired clock shift or other single event or incorrect clocking
frequencies the FIFO_LANE_ALM bit for the erroneous lane will be set to 1. If the INIT_ON_FIFO_ALM bit is set
then the serializers, FIFO and JESD204C block will automatically reinitialize.
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7.4 Device Functional Modes
The ADC12DJ5200RF can be configured to operate in a number of functional modes. These modes are
described in this section.
7.4.1 Dual-Channel Mode
ADC12DJ5200RF can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency
(fS = fCLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs
for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the
desired configuration as described in Table 22. The analog inputs can be swapped by setting DUAL_INPUT (see
the input mux control register). One channel can be powered down to operate ADC12DJ5200RF as a single
channel at the maximum sampling rate of dual channel mode to save power compared to single channel mode
operating at half the rate.
7.4.2 Single-Channel Mode (DES Mode)
ADVANCE INFORMATION
The ADC12DJ5200RF can also be used as a single-channel ADC where the sampling rate is equal to two times
the clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two
ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by
setting JMODE to the appropriate setting for the desired configuration as described in Table 22. INA± or INB±,
can serve as the input to the ADC, however INA± is recommended for highest performance. The analog input
can be selected using SINGLE_INPUT (see the input mux control register).
7.4.3 JESD204C Modes
The ADC12DJ5200RF can be programmed as a single-channel or dual-channel ADC, with or without decimation,
and a number JESD204C output formats. Table 20 summarizes the basic operating mode configuration
parameters and whether they are user configured or derived.
Table 20. ADC12DJ5200RF Operating Mode Configuration Parameters
PARAMETER
DESCRIPTION
USER CONFIGURED
OR DERIVED
VALUE
JMODE
JESD204C operating mode, automatically
derives the rest of the JESD204C
parameters, single-channel or dual-channel
mode and the decimation factor
User configured
Set by JMODE (see the JESD204C mode
register)
D
Decimation factor
Derived
See Table 22
DES
1 = single-channel mode, 0 = dual-channel
mode
Derived
See Table 22
R
Number of bits transmitted per lane per
CLK+/– cycle. The JESD204C line rate is
the CLK+/– frequency times R. This
parameter sets the SerDes PLL
multiplication factor or controls bypassing of
the SerDes PLL.
Derived
See Table 22
Links
Number of JESD204C links used
Derived
See Table 22
K
Number of frames per multiframe (8B/10B
mode)
User configured
Set by KM1 (see the JESD204C K
parameter register), see the allowed values
in Table 22. This parameter is ignored in
64B/66B modes.
E
Number of multiblocks per extended
multiblock (64B/66B mode)
Derived
Always set to '1' in ADC12DJ5200RF. This
parameter is ignored in 8B/10B modes.
There are a number of parameters required to define the JESD204C transport layer format, all of which are sent
across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the
ILAS, however the transport layer uses the same parameters. In the ADC12DJ5200RF, most parameters are
automatically derived based on the selected JMODE; however, a few are configured by the user. Table 21
describes these parameters.
60
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Table 21. JESD204C Initial Lane Alignment Sequence Parameters
DESCRIPTION
USER CONFIGURED
OR DERIVED
VALUE
ADJCNT
LMFC adjustment amount (not applicable)
Derived
Always 0
ADJDIR
LMFC adjustment direction (not applicable)
Derived
Always 0
BID
Bank ID
Derived
Always 0
CF
Number of control words per frame
Derived
Always 0
CS
Control bits per sample
Derived
Always set to 0 in ILAS, see Table 22 for
actual usage
DID
Device identifier, used to identify the link
User configured
Set by DID (see the JESD204C DID
parameter register), see Table 23
F
Number of octets (bytes) per frame (per
lane)
Derived
See Table 22
HD
High-density format (samples split between
lanes)
Derived
Always 0
JESDV
JESD204 standard revision
Derived
Always 1
K
Number of frames per multiframe
User configured
Set by the KM1 register, see the JESD204C
K parameter register
L
Number of serial output lanes per link
Derived
See Table 22
LID
Lane identifier for each lane
Derived
See Table 23
M
Number of converters used to determine
lane bit packing; may not match number of
ADC channels in the device
Derived
See Table 22
N
Sample resolution (before adding control
and tail bits)
Derived
See Table 22
N'
Bits per sample after adding control and tail
bits
Derived
See Table 22
S
Number of samples per converter (M) per
frame
Derived
See Table 22
SCR
Scrambler enabled
User configured
Set by the JESD204C control register
SUBCLASSV
Device subclass version
Derived
Always 1
RES1
Reserved field 1
Derived
Always 0
RES2
Reserved field 2
Derived
Always 0
CHKSUM
Checksum for ILAS checking (sum of all
above parameters modulo 256)
Derived
Computed based on parameters in this table
Configuring the ADC12DJ5200RF is made easy by using a single configuration parameter called JMODE (see
the JESD204C mode register). Using Table 22, the correct JMODE value can be found for the desired operating
mode. The modes listed in Table 22 are the only available operating modes. This table also gives a range and
allowable step size for the K parameter (set by KM1, see the JESD204C K parameter register), which sets the
multiframe length in number of frames.
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Table 22. ADC12DJ5200RF Operating Modes
USER-SPECIFIED
PARAMETER
ADC12DJ5200RF OPERATING MODE
DERIVED PARAMETERS
INPUT
CLOCK
RANGE
(MHz)
ADVANCE INFORMATION
JMODE
K
[Min:Step:Max]
Encoding
D
DES
LINKS
N
CS
N’
L
(Per
Link)
M
(Per
Link)
F
S
HD
E
R
(Fbit /
Fclk)
12-bit, single channel, DDC bypass, 8 lanes
0
3:1:256
8B/10B
1
1
2
12
0
12
4
4 (1)
8
5
0
—
4
800-4290
12-bit, single channel, DDC bypass, 16 lanes
1
3:1:256
8B/10B
1
1
2
12
0
12
8
8 (1)
8
5
0
—
2
800-5200
12-bit, dual channel, DDC bypass, 8 lanes
2
3:1:256
8B/10B
1
0
2
12
0
12
4
4 (1)
8
5
0
—
4
800-4290
12-bit, dual channel, DDC bypass, 16 lanes
3
3:1:256
8B/10B
1
0
2
12
0
12
8
8 (1)
8
5
0
—
2
800-5200
8-bit, single channel, 8 lanes
5
18:2:256
8B/10B
1
1
2
8
0
8
4
1
1
4
0
—
2.5
800-5200
8-bit, dual channel, 8 lanes
7
18:2:256
8B/10B
1
0
2
8
0
8
4
1
1
4
0
—
2.5
800-5200
15-bit, dual channel, decimate-by-4, 4 lanes
10
9:1:256
8B/10B
4
0
2
15
1
16
2
2
2
1
0
—
5
800-3432
15-bit, dual channel, decimate-by-4, 8 lanes
11
9:1:256
8B/10B
4
0
2
15
1
16
4
2
2
2
0
—
2.5
800-5200
15-bit, dual channel, decimate-by-8, 2 lanes
13
5:1:256
8B/10B
8
0
2
15
1
16
1
2
4
1
0
—
5
800-3432
15-bit, dual channel, decimate-by-8, 4 lanes
14
9:1:256
8B/10B
8
0
2
15
1
16
2
2
2
1
0
—
2.5
800-5200
12-bit, single channel, 12 lanes
19
9:1:256
8B/10B
1
1
2
12
0
12
6
1
2
8
1
—
2.5
800-5200
12-bit, dual channel, 12 lanes
20
9:1:256
8B/10B
1
0
2
12
0
12
6
1
2
8
1
—
2.5
800-5200
15-bit, single channel, decimate-by-4, 4 lanes
21
9:1:256
8B/10B
4
1
2
15
1
16
2
1
2
2
0
—
5
800-3432
15-bit, single channel, decimate-by-4, 8 lanes
22
9:1:256
8B/10B
4
1
2
15
1
16
4
1
2
4
0
—
2.5
800-5200
15-bit, single channel, decimate-by-8, 2 lanes
23
9:1:256
8B/10B
8
1
2
15
1
16
1
1
2
1
0
—
5
800-3432
15-bit, single channel, decimate-by-8, 4 lanes
24
9:1:256
8B/10B
8
1
2
15
1
16
2
1
2
2
0
—
2.5
800-5200
12-bit, single channel, DDC bypass, 8 lanes
30
32 (2)
64B/66B
1
1
2
12
0
12
4
4 (1)
8
5
0
1
3.3
800-5200
12-bit, dual channel, DDC bypass, 8 lanes
31
32
(2)
64B/66B
1
0
2
12
0
12
4
(1)
8
5
0
1
3.3
800-5200
12-bit, single channel, DDC bypass, 6 lanes
32
128 (2)
64B/66B
1
1
2
12
0
12
3
1
2
4
1
1
4.125
800-4160
12-bit, dual channel, DDC bypass, 6 lanes
33
128 (2)
64B/66B
1
0
2
12
0
12
3
1
2
4
1
1
4.125
800-4160
8-bit, single channel, DDC bypass, 4 lanes
34
256
(2)
64B/66B
1
1
2
8
0
8
2
1
1
2
0
1
4.125
800-4160
8-bit, dual channel, DDC bypass, 4 lanes
35
256 (2)
64B/66B
1
0
2
8
0
8
2
1
1
2
0
1
4.125
800-4160
15-bit, single channel, decimate-by-4, 4 lanes
36
128 (2)
64B/66B
4
1
2
15
1
16
2
1
2
2
0
1
4.125
800-4160
15-bit, dual channel, decimate-by-4, 4 lanes
37
128 (2)
64B/66B
4
0
2
15
1
16
2
2
2
1
0
1
4.125
800-4160
15-bit, single channel, decimate-by-8, 2 lanes
38
128
(2)
64B/66B
8
1
2
15
1
16
1
1
2
1
0
1
4.125
800-4160
15-bit, dual channel, decimate-by-8, 2 lanes
39
64 (2)
64B/66B
8
0
2
15
1
16
1
2
4
1
0
1
4.125
800-4160
4, 8, 9,
15-18,
25-29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RESERVED
(1)
(2)
62
4
M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter does not represent the actual number of
converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see mode diagrams for more details.
In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K=8*32*E/F. K is not an actual parameter of the 64B/66B link layer.
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The ADC12DJ5200RF has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204C
links. All operating modes use two links with up to eight lanes per link. The lanes and their derived configuration
parameters are described in Table 23. For a specified JMODE, the lowest indexed lanes for each link are used
and the higher indexed lanes for each link are automatically powered down. Always route the lowest indexed
lanes to the logic device.
Table 23. ADC12DJ5200RF Lane Assignment and Parameters
JESD204C LINK
DID (User Configured)
LID (Derived)
DA0±
0
DA1±
1
DA2±
2
DA3±
Set by DID (see the JESD204C DID parameter
register), the effective DID is equal to the DID register
setting (DID)
A
DA4±
3
4
DA5±
5
DA6±
6
DA7±
7
DB0±
0
DB1±
1
DB2±
2
DB3±
Set by DID (see the JESD204C DID parameter
register), the effective DID is equal to the DID register
setting plus 1 (DID+1)
B
DB4±
3
4
DB5±
5
DB6±
6
DB7±
7
7.4.3.1 JESD204C Transport Layer Data Formats
Output data are formatted in a specific optimized fashion for each JMODE setting based on the transport layer
settings for that JMODE. When the DDC is not used (decimation = 1) the 12-bit offset binary values are mapped
into octets. For the DDC mode, the 16-bit values (15-bit complex data plus 1 overrange bit) are mapped into
octets. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol
definitions used in the JMODE tables is provided in Table 24. In all mappings the tail bits (T) are 0 (zero). All
samples are formatted as MSB first, LSB last.
Table 24. JMODE Table Symbol Definitions
NOTATION
MODE
DESCRIPTION
S[n]
Single channel, DDC bypassed
A[n]
Dual channel, DDC bypassed
Sample n from channel A in dual channel mode when DDC is bypassed
B[n]
Dual channel, DDC bypassed
Sample n from channel A in dual channel mode when DDC is bypassed
Sample n from ADC in single channel mode when DDC is bypassed
T
—
AI[n], AQ[n]
Dual channel, DDC enabled
Tail bits, always set to 0
Complex I/Q sample n from DDC A in dual channel mode
BI[n], BQ[n]
Dual channel, DDC enabled
Complex I/Q sample n from DDC B in dual channel mode
ORA0[n]
Dual channel, DDC enabled
Overrange flag for channel A, set high if channel A sample n exceeds
overrange threshold 0 (OVR_T0)
ORA1[n]
Dual channel, DDC enabled
Overrange flag for channel A, set high if channel A sample n exceeds
overrange threshold 1 (OVR_T1)
ORB0[n]
Dual channel, DDC enabled
Overrange flag for channel B, set high if channel B sample n exceeds
overrange threshold 0 (OVR_T0)
ORB1[n]
Dual channel, DDC enabled
Overrange flag for channel B, set high if channel B sample n exceeds
overrange threshold 1 (OVR_T1)
I[n], Q[n]
Single channel, DDC enabled
Complex I/Q sample n from the DDC in single channel mode
OR0[n]
Single channel, DDC enabled
Overrange flag, set high if sample n exceeds overrange threshold 0 (OVR_T0)
OR1[n]
Single channel, DDC enabled
Overrange flag, set high if sample n exceeds overrange threshold 1 (OVR_T1)
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Table 25. JMODE 0 (12-bit, Single Channel, DDC Bypass, 8 lanes, 8B/10B)
OCTET
NIBBLE
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
DA0
S[0]
S[8]
S[16]
S[24]
S[32]
T
DA1
S[2]
S[10]
S[18]
S[26]
S[34]
T
DA2
S[4]
S[12]
S[20]
S[28]
S[36]
T
DA3
S[6]
S[14]
S[22]
S[30]
S[38]
T
DB0
S[1]
S[9]
S[17]
S[25]
S[33]
T
DB1
S[3]
S[11]
S[19]
S[27]
S[35]
T
DB2
S[5]
S[13]
S[21]
S[29]
S[37]
T
DB3
S[7]
S[15]
S[23]
S[31]
S[39]
T
Table 26. JMODE 1 (12-bit, Single Channel, DDC Bypass, 16 lanes, 8B/10B)
OCTET
NIBBLE
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
ADVANCE INFORMATION
DA0
S[0]
S[16]
S[32]
S[48]
S[64]
T
DA1
S[2]
S[18]
S[34]
S[50]
S[66]
T
DA2
S[4]
S[20]
S[36]
S[52]
S[68]
T
DA3
S[6]
S[22]
S[38]
S[54]
S[70]
T
DA4
S[8]
S[24]
S[40]
S[56]
S[72]
T
DA5
S[10]
S[26]
S[42]
S[58]
S[74]
T
DA6
S[12]
S[28]
S[44]
S[60]
S[76]
T
DA7
S[14]
S[30]
S[46]
S[62]
S[78]
T
DB0
S[1]
S[17]
S[33]
S[49]
S[65]
T
DB1
S[3]
S[19]
S[35]
S[51]
S[67]
T
DB2
S[5]
S[21]
S[37]
S[53]
S[69]
T
DB3
S[7]
S[23]
S[39]
S[55]
S[71]
T
DB4
S[9]
S[25]
S[41]
S[57]
S[73]
T
DB5
S[11]
S[27]
S[43]
S[59]
S[75]
T
DB6
S[13]
S[29]
S[45]
S[61]
S[77]
T
DB7
S[15]
S[31]
S[47]
S[63]
S[79]
T
Table 27. JMODE 2 (12-Bit, Dual Channel, DDC Bypass, 8 Lanes, 8B/10B)
OCTET
NIBBLE
64
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
DA0
A[0]
A[4]
A[8]
A[12]
A[16]
T
DA1
A[1]
A[5]
A[9]
A[13]
A[17]
T
DA2
A[2]
A[6]
A[10]
A[14]
A[18]
T
DA3
A[3]
A[7]
A[11]
A[15]
A[19]
T
DB0
B[0]
B[4]
B[8]
B[12]
B[16]
T
DB1
B[1]
B[5]
B[9]
B[13]
B[17]
T
DB2
B[2]
B[6]
B[10]
B[14]
B[18]
T
DB3
B[3]
B[7]
B[11]
B[15]
B[19]
T
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Table 28. JMODE 3 (12-Bit, Dual Channel, DDC Bypass, 16 Lanes, 8B/10B)
0
0
1
1
2
2
3
4
3
5
6
4
7
5
8
9
10
6
11
12
7
13
14
15
DA0
A[0]
A[8]
A[16]
A[24]
A[32]
T
DA1
A[1]
A[9]
A[17]
A[25]
A[33]
T
DA2
A[2]
A[10]
A[18]
A[26]
A[34]
T
DA3
A[3]
A[11]
A[19]
A[27]
A[35]
T
DA4
A[4]
A[12]
A[20]
A[28]
A[36]
T
DA5
A[5]
A[13]
A[21]
A[29]
A[37]
T
DA6
A[6]
A[14]
A[22]
A[30]
A[38]
T
DA7
A[7]
A[15]
A[23]
A[31]
A[39]
T
DB0
B[0]
B[8]
B[16]
B[24]
B[32]
T
DB1
B[1]
B[9]
B[17]
B[25]
B[33]
T
DB2
B[2]
B[10]
B[18]
B[26]
B[34]
T
DB3
B[3]
B[11]
B[19]
B[27]
B[35]
T
DB4
B[4]
B[12]
B[20]
B[28]
B[36]
T
DB5
B[5]
B[13]
B[21]
B[29]
B[37]
T
DB6
B[6]
B[14]
B[22]
B[30]
B[38]
T
DB7
B[7]
B[15]
B[23]
B[31]
B[39]
T
ADVANCE INFORMATION
OCTET
NIBBLE
Table 29. JMODE 5 (8-bit, Single Channel, 8 Lanes, 8B/10B)
OCTET
NIBBLE
0
0
1
DA0
S[0]
DA1
S[2]
DA2
S[4]
DA3
S[6]
DB0
S[1]
DB1
S[3]
DB2
S[5]
DB3
S[7]
Table 30. JMODE 7 (8-bit, Single Channel, 8 Lanes, 8B/10B)
OCTET
NIBBLE
0
0
1
DA0
A[0]
DA1
A[1]
DA2
A[2]
DA3
A[3]
DB0
B[0]
DB1
B[1]
DB2
B[2]
DB3
B[3]
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Table 31. JMODE 10 (15-bit, Dual Channel, Decimate-by-4, 4 lanes, 8B/10B)
OCTET
0
NIBBLE
1
0
1
2
DA0
AI[0], ORA0[0]
DA1
AQ[0], ORA1[0]
DB0
BI[0], ORB0[0]
DB1
BQ[0], ORB1[0]
3
Table 32. JMODE 11 (15-bit, Dual Channel, Decimate-by-4, 8 lanes, 8B/10B)
OCTET
0
NIBBLE
1
0
1
DA0
2
3
AI[0], ORA0[0]
DA1
AI[1], ORA0[1]
DA2
AQ[0], ORA1[0]
DA3
AQ[1], ORA1[1]
DB0
BI[0], ORB0[0]
ADVANCE INFORMATION
DB1
BI[1], ORB0[1]
DB2
BQ[0], ORB1[0]
DB3
BQ[1], ORB1[1]
Table 33. JMODE 13 (15-bit, Dual Channel, Decimate-by-8, 2 lanes, 8B/10B)
OCTET
0
NIBBLE
0
1
1
2
2
3
4
3
5
6
DA0
AI[0], ORA0[0]
AQ[0], ORA1[0]
DB0
BI[0], ORB0[0]
BQ[0], ORB1[0]
7
Table 34. JMODE 14 (15-bit, Dual Channel, Decimate-by-8, 4 lanes, 8B/10B)
OCTET
NIBBLE
66
0
0
1
1
2
DA0
AI[0], ORA0[0]
DA1
AQ[0], ORA1[0]
DB0
BI[0], ORB0[0]
DB1
BQ[0], ORB1[0]
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Table 35. JMODE 19 (12-bit, Single Channel, DDC Bypass, 12 lanes, 8B/10B)
OCTET
NIBBLE
0
0
DA0
S[10][11:8]
S[10][7:0]
S[12][11:4]
S[12][3:0]
S[14][11:0]
DB0
S[1][11:0]
DB1
S[3][11:8]
S[3][7:0]
S[5][11:4]
S[5][3:0]
S[7][11:0]
DB3
S[9][11:0]
DB4
DB5
S[4][11:4]
S[6][11:0]
S[8][11:0]
DA4
DB2
3
S[2][11:8]
S[2][7:0]
S[4][3:0]
DA3
DA5
2
S[0][11:0]
DA1
DA2
1
1
S[11][11:8]
S[11][7:0]
S[13][11:4]
S[13][3:0]
S[15][11:0]
Table 36. JMODE 20 (12-bit, Dual Channel, DDC Bypass, 12 lanes, 8B/10B)
0
0
DA0
A[5][11:8]
A[5][7:0]
A[6][11:4]
A[6][3:0]
A[7][11:0]
DB0
B[0][11:0]
DB1
B[1][11:8]
B[1][7:0]
B[2][11:4]
B[2][3:0]
B[3][11:0]
DB3
B[4][11:0]
DB4
DB5
A[2][11:4]
A[3][11:0]
A[4][11:0]
DA4
DB2
3
A[1][11:8]
A[1][7:0]
A[2][3:0]
DA3
DA5
2
A[0][11:0]
DA1
DA2
1
1
ADVANCE INFORMATION
OCTET
NIBBLE
B[5][11:8]
B[5][7:0]
B[6][3:0]
B[6][11:4]
B[7][11:0]
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Table 37. JMODE 21 (15-bit, Single Channel, Decimate-by-4, 4 lanes, 8B/10B)
OCTET
NIBBLE
0
0
DA0
1
I[0], OR0[0]
DA1
I[1], OR0[1]
DB0
Q[0], OR1[0]
DB1
Q[1], OR1[1]
Table 38. JMODE 22 (15-bit, Single Channel, Decimate-by-4, 8 lanes, 8B/10B)
OCTET
NIBBLE
0
0
1
DA0
I[0], OR0[0]
DA1
I[1], OR0[1]
DA2
I[2], OR0[2]
ADVANCE INFORMATION
DA3
I[3], OR0[3]
DB0
Q[0], OR1[0]
DB1
Q[1], OR1[1]
DB2
Q[2], OR1[2]
DB3
Q[3], OR1[3]
Table 39. JMODE 23 (15-bit, Single Channel, Decimate-by-8, 2 lanes, 8B/10B)
OCTET
NIBBLE
0
0
1
DA0
I[0], OR0[0]
DB0
Q[0], OR1[0]
Table 40. JMODE 24 (15-bit, Single Channel, Decimate-by-8, 4 lanes, 8B/10B)
OCTET
NIBBLE
0
0
DA0
68
1
I[0], OR0[0]
DA1
I[1], OR0[1]
DB0
Q[0], OR1[0]
DB1
Q[1], OR1[1]
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Table 41. JMODE 30 (12-bit, Single Channel, DDC Bypass, 8 lanes, 64B/66B)
OCTET
NIBBLE
0
1
0
1
2
2
3
4
3
5
4
6
7
8
5
9
10
6
11
12
7
13
14
15
DA0
S[0]
S[8]
S[16]
S[24]
S[32]
T
DA1
S[2]
S[10]
S[18]
S[26]
S[34]
T
DA2
S[4]
S[12]
S[20]
S[28]
S[36]
T
DA3
S[6]
S[14]
S[22]
S[30]
S[38]
T
DB0
S[1]
S[9]
S[17]
S[25]
S[33]
T
DB1
S[3]
S[11]
S[19]
S[27]
S[35]
T
DB2
S[5]
S[13]
S[21]
S[29]
S[37]
T
DB3
S[7]
S[15]
S[23]
S[31]
S[39]
T
Table 42. JMODE 31(12-Bit, Dual Channel, DDC Bypass, 8 Lanes, 64B/66B)
0
1
0
1
2
2
3
4
DA0
A[0]
A[4]
DA1
A[1]
DA2
A[2]
DA3
3
5
4
6
7
8
5
9
10
6
11
12
7
13
14
15
A[8]
A[12]
A[16]
T
A[5]
A[9]
A[13]
A[17]
T
A[6]
A[10]
A[14]
A[18]
T
A[3]
A[7]
A[11]
A[15]
A[19]
T
DB0
B[0]
B[4]
B[8]
B[12]
B[16]
T
DB1
B[1]
B[5]
B[9]
B[13]
B[17]
T
DB2
B[2]
B[6]
B[10]
B[14]
B[18]
T
DB3
B[3]
B[7]
B[11]
B[15]
B[19]
T
ADVANCE INFORMATION
OCTET
NIBBLE
Table 43. JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes, 64B/66B)
OCTET
NIBBLE
0
0
DA0
3
S[2][11:8]
S[2][7:0]
S[4][11:4]
S[4][3:0]
S[6][11:0]
DB0
S[1][11:0]
DB1
DB2
2
S[0][11:0]
DA1
DA2
1
1
S[3][11:8]
S[3][7:0]
S[5][11:4]
S[5][3:0]
S[7][11:0]
Table 44. JMODE 33 (12-bit, Dual Channel, DDC Bypass, 6 lanes, 64B/66B)
OCTET
NIBBLE
0
0
DA0
3
A[1][11:8]
A[1][7:0]
A[2][11:4]
A[2][3:0]
A[3][11:0]
DB0
B[0][11:0]
DB1
DB2
2
A[0][11:0]
DA1
DA2
1
1
B[1][11:8]
B[1][7:0]
B[2][3:0]
B[2][11:4]
B[3][11:0]
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Table 45. JMODE 34 (8-bit, Single Channel, 4 lanes, 64B/66B)
OCTET
0
NIBBLE
0
1
DA0
S[0]
DA1
S[2]
DB0
S[1]
DB1
S[3]
Table 46. JMODE 35 (8-bit, Dual Channel, 4 lanes, 64B/66B)
OCTET
0
NIBBLE
0
1
DA0
A[0]
DA1
A[1]
DB0
B[0]
DB1
B[1]
ADVANCE INFORMATION
Table 47. JMODE 36 (15-bit, Single Channel, Decimate-by-4, 4 lanes, 64B/66B)
OCTET
0
NIBBLE
0
1
DA0
I[0], OR0[0]
DA1
I[1], OR0[1]
DB0
Q[0], OR1[0]
DB1
Q[1], OR1[1]
Table 48. JMODE 37 (15-bit, Dual Channel, Decimate-by-4, 4 lanes, 64B/66B)
OCTET
0
NIBBLE
1
0
1
2
DA0
AI[0], ORA0[0]
DA1
AQ[0], ORA1[0]
DB0
BI[0], ORB0[0]
DB1
BQ[0], ORB1[0]
3
Table 49. JMODE 38 (15-bit, Single Channel, Decimate-by-8, 2 lanes, 64B/66B)
OCTET
0
NIBBLE
0
1
DA0
I[0], OR0[0]
DB0
Q[0], OR1[0]
Table 50. JMODE 39 (15-bit, Dual Channel, Decimate-by-8, 2 lanes, 64B/66B)
OCTET
NIBBLE
70
0
0
1
1
2
2
3
4
3
5
6
DA0
AI[0], ORA0[0]
AQ[0], ORA1[0]
DB0
BI[0], ORB0[0]
BQ[0], ORB1[0]
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7.4.3.2 64B/66B Sync Header Stream Configuration
The sync header stream can be used to identify bit errors on the link or to correct bit errors. Two modes of
operation are available in ADC12DJ5200RF. Cyclic redundancy checking (CRC) can be used to identify bit
errors. ADC12DJ5200RF only supports 12-bit CRC (CRC-12) and does not support the optional 3-bit CRC-3
described by JESD204C. Alternatively, forward error correction (FEC) can be used to identify bit errors and then
correct bit errors. For information on CRC-12, see Cyclic Redundancy Check (CRC) Mode. For information on
FEC, see Forward Error Correction (FEC) Mode. Set the sync header stream configuration by using the sync
header mode register.
7.4.3.3 Dual DDC and Redundant Data Mode
Additionally, DIG_BIND_A or DIG_BIND_B can be used to provide redundant data to separate digital processors
by routing data from one ADC channel to both JESD204C links. Redundant data mode is available for all
JMODE modes except for the single-channel modes. Both dual DDC mode and redundant data mode are
demonstrated in Figure 19 where the data for ADC channel A is routed to both DDCs and then transmitted to a
single processor or two processors (for redundancy).
DDC A
DIG_BIND_A = 0
DDC Bypass
MUX
ADC
Channel A
MUX
DDC Bypass
JESD204C
LINK A
(DA0-DA7)
ADC
Channel B
DDC B
MUX
MUX
JMODE
JESD204C
LINK B
(DB0-DB7)
JMODE
DIG_BIND_B = 0
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Figure 19. Dual DDC Mode or Redundant Data Mode for Channel A
7.4.4 Power-Down Modes
The PD input pin allows the ADC12DJ5200RF devices to be entirely powered down. Power-down can also be
controlled by MODE (see the device configuration register). To power down only one channel in dual channel
mode use the channel power down register. The serial data output drivers are disabled when PD is high. When
the device returns to normal operation, the JESD204 link must be re-established, and the ADC pipeline and
decimation filters contain meaningless information so the system must wait a sufficient time for the data to be
flushed.
7.4.5 Test Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.5.1 Serializer Test-Mode Details
Test modes are enabled by setting JTEST (see the JESD204C test pattern control register) to the desired test
mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer
outputs (number of lanes, rate) are powered up based on JMODE. Only enable the test modes when the
JESD204C link is disabled. Figure 20 provides a diagram showing the various test mode insertion points.
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ADVANCE INFORMATION
When operating in dual-channel mode, the data from one channel can be routed to both digital down-converter
blocks by using DIG_BIND_A or DIG_BIND_B (see the digital channel binding register). This feature enables
down-conversion of two separate captured bands from a single ADC channel. The second ADC can be powered
down in this mode by setting PD_ACH or PD_BCH (see the channel power down register).
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ADC
JESD204C Block
TRANSPORT
LAYER
ADC
SCRAMBLER
Short Transport Test
Long Transport Test
Octet Ramp
LINK LAYER
8B/10B or
64B/66B
Encoder
Repeated ILA*
Modified RPAT*
K28.5*
D21.5
SERDES
TX
Active Lanes and
Serial Rates
Set by JMODE
PRBS
Clock Pattern
Serial Outputs High/Low
* Applies only to JMODEs using 8B/10B encoding
Figure 20. Test Mode Insertion Points
7.4.5.2 PRBS Test Modes
ADVANCE INFORMATION
The PRBS test modes bypass the JESD204C transport layer and link layer and are therefore neither scrambled
nor encoded. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150
specification. These bit streams are used with lab test equipment or logic devices that can self-synchronize to the
bit pattern. The initial phase of the pattern is not defined since the receiver self synchronizes.
The sequences are defined by a recursive equation. For example, Equation 14 defines the PRBS7 sequence.
y[n] = y[n – 6]⊕y[n – 7]
where
•
bit n is the XOR of bit [n – 6] and bit [n – 7], which are previously transmitted bits
(14)
Table 51 lists equations and sequence lengths for the available PRBS test modes where ⊕ is the XOR operation
and y[n] represents bit n in the PRBS sequence. The initial phase of the pattern is unique for each lane.
Table 51. PBRS Mode Equations
PRBS TEST MODE
SEQUENCE
SEQUENCE LENGTH (bits)
PRBS7
y[n] = y[n – 6]⊕y[n – 7]
127
PRBS9
y[n] = y[n – 5]⊕y[n – 9]
511
PRBS15
y[n] = y[n – 14]⊕y[n – 15]
32,767
PRBS23
y[n] = y[n – 18]⊕y[n – 23]
8,388,607
PRBS31
y[n] = y[n – 28]⊕y[n – 31]
2,147,483,647
7.4.5.3 Clock Pattern Mode
In the clock pattern mode, the JESD204C transport layer and link layer are bypassed, so the test sequence is
neither scrambled nor encoded. The pattern consists of a 16-bit long sequence of 8 ones and 8 zeros (1111
1111 0000 0000) that repeats indefinitely.
7.4.5.4 Ramp Test Mode
In the ramp test mode, the JESD204C link layer operates normally, but the transport layer is disabled and the
input from the formatter is ignored. In 8B/10B modes, the pattern begins after the ILA sequence finishes. In
64B/66B mode, the pattern begins after the serializers are initialized. Each lane transmits an identical octet
stream that is encoded and scrambled by the link layer. The octet stream increments from 0x00 to 0xFF and
repeats. This mode is available for both 8B/10B and 64B/66B modes.
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7.4.5.5 Short and Long Transport Test Mode
JESD204C defines both short and long transport test modes to verify that the transport layers in the transmitter
and receiver are operating correctly. The ADC12DJ5200RF has three different short transport layer test patterns
depending on the N' value of the specified JMODE (see Table 22). The short transport layer is only used when
control bits are not used. Otherwise, the long transport test mode must be used. ADC12DJ5200RF supports the
long transport test mode for all N' = 16 modes, since these modes use control bits. The transport layer test
modes are the same for 8B/10B mode and 64B/66B modes with identical N' values, since the transport layer is
independent of the link layer.
7.4.5.5.1 Short Transport Test Pattern
Short transport test patterns send a predefined octet format that repeats every frame. In the ADC12DJ5200RF,
all JMODE configurations that have an N' value of 8 or 12 use the short transport test pattern. The N' = 8 short
transport test pattern is shown in Table 52. The N' = 12 test patterns are shown in Table 53 and Table 54 which
cover two different values of F (F = 8, F = 2). All applicable lanes are shown, however only the enabled lanes
(lowest indexed) for the configured JMODE are used.
FRAME
0
1
DA0
0x00
0xFF
DA1
0x01
0xFE
DA2
0x02
0xFD
DA3
0x03
0xFC
DB0
0x00
0xFF
DB1
0x01
0xFE
DB2
0x02
0xFD
DB3
0x03
0xFC
ADVANCE INFORMATION
Table 52. Short Transport Test Pattern for N' = 8 Modes (Length = 2 Frames)
Table 53. Short Transport Test Pattern for N' = 12, F = 8 Modes (Length = 1 Frame)
OCTET
NIBBLE
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
DA0
0xF01
0xF02
0xF03
0xF04
0xF05
T
DA1
0xE11
0xE12
0xE13
0xE14
0xE15
T
DA2
0xD21
0xD22
0xD23
0xD24
0xD25
T
DA3
0xC31
0xC32
0xC33
0xC34
0xC35
T
DA4
0xB41
0xB42
0xB43
0xB44
0xB45
T
DA5
0xA51
0xA52
0xA53
0xA54
0xA55
T
DA6
0x961
0x962
0x963
0x964
0x965
T
DA7
0x871
0x872
0x873
0x874
0x875
T
DB0
0xF01
0xF02
0xF03
0xF04
0xF05
T
DB1
0xE11
0xE12
0xE13
0xE14
0xE15
T
DB2
0xD21
0xD22
0xD23
0xD24
0xD25
T
DB3
0xC31
0xC32
0xC33
0xC34
0xC35
T
DB4
0xB41
0xB42
0xB43
0xB44
0xB45
T
DB5
0xA51
0xA52
0xA53
0xA54
0xA55
T
DB6
0x961
0x962
0x963
0x964
0x965
T
DB7
0x871
0x872
0x873
0x874
0x875
T
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Table 54. Short Transport Test Pattern for N' = 12, F = 2 Modes (Length = 1 Frame)
OCTET
NIBBLE
0
0
DA0
0xF
0x01
0x23
0x4
0x567
DB0
0x012
DB1
0x3
0x45
0x67
0x8
0x9AB
DB3
0xCDE
DB4
DB5
0x67
0x9AB
0xCDE
DA4
DB2
3
0x3
0x45
0x8
DA3
DA5
2
0x012
DA1
DA2
1
1
0xF
0x01
0x4
0x23
0x567
7.4.5.5.2 Long Transport Test Pattern
ADVANCE INFORMATION
The long-transport test mode is used in all of the JMODE modes where N' equals 16 due to the use of control
bits. Patterns are generated in accordance with the JESD204C standard and are different for each output format
as defined in Table 22. The rules for the pattern are defined below. Equation 15 gives the length of the test
pattern. The long transport test pattern is the same for link A and link B, where DAx lanes belong to link A and
DBx lanes belong to link B.
Long Test Pattern Length (Frames) = K × ceil[(M × S + 2) / K]
•
•
(15)
Sample Data:
– Frame 0: Each sample contains N bits, with all samples set to the converter ID (CID) plus 1 (CID + 1). The
CID is defined based on the converter number within the link; two links are used in all modes. Within a
link, the converters are numbered by channel (A or B) and in-phase (I) and quadrature-phase (Q). The
numbering resets for the second link. For instance, in JMODE 11, channel A and channel B data are
separated into separate links (Link A and Link B). The in-phase component for each channel has CID = 0
and the quadrature-phase component has CID = 1.
– Frame 1: Each sample contains N bits, with each sample (for each converter) set as its individual sample
ID (SID) within the frame plus 1 (SID + 1)
– Frame 2 +: Each sample contains N bits, with the data set to 2N–1 for all samples (for example, if N is 15
then 2N–1 = 16384)
Control Bits (if CS > 0):
– Frame 0 to M × S – 1: The control bit belonging to the sample mod (i, S) of the converter floor (i, S) is set
to 1 and all others are set to 0, where i is the frame index (i = 0 is the first frame of the pattern).
Essentially, the control bit walks from the lowest indexed sample to the highest indexed sample and from
the lowest indexed converter to the highest indexed converter, changing position every frame.
– Frame M × S +: All control bits are set to 0
Table 55 describes an example long transport test pattern for when JMODE = 10, K = 10.
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Table 55. Example Long Transport Test Pattern (JMODE = 10, K = 10)
TIME →
OCTET
NUM
0
1
2
3
4
5
6
PATTERN REPEATS →
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DA0
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
DA1
0x0004
0x0003
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0004
DB0
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
DB1
0x0004
0x0003
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0004
Frame
n
Frame
n+1
Frame
n+2
Frame
n+3
Frame
n+4
Frame
n+5
Frame
n+6
Frame
n+7
Frame
n+8
Frame
n+9
Frame
n + 10
The pattern starts at the end of the initial lane alignment sequence (ILAS) and repeats indefinitely as long as the
link remains running. For more details see the JESD204C specification, section 5.1.6.3.
7.4.5.6 D21.5 Test Mode
7.4.5.7 K28.5 Test Mode
In this test mode, the controller transmits a continuous stream of K28.5 characters. This mode only applies to
8B/10B modes.
7.4.5.8 Repeated ILA Test Mode
In this test mode, the JESD204C link layer operates normally, except that the ILA sequence (ILAS) repeats
indefinitely instead of starting the data phase. Whenever the receiver issues a synchronization request, the
transmitter initiates code group synchronization. Upon completion of code group synchronization, the transmitter
repeatedly transmits the ILA sequence. This mode only applies to 8B/10B modes.
7.4.5.9 Modified RPAT Test Mode
A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white
spectral content for JESD204C compliance and jitter testing. Table 56 lists the pattern before and after 8B/10B
encoding. This mode only applies to 8B/10B modes.
Table 56. Modified RPAT Pattern Values
OCTET NUMBER
Dx.y NOTATION
8-BIT INPUT TO 8B/10B ENCODER
0
D30.5
0xBE
1
D23.6
0xD7
2
D3.1
0x23
3
D7.2
0x47
4
D11.3
0x6B
5
D15.4
0x8F
6
D19.5
0xB3
7
D20.0
0x14
8
D30.2
0x5E
9
D27.7
0xFB
10
D21.1
0x35
11
D25.2
0x59
20b OUTPUT OF 8B/10B ENCODER
(Two Characters)
0x86BA6
0xC6475
0xD0E8D
0xCA8B4
0x7949E
0xAA665
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In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s). This
mode applies to 8B/10B and 64B/66B modes.
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7.4.6 Calibration Modes and Trimming
ADC12DJ5200RF has two calibration modes available: foreground calibration and background calibration. When
foreground calibration is initiated the ADCs are automatically taken offline and the output data becomes midcode (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to
continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC
core to take its place. Additional offset calibration features are available in both foreground and background
calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user
system.
ADC A
Interleave
Bank 0
MUX
INA+
Calibration
Signal
INA±
Bank 1
Calibration
Engine
MUX
ADC A
Output
ADC C
Interleave
Bank 2
MUX
Calibration
Signal
Calibration
Engine
Bank 3
Calibration
Engine
INB+
ADC B
MUX
ADC B
Output
Bank 4
INB±
Interleave
ADVANCE INFORMATION
ADC12DJ5200RF consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an
ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form
three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples
INA± and ADC B samples INB± in dual-channel mode and both ADC A and ADC B sample INA± (or INB±) in
single-channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in
periodically for ADC A and ADC B so that they can be calibrated without disrupting operation. Figure 21 provides
a diagram of the calibration system including labeling of the banks that make up each ADC core. When
calibration is performed the linearity, gain and offset voltage for each bank are calibrated to an internally
generated calibration signal. The analog inputs can be driven during calibration, in both foreground and
background calibration, except that when offset calibration (OS_CAL or BGOS_CAL) is used there must be no
signals (or aliased signals) near DC for proper estimation of the offset (see the Offset Calibration section).
MUX
Calibration
Signal
Calibration
Engine
Bank 5
Calibration
Engine
Figure 21. ADC12DJ5200RF Calibration System Block Diagram
In addition to calibration, a number of ADC parameters are user controllable to provide trimming for optimal
performance. These parameters include input offset voltage, ADC gain, interleaving timing, and input termination
resistance. The default trim values are programmed at the factory to unique values for each device that are
determined to be optimal at the test system operating conditions. The user can read the factory-programmed
values from the trim registers and adjust as desired. The register fields that control the trimming are labeled
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according to the input that is being sampled (INA± or INB±), the bank that is being trimmed, or the ADC core that
is being trimmed. The user is not expected to change the trim values as operating conditions change, however
optimal performance can be obtained by doing so. Any custom trimming must be done on a per device basis
because of process variations, meaning that there is no global optimal setting for all parts. See the Trimming
section for information about the available trim parameters and associated registers.
7.4.6.1 Foreground Calibration Mode
Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.
Foreground calibration always runs on power-up and the user must wait a sufficient time before programming the
device to ensure that the calibration is finished. Foreground calibration can be initiated by triggering the
calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (see the calibration
software trigger register) and is chosen by setting CAL_TRIG_EN (see the calibration pin configuration register).
Background calibration mode allows the ADC to continuously operate, with no interruption of data. This
continuous operation is accomplished by activating an extra ADC core that is calibrated and then takes over
operation for one of the other previously active ADC cores. When that ADC core is taken off-line, that ADC is
calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously,
ensuring the ADC cores always provide the optimum performance regardless of system operating condition
changes. Because of the additional active ADC core, background calibration mode has increased power
consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode
discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power
consumption in comparison with the standard background calibration mode. Background calibration can be
enabled by setting CAL_BG (see the calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and
CAL_SOFT_TRIG must be set to 1.
Great care has been taken to minimize effects on converted data as the core switching process occurs, however,
small brief glitches may still occur on the converter data as the cores are swapped.
7.4.6.3 Low-Power Background Calibration (LPBG) Mode
Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores.
Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the lowpower background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps
before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is
allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic
switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is
an increase in power consumption during the ADC core calibration. The power consumption roughly alternates
between the power consumption in foreground calibration when the spare ADC core is sleeping to the power
consumption in background calibration when the spare ADC is being calibrated. Design the power-supply
network to handle the transient power requirements for this mode.
7.4.7 Offset Calibration
Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;
however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the
standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer
offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single-channel mode
uncalibrated input buffer offsets can result in a fixed spur at fS / 2. A separate calibration is provided to correct
the input buffer offsets.
There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration
the offsets, requiring the system to ensure this condition during normal operation or have the ability to mute the
input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the
calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled via
CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for
operating condition changes. When CAL_BGOS is set, the system must ensure that there are no DC or near DC
signals or aliased signals that fall at or near DC during normal operation. Offset calibration can be performed as
a one-time operation when using background calibration by setting CAL_OS to 1 before setting CAL_EN, but
does not correct for variations as operating conditions change.
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7.4.6.2 Background Calibration Mode
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The offset calibration correction uses the input offset voltage trim registers (see Table 57) to correct the offset
and therefore must not be written by the user when offset calibration is used. The user can read the calibrated
values by reading the OADJ_x_VINy registers, where x is the ADC core and y is the input (INA± or INB±), after
calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset
calibration (CAL_OS = 1) and do not read the values when using background offset calibration (CAL_BGOS = 1).
7.4.8 Trimming
Table 57 lists the parameters that can be trimmed and the associated registers. User trimming is limited to
foreground (FG) calibration mode only.
Table 57. Trim Register Descriptions
TRIM PARAMETER
TRIM REGISTER
Band-gap reference
Input termination resistance
BG_TRIM
RTRIM_x,
where x = A for INA± or B for INB±)
NOTES
Measurement on BG output pin.
The device must be powered on with a clock applied.
ADVANCE INFORMATION
OADJ_A_FG0_VINx, OADJ_A_FG90_VINx and
OADJ_B_FG0_VINx,
where OADJ_A applies to ADC core A and
OADJ_B applies to ADC core B, FG0 applies to
dual channel mode for ADC cores A and B and
single channel mode for ADC core B, FG90 applies
to ADC core A in single channel mode and x = A for
INA± or B for INB±)
Input offset adjustment in dual channel mode consists of
changing OADJ_A_FG0_VINA for channel A and
OADJ_B_FG0_VINB for channel B. In single channel
mode, OADJ_A_FG90_VINx and OADJ_B_FG0_VINx
must be adjusted together to trim the input offset or
adjusted separate to compensate the fS/2 offset spur.
INA± and INB± gain
GAIN_Bx,
where x = bank number (0, 1, 4 or 5)
Set FS_RANGE_A and FS_RANGE_B to default values
before trimming the input. Use FS_RANGE_A and
FS_RANGE_B to adjust the full-scale input voltage. To
trim the gain of ADC core A, change GAIN_B0 and
GAIN_B1 together in the same direction. To trim the
gain of ADC core B, change GAIN_B4 and GAIN_B5
together in the same direction. To trim the gain of the
two banks within ADC A, change GAIN_B0 and
GAIN_B1 in opposite directions. To trim the gain of the
two banks within ADC B, change GAIN_B4 and
GAIN_B5 in oppositie directions.
INA± and INB± full-scale
input voltage
FS_RANGE_x,
where x = A for INA± or B for INB±)
Full-scale input voltage adjustment for each input. The
default value is effected by GAIN_Bx (x = 0, 1, 4 or 5).
Trim GAIN_Bx with FS_RANGE_x set to the default
value. FS_RANGE_x can then be used to trim the fullscale input voltage.
Input offset voltage
Intra-ADC core timing (bank
timing)
Bx_TIME_y,
where x = bank number (0, 1, 4 or 5)
and y = 0° (0) or –90° (90) clock phase
Trims the timing between the two banks of an ADC core
(ADC A or B). The 0° clock phase is used for dual
channel mode and for ADC B in single channel mode.
The –90° clock phase is used only for ADC A in singlechannel mode. A mismatch in the timing between the
two banks of an ADC core can result in an fS/2-fIN spur
in dual channel mode or fS/4±fIN spurs in single channel
mode.
TADJ_A, TADJ_B
The suffix letter (A or B) indicates the ADC core that is
being trimmed. Changing either TADJ_A or TADJ_B
adjusts the sampling instance of ADC A relative to ADC
B in dual channel mode.
TADJ_A_FG90_VINx, TADJ_B_FG0_VINx,
where x = analog input (INA± or INB±)
These trim registers are used to adjust the timing of
ADC core A relative to ADC core B in single channel
mode. A mismatch in the timing will result in an fS/2-fIN
spur that is signal dependent. Changing either
TADJ_A_FG90_VINx or TADJ_B_FG0_VINx changes
the relative timing of ADC core A relative to ADC core B
in single channel mode.
Inter-ADC core timing
(dual-channel mode)
Inter-ADC core timing
(single-channel mode)
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7.5 Programming
7.5.1 Using the Serial Interface
The serial interface is accessed using the following four pins: serial clock (SCLK), serial data in (SDI), serial data
out (SDO), and serial interface chip-select (SCS). Register access is enabled through the SCS pin.
7.5.1.1 SCS
This signal must be asserted low to access a register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
7.5.1.2 SCLK
Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write
(R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are
always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with
respect to the SCLK must be observed (see the Timing Requirements table).
7.5.1.4 SDO
The SDO signal provides the output data requested by a read command. This output is high impedance during
write bus cycles and during the read bit and register address portion of read bus cycles.
As shown in Figure 22, each register access consists of 24 bits. The first bit is high for a read and low for a write.
The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits
are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored and,
during this time, the SDO outputs the data from the addressed register. Figure 22 shows the serial protocol
details.
Single Register Access
SCS
1
8
16
17
24
SCLK
Command Field
SDI
R/W
A14
A13 A12
A11
A10
A9
A8
A7
A6
Data Field
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Data Field
SDO
(read mode)
High Z
D7
D6
D5
D4
D3
D2
D1
D0
High Z
Figure 22. Serial Interface Protocol: Single Read/Write
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Programming (continued)
7.5.1.5 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (see
the user SPI configuration register). Figure 23 shows the streaming mode transaction details.
Multiple Register Access
SCS
8
1
16
17
24
25
32
SCLK
Command Field
SDI
R/W A14
A13
A12
A1
1
A10
A9
A8
A7
Data Field (write mode)
Data Field (write mode)
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
ADVANCE INFORMATION
High Z
D7
D6
D5
D4
D3
D2
D1
D0
Data Field
Data Field
SDO
(read mode)
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
High Z
Figure 23. Serial Interface Protocol: Streaming Read/Write
See the SPI_Register_Map Registers section for detailed information regarding the registers.
NOTE
The serial interface must not be accessed during ADC calibration. Accessing the serial
interface during this time impairs the performance of the device until the device is
calibrated correctly. Writing or reading the serial registers also reduces dynamic ADC
performance for the duration of the register access time.
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7.6 SPI_Register_Map Registers
Table 58 lists the memory-mapped registers for the SPI_Register_Map registers. All register offset addresses not
listed in Table 58 should be considered as reserved locations and the register contents should not be modified.
Table 58. SPI_REGISTER_MAP Registers
Acronym
Register Name
0x0
CONFIG_A
Configuration A (default: 0x30)
Section
Go
0x2
DEVICE_CONFIG
Device Configuration (default: 0x00)
Go
0x3
CHIP_TYPE
Chip Type (Default: 0x03)
Go
0x4
CHIP_ID
Chip Identification
Go
0xC
VENDOR_ID
Vendor Identification (Default = 0x0451)
Go
0x10
USR0
User SPI Configuration (Default: 0x00)
Go
0x29
CLK_CTRL0
Clock Control 0 (default: 0x00)
Go
0x2A
CLK_CTRL1
Clock Control 1 (default: 0x00)
Go
0x2C
SYSREF_POS
SYSREF Capture Position (Read-Only, Default: undefined)
Go
0x30
FS_RANGE_A
FS_RANGE_A (default: 0xA000)
Go
0x32
FS_RANGE_B
FS_RANGE_B (default: 0xA000)
Go
0x38
BG_BYPASS
Band-Gap Bypass (default: 0x00)
Go
0x3B
TMSTP_CTRL
TMSTP Control (default: 0x00)
Go
0x48
SER_PE
Serializer Pre-Emphasis Control (default: 0x00)
Go
0x60
INPUT_MUX
Input Mux Control (default: 0x01)
Go
0x61
CAL_EN
Calibration Enable (Default: 0x01)
Go
0x62
CAL_CFG0
Calibration Configuration 0 (Default: 0x01)
Go
0x68
CAL_AVG
Calibration Averaging (default: 0x61)
Go
0x6A
CAL_STATUS
Calibration Status (default: undefined) (read-only)
Go
0x6B
CAL_PIN_CFG
Calibration Pin Configuration (default: 0x00)
Go
0x6C
CAL_SOFT_TRIG
Calibration Software Trigger (default: 0x01)
Go
0x6E
CAL_LP
Low-Power Background Calibration (default: 0x88)
Go
0x70
CAL_DATA_EN
Calibration Data Enable (default: 0x00)
Go
0x71
CAL_DATA
Calibration Data (default: undefined)
Go
0x7A
GAIN_TRIM_A
Gain DAC Trim A (default from Fuse ROM)
Go
0x7B
GAIN_TRIM_B
Gain DAC Trim B (default from Fuse ROM)
Go
0x7C
BG_TRIM
Band-Gap Trim (default from Fuse ROM)
Go
0x7E
RTRIM_A
Resistor Trim for VinA (default from Fuse ROM)
Go
0x7F
RTRIM_B
Resistor Trim for VinB (default from Fuse ROM)
Go
0x9D
ADC_DITH
ADC Dither Control (default from Fuse ROM)
Go
0x102
B0_TIME_0
Time Adjustment for Bank 0 (0° clock) (default from Fuse ROM)
Go
0x103
B0_TIME_90
Time Adjustment for Bank 0 (-90° clock) (default from Fuse ROM)
Go
0x112
B1_TIME_0
Time Adjustment for Bank 1 (0° clock) (default from Fuse ROM)
Go
0x113
B1_TIME_90
Time Adjustment for Bank 1 (-90° clock) (default from Fuse ROM)
Go
0x142
B4_TIME_0
Time Adjustment for Bank 4 (0° clock) (default from Fuse ROM)
Go
0x152
B5_TIME_0
Time Adjustment for Bank 5 (0° clock) (default from Fuse ROM)
Go
0x160
LSB_CTRL
LSB Control Bit Output (default: 0x00)
Go
0x200
JESD_EN
JESD204C Subsystem Enable (default: 0x01)
Go
0x201
JMODE
JESD204C Mode (default: 0x02)
Go
0x202
KM1
JESD204C K Parameter (default: 0x1F)
Go
0x203
JSYNC_N
JESD204C Manual Sync Request (default: 0x01)
Go
0x204
JCTRL
JESD204C Control (default: 0x02)
Go
0x205
JTEST
JESD204C Test Control (default: 0x00)
Go
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Offset
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Table 58. SPI_REGISTER_MAP Registers (continued)
ADVANCE INFORMATION
82
Offset
Acronym
Register Name
0x206
DID
JESD204C DID Parameter (default: 0x00)
Section
Go
0x207
FCHAR
JESD204C Frame Character (default: 0x00)
Go
0x208
JESD_STATUS
JESD204C / System Status Register
Go
0x209
PD_CH
JESD204C Channel Power Down (default: 0x00)
Go
0x20A
JEXTRA_A
JESD204C Extra Lane Enable (Link A) (default: 0x00)
Go
0x20B
JEXTRA_B
JESD204C Extra Lane Enable (Link B) (default: 0x00)
Go
0x20F
SHMODE
JESD204C Sync Word Mode (default: 0x00)
Go
0x210
DDC_CFG
DDC Configuration (default: 0x00)
Go
0x211
OVR_T0
Over-range Threshold 0 (default: 0xF2)
Go
0x212
OVR_T1
Over-range Threshold 1 (default: 0xAB)
Go
0x213
OVR_CFG
Over-range Enable / Hold Off (default: 0x07)
Go
0x214
CMODE
DDC NCO Configuration Preset Mode (default: 0x00)
Go
0x215
CSEL
DDC NCO Configuration Preset Select (default: 0x00)
Go
0x216
DIG_BIND
Digital Channel Binding (default: 0x02)
Go
0x217
NCO_RDIV
NCO Reference Divisor (default: 0x0000)
Go
0x219
NCO_SYNC
NCO Synchronization (default: 0x02)
Go
0x220
FREQA0
NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)
Go
0x224
PHASEA0
NCO Phase (Channel A, Preset 0) (default: 0x0000)
Go
0x228
FREQA1
NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)
Go
0x22C
PHASEA1
NCO Phase (Channel A, Preset 1) (default: 0x0000)
Go
0x230
FREQA2
NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)
Go
0x234
PHASEA2
NCO Phase (Channel A, Preset 2) (default: 0x0000)
Go
0x238
FREQA3
NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)
Go
0x23C
PHASEA3
NCO Phase (Channel A, Preset 3) (default: 0x0000)
Go
0x240
FREQB0
NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)
Go
0x244
PHASEB0
NCO Phase (Channel B, Preset 0) (default: 0x0000)
Go
0x248
FREQB1
NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)
Go
0x24C
PHASEB1
NCO Phase (Channel B, Preset 1) (default: 0x0000)
Go
0x250
FREQB2
NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)
Go
0x254
PHASEB2
NCO Phase (Channel B, Preset 2) (default: 0x0000)
Go
0x258
FREQB3
NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)
Go
0x25C
PHASEB3
NCO Phase (Channel B, Preset 3) (default: 0x0000)
Go
0x297
SPIN_ID
Chip Spin Identifier (default: See description, read-only)
Go
0x2B0
SRC_EN
SYSREF Calibration Enable (default: 0x00)
Go
0x2B1
SRC_CFG
SYSREF Calibration Configuration (default: 0x05)
Go
0x2B2
SRC_STATUS
SYSREF Calibration Status (read-only, default: undefined)
Go
0x2B5
TAD
DEVCLK Timing Adjust (default: 0x00)
Go
0x2B8
TAD_RAMP
DEVCLK Timing Adjust Ramp Control (default: 0x00)
Go
0x2C0
ALARM
Alarm Interrupt (read-only)
Go
0x2C1
ALM_STATUS
Alarm Status (default: 0x3F, write to clear)
Go
0x2C2
ALM_MASK
Alarm Mask Register (default: 0x3F)
Go
0x2C4
FIFO_LANE_ALM
FIFO Overflow/Underflow Alarm (default: 0xFFFF)
Go
0x310
TADJ_A
Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)
Go
0x313
TADJ_B
Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)
Go
0x314
TADJ_A_FG90_VINA
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA±
(default from Fuse ROM)
Go
0x315
TADJ_B_FG0_VINA
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA±
(default from Fuse ROM)
Go
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Table 58. SPI_REGISTER_MAP Registers (continued)
Acronym
Register Name
0x31A
TADJ_A_FG90_VINB
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB±
(default from Fuse ROM)
Section
Go
0x31B
TADJ_B_FG0_VINB
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB±
(default from Fuse ROM)
Go
0x344
OADJ_A_FG0_VINA
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA±
(default from Fuse ROM)
Go
0x346
OADJ_A_FG0_VINB
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB±
(default from Fuse ROM)
Go
0x348
OADJ_A_FG90_VINA
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA±
(default from Fuse ROM)
Go
0x34A
OADJ_A_FG90_VINB
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB±
(default from Fuse ROM)
Go
0x34C
OADJ_B_FG0_VINA
Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM)
Go
0x34E
OADJ_B_FG0_VINB
Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM)
Go
0x360
GAIN_B0
Fine Gain Adjust for Bank 0 (default from Fuse ROM)
Go
0x361
GAIN_B1
Fine Gain Adjust for Bank 1 (default from Fuse ROM)
Go
0x364
GAIN_B4
Fine Gain Adjust for Bank 4 (default from Fuse ROM)
Go
0x365
GAIN_B5
Fine Gain Adjust for Bank 5 (default from Fuse ROM)
Go
Complex bit access types are encoded to fit into small table cells. Table 59 shows the codes that are used for
access types in this section.
Table 59. SPI_Register_Map Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
7.6.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]
CONFIG_A is shown in Figure 24 and described in Table 60.
Return to Summary Table.
Configuration A (default: 0x30)
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Figure 24. CONFIG_A Register
7
SOFT_RESET
R/W-0x0
6
RESERVED
R/W-0x0
5
ASCEND
R/W-0x1
4
SDO_ACTIVE
R-0x1
3
2
1
0
RESERVED
R/W-0x0
Table 60. CONFIG_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SOFT_RESET
R/W
0x0
Setting this bit causes a full reset of the chip and all SPI registers
(including CONFIG_A). This bit is self-clearing. After writing this bit,
the part may take up to 750ns to reset. During this time, do not
perform any SPI transactions.
6
RESERVED
R/W
0x0
5
ASCEND
R/W
0x1
0 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)
4
SDO_ACTIVE
R
0x1
Always returns 1. Always use SDO for SPI reads.
No SDIO mode supported.
RESERVED
R/W
0x0
3:0
ADVANCE INFORMATION
7.6.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]
DEVICE_CONFIG is shown in Figure 25 and described in Table 61.
Return to Summary Table.
Device Configuration (default: 0x00)
Figure 25. DEVICE_CONFIG Register
7
6
5
4
3
2
1
RESERVED
R/W-0x0
0
MODE
R/W-0x0
Table 61. DEVICE_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
1:0
MODE
R/W
0x0
Description
0
1
2
3
:
:
:
:
Normal operation (default)
Reserved
Reserved
Power down (lowest power, slower resume)
7.6.3 CHIP_TYPE Register (Address = 0x3) [reset = 0x03]
CHIP_TYPE is shown in Figure 26 and described in Table 62.
Return to Summary Table.
Chip Type (Default: 0x03)
Figure 26. CHIP_TYPE Register
7
6
5
4
3
RESERVED
R/W-0x0
84
2
1
0
CHIP_TYPE
R-0x3
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Table 62. CHIP_TYPE Register Field Descriptions
Bit
Field
Type
Reset
7:4
RESERVED
R/W
0x0
3:0
CHIP_TYPE
R
0x3
Description
Always returns 0x3, indicating that the part is a high speed ADC.
7.6.4 CHIP_ID Register (Address = 0x4) [reset = 0x0]
CHIP_ID is shown in Figure 27 and described in Table 63.
Return to Summary Table.
Chip Identification
Figure 27. CHIP_ID Register
14
13
12
11
10
9
8
7
CHIP_ID
R-0x0
6
5
4
3
2
1
0
ADVANCE INFORMATION
15
Table 63. CHIP_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CHIP_ID
R
0x0
Returns 0x0021 indicating the device is an ADC12DJ5200RF.
7.6.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0]
VENDOR_ID is shown in Figure 28 and described in Table 64.
Return to Summary Table.
Vendor Identification (Default = 0x0451)
Figure 28. VENDOR_ID Register
15
14
13
12
11
10
9
8
7
VENDOR_ID
R-0x0
6
5
4
3
2
1
0
Table 64. VENDOR_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
VENDOR_ID
R
0x0
Always returns 0x0451 (Vendor ID for Texas Instruments)
7.6.6 USR0 Register (Address = 0x10) [reset = 0x00]
USR0 is shown in Figure 29 and described in Table 65.
Return to Summary Table.
User SPI Configuration (Default: 0x00)
Figure 29. USR0 Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
ADDR_HOLD
R/W-0x0
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Table 65. USR0 Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
ADDR_HOLD
R/W
0x0
0
Description
0 : Use ASCEND register to select address ascend/descend mode
(default)
1 : Address stays constant throughout streaming operation; useful
for reading and writing calibration vector information at the
CAL_DATA register
7.6.7 CLK_CTRL0 Register (Address = 0x29) [reset = 0x00]
CLK_CTRL0 is shown in Figure 30 and described in Table 66.
Return to Summary Table.
Clock Control 0 (default: 0x00)
Figure 30. CLK_CTRL0 Register
ADVANCE INFORMATION
7
RESERVED
R/W-0x0
6
SYSREF_PRO
C_EN
R/W-0x0
5
SYSREF_REC
V_EN
R/W-0x0
4
SYSREF_ZOO
M
R/W-0x0
3
2
1
0
SYSREF_SEL
R/W-0x0
Table 66. CLK_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
7
RESERVED
R/W
0x0
6
SYSREF_PROC_EN
R/W
0x0
This bit enables the SYSREF processor, which allows the device to
process SYSREF events (default: disabled). SYSREF_RECV_EN
must be set before setting SYSREF_PROC_EN.
5
SYSREF_RECV_EN
R/W
0x0
Set this bit to enable the SYSREF receiver circuit (default: disabled)
4
SYSREF_ZOOM
R/W
0x0
Set this bit to zoom in the SYSREF windowing status and delays
(impacts SYSERF_POS and SYSREF_SEL). When set, the delays
used in the SYSREF windowing feature (reported in the
SYSREF_POS register) become smaller. Use SYSREF_ZOOM for
high clock rates, specifically when multiple SYSREF valid windows
are encountered in the SYSREF_POS register; see the SYSREF
Position Detector and Sampling Position Selection (SYSREF
Windowing) section.
SYSREF_SEL
R/W
0x0
Set this field to select which SYSREF delay to use. Set this field
based on the results returned by SYSREF_POS; see the SYSREF
Position Detector and Sampling Position Selection (SYSREF
Windowing) section. These bits must be set to 0 to use SYSREF
calibration; see the Automatic SYSREF Calibration section.
3:0
Description
7.6.8 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]
CLK_CTRL1 is shown in Figure 31 and described in Table 67.
Return to Summary Table.
Clock Control 1 (default: 0x00)
Figure 31. CLK_CTRL1 Register
7
6
5
RESERVED
R/W-0x0
86
4
3
2
1
0
SYSREF_TIME DEVCLK_LVPE SYSREF_LVPE SYSREF_INVE
_STAMP_EN
CL_EN
CL_EN
RTED
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
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Table 67. CLK_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
7:4
RESERVED
R/W
0x0
Description
3
SYSREF_TIME_STAMP_
EN
R/W
0x0
The SYSREF signal can be observed on the LSB of the JESD204C
output
samples
when
SYSREF_TIMESTAMP_EN
and
TIME_STAMP_EN are both set. Only supported in DDC bypass
modes (i.e. D=1). This bit allows SYSREF± to be used as the
timestamp input.
2
DEVCLK_LVPECL_EN
R/W
0x0
Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin
Functions table.
1
SYSREF_LVPECL_EN
R/W
0x0
Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the
Pin Functions table.
0
SYSREF_INVERTED
R/W
0x0
This bit inverts the SYSREF signal used for alignment.
7.6.9 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]
Return to Summary Table.
SYSREF Capture Position (Read-Only, Default: undefined)
Figure 32. SYSREF_POS Register
Table 68. SYSREF_POS Register Field Descriptions
Bit
Field
Type
Reset
Description
23:0
SYSREF_POS
R/W
0x0
Returns a 24-bit status value that indicates the position of the
SYSREF edge with respect to CLK±. Use this to program
SYSREF_SEL.
7.6.10 FS_RANGE_A Register (Address = 0x30) [reset = 0x0]
FS_RANGE_A is shown in Figure 33 and described in Table 69.
Return to Summary Table.
FS_RANGE_A (default: 0xA000)
Figure 33. FS_RANGE_A Register
15
14
13
12
11
10
9
8
7
FS_RANGE_A
R/W-0x0
6
5
4
3
2
1
0
Table 69. FS_RANGE_A Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
FS_RANGE_A
R/W
0x0
These bits enable adjustment of the analog full-scale range for INA±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting
7.6.11 FS_RANGE_B Register (Address = 0x32) [reset = 0x0]
FS_RANGE_B is shown in Figure 34 and described in Table 70.
Return to Summary Table.
FS_RANGE_B (default: 0xA000)
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SYSREF_POS is shown in Figure 32 and described in Table 68.
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Figure 34. FS_RANGE_B Register
15
14
13
12
11
10
9
8
7
FS_RANGE_B
R/W-0x0
6
5
4
3
2
1
0
Table 70. FS_RANGE_B Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
FS_RANGE_B
R/W
0x0
These bits enable adjustment of the analog full-scale range for INB±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting
7.6.12 BG_BYPASS Register (Address = 0x38) [reset = 0x00]
BG_BYPASS is shown in Figure 35 and described in Table 71.
Return to Summary Table.
ADVANCE INFORMATION
Band-Gap Bypass (default: 0x00)
Figure 35. BG_BYPASS Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
BG_BYPASS
R/W-0x0
Table 71. BG_BYPASS Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
0
BG_BYPASS
R/W
0x0
Description
When set, VA11 is used as the voltage reference instead of the
band-gap voltage.
7.6.13 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]
TMSTP_CTRL is shown in Figure 36 and described in Table 72.
Return to Summary Table.
TMSTP Control (default: 0x00)
Figure 36. TMSTP_CTRL Register
7
6
5
4
3
2
RESERVED
R/W-0x0
1
TMSTP_LVPE
CL_EN
R/W-0x0
0
TMSTP_RECV
_EN
R/W-0x0
Table 72. TMSTP_CTRL Register Field Descriptions
88
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
Description
1
TMSTP_LVPECL_EN
R/W
0x0
When set, activates the low voltage PECL mode for the differential
TMSTP± input.
0
TMSTP_RECV_EN
R/W
0x0
Enables the differential differential TMSTP± input.
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7.6.14 SER_PE Register (Address = 0x48) [reset = 0x00]
SER_PE is shown in Figure 37 and described in Table 73.
Return to Summary Table.
Serializer Pre-Emphasis Control (default: 0x00)
Figure 37. SER_PE Register
7
6
5
4
3
2
1
RESERVED
R/W-0x0
0
SER_PE
R/W-0x0
Table 73. SER_PE Register Field Descriptions
Field
Type
Reset
RESERVED
R/W
0x0
3:0
SER_PE
R/W
0x0
Description
Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis
can be used to compensate for the high-frequency loss of the PCB
trace. This is a global setting that affects all 16 lanes (DA[7:0]±,
DB[7:0]±).
7.6.15 INPUT_MUX Register (Address = 0x60) [reset = 0x01]
INPUT_MUX is shown in Figure 38 and described in Table 74.
Return to Summary Table.
Input Mux Control (default: 0x01)
Figure 38. INPUT_MUX Register
7
6
RESERVED
R/W-0x0
5
4
DUAL_INPUT
R/W-0x0
3
2
1
RESERVED
R/W-0x0
0
SINGLE_INPUT
R/W-0x1
Table 74. INPUT_MUX Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
DUAL_INPUT
R/W
0x0
3:2
RESERVED
R/W
0x0
1:0
SINGLE_INPUT
R/W
0x1
4
Description
Select inputs for dual channel modes. If JMODE is selecting a single
channel mode, this register has no effect.
0: A channel samples INA±, B channel samples INB± (no swap)
(default)
1: A channel samples INB±, B channel samples INA± (swap)
Defines which input is sampled in single channel mode. If JMODE is
not selecting a single channel mode, this register has no effect.
0: RESERVED
1: INA± is used (default)
2: INB± is used
3: RESERVED
7.6.16 CAL_EN Register (Address = 0x61) [reset = 0x01]
CAL_EN is shown in Figure 39 and described in Table 75.
Return to Summary Table.
Calibration Enable (Default: 0x01)
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Figure 39. CAL_EN Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
CAL_EN
R/W-0x1
Table 75. CAL_EN Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
CAL_EN
R/W
0x1
0
Description
Calibration Enable. Set high to run calibration. Set low to hold
calibration in reset to program new calibration settings. Clearing
CAL_EN also resets the clock dividers that clock the digital block
and JESD204C interface.
Some calibration registers require clearing CAL_EN before making
any changes. All registers with this requirement contain a note in
their descriptions. After changing the registers, set CAL_EN to re-run
calibration with the new settings. Always set CAL_EN before setting
JESD_EN. Always clear JESD_EN before clearing CAL_EN.
7.6.17 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]
ADVANCE INFORMATION
CAL_CFG0 is shown in Figure 40 and described in Table 76.
Return to Summary Table.
Calibration Configuration 0 (Default: 0x01)
Figure 40. CAL_CFG0 Register
7
6
5
4
RESERVED
R/W-0x0
3
CAL_BGOS
R/W-0x0
2
CAL_OS
R/W-0x0
1
CAL_BG
R/W-0x0
0
CAL_FG
R/W-0x1
Table 76. CAL_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
RESERVED
R/W
0x0
3
CAL_BGOS
R/W
0x0
0 : Disable background offset calibration (default)
1 : Enable background offset calibration (requires CAL_BG to be
set).
2
CAL_OS
R/W
0x0
0 : Disable foreground offset calibration (default)
1 : Enable foreground offset calibration (requires CAL_FG to be set).
1
CAL_BG
R/W
0x0
0 : Disable background calibration (default)
1 : Enable background calibration
0
CAL_FG
R/W
0x1
0 : Reset calibration values, skip foreground calibration.
1 : Reset calibration values, then run foreground calibration (default).
7.6.18 CAL_AVG Register (Address = 0x68) [reset = 0x61]
CAL_AVG is shown in Figure 41 and described in Table 77.
Return to Summary Table.
Calibration Averaging (default: 0x61)
Figure 41. CAL_AVG Register
7
RESERVED
R/W-0x0
90
6
5
OS_AVG
R/W-0x6
4
3
RESERVED
R/W-0x0
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1
CAL_AVG
R/W-0x1
0
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Table 77. CAL_AVG Register Field Descriptions
Bit
7
6:4
3
2:0
Field
Type
Reset
RESERVED
R/W
0x0
OS_AVG
R/W
0x6
RESERVED
R/W
0x0
CAL_AVG
R/W
0x1
Description
Select the amount of averaging used for the offset correction routine.
A larger number corresponds to more averaging.
Select the amount of averaging used for the linearity calibration
routine. A larger number corresponds to more averaging.
7.6.19 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]
CAL_STATUS is shown in Figure 42 and described in Table 78.
Return to Summary Table.
Calibration Status (default: undefined) (read-only)
7
6
RESERVED
5
4
3
CAL_STAT
R-0x0
2
1
CAL_STOPPE
D
R-0x0
R-0x0
0
FG_DONE
R-0x0
Table 78. CAL_STATUS Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R
0x0
Description
4:2
CAL_STAT
R
0x0
Calibration status code
1
CAL_STOPPED
R
0x0
This bit returns a 1 when background calibration is successfully
stopped at the requested phase. This bit returns a 0 when calibration
starts operating again. If background calibration is disabled, this bit is
set when foreground calibration is completed or skipped.
0
FG_DONE
R
0x0
This bit is high to indicate that foreground calibration has completed
(or was skipped).
7.6.20 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]
CAL_PIN_CFG is shown in Figure 43 and described in Table 79.
Return to Summary Table.
Calibration Pin Configuration (default: 0x00)
Figure 43. CAL_PIN_CFG Register
7
6
5
RESERVED
R/W-0x0
4
3
2
1
CAL_STATUS_SEL
R/W-0x0
0
CAL_TRIG_EN
R/W-0x0
Table 79. CAL_PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
7:3
RESERVED
R/W
0x0
2:1
CAL_STATUS_SEL
R/W
0x0
Description
0
1
2
3
:
:
:
:
CALSTAT
CALSTAT
CALSTAT
CALSTAT
output matches FG_DONE.
output matches CAL_STOPPED.
output matches ALARM.
output is always low.
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ADVANCE INFORMATION
Figure 42. CAL_STATUS Register
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Table 79. CAL_PIN_CFG Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
CAL_TRIG_EN
R/W
0x0
This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The
CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The
CAL_SOFT_TRIG register is ignored.
7.6.21 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]
CAL_SOFT_TRIG is shown in Figure 44 and described in Table 80.
Return to Summary Table.
Calibration Software Trigger (default: 0x01)
Figure 44. CAL_SOFT_TRIG Register
7
6
5
4
RESERVED
3
2
1
ADVANCE INFORMATION
R/W-0x0
0
CAL_SOFT_TR
IG
R/W-0x1
Table 80. CAL_SOFT_TRIG Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
CAL_SOFT_TRIG
R/W
0x1
0
Description
CAL_SOFT_TRIG is a software bit to provide the functionality of the
CALTRIG input pin when there are no hardware resources to drive
CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for
the calibration trigger.
Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and
CAL_SOFT_TRIG=1 (trigger set high).
7.6.22 CAL_LP Register (Address = 0x6E) [reset = 0x88]
CAL_LP is shown in Figure 45 and described in Table 81.
Return to Summary Table.
Low-Power Background Calibration (default: 0x88)
Figure 45. CAL_LP Register
7
92
6
LP_SLEEP_DLY
R/W-0x4
5
4
3
LP_WAKE_DLY
R/W-0x1
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2
RESERVED
R/W-0x0
1
LP_TRIG
R/W-0x0
0
LP_EN
R/W-0x0
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Bit
Field
Type
Reset
Description
7:5
LP_SLEEP_DLY
R/W
0x4
These bits adjust how long an ADC sleeps before waking for
calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values
below 4 are not recommended because of limited overall power
reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tCLK
1: Sleep delay = (215 + 1) × 256 × tCLK
2: Sleep delay = (218 + 1) × 256 × tCLK
3: Sleep delay = (221 + 1) × 256 × tCLK
4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately
1.338 seconds with a 3.2-GHz clock)
5: Sleep delay = (227 + 1) × 256 × tCLK
6: Sleep delay = (230 + 1) × 256 × tCLK
7: Sleep delay = (233 + 1) × 256 × tCLK
4:3
LP_WAKE_DLY
R/W
0x1
These bits adjust how much time is provided for settling before
calibrating an ADC after the ADC wakes up (only applies when
LP_EN = 1). Values lower than 1 are not recommended because
there is insufficient time for the core to stabilize before calibration
begins.
0: Wake delay = (23 + 1) × 256 × tCLK
1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21
ms with a 3.2-GHz clock)
2: Wake delay = (221 + 1) × 256 × tCLK
3: Wake delay = (224 + 1) × 256 × tCLK
2
RESERVED
R/W
0x0
1
LP_TRIG
R/W
0x0
0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous
mode).
1 : ADCs sleep until awoken by a trigger. An ADC is awoken when
the calibration trigger is low.
0
LP_EN
R/W
0x0
0 : Disable low-power background calibration (default)
1 : Enable low-power background calibration (only applies when
CAL_BG=1).
7.6.23 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]
CAL_DATA_EN is shown in Figure 46 and described in Table 82.
Return to Summary Table.
Calibration Data Enable (default: 0x00)
Figure 46. CAL_DATA_EN Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
CAL_DATA_EN
R/W-0x0
Table 82. CAL_DATA_EN Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
CAL_DATA_EN
R/W
0x0
0
Description
Set this bit to enable the CAL_DATA register to enable reading and
writing of calibration data; see the CAL_DATA register for more
information.
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Table 81. CAL_LP Register Field Descriptions
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7.6.24 CAL_DATA Register (Address = 0x71) [reset = 0x0]
CAL_DATA is shown in Figure 47 and described in Table 83.
Return to Summary Table.
Calibration Data (default: undefined)
Figure 47. CAL_DATA Register
7
6
5
4
3
2
1
0
CAL_DATA
R/W-0x0
Table 83. CAL_DATA Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
Description
7:0
CAL_DATA
R/W
0x0
After setting CAL_DATA_EN, repeated reads of this register return
all calibration values for the ADCs. Repeated writes of this register
input all calibration values for the ADCs. To read the calibration data,
read the register 673 times. To write the vector, write the register
673 times with previously stored calibration data. To speed up the
read or write operation, set ADDR_HOLD = 1 and use streaming
read or write process.
IMPORTANT:
Accessing
the
CAL_DATA
register
when
CAL_STOPPED = 0 corrupts the calibration. Also, stopping the
process before reading or writing 673 times leaves the calibration
data in an invalid state.
7.6.25 GAIN_TRIM_A Register (Address = 0x7A) [reset = 0x0]
GAIN_TRIM_A is shown in Figure 48 and described in Table 84.
Return to Summary Table.
Gain DAC Trim A (default from Fuse ROM)
Figure 48. GAIN_TRIM_A Register
7
6
5
4
3
2
1
0
GAIN_TRIM_A
R/W-0x0
Table 84. GAIN_TRIM_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
GAIN_TRIM_A
R/W
0x0
This register enables gain trim of INA±. After reset, the factory
trimmed value can be read and adjusted as required. Use
FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±.
7.6.26 GAIN_TRIM_B Register (Address = 0x7B) [reset = 0x0]
GAIN_TRIM_B is shown in Figure 49 and described in Table 85.
Return to Summary Table.
Gain DAC Trim B (default from Fuse ROM)
Figure 49. GAIN_TRIM_B Register
7
6
5
4
3
2
1
0
GAIN_TRIM_B
R/W-0x0
94
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Table 85. GAIN_TRIM_B Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
GAIN_TRIM_B
R/W
0x0
This register enables gain trim of INB±. After reset, the factory
trimmed value can be read and adjusted as required. Use
FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±.
7.6.27 BG_TRIM Register (Address = 0x7C) [reset = 0x0]
BG_TRIM is shown in Figure 50 and described in Table 86.
Return to Summary Table.
Band-Gap Trim (default from Fuse ROM)
Figure 50. BG_TRIM Register
6
5
4
3
2
RESERVED
R/W-0x0
1
0
BG_TRIM
R/W-0x0
Table 86. BG_TRIM Register Field Descriptions
Bit
Field
Type
Reset
7:4
RESERVED
R/W
0x0
3:0
BG_TRIM
R/W
0x0
Description
This register enables trimming of the internal band-gap reference.
After reset, the factory trimmed value can be read and adjusted as
required.
7.6.28 RTRIM_A Register (Address = 0x7E) [reset = 0x0]
RTRIM_A is shown in Figure 51 and described in Table 87.
Return to Summary Table.
Resistor Trim for VinA (default from Fuse ROM)
Figure 51. RTRIM_A Register
7
6
5
4
3
2
1
0
RTRIM_A
R/W-0x0
Table 87. RTRIM_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
RTRIM_A
R/W
0x0
This register controls the INA± ADC input termination trim. After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.29 RTRIM_B Register (Address = 0x7F) [reset = 0x0]
RTRIM_B is shown in Figure 52 and described in Table 88.
Return to Summary Table.
Resistor Trim for VinB (default from Fuse ROM)
Figure 52. RTRIM_B Register
7
6
5
4
3
2
1
0
RTRIM_B
R/W-0x0
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Table 88. RTRIM_B Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
RTRIM_B
R/W
0x0
This register controls the INB± ADC input termination trim. After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.30 ADC_DITH Register (Address = 0x9D) [reset = 0x0]
ADC_DITH is shown in Figure 53 and described in Table 89.
Return to Summary Table.
ADC Dither Control (default from Fuse ROM)
Figure 53. ADC_DITH Register
7
6
5
RESERVED
4
3
2
1
0
ADC_DITH_ER ADC_DITH_AM ADC_DITH_EN
R
P
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
ADVANCE INFORMATION
Table 89. ADC_DITH Register Field Descriptions
Bit
Field
Type
Reset
7:3
RESERVED
R/W
0x0
Description
2
ADC_DITH_ERR
R/W
0x0
Small rounding errors may occur when subtracting the dither signal.
The error can be chosen to either slightly degrade SNR or to slightly
increase the DC offset and FS/2 spur. In addition, the FS/4 spur will
also be increased slightly while in single channel mode.
0 : Rounding error degrades SNR
1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur
1
ADC_DITH_AMP
R/W
0x0
0 : Small dither for better SNR (default)
1 : Large dither for better spurious performance
0
ADC_DITH_EN
R/W
0x0
Set this bit to enable ADC dither. Dither can improve spurious
performance at the expense of slightly degraded SNR. The dither
amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR
and spurious performance.
7.6.31 B0_TIME_0 Register (Address = 0x102) [reset = 0x0]
B0_TIME_0 is shown in Figure 54 and described in Table 90.
Return to Summary Table.
Time Adjustment for Bank 0 (0° clock) (default from Fuse ROM)
Figure 54. B0_TIME_0 Register
7
6
5
4
3
2
1
0
B0_TIME_0
R/W-0x0
Table 90. B0_TIME_0 Register Field Descriptions
96
Bit
Field
Type
Reset
Description
7:0
B0_TIME_0
R/W
0x0
Time adjustment for bank 0 applied when ADC A is configured for 0°
clock phase (dual channel mode). After reset, the factory trimmed
value can be read and adjusted as required.
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7.6.32 B0_TIME_90 Register (Address = 0x103) [reset = 0x0]
B0_TIME_90 is shown in Figure 55 and described in Table 91.
Return to Summary Table.
Time Adjustment for Bank 0 (-90° clock) (default from Fuse ROM)
Figure 55. B0_TIME_90 Register
7
6
5
4
3
2
1
0
B0_TIME_90
R/W-0x0
Table 91. B0_TIME_90 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
B0_TIME_90
R/W
0x0
Time adjustment for bank 0 applied when ADC A is configured for
-90° clock phase(single channel mode). After reset, the factory
trimmed value can be read and adjusted as required.
B1_TIME_0 is shown in Figure 56 and described in Table 92.
Return to Summary Table.
Time Adjustment for Bank 1 (0° clock) (default from Fuse ROM)
Figure 56. B1_TIME_0 Register
7
6
5
4
3
2
1
0
B1_TIME_0
R/W-0x0
Table 92. B1_TIME_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
B1_TIME_0
R/W
0x0
Time adjustment for bank 1 applied when ADC A is configured for 0°
clock phase (dual channel mode). After reset, the factory trimmed
value can be read and adjusted as required.
7.6.34 B1_TIME_90 Register (Address = 0x113) [reset = 0x0]
B1_TIME_90 is shown in Figure 57 and described in Table 93.
Return to Summary Table.
Time Adjustment for Bank 1 (-90° clock) (default from Fuse ROM)
Figure 57. B1_TIME_90 Register
7
6
5
4
3
2
1
0
B1_TIME_90
R/W-0x0
Table 93. B1_TIME_90 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
B1_TIME_90
R/W
0x0
Time adjustment for bank 1 applied when ADC A is configured for
-90° clock phase(single channel mode). After reset, the factory
trimmed value can be read and adjusted as required.
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7.6.33 B1_TIME_0 Register (Address = 0x112) [reset = 0x0]
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7.6.35 B4_TIME_0 Register (Address = 0x142) [reset = 0x0]
B4_TIME_0 is shown in Figure 58 and described in Table 94.
Return to Summary Table.
Time Adjustment for Bank 4 (0° clock) (default from Fuse ROM)
Figure 58. B4_TIME_0 Register
7
6
5
4
3
2
1
0
B4_TIME_0
R/W-0x0
Table 94. B4_TIME_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
B4_TIME_0
R/W
0x0
Time adjustment for bank 4 applied when ADC B is configured for 0°
clock phase (dual channel mode and single channel mode). After
reset, the factory trimmed value can be read and adjusted as
required.
ADVANCE INFORMATION
7.6.36 B5_TIME_0 Register (Address = 0x152) [reset = 0x0]
B5_TIME_0 is shown in Figure 59 and described in Table 95.
Return to Summary Table.
Time Adjustment for Bank 5 (0° clock) (default from Fuse ROM)
Figure 59. B5_TIME_0 Register
7
6
5
4
3
2
1
0
B5_TIME_0
R/W-0x0
Table 95. B5_TIME_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
B5_TIME_0
R/W
0x0
Time adjustment for bank 5 applied when ADC B is configured for 0°
clock phase (dual channel mode and single channel mode). After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.37 LSB_CTRL Register (Address = 0x160) [reset = 0x00]
LSB_CTRL is shown in Figure 60 and described in Table 96.
Return to Summary Table.
LSB Control Bit Output (default: 0x00)
Figure 60. LSB_CTRL Register
7
6
5
4
RESERVED
3
R/W-0x0
98
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2
1
0
TIME_STAMP_
EN
R/W-0x0
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Table 96. LSB_CTRL Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
TIME_STAMP_EN
R/W
0x0
0
Description
When set, the timestamp signal is transmitted on the LSB of the
output samples. The latency of the timestamp signal (through the
entire chip) matches the latency of the analog ADC inputs. Also set
SYNC_RECV_EN when using TIME_STAMP_EN.
Note 1: In 8-bit modes, the control bit is placed on the LSB of the 8bit samples (leaving 7-bits of sample data). If the part is configured
for 12-bit data, the control bit is placed on the LSB of the 12-bit bit
data (leaving 11-bits of sample data).
Note 2: The control bit that is enabled by this register is never
advertised in the ILA (CS is 0 in the ILA).
7.6.38 JESD_EN Register (Address = 0x200) [reset = 0x01]
JESD_EN is shown in Figure 61 and described in Table 97.
JESD204C Subsystem Enable (default: 0x01)
Figure 61. JESD_EN Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
JESD_EN
R/W-0x1
Table 97. JESD_EN Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
JESD_EN
R/W
0x1
0
Description
0 : Disable JESD204C interface
1 : Enable JESD204C interface
Note: Before altering other JESD204C registers, you must clear
JESD_EN. When JESD_EN is 0, the block is held in reset and the
serializers are powered down. The clocks are gated off to save
power. The LMFC/LEMC counter is also held in reset, so SYSREF
will not align the LMFC/LEMC.
Note 2: Always set CAL_EN before setting JESD_EN.
Note 3: Always clear JESD_EN before clearing CAL_EN.
7.6.39 JMODE Register (Address = 0x201) [reset = 0x02]
JMODE is shown in Figure 62 and described in Table 98.
Return to Summary Table.
JESD204C Mode (default: 0x02)
Figure 62. JMODE Register
7
6
5
RESERVED
R/W-0x0
4
3
2
1
0
JMODE
R/W-0x2
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Return to Summary Table.
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Table 98. JMODE Register Field Descriptions
Bit
Field
Type
Reset
7:6
RESERVED
R/W
0x0
5:0
JMODE
R/W
0x2
Description
Specify the JESD204C output mode (including DDC decimation
factor).
Note 1: This register should only be changed when JESD_EN=0 and
CAL_EN=0.
7.6.40 KM1 Register (Address = 0x202) [reset = 0x1]
KM1 is shown in Figure 63 and described in Table 99.
Return to Summary Table.
JESD204C K Parameter (default: 0x1F)
Figure 63. KM1 Register
7
6
5
4
3
2
1
0
ADVANCE INFORMATION
KM1
R/W-0x1
Table 99. KM1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
KM1
R/W
0x1
K is the number of frames per multiframe and this register must be
programmed as K-1. Depending on the JMODE setting, there are
constraints on the legal values of K (see KR).
The default values is KM1=31, which corresponds to K=32.
Note: For modes using the 64b/66b link layer, the KM1 register is
ignored and the value of K is determined from JMODE. The effective
value of K is 256*E/F.
Note: This register should only be changed when JESD_EN is 0.
7.6.41 JSYNC_N Register (Address = 0x203) [reset = 0x01]
JSYNC_N is shown in Figure 64 and described in Table 100.
Return to Summary Table.
JESD204C Manual Sync Request (default: 0x01)
Figure 64. JSYNC_N Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
JSYNC_N
R/W-0x1
Table 100. JSYNC_N Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
JSYNC_N
R/W
0x1
0
100
Description
Set this bit to 0 to request JESD204C synchronization (equivalent to
the SYNC~ signal being asserted). For normal operation, leave this
bit set to 1.
Note: The JSYNC_N register can always generate a synchronization
request, regardless of the SYNC_SEL register. However, if the
selected sync pin is stuck low, you cannot de-assert the
synchronization request unless you program SYNC_SEL=2.
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7.6.42 JCTRL Register (Address = 0x204) [reset = 0x02]
JCTRL is shown in Figure 65 and described in Table 101.
Return to Summary Table.
JESD204C Control (default: 0x02)
Figure 65. JCTRL Register
7
6
RESERVED
R/W-0x0
5
4
ALT_LANES
R/W-0x0
3
2
1
SFORMAT
R/W-0x1
SYNC_SEL
R/W-0x0
0
SCR
R/W-0x0
Table 101. JCTRL Register Field Descriptions
Field
Type
Reset
RESERVED
R/W
0x0
Description
4
ALT_LANES
R/W
0x0
0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3
and link B uses lanes DB0 to DB3. Other lanes are powered down.
1 : Alternate lane mapping (use upper lanes). Link A uses lanes DA4
to DA7 and link B uses lanes DB4 to DB7. Lanes DA0 to DA3 and
DB0 to DB3 are powered down.
Note: This option is only supported when JMODE selects a mode
that uses 8 or less lanes. The behavior is undefined for modes that
do not meet this requirement.
3:2
SYNC_SEL
R/W
0x0
0 : Use the SYNCSE input for SYNC~ function (default)
1 : Use the TMSTP input for SYNC~ function. TMSTP_RECV_EN
must also be set.
2 : Do not use any sync input pin (use software SYNC~ through
JSYNC_N)
1
SFORMAT
R/W
0x1
Output sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)
0
SCR
R/W
0x0
0 : 8B/10B Scrambler disabled (default) (applies only to 8B/10B
modes)
1 : 8b/10b Scrambler enabled
Note 1: 64B/66B modes always use scrambling. This register does
not apply to 64B/66B modes.
Note 2: This register should only be changed when JESD_EN is 0.
7.6.43 JTEST Register (Address = 0x205) [reset = 0x00]
JTEST is shown in Figure 66 and described in Table 102.
Return to Summary Table.
JESD204C Test Control (default: 0x00)
Figure 66. JTEST Register
7
6
RESERVED
R/W-0x0
5
4
3
2
JTEST
R/W-0x0
1
0
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Bit
7:5
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Table 102. JTEST Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
4:0
JTEST
R/W
0x0
Description
ADVANCE INFORMATION
0 : Test mode disabled. Normal operation (default)
1 : PRBS7 test mode
2 : PRBS15 test mode
3 : PRBS23 test mode
4 : Ramp test mode
5 : Transport Layer test mode
6 : D21.5 test mode
7 : K28.5 test mode*
8 : Repeated ILA test mode*
9 : Modified RPAT test mode*
10: Serial outputs held low
11: Serial outputs held high
12: RESERVED
13: PRBS9 test mode
14: PRBS31 test mode
15: Clock test pattern (0x00FF)
16: K28.7 test mode*
17-31: RESERVED
* These test modes are only supported when JMODE is selecting a
mode that utilizes 8b/10b encoding.
Note: This register should only be changed when JESD_EN is 0.
7.6.44 DID Register (Address = 0x206) [reset = 0x00]
DID is shown in Figure 67 and described in Table 103.
Return to Summary Table.
JESD204C DID Parameter (default: 0x00)
Figure 67. DID Register
7
6
5
4
3
2
1
0
DID
R/W-0x0
Table 103. DID Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
DID
R/W
0x0
Specifies the DID (Device ID) value that is transmitted during the
second multiframe of the JESD204B ILA. Link A will transmit DID,
and link B will transmit DID+1. Bit 0 is ignored and always returns 0
(if you program an odd number, it will be decremented to an even
number).
Note: This register should only be changed when JESD_EN is 0.
7.6.45 FCHAR Register (Address = 0x207) [reset = 0x00]
FCHAR is shown in Figure 68 and described in Table 104.
Return to Summary Table.
JESD204C Frame Character (default: 0x00)
Figure 68. FCHAR Register
7
6
5
4
3
RESERVED
R/W-0x0
102
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1
0
FCHAR
R/W-0x0
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Table 104. FCHAR Register Field Descriptions
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
1:0
FCHAR
R/W
0x0
Description
Specify which comma character is used to denote end-of-frame. This
character is transmitted opportunistically. This only applies to modes
that utilize 8B/10B encoding.
0 : Use K28.7 (default) (JESD204C compliant)
1 : Use K28.1 (not JESD204C compliant)
2 : Use K28.5 (not JESD204C compliant)
3 : Reserved
When using a JESD204C receiver, always use FCHAR=0.
When using a general purpose 8B/10B receiver, the K28.7 character
may cause issues. When K28.7 is combined with certain data
characters, a false, misaligned comma character can result, and
some receivers will re-align to the false comma. To avoid this,
program FCHAR to 1 or 2.
Note: This register should only be changed when JESD_EN is 0.
7.6.46 JESD_STATUS Register (Address = 0x208) [reset = 0x0]
ADVANCE INFORMATION
JESD_STATUS is shown in Figure 69 and described in Table 105.
Return to Summary Table.
JESD204C / System Status Register
Figure 69. JESD_STATUS Register
7
RESERVED
6
LINK_UP
R/W-0x0
R/W-0x0
5
SYNC_STATU
S
R/W-0x0
4
REALIGNED
3
ALIGNED
2
PLL_LOCKED
R/W-0x0
R/W-0x0
R/W-0x0
1
0
RESERVED
R/W-0x0
Table 105. JESD_STATUS Register Field Descriptions
Bit
Field
Type
Reset
7
RESERVED
R/W
0x0
6
LINK_UP
R/W
0x0
When set, indicates that the JESD204C link is up.
5
SYNC_STATUS
R/W
0x0
Returns the state of the JESD204C SYNC~ signal.
0 : SYNC~ asserted
1 : SYNC~ de-asserted
4
REALIGNED
R/W
0x0
When high, indicates that the digital block clock, frame clock, or
multiframe (LMFC) clock phase was realigned by SYSREF. Writing a
1 to this bit will clear it.
3
ALIGNED
R/W
0x0
When high, indicates that the multiframe (LMFC) clock phase has
been established by SYSREF. The first SYSREF event after
enabling the JESD204B encoder will set this bit. Writing a 1 to this
bit will clear it.
2
PLL_LOCKED
R/W
0x0
When high, indicates that the serializer PLL is locked.
RESERVED
R/W
0x0
1:0
Description
7.6.47 PD_CH Register (Address = 0x209) [reset = 0x00]
PD_CH is shown in Figure 70 and described in Table 106.
Return to Summary Table.
JESD204C Channel Power Down (default: 0x00)
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Figure 70. PD_CH Register
7
6
5
4
3
2
RESERVED
R/W-0x0
1
PD_BCH
R/W-0x0
0
PD_ACH
R/W-0x0
Table 106. PD_CH Register Field Descriptions
Bit
Field
Type
Reset
7:2
Description
ADVANCE INFORMATION
RESERVED
R/W
0x0
1
PD_BCH
R/W
0x0
When set, the “B” ADC channel is powered down. The digital
channels that are bound to the “B” ADC channel are also powered
down (see DIG_BIND).
Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C
subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A,
and the B digital channel is disabled, link A remains operational, but
the B-channel samples are undefined.
0
PD_ACH
R/W
0x0
When set, the “A” ADC channel is powered down. The digital
channels that are bound to the “A” ADC channel are also powered
down (see DIG_BIND).
Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C
subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A,
and the B digital channel is disabled, link A remains operational, but
the B-channel samples are undefined.
7.6.48 JEXTRA_A Register (Address = 0x20A) [reset = 0x00]
JEXTRA_A is shown in Figure 71 and described in Table 107.
Return to Summary Table.
JESD204C Extra Lane Enable (Link A) (default: 0x00)
Figure 71. JEXTRA_A Register
Table 107. JEXTRA_A Register Field Descriptions
Bit
0
104
Field
Type
Reset
Description
EXTRA_SER_A
R/W
0x0
0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer
clocks). Use this mode to transmit data from the extra lanes.
Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and
JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by
JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp
(same as JTEST=4).
4. This register doesn’t override the PD_CH register, so ensure that
the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also
be enabled, otherwise serializer 'n' will not receive a clock.
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7.6.49 JEXTRA_B Register (Address = 0x20B) [reset = 0x00]
JEXTRA_B is shown in Figure 72 and described in Table 108.
Return to Summary Table.
JESD204C Extra Lane Enable (Link B) (default: 0x00)
Figure 72. JEXTRA_B Register
Bit
0
Field
Type
Reset
Description
EXTRA_SER_B
R/W
0x0
0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer
clocks). Use this mode to transmit data from the extra lanes.
Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and
JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by
JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp
(same as JTEST=4).
4. This register doesn’t override the PD_CH register, so ensure that
the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also
be enabled, otherwise serializer 'n' will not receive a clock.
7.6.50 SHMODE Register (Address = 0x20F) [reset = 0x00]
SHMODE is shown in Figure 73 and described in Table 109.
Return to Summary Table.
JESD204C Sync Word Mode (default: 0x00)
Figure 73. SHMODE Register
7
6
5
4
3
2
1
RESERVED
R/W-0x0
0
SHMODE
R/W-0x0
Table 109. SHMODE Register Field Descriptions
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
1:0
SHMODE
R/W
0x0
Description
Select the mode for the 64b/66b sync word (32 bits of data per multiblock). This only applies when JMODE is selecting a 64b/66b mode.
0 : Transmit CRC-12 signal (default setting)
1 : RESERVED
2 : Transmit FEC signal
3 : RESERVED
Note: This device does not support any JESD204C command
features. All command fields will be set to zero (idle headers).
Note: This register should only be changed when JESD_EN is 0.
7.6.51 DDC_CFG Register (Address = 0x210) [reset = 0x00]
DDC_CFG is shown in Figure 74 and described in Table 110.
Return to Summary Table.
DDC Configuration (default: 0x00)
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Table 108. JEXTRA_B Register Field Descriptions
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Figure 74. DDC_CFG Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
BOOST
R/W-0x0
Table 110. DDC_CFG Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
BOOST
R/W
0x0
0
Description
DDC gain control.
0 : DDC filter has 0dB gain (default).
1 : DDC filter has 6.02dB gain. Only use this setting when you are
certain the negative image of your input signal is filtered out by the
DDC, otherwise clipping may occur.
7.6.52 OVR_T0 Register (Address = 0x211) [reset = 0x0]
OVR_T0 is shown in Figure 75 and described in Table 111.
Return to Summary Table.
ADVANCE INFORMATION
Over-range Threshold 0 (default: 0xF2)
Figure 75. OVR_T0 Register
7
6
5
4
3
2
1
0
OVR_T0
R/W-0x0
Table 111. OVR_T0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
OVR_T0
R/W
0x0
This parameter defines the absolute sample level that causes control
bit 0 to be set. Control bit 0 is attached to the DDC I output samples.
The detection level in dBFS (peak) is 20log10(OVR_T0/256)
(Default: 0xF2 = 242-> -0.5dBFS)
7.6.53 OVR_T1 Register (Address = 0x212) [reset = 0x0]
OVR_T1 is shown in Figure 76 and described in Table 112.
Return to Summary Table.
Over-range Threshold 1 (default: 0xAB)
Figure 76. OVR_T1 Register
7
6
5
4
3
2
1
0
OVR_T1
R/W-0x0
Table 112. OVR_T1 Register Field Descriptions
106
Bit
Field
Type
Reset
Description
7:0
OVR_T1
R/W
0x0
This parameter defines the absolute sample level that causes control
bit 1 to be set. Control bit 1 is attached to the DDC Q output
samples.
The
detection
level
in
dBFS
(peak)
is
20log10(OVR_T1/256) (Default: 0xAB = 171 -> -3.5dBFS)
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7.6.54 OVR_CFG Register (Address = 0x213) [reset = 0x07]
OVR_CFG is shown in Figure 77 and described in Table 113.
Return to Summary Table.
Over-range Enable / Hold Off (default: 0x07)
Figure 77. OVR_CFG Register
7
6
5
4
3
OVR_EN
R/W-0x0
RESERVED
R/W-0x0
2
1
OVR_N
R/W-0x7
0
Table 113. OVR_CFG Register Field Descriptions
Field
Type
Reset
RESERVED
R/W
0x0
OVR_EN
R/W
0x0
Enables over-range status output pins when set high. The ORA0,
ORA1, ORB0 and ORB1 outputs are held low when OVR_EN is set
low. This register only affects the over-range output pins (ORxx).
JESD204C modes that transmit over-range bits are not affected by
this register.
OVR_N
R/W
0x7
Program this register to adjust the pulse extension for the ORA0/1
and ORB0/1 outputs. The minimum pulse duration of the over-range
outputs is 8 * 2OVR_N DEVCLK cycles. Incrementing this field
doubles the monitoring period.
3
2:0
Description
7.6.55 CMODE Register (Address = 0x214) [reset = 0x00]
CMODE is shown in Figure 78 and described in Table 114.
Return to Summary Table.
DDC NCO Configuration Preset Mode (default: 0x00)
Figure 78. CMODE Register
7
6
5
4
3
2
1
RESERVED
R/W-0x0
0
CMODE
R/W-0x0
Table 114. CMODE Register Field Descriptions
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
1:0
CMODE
R/W
0x0
Description
This register sets the selection mode for the NCO frequency used in
the DDC block. The NCO frequency and phase for DDC A are set by
the FREQAx and PHASEAx registers and the NCO frequency and
phase for DDC B are set by the FREQBx and PHASEBx registers,
where x is the configuration preset (0 through 3). In single channel
mode, the NCO selection method for DDC A in dual channel mode is
used to set the NCO for the single channel DDC.
0: Use CSEL register to select the active NCO configuration preset
for DDC A and DDC B
1: Use NCOA[1:0] pins to select the active NCO configuration preset
for DDC A and use NCOB[1:0] pins to select the active NCO
configuration preset for DDC B
2: Use NCOA[1:0] pins to select the active NCO configuration preset
for both DDC A and DDC B
3: RESERVED
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7:4
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7.6.56 CSEL Register (Address = 0x215) [reset = 0x00]
CSEL is shown in Figure 79 and described in Table 115.
Return to Summary Table.
DDC NCO Configuration Preset Select (default: 0x00)
Figure 79. CSEL Register
7
6
5
4
3
RESERVED
R/W-0x0
2
CSELB
R/W-0x0
1
0
CSELA
R/W-0x0
Table 115. CSEL Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
7:4
RESERVED
R/W
0x0
Description
3:2
CSELB
R/W
0x0
When CMODE=0, this register is used to select the active NCO
configuration preset for DDC B In single channel mode, this register
is ignored and CSELA must be used instead.
1:0
CSELA
R/W
0x0
When CMODE=0, this register is used to select the active NCO
configuration preset for DDC A Example: If CSELA=0, then FREQA0
and PHASEA0 are the active settings. If CSELA=1, then FREQA1
and PHASEA1 are the active settings.
In single channel mode CSELA selects the NCO frequency for the
DDC.
7.6.57 DIG_BIND Register (Address = 0x216) [reset = 0x02]
DIG_BIND is shown in Figure 80 and described in Table 116.
Return to Summary Table.
Digital Channel Binding (default: 0x02)
Figure 80. DIG_BIND Register
7
6
5
4
3
2
RESERVED
R/W-0x0
1
DIG_BIND[1]
R/W-0x1
0
DIG_BIND[0]
R/W-0x0
Table 116. DIG_BIND Register Field Descriptions
108
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
Description
1
DIG_BIND[1]
R/W
0x1
Digital channel B input select:
0: Digital channel B receives data from ADC channel A
1: Digital channel B receives data from ADC channel B (default)
0
DIG_BIND[0]
R/W
0x0
Digital channel A input select:
0: Digital channel A receives data from ADC channel A (default)
1: Digital channel A receives data from ADC channel B
Note 1: When using single channel mode, you must always use the
default setting for DIG_BIND or the device will not work.
Note 2: You must set JESD_EN=0 and CAL_EN=0 before changing
DIG_BIND.
Note 3: The DIG_BIND setting is combined with PD_ACH/PD_BCH
to determine if a digital channel is powered down. Each digital
channel (and link) is powered down when the ADC channel it is
bound to is powered down (by PD_ACH/PD_BCH).
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7.6.58 NCO_RDIV Register (Address = 0x217) [reset = 0x0000]
NCO_RDIV is shown in Figure 81 and described in Table 117.
Return to Summary Table.
NCO Reference Divisor (default: 0x0000)
Figure 81. NCO_RDIV Register
15
14
13
12
11
10
9
8
7
NCO_RDIV
R/W-0x0
6
5
4
3
2
1
0
Bit
Field
Type
Reset
Description
15:0
NCO_RDIV
R/W
0x0
Sometimes the 32-bit NCO frequency word does not provide the
desired frequency step size and can only approximate the desired
frequency. This results in a frequency error. Use this register to
eliminate the frequency error.
The default value of 0 disables the reference divisor and the NCO
operates as a traditional 32-bit NCO.
Any combination of FS and FSTEP that results in a fractional value
for NCO_RDIV is not supported. Values of NCO_RDIV larger than
8192 may degrade the NCO’s SFDR performance and are not
recommended. This register is used for all NCO configuration
presets.
7.6.59 NCO_SYNC Register (Address = 0x219) [reset = 0x02]
NCO_SYNC is shown in Figure 82 and described in Table 118.
Return to Summary Table.
NCO Synchronization (default: 0x02)
Figure 82. NCO_SYNC Register
7
6
5
4
3
2
1
0
NCO_SYNC_IL NCO_SYNC_N
A
EXT
R/W-0x1
R/W-0x0
RESERVED
R/W-0x0
Table 118. NCO_SYNC Register Field Descriptions
Bit
Field
Type
Reset
7:2
RESERVED
R/W
0x0
NCO_SYNC_ILA
R/W
0x1
1
Description
When this bit is set, the NCO phase is initialized on the LMFC/LEMC
boundary immediately after the rising edge of the SYNC~ signal
(default). This feature works in 8B/10B and 64B/66B modes. This
feature can be used to precisely align the NCO phase in several
ADCs. In 64B/66B modes SYNC~ is only used for this purpose and
does not affect the link operation.
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Table 117. NCO_RDIV Register Field Descriptions
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Table 118. NCO_SYNC Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
NCO_SYNC_NEXT
R/W
0x0
After writing ‘0’ and then ‘1’ to this bit, the next SYSREF rising edge
will initialize the NCO phase. Once the NCO phase has been
initialized by SYSREF, the NCO will not re-initialize on future
SYSREF edges unless ‘0’ and ‘1’ is written to this bit again.
Use this to align the NCO in multiple parts (without the need to
restart the JESD link).
1. Ensure the part is powered up, JESD_EN is set, and the device
clock is running.
2. Ensure that SYSREF is disabled (not toggling).
3. Program NCO_SYNC_ILA=0 on all parts.
4. Write NCO_SYNC_NEXT=0 on all parts.
5. Write NCO_SYNC_NEXT=1 on all parts. NCO sync is armed.
6. Instruct the SYSREF source to generate 1 or more SYSREF
pulses.
7. All parts will initialize their NCO using the first SYSREF rising
edge.
7.6.60 FREQA0 Register (Address = 0x220) [reset = 0x0]
ADVANCE INFORMATION
FREQA0 is shown in Figure 83 and described in Table 119.
Return to Summary Table.
NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)
Figure 83. FREQA0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQA0
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Table 119. FREQA0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQA0
R/W
0x0
The following description applies to FREQA0 thru FREQA3 and
FREQB0 thru FREQB3.
The NCO frequency (FNCO) is:
FNCO = FREQA0 * 232 * FADC
FADC is the sampling frequency of the ADC. FREQA0 is the integer
value of this register. This register can be interpreted as signed or
unsigned (both interpretations are valid).
Use this equation to determine the value to program:
FREQA0 = 232 * FNCO /FS
If the equation does not result in an integer value, you must choose
an alternate frequency step (FSTEP) and program the NCO_RDIV
register. Then use one of these equations to compute FREQA0:
FREQA0 = round(232 * FNCO/FS)
FREQA0 = round(225 * FNCO/FSTEP/NCO_RDIV)
Changing this register after the NCO has been synchronized is
running will result in non-deterministic NCO phase. If deterministic
phase is required, the NCO should be re-synchronized after
changing this register.
7.6.61 PHASEA0 Register (Address = 0x224) [reset = 0x0000]
PHASEA0 is shown in Figure 84 and described in Table 120.
Return to Summary Table.
NCO Phase (Channel A, Preset 0) (default: 0x0000)
110
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Figure 84. PHASEA0 Register
15
14
13
12
11
10
9
8
7
PHASEA0
R/W-0x0
6
5
4
3
2
1
0
Table 120. PHASEA0 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
PHASEA0
R/W
0x0
NCO phase for configuration preset 0. This value is left justified into
a 32−bit field and then added to the phase accumulator. The phase
(in radians) is PHASEA0 * 2-16 * 2π. This register can be interpreted
as signed or unsigned.
7.6.62 FREQA1 Register (Address = 0x228) [reset = 0x0]
FREQA1 is shown in Figure 85 and described in Table 121.
Return to Summary Table.
Figure 85. FREQA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQA1
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Table 121. FREQA1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQA1
R/W
0x0
NCO frequency for channel A, NCO preset 1
7.6.63 PHASEA1 Register (Address = 0x22C) [reset = 0x0000]
PHASEA1 is shown in Figure 86 and described in Table 122.
Return to Summary Table.
NCO Phase (Channel A, Preset 1) (default: 0x0000)
Figure 86. PHASEA1 Register
15
14
13
12
11
10
9
8
7
PHASEA1
R/W-0x0
6
5
4
3
2
1
0
Table 122. PHASEA1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
PHASEA1
R/W
0x0
NCO phase for channel A, preset 1
7.6.64 FREQA2 Register (Address = 0x230) [reset = 0x0]
FREQA2 is shown in Figure 87 and described in Table 123.
Return to Summary Table.
NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)
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NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)
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Figure 87. FREQA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQA2
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Table 123. FREQA2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQA2
R/W
0x0
NCO frequency for channel A, NCO preset 2
7.6.65 PHASEA2 Register (Address = 0x234) [reset = 0x0000]
PHASEA2 is shown in Figure 88 and described in Table 124.
Return to Summary Table.
NCO Phase (Channel A, Preset 2) (default: 0x0000)
Figure 88. PHASEA2 Register
15
14
13
12
11
10
9
ADVANCE INFORMATION
8
7
PHASEA2
R/W-0x0
6
5
4
3
2
1
0
Table 124. PHASEA2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
PHASEA2
R/W
0x0
NCO phase for channel A, preset 2
7.6.66 FREQA3 Register (Address = 0x238) [reset = 0x0]
FREQA3 is shown in Figure 89 and described in Table 125.
Return to Summary Table.
NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)
Figure 89. FREQA3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQA3
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Table 125. FREQA3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQA3
R/W
0x0
NCO frequency for channel A, NCO preset 3
7.6.67 PHASEA3 Register (Address = 0x23C) [reset = 0x0000]
PHASEA3 is shown in Figure 90 and described in Table 126.
Return to Summary Table.
NCO Phase (Channel A, Preset 3) (default: 0x0000)
Figure 90. PHASEA3 Register
15
112
14
13
12
11
10
9
8
7
PHASEA3
R/W-0x0
6
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4
3
2
1
0
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Table 126. PHASEA3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
PHASEA3
R/W
0x0
NCO phase for channel A, preset 3
7.6.68 FREQB0 Register (Address = 0x240) [reset = 0x0]
FREQB0 is shown in Figure 91 and described in Table 127.
Return to Summary Table.
NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)
Figure 91. FREQB0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQB0
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Bit
Field
Type
Reset
Description
31:0
FREQB0
R/W
0x0
NCO frequency for channel B, NCO preset 0.
Note: If the ADC is in DES mode, the NCO frequency and phase
settings for channel B are ignored. Use the NCO frequency and
phase registers for channel A only.
7.6.69 PHASEB0 Register (Address = 0x244) [reset = 0x0000]
PHASEB0 is shown in Figure 92 and described in Table 128.
Return to Summary Table.
NCO Phase (Channel B, Preset 0) (default: 0x0000)
Figure 92. PHASEB0 Register
15
14
13
12
11
10
9
8
7
PHASEB0
R/W-0x0
6
5
4
3
2
1
0
Table 128. PHASEB0 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
PHASEB0
R/W
0x0
NCO phase for channel B, preset 0
7.6.70 FREQB1 Register (Address = 0x248) [reset = 0x0]
FREQB1 is shown in Figure 93 and described in Table 129.
Return to Summary Table.
NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)
Figure 93. FREQB1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQB1
R/W-0x0
9
8
7
6
5
4
3
2
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Table 127. FREQB0 Register Field Descriptions
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Table 129. FREQB1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQB1
R/W
0x0
NCO frequency for channel B, NCO preset 1
7.6.71 PHASEB1 Register (Address = 0x24C) [reset = 0x0000]
PHASEB1 is shown in Figure 94 and described in Table 130.
Return to Summary Table.
NCO Phase (Channel B, Preset 1) (default: 0x0000)
Figure 94. PHASEB1 Register
15
14
13
12
11
10
9
8
7
PHASEB1
R/W-0x0
6
5
4
3
2
1
0
Table 130. PHASEB1 Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
Description
15:0
PHASEB1
R/W
0x0
NCO phase for channel B, preset 1
7.6.72 FREQB2 Register (Address = 0x250) [reset = 0x0]
FREQB2 is shown in Figure 95 and described in Table 131.
Return to Summary Table.
NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)
Figure 95. FREQB2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQB2
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Table 131. FREQB2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQB2
R/W
0x0
NCO frequency for channel B, NCO preset 2
7.6.73 PHASEB2 Register (Address = 0x254) [reset = 0x0000]
PHASEB2 is shown in Figure 96 and described in Table 132.
Return to Summary Table.
NCO Phase (Channel B, Preset 2) (default: 0x0000)
Figure 96. PHASEB2 Register
15
14
13
12
11
10
9
8
7
PHASEB2
R/W-0x0
6
5
4
3
2
1
0
Table 132. PHASEB2 Register Field Descriptions
114
Bit
Field
Type
Reset
Description
15:0
PHASEB2
R/W
0x0
NCO phase for channel B, preset 2
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7.6.74 FREQB3 Register (Address = 0x258) [reset = 0x0]
FREQB3 is shown in Figure 97 and described in Table 133.
Return to Summary Table.
NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)
Figure 97. FREQB3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FREQB3
R/W-0x0
9
8
7
6
5
4
3
2
1
0
Table 133. FREQB3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31:0
FREQB3
R/W
0x0
NCO frequency for channel B, NCO preset 3
7.6.75 PHASEB3 Register (Address = 0x25C) [reset = 0x0000]
ADVANCE INFORMATION
PHASEB3 is shown in Figure 98 and described in Table 134.
Return to Summary Table.
NCO Phase (Channel B, Preset 3) (default: 0x0000)
Figure 98. PHASEB3 Register
15
14
13
12
11
10
9
8
7
PHASEB3
R/W-0x0
6
5
4
3
2
1
0
Table 134. PHASEB3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
PHASEB3
R/W
0x0
NCO phase for channel B, preset 3
7.6.76 SPIN_ID Register (Address = 0x297) [reset = 0x0]
SPIN_ID is shown in Figure 99 and described in Table 135.
Return to Summary Table.
Chip Spin Identifier (default: See description, read-only)
Figure 99. SPIN_ID Register
7
6
RESERVED
R/W-0x0
5
4
3
2
SPIN_ID
R/W-0x0
1
0
Table 135. SPIN_ID Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
4:0
SPIN_ID
R/W
0x0
Description
Spin identification value:
0 : ADC12DJ5200RF
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7.6.77 SRC_EN Register (Address = 0x2B0) [reset = 0x00]
SRC_EN is shown in Figure 100 and described in Table 136.
Return to Summary Table.
SYSREF Calibration Enable (default: 0x00)
Figure 100. SRC_EN Register
7
6
5
4
RESERVED
R/W-0x0
3
2
1
0
SRC_EN
R/W-0x0
Table 136. SRC_EN Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R/W
0x0
SRC_EN
R/W
0x0
0
Description
ADVANCE INFORMATION
0: SYSREF Calibration Disabled. Use the TAD register to manually
control the tad[16:0] output and adjust the DEVCLK delay. (default)
1: SYSREF Calibration Enabled. The DEVCLK delay is automatically
calibrated. The TAD register is ignored.
A 0-to-1 transition on SRC_EN starts the SYSREF calibration
sequence. Program SRC_CFG before setting SRC_EN. Ensure that
ADC calibration is not currently running before setting SRC_EN.
7.6.78 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]
SRC_CFG is shown in Figure 101 and described in Table 137.
Return to Summary Table.
SYSREF Calibration Configuration (default: 0x05)
Figure 101. SRC_CFG Register
7
6
5
4
RESERVED
R/W-0x0
3
2
SRC_AVG
R/W-0x1
1
0
SRC_HDUR
R/W-0x1
Table 137. SRC_CFG Register Field Descriptions
116
Bit
Field
Type
Reset
7:4
RESERVED
R/W
0x0
3:2
SRC_AVG
R/W
0x1
Description
Specifies the amount of averaging used for SYSREF Calibration.
Larger values will increase calibration time and reduce the variance
of the calibrated value.
0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages
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Table 137. SRC_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1:0
SRC_HDUR
R/W
0x1
Specifies the duration of each high-speed accumulation for SYSREF
Calibration. If the SYSREF period exceeds the supported value,
calibration will fail. Larger values will increase calibration time and
support longer SYSREF periods. For a given SYSREF period, larger
values will also reduce the variance of the calibrated value.
0: 4 cycles per accumulation, max SYSREF period of 128 DEVCLK
cycles
1: 16 cycles per accumulation, max SYSREF period of 1664
DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 7808
DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 32384
DEVCLK cycles
Max duration of SYSREF calibration is bounded by: TSYSREFCAL
(in DEVCLK cycles) = 384 * 19 * 4^(SRC_AVG + SRC_HDUR + 2)
7.6.79 SRC_STATUS Register (Address = 0x2B2) [reset = 0x0]
Return to Summary Table.
SYSREF Calibration Status (read-only, default: undefined)
Figure 102. SRC_STATUS Register
Table 138. SRC_STATUS Register Field Descriptions
Field
Type
Reset
23:18
Bit
RESERVED
R/W
0x0
17
SRC_DONE
R/W
0x0
This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has
been completed.
SRC_TAD
R/W
0x0
This field returns the value for TAD[16:0] computed by SYSREF
Calibration. It is only valid if SRC_DONE=1.
SRC_TAD[16] indicates if DEVCLK has been inverted.
SRC_TAD[15:8] indicates the coarse delay adjustment.
SRC_TAD[7:0] indicates the fine delay adjustment.
16:0
Description
7.6.80 TAD Register (Address = 0x2B5) [reset = 0x00]
TAD is shown in Figure 103 and described in Table 139.
Return to Summary Table.
DEVCLK Timing Adjust (default: 0x00)
Figure 103. TAD Register
Table 139. TAD Register Field Descriptions
Bit
23:17
16
15:8
Field
Type
Reset
RESERVED
R/W
0x0
Description
TAD_INV
R/W
0x0
Inverts the sampling clock when set.
TAD_FINE
R/W
0x0
Refer to Switching Characteristics for TAD_FINE resolution.
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SRC_STATUS is shown in Figure 102 and described in Table 138.
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Table 139. TAD Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15:8
TAD_COARSE
R/W
0x0
This register controls the sampling aperture delay adjustment when
SRC_EN=0. Use this register to manually control the DEVCLK
aperture delay when SYSREF Calibration is disabled. If ADC
calibration or JESD204B is running, it is recommended that you
gradually increase or decrease this value (1 code at a time) to avoid
clock glitches. Refer to Switching Characteristics for TAD_COARSE
resolution.
If ADC calibration is enabled (CAL_EN=1), or the JESD204C link is
enabled (JESD_EN=1), the following rules must be obeyed to avoid
clock glitches and unpredictable behavior:
1. Do not change TAD_INV. You must program CAL_EN=0 and
JESD_EN=0 before changing TAD_INV.
2. TAD_COARSE must be increased or decreased gradually (no
more than 4 codes at a time). This rule can be obeyed manually via
SPI writes, or by setting TAD_RAMP_EN.
3. TAD_FINE may be changed to any value at any time (its
adjustment is too fine to cause clock glitches).
7:0
RESERVED
R
0x0
ADVANCE INFORMATION
7.6.81 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]
TAD_RAMP is shown in Figure 104 and described in Table 140.
Return to Summary Table.
DEVCLK Timing Adjust Ramp Control (default: 0x00)
Figure 104. TAD_RAMP Register
7
6
5
4
3
2
RESERVED
R/W-0x0
1
TAD_RAMP_R
ATE
R/W-0x0
0
TAD_RAMP_E
N
R/W-0x0
Table 140. TAD_RAMP Register Field Descriptions
Bit
Field
Type
Reset
7:2
Description
RESERVED
R/W
0x0
1
TAD_RAMP_RATE
R/W
0x0
Specifies the ramp rate for TAD_COARSE when the TAD_COARSE
register is written while TAD_RAMP_EN=1.
0: TAD_COARSE ramps up or down one code per 384 sampling
clock cycles.
1: TAD_COARSE ramps up or down 4 codes per 384 sampling clock
cycles.
0
TAD_RAMP_EN
R/W
0x0
TAD ramp enable. Set this bit if you want the coarse TAD
adjustment (TAD_COARSE) to ramp up or down instead of changing
abruptly.
0 : After writing the TAD_COARSE register, the applied
TAD_COARSE setting is updated within 1536 CLK cycles (ramp
feature disabled).
1 : After writing the TAD_COARSE register, the applied
TAD_COARSE setting ramps up or down gradually until it matches
the TAD_COARSE register.
7.6.82 ALARM Register (Address = 0x2C0) [reset = 0x0]
ALARM is shown in Figure 105 and described in Table 141.
Return to Summary Table.
Alarm Interrupt (read-only)
118
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Figure 105. ALARM Register
7
6
5
4
RESERVED
R-0x0
3
2
1
0
ALARM
R-0x0
Table 141. ALARM Register Field Descriptions
Bit
Field
Type
Reset
7:1
RESERVED
R
0x0
ALARM
R
0x0
0
Description
This bit returns a ‘1’ whenever any alarm occurs that is unmasked in
the ALM_STATUS register. Use ALM_MASK to mask (disable)
individual alarms. CAL_STATUS_SEL can be used to drive the
ALARM bit onto the CALSTAT output pin to provide a hardware
alarm interrupt signal.
7.6.83 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3]
ALM_STATUS is shown in Figure 106 and described in Table 142.
Alarm Status (default: 0x3F, write to clear)
Figure 106. ALM_STATUS Register
7
RESERVED
6
5
FIFO_ALM
4
PLL_ALM
3
LINK_ALM
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
2
REALIGNED_A
LM
R/W-0x0
1
NCO_ALM
0
CLK_ALM
R/W-0x1
R/W-0x1
Table 142. ALM_STATUS Register Field Descriptions
Bit
Field
Type
Reset
7:6
Description
RESERVED
R/W
0x0
5
FIFO_ALM
R/W
0x0
FIFO overflow/underflow alarm: This bit is set whenever an active
JESD204C lane FIFO experiences an underflow or overflow
condition. Write a ‘1’ to clear this bit. To inspect which lane
generated the alarm, read FIFO_LANE_ALM.
4
PLL_ALM
R/W
0x0
PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked.
Write a ‘1’ to clear this bit.
3
LINK_ALM
R/W
0x0
Link Alarm: This bit is set whenever the JESD204C link is enabled,
but is not in the data encoder state (for 8B/10B modes). In 64B/66B
modes, there is no data encoder state, so this alarm will be set when
the link first starts up, and will also be set if any event causes a
FIFO/serializer realignment. Write a ‘1’ to clear this bit.
2
REALIGNED_ALM
R/W
0x0
Realigned Alarm: This bit is set whenever SYSREF causes the
internal clocks (including the LMFC/LEMC) to be realigned. Write a
‘1’ to clear this bit.
1
NCO_ALM
R/W
0x1
NCO Alarm: This bit can be used to detect an upset to the NCO
phase. This bit is set when any of the following occur:
- The NCOs are disabled (JESD_EN=0).
- The NCOs are synchronized (intentionally or unintentionally)
- Any phase accumulators in channel A do not match channel B.
Write a ‘1’ to clear this bit. Refer to the alarm section for the proper
usage of this register.
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Return to Summary Table.
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Table 142. ALM_STATUS Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
CLK_ALM
R/W
0x1
Clock Alarm: This bit can be used to detect an upset to the internal
DDC/JESD204C clocks. This bit is set whenever the internal clock
dividers for the A and B channels do not match. Write a ‘1’ to clear
this bit. Refer to the alarm section for the proper usage of this
register.
Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’
Note: When JESD_EN=0, all alarms (except CLK_ALM) are
undefined. It is recommended that the user clears the alarms after
setting JESD_EN=1.
7.6.84 ALM_MASK Register (Address = 0x2C2) [reset = 0x3]
ALM_MASK is shown in Figure 107 and described in Table 143.
Return to Summary Table.
Alarm Mask Register (default: 0x3F)
Figure 107. ALM_MASK Register
ADVANCE INFORMATION
7
6
5
4
3
2
1
0
MASK_FIFO_A MASK_PLL_AL MASK_LINK_A MASK_REALIG MASK_NCO_A MASK_CLK_AL
LM
M
LM
NED_ALM
LM
M
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x1
R/W-0x1
RESERVED
R/W-0x0
Table 143. ALM_MASK Register Field Descriptions
Bit
Field
Type
Reset
7:6
Description
RESERVED
R/W
0x0
5
MASK_FIFO_ALM
R/W
0x0
When set, FIFO_ALM is masked and will not impact the ALARM
register bit.
4
MASK_PLL_ALM
R/W
0x0
When set, PLL_ALM is masked and will not impact the ALARM
register bit.
3
MASK_LINK_ALM
R/W
0x0
When set, LINK_ALM is masked and will not impact the ALARM
register bit.
2
MASK_REALIGNED_ALM R/W
0x0
When set, REALIGNED_ALM is masked and will not impact the
ALARM register bit.
1
MASK_NCO_ALM
R/W
0x1
When set, NCO_ALM is masked and will not impact the ALARM
register bit.
0
MASK_CLK_ALM
R/W
0x1
When set, CLK_ALM is masked and will not impact the ALARM
register bit.
7.6.85 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0x0]
FIFO_LANE_ALM is shown in Figure 108 and described in Table 144.
Return to Summary Table.
FIFO Overflow/Underflow Alarm (default: 0xFFFF)
Figure 108. FIFO_LANE_ALM Register
15
120
14
13
12
11
10
9
8
7
FIFO_LANE_ALM
R/W-0x0
6
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4
3
2
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Table 144. FIFO_LANE_ALM Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
FIFO_LANE_ALM
R/W
0x0
FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow
or underflow. Use this register to determine which lane(s) generated
an alarm. Writing a ‘1’ to any bit in this register will clear the alarm
(the alarm may immediately trip again if the overflow/underflow
condition persists). Writing a ‘1’ to the FIFO_ALM bit in the
ALM_STATUS register will clear all bits of this register.
7.6.86 TADJ_A Register (Address = 0x310) [reset = 0x0]
TADJ_A is shown in Figure 109 and described in Table 145.
Return to Summary Table.
Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)
Figure 109. TADJ_A Register
6
5
4
3
2
1
0
TADJ_A
R/W-0x0
Table 145. TADJ_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TADJ_A
R/W
0x0
This register (and other TADJ* registers that follow it) are used to
adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes. The default
values for all TADJ* registers are factory programmed values. The
factory trimmed values can be read out and adjusted as required.
7.6.87 TADJ_B Register (Address = 0x313) [reset = 0x0]
TADJ_B is shown in Figure 110 and described in Table 146.
Return to Summary Table.
Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)
Figure 110. TADJ_B Register
7
6
5
4
3
2
1
0
TADJ_B
R/W-0x0
Table 146. TADJ_B Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TADJ_B
R/W
0x0
See TADJ_A register for description. Adjusts timing of B-ADC in dual
channel mode with foreground calibration enabled.
7.6.88 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = 0x0]
TADJ_A_FG90_VINA is shown in Figure 111 and described in Table 147.
Return to Summary Table.
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)
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Figure 111. TADJ_A_FG90_VINA Register
7
6
5
4
3
TADJ_A_FG90_VINA
R/W-0x0
2
1
0
Table 147. TADJ_A_FG90_VINA Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TADJ_A_FG90_VINA
R/W
0x0
See TADJ_A register for description. Adjusts timing of A-ADC in
single channel mode with foreground calibration enabled and
sampling INA±.
7.6.89 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = 0x0]
TADJ_B_FG0_VINA is shown in Figure 112 and described in Table 148.
Return to Summary Table.
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)
Figure 112. TADJ_B_FG0_VINA Register
ADVANCE INFORMATION
7
6
5
4
3
TADJ_B_FG0_VINA
R/W-0x0
2
1
0
Table 148. TADJ_B_FG0_VINA Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TADJ_B_FG0_VINA
R/W
0x0
See TADJ_A register for description. Adjusts timing of B-ADC in
single channel mode with foreground calibration enabled and
sampling INA±.
7.6.90 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = 0x0]
TADJ_A_FG90_VINB is shown in Figure 113 and described in Table 149.
Return to Summary Table.
Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)
Figure 113. TADJ_A_FG90_VINB Register
7
6
5
4
3
TADJ_A_FG90_VINB
R/W-0x0
2
1
0
Table 149. TADJ_A_FG90_VINB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TADJ_A_FG90_VINB
R/W
0x0
See TADJ_A register for description. Adjusts timing of A-ADC in
single channel mode with foreground calibration enabled and
sampling INB±.
7.6.91 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]
TADJ_B_FG0_VINB is shown in Figure 114 and described in Table 150.
Return to Summary Table.
Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)
122
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Figure 114. TADJ_B_FG0_VINB Register
7
6
5
4
3
TADJ_B_FG0_VINB
R/W-0x0
2
1
0
Table 150. TADJ_B_FG0_VINB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
TADJ_B_FG0_VINB
R/W
0x0
See TADJ_A register for description. Adjusts timing of B-ADC in
single channel mode with foreground calibration enabled and
sampling INB±.
7.6.92 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = 0x0]
OADJ_A_FG0_VINA is shown in Figure 115 and described in Table 151.
Return to Summary Table.
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM)
15
14
13
12
11
5
4
3
OADJ_A_FG0_VINA
R/W-0x0
RESERVED
R/W-0x0
7
6
10
9
OADJ_A_FG0_VINA
R/W-0x0
2
1
8
0
Table 151. OADJ_A_FG0_VINA Register Field Descriptions
Field
Type
Reset
15:12
Bit
RESERVED
R/W
0x0
11:0
OADJ_A_FG0_VINA
R/W
0x0
Description
Offset adjustment value applied to A-ADC when it samples INA± in
dual channel mode and foreground calibration is enabled.
7.6.93 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = 0x0]
OADJ_A_FG0_VINB is shown in Figure 116 and described in Table 152.
Return to Summary Table.
Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM)
Figure 116. OADJ_A_FG0_VINB Register
15
14
13
12
11
5
4
3
OADJ_A_FG_VINB
R/W-0x0
RESERVED
R/W-0x0
7
6
10
9
OADJ_A_FG_VINB
R/W-0x0
8
2
0
1
Table 152. OADJ_A_FG0_VINB Register Field Descriptions
Field
Type
Reset
15:12
Bit
RESERVED
R/W
0x0
11:0
OADJ_A_FG_VINB
R/W
0x0
Description
Offset adjustment value applied to A-ADC when it samples INB± in
dual channel mode and foreground calibration is enabled.
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Figure 115. OADJ_A_FG0_VINA Register
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7.6.94 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = 0x0]
OADJ_A_FG90_VINA is shown in Figure 117 and described in Table 153.
Return to Summary Table.
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM)
Figure 117. OADJ_A_FG90_VINA Register
15
14
13
12
11
RESERVED
R/W-0x0
7
6
5
4
3
OADJ_A_FG90_VINA
R/W-0x0
10
9
OADJ_A_FG90_VINA
R/W-0x0
2
1
8
0
Table 153. OADJ_A_FG90_VINA Register Field Descriptions
Bit
ADVANCE INFORMATION
Field
Type
Reset
15:12
RESERVED
R/W
0x0
11:0
OADJ_A_FG90_VINA
R/W
0x0
Description
Offset adjustment value applied to A-ADC when it samples INA± in
single channel mode and foreground calibration is enabled.
7.6.95 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = 0x0]
OADJ_A_FG90_VINB is shown in Figure 118 and described in Table 154.
Return to Summary Table.
Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM)
Figure 118. OADJ_A_FG90_VINB Register
15
14
13
12
11
RESERVED
R/W-0x0
7
6
5
4
3
OADJ_A_FG90_VINB
R/W-0x0
10
9
OADJ_A_FG90_VINB
R/W-0x0
2
1
8
0
Table 154. OADJ_A_FG90_VINB Register Field Descriptions
Bit
Field
Type
Reset
15:12
RESERVED
R/W
0x0
11:0
OADJ_A_FG90_VINB
R/W
0x0
Description
Offset adjustment value applied to A-ADC when it samples INB±
using 90° clock phase and foreground calibration is enabled.
7.6.96 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = 0x0]
OADJ_B_FG0_VINA is shown in Figure 119 and described in Table 155.
Return to Summary Table.
Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM)
Figure 119. OADJ_B_FG0_VINA Register
15
14
13
12
11
5
4
3
RESERVED
R/W-0x0
7
124
6
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9
OADJ_B_FG0_VINA
R/W-0x0
2
1
8
0
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OADJ_B_FG0_VINA
R/W-0x0
Table 155. OADJ_B_FG0_VINA Register Field Descriptions
Field
Type
Reset
15:12
Bit
RESERVED
R/W
0x0
11:0
OADJ_B_FG0_VINA
R/W
0x0
Description
Offset adjustment value applied to B-ADC when it samples INA± and
foreground calibration is enabled. Applies to both dual channel mode
and single channel mode.
7.6.97 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = 0x0]
OADJ_B_FG0_VINB is shown in Figure 120 and described in Table 156.
Return to Summary Table.
Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM)
Figure 120. OADJ_B_FG0_VINB Register
14
13
12
11
5
4
3
OADJ_B_FG0_VINB
R/W-0x0
RESERVED
R/W-0x0
7
6
10
9
OADJ_B_FG0_VINB
R/W-0x0
2
1
8
0
Table 156. OADJ_B_FG0_VINB Register Field Descriptions
Field
Type
Reset
15:12
Bit
RESERVED
R/W
0x0
11:0
OADJ_B_FG0_VINB
R/W
0x0
Description
Offset adjustment value applied to B-ADC when it samples INB± and
foreground calibration is enabled. Applies to both dual channel mode
and single channel mode.
7.6.98 GAIN_B0 Register (Address = 0x360) [reset = 0x0]
GAIN_B0 is shown in Figure 121 and described in Table 157.
Return to Summary Table.
Fine Gain Adjust for Bank 0 (default from Fuse ROM)
Figure 121. GAIN_B0 Register
7
6
RESERVED
R/W-0x0
5
4
3
2
GAIN_B0
R/W-0x0
1
0
Table 157. GAIN_B0 Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
4:0
GAIN_B0
R/W
0x0
Description
Fine gain adjustment for bank 0.
7.6.99 GAIN_B1 Register (Address = 0x361) [reset = 0x0]
GAIN_B1 is shown in Figure 122 and described in Table 158.
Return to Summary Table.
Fine Gain Adjust for Bank 1 (default from Fuse ROM)
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Figure 122. GAIN_B1 Register
7
6
RESERVED
R/W-0x0
5
4
3
2
GAIN_B1
R/W-0x0
1
0
1
0
1
0
Table 158. GAIN_B1 Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
4:0
GAIN_B1
R/W
0x0
Description
Fine gain adjustment for bank 1.
7.6.100 GAIN_B4 Register (Address = 0x364) [reset = 0x0]
GAIN_B4 is shown in Figure 123 and described in Table 159.
Return to Summary Table.
Fine Gain Adjust for Bank 4 (default from Fuse ROM)
Figure 123. GAIN_B4 Register
ADVANCE INFORMATION
7
6
RESERVED
R/W-0x0
5
4
3
2
GAIN_B4
R/W-0x0
Table 159. GAIN_B4 Register Field Descriptions
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
4:0
GAIN_B4
R/W
0x0
Description
Fine gain adjustment for bank 4.
7.6.101 GAIN_B5 Register (Address = 0x365) [reset = 0x0]
GAIN_B5 is shown in Figure 124 and described in Table 160.
Return to Summary Table.
Fine Gain Adjust for Bank 5 (default from Fuse ROM)
Figure 124. GAIN_B5 Register
7
6
RESERVED
R/W-0x0
5
4
3
2
GAIN_B5
R/W-0x0
Table 160. GAIN_B5 Register Field Descriptions
126
Bit
Field
Type
Reset
7:5
RESERVED
R/W
0x0
4:0
GAIN_B5
R/W
0x0
Description
Fine gain adjustment for bank 5.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
ADC12DJ5200RF can be used in a wide range of applications including radar, satellite communications, test
equipment (communications testers and oscilloscopes), and software-defined radios (SDRs). The wide input
bandwidth enables direct RF sampling to at least 10 GHz and the high sampling rate allows signal bandwidths of
greater than 5 GHz. ADC12DJ5200RF can also be DC-coupled to meet the needs of oscilloscopes or wideband
digitizers. The Typical Applications section describes two configurations that meet the needs of a number of
these applications.
8.2.1 Wideband RF Sampling Receiver
This section demonstrates the use of ADC12DJ5200RF as a wideband RF sampling receiver. The solution is
flexible and can be used as either a 2-channel receiver (such as a diversity receiver) or as a single channel
receiver allowing double the signal bandwidth. The ADC is driven by single-ended RF amplifiers and the
conversion to differential signaling is achieved by a transformer (balun). ADC12DJ5200RF includes digital downconverters (DDCs) in both single-channel and dual-channel modes to mix the desired frequency band to
baseband and down-sample the data to reduce the interface rate. The block diagram for the wideband RF
sampling receiver is shown in Figure 125 with ADC12DJ5200RF is configured in single-channel mode for
maximum signal bandwidth.
LNA
LNA
Up to 16 lanes
JESD204C
Anti-Alias BPF
ADC
(Interleaved)
JESD
204C
DDC
SYNC~
JESD
204C
FPGA or ASIC
Clocking
Subsystem
÷
R÷
PFD
N÷
SPI
Device
Clock
LMK04832
10 MHz
Reference
User Control
Logic
÷
LMX
2594
SYSREF
Device Clock
÷
÷
SYSREF
Figure 125. Typical Configuration for Wideband RF Sampling
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8.2 Typical Applications
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Typical Applications (continued)
8.2.1.1 Design Requirements
8.2.1.1.1 Input Signal Path
Use appropriate band-limiting filters to reject unwanted frequencies in the input signal path.
A 1:2 balun transformer is needed to convert the 50-Ω, single-ended signal to 100-Ω differential for input to the
ADC. The balun outputs can be either AC-coupled, or directly connected to the ADC differential inputs, which are
terminated internally to GND.
Drivers must be selected to provide any needed signal gain and that have the necessary bandwidth capabilities.
In general, baluns must be selected to cover the needed frequency range, have a 1:2 impedance ratio, and have
acceptable gain and phase balance over the frequency range of interest. Mount baluns with poor differential
output return loss as close to the ADC inputs as possible to avoid ripples in the frequency response at high input
frequencies. Resistive attenuators (Pi- or T-type) can also help dampen ripples caused by poor return loss.
Table 161 lists a number of recommended baluns for different frequency ranges.
Table 161. Recommended Baluns
ADVANCE INFORMATION
(1)
PART NUMBER
MANUFACTURER (1)
MINIMUM FREQUENCY (MHz)
MAXIMUM FREQUENCY (MHz)
BAL-0009SMG
Marki Microwave
0.5
9000
BAL-0208SMG
Marki Microwave
2000
8000
TCM2-43X+
Mini-Circuits
10
4000
TCM2-33WX+
Mini-Circuits
10
3000
B0430J50100AHF
Anaren
400
3000
See the Third-Party Products Disclaimer section.
8.2.1.1.2 Clocking
The ADC12DJ5200RF clock inputs must be AC-coupled to the device to ensure rated performance. The clock
source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended
clock synthesizers include LMX2594 and LMX2572.
The JESD204C data converter system (ADC plus logic device) requires additional SYSREF and device clocks.
LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on
the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or
as a device clock and SYSREF distribution device when multiple ADC12DJ5200RF devices are used in a
system. For clock frequencies higher than 3.2 GHz, LMX2594 and LMX2572 can supply both the device clock
and SYSREF from a single device as demonstrated in Figure 125.
8.2.1.2 Detailed Design Procedure
Certain component values used in conjunction with the ADC12DJ5200RF must be calculated based on system
parameters. Those items are covered in this section.
128
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8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
AC-coupling capacitors are used in the input CLK± and JESD204C output data pairs. The capacitor values must
be large enough to address the lowest frequency signals of interest, but not so large as to cause excessively
long startup biasing times, or unwanted parasitic inductance.
The minimum capacitor value can be calculated based on the lowest frequency signal that is transferred through
the capacitor. Given a 50-Ω single-ended clock or data path impedance, good practice is to set the capacitor
impedance to be <1 Ω at the lowest frequency of interest. This setting ensures minimal impact on signal level at
that frequency. For the CLK± path, the minimum-rated clock frequency is 800 MHz. Therefore, the minimum
capacitor value can be calculated from:
ZC = 1/ (2 ´ p ´ ¦ CLK ´ C )
(16)
Setting Zc = 1 Ω and rearranging gives:
C = 1/ (2 ´ p ´ 800 MHz ´ 1 W ) = 199 pF
Therefore, a capacitance value of at least 199 pF is needed to provide the low-frequency response for the CLK±
path. If the minimum clock frequency is higher than 800 MHz, this calculation can be revisited for that frequency.
Similar calculations can be done for the JESD204C output data capacitors based on the minimum frequency in
that interface. Capacitors must also be selected for good response at high frequencies, and with dimensions that
match the high-frequency signal traces they are connected to. Capacitors of the 0201 size are frequently well
suited to these applications.
8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
This section demonstrates the use of the ADC12DJ5200RF in a reconfigurable oscilloscope. ADC12DJ5200RF is
ideally suited for oscilloscope applications. The ability to tradeoff channel count and sampling speed allows
designers to build flexible hardware to meet multiple needs. This flexibility saves development time and cost,
allows hardware reuse for various projects and enables software upgrade paths for additional functionality. This
section describes an oscilloscope that can operate as a dual-channel oscilloscope running at 5 GSPS or can be
reconfigured through SPI programming as a single-channel, 10-GSPS oscilloscope. A reconfigurable setup
allows users to trade off the number of channels and the sampling rate of the oscilloscope as needed without
changing the hardware. Set the input bandwidth to the desired maximum signal bandwidth through the use of an
antialiasing, low-pass filter. Digital filtering can then be used to reconfigure the analog bandwidth as required. For
instance, the maximum bandwidth can be set to 2 GHz for use during pulsed transient detection and then
reconfigured to 100 MHz through digital filtering for low-noise, power-supply ripple observation. Figure 126 shows
the application block diagram.
Front Panel
Channel A
Programmable
Termination
LMH5401
LMH6401
LMH6559 OPA703
Programmable
Termination
JESD
204C
ADC A
DC Offset
Adjustment
DAC
Front Panel
Channel B
Up to 16 lanes
JESD204C
Anti-Alias LPF
LMH5401
SYNC~
DAC8560
LMH6401
Anti-Alias LPF
JESD
204C
ADC B
DC Offset
Adjustment
DAC
LMH6559 OPA703
DAC8560
÷
R÷
PFD
N÷
User Control
Logic
SPI
Device
Clock
LMK04832
10 MHz
Reference
FPGA or ASIC
Clocking
Subsystem
÷
LMX
2594
SYSREF
Device Clock
÷
÷
SYSREF
Figure 126. Typical Configuration for Reconfigurable Oscilloscope
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8.2.2.1 Design Requirements
8.2.2.1.1 Input Signal Path
Most oscilloscopes are required to be DC-coupled in order to monitor DC or low-frequency signals. This
requirement forces the design to use DC-coupled, fully differential amplifiers to convert from single-ended
signaling at the front panel to differential signaling at the ADC. This design uses two differential amplifiers. The
first amplifier shown in Figure 126 is the LMH5401 that converts from single-ended to differential signaling. The
LMH5401 interfaces with the front panel through a programmable termination network and has an offset
adjustment input. The amplifier has an 8-GHz, gain-bandwidth product that is sufficient to support a 1-GHz
bandwidth oscilloscope. A second amplifier, the LMH6401, comes after the LMH5401 to provide a digitally
programmable gain control for the oscilloscope. The LMH6401 supports a gain range from –6 dB to 26 dB in 1dB steps. If gain control is not necessary or is performed in a different location in the signal chain, then this
amplifier can be replaced with a second LMH5401 for additional fixed gain or omitted altogether.
The input of the oscilloscope contains a programmable termination block that is not covered in detail here. This
block enables the front-panel input termination to be programmed. For instance, many oscilloscopes allow the
termination to be programmed as either 50-Ω or 1-MΩ to meet the needs of various applications. A 75-Ω
termination can also be desired to support cable infrastructure use cases. This block can also contain an option
for DC blocking to remove the DC component of the external signal and therefore pass only AC signals.
ADVANCE INFORMATION
A precision DAC is used to configure the offset of the oscilloscope front-end to prevent saturation of the analog
signal chain for input signals containing large DC offsets. The DAC8560 is shown in Figure 126 along with
signal-conditioning amplifiers OPA703 and LMH6559. The first differential amplifier, LMH5401, is driven by the
front panel input circuitry on one input, and the DC offset bias on the second input. The impedance of these
driving signals must be matched at DC and over frequency to ensure good even-order harmonic performance in
the single-ended to differential conversion operation. The high bandwidth of the LMH6559 allows the device to
maintain low impedance over a wide frequency range.
An antialiasing, low-pass filter is positioned at the input of the ADC to limit the bandwidth of the input signal into
the ADC. This amplifier also band-limits the front-end noise to prevent aliased noise from degrading the signal-tonoise ratio of the overall system. Design this filter for the maximum input signal bandwidth specified by the
oscilloscope. The input bandwidth can then be reconfigured through the use of digital filters in the FPGA or ASIC
to limit the oscilloscope input bandwidth to a bandwidth less than the maximum.
8.2.2.1.2 Clocking
The ADC12DJ5200RF clock inputs must be AC-coupled to the device to ensure rated performance. The clock
source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended
clock synthesizers include LMX2594 and LMX2572.
The JESD204C data converter system (ADC plus logic device) requires additional SYSREF and device clocks.
LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on
the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or
as a device clock and SYSREF distribution device when multiple ADC12DJ5200RF devices are used in a
system. For clock frequencies higher than 3.2 GHz, LMX2594 and LMX2572 can supply both the device clock
and SYSREF from a single device as demonstrated in Figure 125.
8.2.2.1.3 ADC12DJ5200RF
ADC12DJ5200RF has a number of features that make it a great fit for oscilloscope applications. The low codeerror rate (CER) eliminates concerns about undesired time domain glitches or sparkle codes. The low CER
makes ADC12DJ5200RF a perfect fit for long-duration transient detection measurements and reduces the
probability of false triggers. The input common-mode voltage of 0 V allows the driving amplifiers to use equal
split power supplies that center the amplifier output common-mode voltage at 0 V and eliminates the need for
common-mode voltage shifting before the ADC inputs. The high input bandwidth of the ADC12DJ5200RF
simplifies the design of the driving amplifier circuit and antialiasing, low-pass filter. The use of dual-edge
sampling (DES) in single-channel mode eliminates the need to change the clock frequency when switching
between dual- and single-channel modes and simplifies synchronization by relaxing the setup and hold timing
requirements of SYSREF. The tAD adjust circuit allows the user to time-align the sampling instances of multiple
ADC12DJ5200RF devices or to set the ideal sampling point of a front-end track and hold (T&H) amplifier.
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The device and JESD204C interface require a specific startup and alignment sequence. The order of that
sequence is listed in the following steps.
1. Power-up or reset the device.
2. Apply a stable device CLK signal at the desired frequency.
3. Perform a software reset by toggling SOFT_RESET to 1. Wait at least 1 µs before continuing.
4. Program JESD_EN = 0 to stop the JESD204C state machine and allow setting changes.
5. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.
6. Program the desired JMODE.
7. Program the desired KM1 value. KM1 = K–1.
8. Program SYNC_SEL as needed. Choose SYNCSE or timestamp differential inputs.
9. Program the GAIN_Bx registers (addresses 0x360 to 0x365), where x is the bank number, as follows:
– Single-channel mode, background calibration: Use default values (no write needed after device reset)
– Single-channel mode, foreground calibration: Write 0x10 to each register
– Dual-channel mode: Write 0x10 to each register
10. Configure device calibration settings as desired. Select foreground or background calibration modes and
offset calibration as needed.
11. Program CAL_EN = 1 to enable the calibration state machine.
12. Enable overrange via OVR_EN and adjust settings if desired.
13. Program JESD_EN = 1 to re-start the JESD204C state machine and allow the link to restart.
14. The JESD204C interface operates in response to the applied SYNC signal from the receiver.
15. Program CAL_SOFT_TRIG = 0.
16. Program CAL_SOFT_TRIG = 1 to initiate a calibration.
9 Power Supply Recommendations
The device requires two different power-supply voltages. 1.9-V DC is required for the VA19 power bus and 1.1-V
DC is required for the VA11 and VD11 power buses.
The power-supply voltages must be low noise and provide the needed current to achieve rated device
performance.
There are two recommended power supply architectures:
1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide
switching noise reduction and improved voltage accuracy.
2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent
degraded ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power supply elements needed:
see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include LMS3635-Q1, LMS3655-Q1, TPSM84424 and
similar devices.
Recommended low drop-out (LDO), low-noise linear regulators include the TPS7A84, TPS7A83A, TPS7A47 and
similar devices.
For the switcher only approach, the ripple filter must be designed to provide sufficient filtering at the switching
frequency of the DC-DC converter and harmonics of the switching frequency. Make a note of the switching
frequency reported from WEBENCH® and design the EMI filter and capacitor combination to have the notch
frequency centered as needed. Each application will have different tolerances for noise on the supply voltage so
strict ripple requirements are not provided. Figure 127 and Figure 128 illustrate the two approaches.
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8.3 Initialization Set Up
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1.9 V
2.2 V
5 V - 12 V
Buck
FB
+
±
LDO
47 F
1.4 V
Buck
FB
47 F
Power
Good
GND
GND
VA19
10 F 0.1 F 0.1 F
GND
GND
VA11
1.1 V
FB
LDO
47 F
FB
47 F
GND
10 F 0.1 F 0.1 F
GND
GND
VD11
FB
10 F 0.1 F 0.1 F
ADVANCE INFORMATION
GND
Copyright © 2018, Texas Instruments Incorporated
NOTE: FB = ferrite bead filter.
Figure 127. LDO Linear Regulator Approach Example
Ripple Filter
5 V - 12 V
Buck
FB
+
±
GND
VA19
1.9 V
Power
Good
FB
10 F 10 F 10 F
GND
10 F 0.1 F 0.1 F
GND
Ripple Filter
Buck
VA11
1.1 V
FB
FB
10 F 10 F 10 F
GND
10 F 0.1 F 0.1 F
GND
VD11
FB
10 F 0.1 F 0.1 F
GND
Copyright © 2018, Texas Instruments Incorporated
NOTE: Ripple filter notch frequency to match the fs of the buck converter.
NOTE: FB = ferrite bead filter.
Figure 128. Switcher-Only Approach Example
132
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9.1 Power Sequencing
The voltage regulators must be sequenced using the power-good outputs and enable inputs to ensure that the
Vx11 regulator is enabled after the VA19 supply is good. Similarly, as soon as the VA19 supply drops out of
regulation on power-down, the Vx11 regulator is disabled.
The general requirement for the ADC is that VA19 ≥ Vx11 during power-up, operation, and power-down.
TI also recommends that VA11 and VD11 are derived from a common 1.1-V regulator. This recommendation
ensures that all 1.1-V blocks are at the same voltage, and no sequencing problems exist between these supplies.
Also use ferrite bead filters to isolate any noise on the VA11 and VD11 buses from affecting each other.
10 Layout
There are many critical signals that require specific care during board design:
1. Analog input signals
2. CLK and SYSREF
3. JESD204C data outputs
4. Power connections
5. Ground connections
The analog input signals, clock signals and JESD204C data outputs must be routed for excellent signal quality at
high frequencies, but should also be routed for maximum isolation from each other. Use the following general
practices:
1. Route using loosely coupled 100-Ω differential traces when possible. This routing minimizes impact of
corners and length-matching serpentines on pair impedance.
2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential
traces. Tightly coupled differential traces may be used to reduce self-radiated noise or to improve
neighboring trace noise immunity when adequate spacing cannot be provided.
3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground
plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or
poorly connected ground pours.
4. Use smoothly radiused corners. Avoid 45- or 90-degree bends to reduce impedance mismatches.
5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these
locations. Cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup
height that achieves the needed 50-Ω, single-ended impedance.
6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the
ground plane or ground plane clearances associated with power and signal vias and through-hole
component leads.
7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias at an appropriate
spacing as determined by the maximum frequency the trace will transport (<< λMIN/8).
8. When high-speed signals must transition to another layer using vias, transition as far through the board as
possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is
not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place ground vias close to the
signal vias when transitioning between layers to provide a nearby ground return path.
Pay particular attention to potential coupling between JESD204C data output routing and the analog input
routing. Switching noise from the JESD204C outputs can couple into the analog input traces and show up as
wideband noise due to the high input bandwidth fo the ADC. Ideally, route the JESD204C data outputs on a
separate layer from the ADC input traces to avoid noise coupling (not shown in the Layout Example section).
Tightly coupled traces can also be used to reduce noise coupling.
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10.1 Layout Guidelines
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Layout Guidelines (continued)
Impedance mismatch between the CLK± input pins and the clock source can result in reduced amplitude of the
clock signal at the ADC CLK± pins due to signal reflections or standing waves. A reduction in the clock amplitude
may degrade ADC noise performance, especially at high input frequencies. To avoid this, keep the clock source
close to the ADC (as shown in the Layout Example section) or implement impedance matching at the ADC CLK±
input pins.
In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to
fabrication. Insertion loss, return loss, and time domain reflectometry (TDR) evaluations should be done.
The power and ground connections for the device are also very important. These rules must be followed:
1. Provide low-resistance connection paths to all power and ground pins.
2. Use multiple power layers if necessary to access all pins.
3. Avoid narrow isolated paths that increase connection resistance.
4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power
planes.
ADVANCE INFORMATION
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10.2 Layout Example
ADVANCE INFORMATION
Figure 129 to Figure 131 provide examples of the critical traces routed on the device evaluation module (EVM).
Figure 129. Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3
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Layout Example (continued)
ADVANCE INFORMATION
Figure 130. GND1 Cutouts to Optimize Impedance of Component Pads
136
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Layout Example (continued)
Figure 131. Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
WEBENCH® Power Designer
11.2 Documentation Support
11.2.1 Related Documentation
ADVANCE INFORMATION
For related documentation see the following:
• ADC12DJ5200RF Evaluation Module User's Guide
• JESD204B multi-device synchronization: Breaking down the requirements
• Scalable 20.8 GSPS reference design for high speed 12 bit digitizers
• Synchronizing multi-channel data converter DDC and NCO features for RF systems reference design
• Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
• Flexible 3.2 GSPS Multi-Channel AFE Reference Design for DSOs, RADAR, and 5G Wireless Test Systems
• Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
• 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
• Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design
• LMX2594 Multiple PLL Reference Design
• LMX2594 15-GHz Wideband PLLatinum™ RF Synthesizer With Phase Synchronization and JESD204B
• LMX2572 6.4-GHz Low Power Wideband RF Synthesizer With Phase Synchronization and JESD204B
• LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
• LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
• LMK61E2 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM
• LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier
• LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier
• TPSM84424 4.5-V to 17-V Input, 0.6-V to 10-V Output, 4-A Power Module
• TPS7A470x 36-V, 1-A, 4-µVRMS, RF LDO Voltage Regulator
• TPS7A83A 2-A, High-Accuracy (0.75%), Low-Noise (4.4 µVRMS) LDO Regulator
• TPS7A84 High-Current (3 A), High-Accuracy (1%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator
• DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C
Reference
• LM95233 Dual Remote Diode and Local Temperature Sensor with SMBus Interface and TruTherm™
• TMP461 High-Accuracy Remote and Local Temperature Sensor with Pin-Programmable Bus Address
138
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11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11.5 Trademarks
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC12DJ5200RFAAV
PREVIEW
FCBGA
AAV
144
168
TBD
Call TI
Call TI
-40 to 85
ADC12DJ5200RFAAVT
PREVIEW
FCBGA
AAV
144
250
TBD
Call TI
Call TI
-40 to 85
PADC12DJ5200RFAAV
ACTIVE
FCBGA
AAV
144
168
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
AAV0144A
FCBGA - 1.94 mm max height
SCALE 1.400
BALL GRID ARRAY
10.15
9.85
A
B
BALL A1 CORNER
10.15
9.85
( 8)
(0.68)
(0.5)
1.94 MAX
C
SEATING PLANE
NOTE 4
BALL TYP
0.405
TYP
0.325
0.2 C
8.8 TYP
(0.6) TYP
SYMM
0.8 TYP
(0.6) TYP
M
L
K
J
H
SYMM
8.8
TYP
G
F
E
D
0.51
144X
0.41
0.15
C A B
0.08
C NOTE 3
C
B
A
1
2
3
4
5
6
7
8
9
10
11 12
0.8 TYP
4219578/A 04/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
AAV0144A
FCBGA - 1.94 mm max height
BALL GRID ARRAY
(0.8) TYP
A
1
2
3
4
5
6
7
8
10
9
11
12
B
(0.8) TYP
C
D
144X ( 0.4)
E
F
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
( 0.4)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219578/A 04/2016
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
AAV0144A
FCBGA - 1.94 mm max height
BALL GRID ARRAY
144X ( 0.4)
(0.8) TYP
A
1
2
3
4
5
6
7
8
9
10
11
12
B
(0.8)
TYP
C
D
E
F
SYMM
G
H
J
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4219578/A 04/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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